Freescale MC68EC030 User Manual

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded
Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:

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• Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

• Burst-Mode Bus Interface for Efficient DRAM Access

• On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

• Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

• 25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

• Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

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Additional features of the MC68EC030 include:

• Complete 32-Bit Nonmultiplexed Address and Data Buses

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

• Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

• Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution

• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

• Complete Support for Coprocessors with the M68000 Coprocessor Interface

• Internal Status Indication for Hardware Emulation Support

• 4-Gbyte Direct Addressing Range

• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

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INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as t he
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

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chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.

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The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

20 MHz

OSC.

MC88916

3

MC68EC030

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

Figure 1. MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates t he
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

BUS CLOCK

(40 MHz)

(80 MHz)

2 MC68EC030 TECHNICAL DATA MOTOROLA

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information. The instruction pipe and other individual control sections provide the secondary decode of
instructions and generate the actual control signals that result in the decoding and interpretation of
nanoROM and microROM information.

The instruction and data cache blocks operate independently from the rest of the machine, storing
information read by the bus controller for future use with very fast access time. Each cache resides on its
own address bus and data bus, allowing simultaneous access to both. The data and instruction caches
are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache misses.

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INTERNAL

DATA

BUS

(CAHR)

CACHE

HOLDING

REGISTER

B

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STAGE

C

STAGE

INSTRUCTION PIPE

D

STAGE

STORE

CONTROL

CONTROL

MICROSEQUENCER AND

CONTROL

CACHE

INSTRUCTION

LOGIC

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EXECUTION UNIT

BUS

ADDRESS

INSTRUCTION

BUS

DATA

DATA

PADS

SIZE

MULTIPLEXER

DATA

SECTION

SECTION

ADDRESS

SECTION

COUNTER

PROGRAM

ADDRESS

ADDRESS

UNIT

ACCESS

CONTROL

MULTIPLEXER

MISALIGNMENT

BUS

BUS CONTROLLER

DATA

CACHE

BUS

DATA

ADDRESS

BUFFER

PREFETCH PENDING

MICROBUS

CONTROLLER

SIGNALS

BUS CONTROL

Figure 2. Block Diagram

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PADS

ADDRESS

BUS

ADDRESS

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The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.

PROGRAMMING MODEL

As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general­purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, th e

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address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.

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31 1516 0

31 1516 0

31 1516 0

31 0

78

D0
D1

D2
D3
D4

D5
D6
D7

A0
A1

A2
A3

A4
A5
A6

A7

(USP)

PC

DATA
REGISTERS

ADDRESS
REGISTERS

USER STACK
POINTER

PROGRAM
COUNTER

15

Figure 3. User Programming Model

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8

7

0

0

CCR

CONDITION CODE
REGISTER

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31 1516 0

31 1516 0

31 0

31 0

31 0

31 0

31 0

31 0

15

7815 0

(CCR)

2

0

A7'
(ISP)

A7"
(MSP)

SR

VBR

SFC
DFC

CACR

CAAR

AC0

AC1

ACUSR

INTERRUPT
STACK POINTER

MASTER
STACK POINTER

STATUS
REGISTER

VECTOR
BASE REGISTER

ALTERNATE FUNCTION
CODE REGISTERS

CACHE CONTROL
REGISTER

CACHE ADDRESS
REGISTER

ACCESS CONTROL
REGISTER 0

ACCESS CONTROL
REGISTER 1

ACU STATUS
REGISTER

Figure 4. Supervisor Programming Model Supplement

The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following
condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits
indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt
state (M).

TRACE ENABLE

SYSTEM BYTE

14

15 13 10 8 4 0

T

T

S

0

1

III XNZVC

0

M

2

INTERRUPT

PRIORITY MASK

1

000

0

USER BYTE

11211 9 765 32

SUPERVISOR/USER STATE

MASTER/INTERRUPT STATE

CONDITION

CODES

EXTEND

NEGATIVE

ZERO

OVERFLOW

CARRY

Figure 5. Status Register

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All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the
MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The
MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow
instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are
important for software program development and debug.

The vector base register (VBR) is used to determine the run-time location of the exception vector table in
memory; thus, each separate vector table for each process or task can properly manage exceptions
independent of each other.

The M68000 Family processors distinguish address spaces as supervisor/user, program/data, and CPU
space. These five combinations are specified by the function code pins (FC0/FC1/FC2) during bus
cycles, indicating the particular address space. Using the function codes, the memory subsystem
(hardware) can distinguish between supervisor accesses and user accesses as well as program accesses,
data accesses, and CPU space accesses. To support the full privileges of the supervisor, the alternate
function code registers allow the supervisor to specify the function code for an access by appropriately

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preloading the SFC/DFC registers.
The cache registers allow supervisor software manipulation of the on-chip instruction and data caches.

Control and status accesses to the caches are provided by the cache control register (CACR); the cache
address register (CAAR) specifies the address for those cache control functions that require an address.

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The access control registers are accessible by the supervisor only. The access control registers are used
to define two memory spaces with caching restrictions. The ACU status register (ACUSR) is used to show
the result of PTEST operations on the ACU.

DATA TYPES AND ADDRESSING MODES

Seven basic data types are supported by the MC68EC030:

• Bits

• Bit Fields (String of consecutive bits, 1–32 bits long)

• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)

• Byte Integers (8 bits)

• Word Integers (16 bits)

• Long-Word Integers (32 bits)

• Quad-Word Integers (64 bits)

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In addition, operations on other data types, such as memory addresses, status word data, etc., are
provided in the instruction set. The coprocessor mechanism allows direct support of floating-point data
types with the MC68881/MC68882 floating-point coprocessors as well as specialized user-defined data
types and functions. The 18 addressing modes, listed in Table 1, include nine basic types:

• Register Direct

• Register Indirect

• Register Indirect with Index

• Memory Indirect

• Program Counter Indirect with Displacement

• Program Counter Indirect with Index

• Program Counter Memory Indirect

• Absolute

• Immediate

The register indirect addressing modes support postincrement, predecrement, offset, and indexing.
These capabilities are particularly useful for handling advanced data structures common to sophisticated
applications and high-level languages. The program counter relative mode also has index and offset

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capabilities; this addressing mode is generally required to support position- independent software. In
addition to these addressing modes, the MC68EC030 provides data operand sizing and scaling; these
features provide performance enhancements to the programmer.

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Table 1. MC68EC030 Addressing Modes

Addressing Modes Syntax

Register Direct Addressing

Data Register Direct
Address Register Direct

Register Indirect

Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement

Register Indirect with Index

Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)

Memory Indirect

Memory Indirect Postindexed
Memory Indirect Preindexed

Program Counter Indirect with Displacement (d16,PC)
Program Counter Indirect with Index

PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)

Program Counter Memory Indirect

PC Memory Indirect Postindexed
PC Memory Indirect Preindexed

Absolute Data Addressing

Absolute Short
Absolute Long

Immediate #<data>

NOTES:

Dn = Data Register, D0–D7
An = Address Register, A0–A7
d8, d16= A twos-complement or sign-extended displacement; added as part of

the effective address calculation; size is 8 (d8) or 16 (d16) bits;

Xn = Address or data register used as an index register; form is

bd = A twos-complement base displacement; when present, size can be
od = Outer displacement added as part of effective address calculation

PC = Program Counter
<data> = Immediate value of 8, 16, or 32 bits
( ) = Effective Address
[ ] = Used as indirect address to long-word address.

when omitted, assemblers use a value of zero.

Xn.SIZE*SCALE, where SIZE is .W or .L (indicates index register
size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by
SCALE); use of SIZE and/or SCALE is optional.

16 or 32 bits.

after any memory indirection; use is optional with a size of 16 or 32

bits.

Dn
An

(An)
(An);pl

-(An)
(d16,An)

(d8,An,Xn)
(bd,An,Xn)

([bd,An],Xn,od)
([bd,An,Xn],od)

(d8,PC,Xn)
(bd,PC,Xn)

([bd,PC],Xn,od)
([bd,PC,Xn],od)

xxx.W
xxx.L

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INSTRUCTION SET OVERVIEW

The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on
bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The
MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it
supports all instructions of previous family members.

Table 2. Instruction Set

Mnemonic Description Mnemonic Description

ABCD Add Decimal with Extend MOVE Move
AD D Add MOVEA Move Address
ADDA Add Address MOVE CCR Move Condition Code Register
ADDI Add Immediate MOVE SR Move Status Register
ADDQ Add Quick MOVE USP Move User Stack Pointer
ADDX Add with Extend MOVEC Move Control Register
AND Logical AND MOVEM Move Multiple Registers
ANDI Logical AND Immediate MOVEP Move Peripheral
ASL,ASR Arithmetic Shift Left and Right MOVEQ Move Quick

Bcc Branch Conditionally MOVES Move Alternate Address Space
BCHG Test Bit and Change MULS Signed Multiply
BCLR Test Bit and Clear MULU Unsigned Multiply

BFCHG Test Bit Field and Change NBCD Negate Decimal with Extend
BFCLR Test Bit Field and Clear NEG Negate
BFEXTS Signed Bit Field Extract NEGX Negate with Extend
BEFXTU Unsigned Bit Field Extract NOP No Operation
BFFFO Bit Field Find First One NOT Logical Complement

BFINS Bit Field Insert OR Logical Inclusive OR
BFSET Test Bit Field and Set ORI Logical Inclusive OR Immediate

BFTST Test Bit Field PACK Pack BCD
BKPT Breakpoint PEA Push Effective Address
BRA Branch PFLUSH No Effect
BSET Test Bit and Set PLOAD No Effect
BSR Branch to Subroutine PMOVE Move to/from ACx Registers
BTST Test Bit PTEST Test Address in ACx Registers

CAS Compare and Swap Operands RESET Reset External Devices
CAS2 Compare and Swap Dual Operands ROL, ROR Rotate Left and Right
CHK Check Register Against Bound ROXL, ROXR Rotate with Extend Left and Right
CHK2 Check Register Against Upper and Lower RTD Return and Deallocate

Bounds RTE Return from Exception
CLR Clear R TR Return and Restore Codes
CMP Compare RTS Return from Subroutine

CMPA Compare Address SBCD Subtract Decimal with Extend
CMPI Compare Immediate Scc Set Conditionally
CMPM Compare Memory to Memory STOP Stop
CMP2 Compare Register Against Upper and SUB Subtract

Lower Bounds SUBA Subtract Address

DBcc Test Condition, Decrement and Branch SUBI Subtract Immediate
DIVS,DIVSL Signed Divide SUBQ Subtract Quick
DIVU, DIVUL Unsigned Divide SUBX Subtract with Extend

EOR Logical Exclusive OR SWAP Swap Register Words
EORI Logical Exclusive OR Immediate TAS Test Operand and Set

EXG Exchange Registers TRAP Trap
EXT, EXTB Sign Extend TRAPcc Trap Conditionally

ILLEGAL Take Illegal Instruction Trap TRAPV Trap on Overflow
JMP Jump TST Test Operand
JSR Jump to Subroutine UNLK Unlink
LEA Load Effective Address UNPK Unpack BCD
LINK Link and Allocate

LSL, LSR Logical Shift Left and Right

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cpBCC Branch Conditionally cpRESTORE Restore Internal State of Coprocessor
cpDBcc Test Coprocessor Condition, cpSAVE Save Internal State of Coprocessor

Decrement and Branch cpScc Set Conditionally
cpGEN Coprocessor General Instruction cpTRAPcc Trap Conditionally

Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds
checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)
offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030
can be used on the MC68040 for even more performance. The memory management unit (MMU)
instructions of the MC68030, and MC68040 are not supported by the MC68EC030.

Coprocessor Instructions

INSTRUCTION AND DATA CACHES

Studies have shown that typical programs spend most of their execution time in a few main routines or
tight loops. This phenomenon, known as locality of reference, has an impact on program performance.

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The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can b e
used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to
provide the system with two on-chip caches, one for instructions and one for data.

MC68EC030 CACHE GOALS

Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030
embedded controller caches. The first design goal was t o reduce the external bus activity of the CPU
even more than was accomplished with the MC68020. The second design goal was to increase effective
CPU throughput as larger memory sizes or slower memories increased average access time. By placing a
high-speed cache between the controller and the rest of the memory system, the effective memory
access time becomes:

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where t
the rest of the system, and Rh is the hit ratio or the percentage of time that the data is found in the cache.
Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial
CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower
and less expensive memories can be used for the same controller performance.

The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are
accessed in less time than is required for external accesses, providing improvement in the access time for
items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be
found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time
required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time
for items found in the caches even further. Third, the autonomous nature of the caches allows instruction
stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.
The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently
so that several internal instructions (those that do not require any external accesses) can execute while
the controller is performing an external access for a previous instruction.

is the effective system access time, t

acc

t

acc

=Rh*t

+ (1-Rh)*t

cache

is the cache access time, t

cache

ext

is the access time o f

ext

INSTRUCTION CACHE

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