Freescale MC68EC030 User Manual

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68EC030

Technical Summary

Second-Generation 32-Bit Enhanced Embedded
Controller

The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:

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• Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors

• Burst-Mode Bus Interface for Efficient DRAM Access

• On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)

• Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices

• 25- and 40-MHz Operating Frequency (up to 9.2 MIPS)

• Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

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Additional features of the MC68EC030 include:

• Complete 32-Bit Nonmultiplexed Address and Data Buses

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers

• Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection

• Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution

• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)

• Complete Support for Coprocessors with the M68000 Coprocessor Interface

• Internal Status Indication for Hardware Emulation Support

• 4-Gbyte Direct Addressing Range

• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

©MOTOROLA INC., 1991

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INTRODUCTION

The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as t he
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.

The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-

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chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.

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The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems. Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure

1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.

CONTROLLER

CLOCK (40 MHz)

20 MHz

OSC.

MC88916

3

MC68EC030

(40 MHz)

BUS CLOCK

(20 MHz)

BUS CLOCK

Figure 1. MC68EC030 Clock Circuitry

The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates t he
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing

BUS CLOCK

(40 MHz)

(80 MHz)

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information. The instruction pipe and other individual control sections provide the secondary decode of
instructions and generate the actual control signals that result in the decoding and interpretation of
nanoROM and microROM information.

The instruction and data cache blocks operate independently from the rest of the machine, storing
information read by the bus controller for future use with very fast access time. Each cache resides on its
own address bus and data bus, allowing simultaneous access to both. The data and instruction caches
are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache misses.

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INTERNAL

DATA

BUS

(CAHR)

CACHE

HOLDING

REGISTER

B

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STAGE

C

STAGE

INSTRUCTION PIPE

D

STAGE

STORE

CONTROL

CONTROL

MICROSEQUENCER AND

CONTROL

CACHE

INSTRUCTION

LOGIC

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EXECUTION UNIT

BUS

ADDRESS

INSTRUCTION

BUS

DATA

DATA

PADS

SIZE

MULTIPLEXER

DATA

SECTION

SECTION

ADDRESS

SECTION

COUNTER

PROGRAM

ADDRESS

ADDRESS

UNIT

ACCESS

CONTROL

MULTIPLEXER

MISALIGNMENT

BUS

BUS CONTROLLER

DATA

CACHE

BUS

DATA

ADDRESS

BUFFER

PREFETCH PENDING

MICROBUS

CONTROLLER

SIGNALS

BUS CONTROL

Figure 2. Block Diagram

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PADS

ADDRESS

BUS

ADDRESS

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The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.

PROGRAMMING MODEL

As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general­purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, th e

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address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.

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31 1516 0

31 1516 0

31 1516 0

31 0

78

D0
D1

D2
D3
D4

D5
D6
D7

A0
A1

A2
A3

A4
A5
A6

A7

(USP)

PC

DATA
REGISTERS

ADDRESS
REGISTERS

USER STACK
POINTER

PROGRAM
COUNTER

15

Figure 3. User Programming Model

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8

7

0

0

CCR

CONDITION CODE
REGISTER

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31 1516 0

31 1516 0

31 0

31 0

31 0

31 0

31 0

31 0

15

7815 0

(CCR)

2

0

A7'
(ISP)

A7"
(MSP)

SR

VBR

SFC
DFC

CACR

CAAR

AC0

AC1

ACUSR

INTERRUPT
STACK POINTER

MASTER
STACK POINTER

STATUS
REGISTER

VECTOR
BASE REGISTER

ALTERNATE FUNCTION
CODE REGISTERS

CACHE CONTROL
REGISTER

CACHE ADDRESS
REGISTER

ACCESS CONTROL
REGISTER 0

ACCESS CONTROL
REGISTER 1

ACU STATUS
REGISTER

Figure 4. Supervisor Programming Model Supplement

The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following
condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits
indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt
state (M).

TRACE ENABLE

SYSTEM BYTE

14

15 13 10 8 4 0

T

T

S

0

1

III XNZVC

0

M

2

INTERRUPT

PRIORITY MASK

1

000

0

USER BYTE

11211 9 765 32

SUPERVISOR/USER STATE

MASTER/INTERRUPT STATE

CONDITION

CODES

EXTEND

NEGATIVE

ZERO

OVERFLOW

CARRY

Figure 5. Status Register

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All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the
MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The
MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow
instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are
important for software program development and debug.

The vector base register (VBR) is used to determine the run-time location of the exception vector table in
memory; thus, each separate vector table for each process or task can properly manage exceptions
independent of each other.

The M68000 Family processors distinguish address spaces as supervisor/user, program/data, and CPU
space. These five combinations are specified by the function code pins (FC0/FC1/FC2) during bus
cycles, indicating the particular address space. Using the function codes, the memory subsystem
(hardware) can distinguish between supervisor accesses and user accesses as well as program accesses,
data accesses, and CPU space accesses. To support the full privileges of the supervisor, the alternate
function code registers allow the supervisor to specify the function code for an access by appropriately

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preloading the SFC/DFC registers.
The cache registers allow supervisor software manipulation of the on-chip instruction and data caches.

Control and status accesses to the caches are provided by the cache control register (CACR); the cache
address register (CAAR) specifies the address for those cache control functions that require an address.

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The access control registers are accessible by the supervisor only. The access control registers are used
to define two memory spaces with caching restrictions. The ACU status register (ACUSR) is used to show
the result of PTEST operations on the ACU.

DATA TYPES AND ADDRESSING MODES

Seven basic data types are supported by the MC68EC030:

• Bits

• Bit Fields (String of consecutive bits, 1–32 bits long)

• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)

• Byte Integers (8 bits)

• Word Integers (16 bits)

• Long-Word Integers (32 bits)

• Quad-Word Integers (64 bits)

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In addition, operations on other data types, such as memory addresses, status word data, etc., are
provided in the instruction set. The coprocessor mechanism allows direct support of floating-point data
types with the MC68881/MC68882 floating-point coprocessors as well as specialized user-defined data
types and functions. The 18 addressing modes, listed in Table 1, include nine basic types:

• Register Direct

• Register Indirect

• Register Indirect with Index

• Memory Indirect

• Program Counter Indirect with Displacement

• Program Counter Indirect with Index

• Program Counter Memory Indirect

• Absolute

• Immediate

The register indirect addressing modes support postincrement, predecrement, offset, and indexing.
These capabilities are particularly useful for handling advanced data structures common to sophisticated
applications and high-level languages. The program counter relative mode also has index and offset

I

capabilities; this addressing mode is generally required to support position- independent software. In
addition to these addressing modes, the MC68EC030 provides data operand sizing and scaling; these
features provide performance enhancements to the programmer.

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Table 1. MC68EC030 Addressing Modes

Addressing Modes Syntax

Register Direct Addressing

Data Register Direct
Address Register Direct

Register Indirect

Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement

Register Indirect with Index

Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)

Memory Indirect

Memory Indirect Postindexed
Memory Indirect Preindexed

Program Counter Indirect with Displacement (d16,PC)
Program Counter Indirect with Index

PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)

Program Counter Memory Indirect

PC Memory Indirect Postindexed
PC Memory Indirect Preindexed

Absolute Data Addressing

Absolute Short
Absolute Long

Immediate #<data>

NOTES:

Dn = Data Register, D0–D7
An = Address Register, A0–A7
d8, d16= A twos-complement or sign-extended displacement; added as part of

the effective address calculation; size is 8 (d8) or 16 (d16) bits;

Xn = Address or data register used as an index register; form is

bd = A twos-complement base displacement; when present, size can be
od = Outer displacement added as part of effective address calculation

PC = Program Counter
<data> = Immediate value of 8, 16, or 32 bits
( ) = Effective Address
[ ] = Used as indirect address to long-word address.

when omitted, assemblers use a value of zero.

Xn.SIZE*SCALE, where SIZE is .W or .L (indicates index register
size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by
SCALE); use of SIZE and/or SCALE is optional.

16 or 32 bits.

after any memory indirection; use is optional with a size of 16 or 32

bits.

Dn
An

(An)
(An);pl

-(An)
(d16,An)

(d8,An,Xn)
(bd,An,Xn)

([bd,An],Xn,od)
([bd,An,Xn],od)

(d8,PC,Xn)
(bd,PC,Xn)

([bd,PC],Xn,od)
([bd,PC,Xn],od)

xxx.W
xxx.L

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INSTRUCTION SET OVERVIEW

The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on
bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The
MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it
supports all instructions of previous family members.

Table 2. Instruction Set

Mnemonic Description Mnemonic Description

ABCD Add Decimal with Extend MOVE Move
AD D Add MOVEA Move Address
ADDA Add Address MOVE CCR Move Condition Code Register
ADDI Add Immediate MOVE SR Move Status Register
ADDQ Add Quick MOVE USP Move User Stack Pointer
ADDX Add with Extend MOVEC Move Control Register
AND Logical AND MOVEM Move Multiple Registers
ANDI Logical AND Immediate MOVEP Move Peripheral
ASL,ASR Arithmetic Shift Left and Right MOVEQ Move Quick

Bcc Branch Conditionally MOVES Move Alternate Address Space
BCHG Test Bit and Change MULS Signed Multiply
BCLR Test Bit and Clear MULU Unsigned Multiply

BFCHG Test Bit Field and Change NBCD Negate Decimal with Extend
BFCLR Test Bit Field and Clear NEG Negate
BFEXTS Signed Bit Field Extract NEGX Negate with Extend
BEFXTU Unsigned Bit Field Extract NOP No Operation
BFFFO Bit Field Find First One NOT Logical Complement

BFINS Bit Field Insert OR Logical Inclusive OR
BFSET Test Bit Field and Set ORI Logical Inclusive OR Immediate

BFTST Test Bit Field PACK Pack BCD
BKPT Breakpoint PEA Push Effective Address
BRA Branch PFLUSH No Effect
BSET Test Bit and Set PLOAD No Effect
BSR Branch to Subroutine PMOVE Move to/from ACx Registers
BTST Test Bit PTEST Test Address in ACx Registers

CAS Compare and Swap Operands RESET Reset External Devices
CAS2 Compare and Swap Dual Operands ROL, ROR Rotate Left and Right
CHK Check Register Against Bound ROXL, ROXR Rotate with Extend Left and Right
CHK2 Check Register Against Upper and Lower RTD Return and Deallocate

Bounds RTE Return from Exception
CLR Clear R TR Return and Restore Codes
CMP Compare RTS Return from Subroutine

CMPA Compare Address SBCD Subtract Decimal with Extend
CMPI Compare Immediate Scc Set Conditionally
CMPM Compare Memory to Memory STOP Stop
CMP2 Compare Register Against Upper and SUB Subtract

Lower Bounds SUBA Subtract Address

DBcc Test Condition, Decrement and Branch SUBI Subtract Immediate
DIVS,DIVSL Signed Divide SUBQ Subtract Quick
DIVU, DIVUL Unsigned Divide SUBX Subtract with Extend

EOR Logical Exclusive OR SWAP Swap Register Words
EORI Logical Exclusive OR Immediate TAS Test Operand and Set

EXG Exchange Registers TRAP Trap
EXT, EXTB Sign Extend TRAPcc Trap Conditionally

ILLEGAL Take Illegal Instruction Trap TRAPV Trap on Overflow
JMP Jump TST Test Operand
JSR Jump to Subroutine UNLK Unlink
LEA Load Effective Address UNPK Unpack BCD
LINK Link and Allocate

LSL, LSR Logical Shift Left and Right

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cpBCC Branch Conditionally cpRESTORE Restore Internal State of Coprocessor
cpDBcc Test Coprocessor Condition, cpSAVE Save Internal State of Coprocessor

Decrement and Branch cpScc Set Conditionally
cpGEN Coprocessor General Instruction cpTRAPcc Trap Conditionally

Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds
checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)
offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030
can be used on the MC68040 for even more performance. The memory management unit (MMU)
instructions of the MC68030, and MC68040 are not supported by the MC68EC030.

Coprocessor Instructions

INSTRUCTION AND DATA CACHES

Studies have shown that typical programs spend most of their execution time in a few main routines or
tight loops. This phenomenon, known as locality of reference, has an impact on program performance.

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The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can b e
used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to
provide the system with two on-chip caches, one for instructions and one for data.

MC68EC030 CACHE GOALS

Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030
embedded controller caches. The first design goal was t o reduce the external bus activity of the CPU
even more than was accomplished with the MC68020. The second design goal was to increase effective
CPU throughput as larger memory sizes or slower memories increased average access time. By placing a
high-speed cache between the controller and the rest of the memory system, the effective memory
access time becomes:

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where t
the rest of the system, and Rh is the hit ratio or the percentage of time that the data is found in the cache.
Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial
CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower
and less expensive memories can be used for the same controller performance.

The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are
accessed in less time than is required for external accesses, providing improvement in the access time for
items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be
found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time
required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time
for items found in the caches even further. Third, the autonomous nature of the caches allows instruction
stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.
The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently
so that several internal instructions (those that do not require any external accesses) can execute while
the controller is performing an external access for a previous instruction.

is the effective system access time, t

acc

t

acc

=Rh*t

+ (1-Rh)*t

cache

is the cache access time, t

cache

ext

is the access time o f

ext

INSTRUCTION CACHE

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The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting
of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with
address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed o f
the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry),
and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the
MC68EC030 whenever a cache miss occurs; using the burst transfer capability, up to four long words can
be filled in one burst operation. The caches cannot be manipulated directly by the programmer except b y
the use of the CACR, which provides cache clearing and cache entry clearing facilities. The caches can
also be enabled/disabled by this register. Finally, the system hardware can disable the on-chip caches at
any time by asserting the CDIS signal.

LONG WORD

SELECT

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F F F

A
3

CCC
210

1

CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1

AAAAAAAAAAAAAAAAAAAAAAAA

22211111111110000000000

2

3

201 98765432109876543210

1 OF 16
SELECT

TAG REPLACE

COMPARATOR

TAG

TAG

V

LINE HIT

V V V

VALID

INDEX

ENTRY HIT

ACCESS ADDRESS

DATA FROM INSTRUCTION
CACHE DATA BUS

DATA TO INSTRUCTION
CACHE HOLDING REGISTER

CACHE CONTROL LOGIC

Figure 6. On-Chip Instruction Cache Organization

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DATA CACHE

The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, t he
tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly
specifying the address space associated with each line. The data cache employs a write-through policy
with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data
cache and the external device are updated with the new data. If a write cycle generates a cache miss, th e
external device is updated, and a new data cache entry can b e replaced or allocated for that address,
depending on the state of the write-allocate (WA) bit in the CACR.

LONG-WORD

SELECT

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F F F

A
3

CCC
210

1

CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1

AAAAAAAAAAAAAAAAAAAAAAAA

22211111111110000000000

2
3

201 98765432109876543210

1 OF 16

SELECT

TAG REPLACE

COMPARATOR

TAG

TAG

V

LINE HIT

V V V

VALID

INDEX

ENTRY HIT

ACCESS ADDRESS

DATA FROM DATA
CACHE DATA BUS

DATA TO EXECUTION
UNIT

CACHE CONTROL LOGIC

Figure 7. On-Chip Data Cache Organization

OPERAND TRANSFER MECHANISM

The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the
chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,
can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is
determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size
acknowledge (DSACKx) signals. Synchronous bus cycles, compatible with the synchronous bus on t he
MC68030, are terminated with the synchronous termination (STERM) signal and always transfer 32-bits
of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,

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thereby increasing possible performance. Burst mode transfers can be used to fill lines of the instruction
and data caches when the MC68EC030 asserts cache burst request (CBREQ). After completing the first
cycle with STERM, subsequent cycles may accept data on every clock cycle where STERM is asserted
until the burst is completed. Use of this mode can further increase the available bus bandwidth in systems
that use DRAMs with page, nibble, or static-column mode operation.

ASYNCHRONOUS TRANSFERS

Though the MC68EC030 has a full 32-bit data bus, it offers the ability to automatically and dynamically
downsize its bus to 8 or 16 bits if peripheral devices are unable to accommodate the entire 32 bits. This
feature allows the programmer to write code that is not bus-width specific. For example, long-word (32 bit)
accesses to peripherals may be used in the code; yet, the MC68EC030 will transfer only the amount o f
data that the peripheral can manage. This feature allows the peripheral to define its port size as 8, 16, or
32 bits wide, and the MC68EC030 will dynamically size the data transfer accordingly, using multiple bu s
cycles when necessary. Hence, programmers are not required to program for each device port size or
know the specific port size before coding; hardware designers have the flexibility to choose hardware
implementations regardless of software implementations.

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The dynamic bus sizing mechanism is invoked by DSACKx and occurs on a cycle-by-cycle basis. For
example, if the controller is executing an instruction that requires reading a long-word operand, it will
attempt to read 32 bits during the first bus cycle to a long-word address boundary. If the port responds
that it is 32 bits wide, the MC68EC030 latches all 32 bits of data and continues. If the port responds that it
is 16 bits wide, the MC68EC030 latches the 16 valid bits of data and continues. An 8-bit port is handled
similarly but has four bus read cycles. Each port is fixed in the assignment to particular sections of the data
bus. However, the MC68EC030 has no restrictions concerning the alignment of operands in memory;
long-word operands need not be aligned to long-word address boundaries. When misaligned data
requires multiple bus cycles, the MC68EC030 automatically runs the minimum number of bus cycles.
Instructions must still be aligned to word boundaries.

The timing of asynchronous bus cycles is also determined by the assertion of DSACKx on a cycle-by­cycle basis. If the DSACKx signals are valid 1.5 clocks after the beginning of the bus cycle (with the
appropriate setup time), the cycle terminates in the minimum amount of time (corresponding to three­clock-cycle total). The cycle can be lengthened by delaying DSACKx (effectively inserting wait states i n
one-clock increments) until the device being accessed is able to terminate the cycle. This flexibility gives
the controller the ability to communicate with devices of varying speeds while operating at the fastest rate
possible for each device.

The asynchronous transfer mechanism allows external errors to abort cycles upon the assertion of b us
error (BERR) or allows individual bus cycles to be retried with the simultaneous assertion of BERR and

HALT.

14 MC68EC030 TECHNICAL DATA MOTOROLA

Freescale Semiconductor, Inc.

SYNCHRONOUS TRANSFERS

Synchronous bus cycles are terminated by asserting STERM, which automatically indicates that the bus
transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can b e
performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup
time. However, the bus cycle may be lengthened by delaying STERM (inserting wait states in one-clock
increments) until the device being accessed is able to terminate the cycle. After the assertion of STERM,
these cycles may be aborted upon the assertion of BERR, or they may b e retried with the simultaneous
assertion of BERR and HALT.

BURST READ CYCLES

The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding t o
the overall system performance. The on-chip caches are organized with a line size of four long words;
there is only one tag for the four long words in a line. Since locality of reference is present to some

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degree in most programs, filling of all four entries when a single entry misses can be advantageous,
especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data
can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be
performed only when the MC68EC030 requests them (with the assertion of CBREQ) and only when th e
first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (CBACK) input
is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original AS, DS,
R/W, address, function code, and size outputs asserted and latches 32 bits from the data bus at the en d
of each subsequent clock cycle that has STERM asserted. This procedure continues until the burst is
complete (the entire block has been transferred), BERR is asserted in lieu of or after STERM, the cache
inhibit in (CIIN) input is asserted, or the CBACK input is negated. The cache preloading allowed by th e
bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal
performance impact.

The types of exceptions and the exception processing sequence are discussed in the following
paragraphs.

TYPES OF EXCEPTIONS

Exceptions can be generated by either internal or external causes. The externally generated exceptions
are interrupts, BERR, and RESET. Interrupts are requests from peripheral devices for controller action;
whereas, BERR and RESET are used for access control and controller restart. The internally generated
exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction
execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is
processed. The other internally generated exceptions are caused by illegal instructions, instruction
fetches from odd addresses, and privilege violations.

EXCEPTIONS

MOTOROLA MC68EC030 TECHNICAL DATA 15

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EXCEPTION PROCESSING SEQUENCE

Exception processing occurs in four steps. During the first step, an internal copy is made of the status
register. After the copy is made, the special controller state bits in the status register are changed. The S­bit is set, putting the controller into the supervisor state. Also, the T1 and T0 bits are negated, allowing
the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the
interrupt priority mask is also updated.

In the second step, the vector number of the exception is determined. For interrupts, the vector number
is obtained by a controller read that is classified as an interrupt acknowledge cycle. For coprocessor­detected exceptions, the vector number is included in the coprocessor exception primitive response.
For all other exceptions, internal logic provides the vector number. This vector number is then used t o
generate the address of the exception vector.

The third step is to save the current controller status. The exception stack frame is created and filled o n
the current supervisor stack. To minimize the amount of machine state that is saved, various stack frame

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sizes are used to contain the controller state, depending on the type of exception and where it occurred
during instruction execution. If the exception is an interrupt and the M-bit is set, the M-bit is then cleared,
and the short four-word exception stack frame that is saved on the master stack is also saved on the
interrupt stack. If the exception is a reset, the M-bit is simply cleared, and the reset vector is accessed.

The MC68EC030 provides the same extensions to the exception stacking process as the MC68020,
MC68030, and MC68040. If the M-bit is set, the master stack pointer (MSP) is used for all task-related
exceptions. When a nontask-related exception occurs (i.e., an interrupt), the M bit is cleared, and the
interrupt stack pointer (ISP) is used. This feature allows all the task's stack area to be carried within a single
controller control block, and new tasks can be initiated by simply reloading the MSP and setting the M-bit.

The fourth and last step of exception processing is the same for all exceptions. The exception vector
offset is determined by multiplying the vector number by four. This offset is then added to the contents of
the vector base register (VBR) to determine the memory address of the exception vector. The new
program counter is fetched from the exception vector. The instruction at the address given in the
exception vector is fetched, and normal instruction decoding and execution is started.

cale Semiconductor,

STATUS and REFILL

The MC68EC030 provides the STATUS and REFILL signals to identify internal microsequencer activity

Frees

associated with the processing of data pipelined in the pipeline. Since bus cycles are independently
controlled and scheduled by the bus controller, information concerning the processing state of the
microsequencer is not available by monitoring bus signals by themselves. The internal activity identified
by the STATUS and REFILL signals include instruction boundaries, some exception conditions, when
the microsequencer has halted, and instruction pipeline refills. STATUS and REFILL track only the
internal microsequencer activity and are not directly related to bus activity.

16 MC68EC030 TECHNICAL DATA MOTOROLA

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ACCESS CONTROL

Two access control registers are provided on the MC68EC030 to control cachability of accesses for tw o
independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is
specified in the corresponding ACx register with a base address, a base mask, function code, function
code mask, and read/write mask. A typical use for an access control register is to designate a block of
memory containing I/O devices as non-cachable.

The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. Th e
interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples o f
these extensions are the addition of specialized data operands for the existing data types or, for the case
of floating point, the inclusion of new data types and operations implemented by the
MC68881/MC68882 floating-point coprocessors.

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Freescale Semiconductor, Inc.

COPROCESSOR INTERFACE

SIGNAL DESCRIPTION

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Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.

FUNCTION

CODES

ADDRESS

BUS

DATA

BUS

TRANSFER

SIZE

ASYNCHRONOUS

BUS CONTROL

CACHE

CONTROL

FC0–FC2

A0–A31

D0–D31

SIZ0
SIZ1

OCS
ECS

R/W

RMC

AS
DS

DBEN
DSACK0
DSACK1

CIIN

CIOUT
CBREQ

CBACK GND (14)

MC68EC030

IPL0
IPL1

IPL2

IPEND

AVEC

BR
BG

BGACK

RESET

HALT
BERR

STERM

REFILL
STATUS

CDIS

CLK

V (10)

CC

INTERRUPT
CONTROL

BUS ARBITRATION
CONTROL

BUS EXCEPTION
CONTROL

SYNCHRONOUS
BUS CONTROL

EMULATOR
SUPPORT

Figure 8. Functional Signal Groups

MOTOROLA MC68EC030 TECHNICAL DATA 17

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Freescale Semiconductor, Inc.

Signal Name Mnemonic Function

Function Codes FC0–FC2 3-bit function code used to identify the address space of each bus

Address Bus A0–A31 32-bit address bus.
Data Bus D0–D31 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus

Size SIZ0–SIZ1 Indicates the number of bytes remaining to be transferred for this

Operand Cycle Start

External Cycle Start
Read/Write
Read-Modify-Write Cycle

Address Strobe
Data Strobe

Data Buffer Enable
Data Transfer and Size

Acknowledge

Synchronous
Termination

Cache Inhibit In

Cache Inhibit Out

Cache Burst Request
Cache Burst

Acknowledge
Interrupt Priority Level

Interrupt Pending
Autovector
Bus Request
Bus Grant
Bus Grant Acknowledge
Reset
Halt
Bus Error
Cache Disable
Pipe Refill
Microsequencer Status

DSACK0,

DSACK1

STERM

CIOUT

CBREQ

CBACK

IPL0–IPL2

IPEND

BGACK

RESET

REFILL

STATUS

Table 3. Signal Index

cycle.

cycle.

cycle. These signals, together with A0 and A1, define the active
sections of the data bus.

OCS Identical operation to that of ECS except that OCS is asserted only

ECS

R/

W

RMC

AS
DS

DBEN

CIIN

AVEC

BR
BG

HALT

BERR

CDIS

during the first bus cycle of an operand transfer
Provides an indication that a bus cycle is beginning.

Defines the bus transfer as a controller read or write.
Provides an indicator that the current bus cycle is part of an indivisible

read-modify-write operation.
Indicates that a valid address is on the bus.

Indicates that valid data is to be placed on the data bus by an external
device or has been replaced by the MC68EC030.

Provides an enable signal for external data buffers.
Bus response signals that indicate the requested data transfer

operation has completed. In addition, these two lines indicate the size
of the external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.

Bus response signal that indicates a port size of 32 bits and that data
may be latched on the next falling clock edge.

Prevents data from being loaded into the MC68EC030 instruction and
data caches.

Reflects the CI bit in ACx registers; indicates that external caches
should ignore these accesses.

Indicates a burst request for the instruction or data cache.
Indicates that the accessed device can operate in burst mode.

Provides an encoded interrupt level to the controller.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge cycle.
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus mastership.
Indicates that an external device has assumed bus mastership.
System reset.
Indicates that the controller should suspended bus activity.
Indicates that an erroneous bus operation is being attempted.
Dynamically disables the on-chip cache to assist emulator support.
Indicates when the MC68EC030 is beginning to fill pipeline.
Indicates the state of the microsequencer.

18 MC68EC030 TECHNICAL DATA MOTOROLA

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Clock CLK Clock input to the controller.

Table 3. Signal Index – Continued

Signal Name Mnemonic Function

Power Supply V
Ground GND Ground connection.

No Connect NC Do not connect.

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CC

Power supply.

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MOTOROLA MC68EC030 TECHNICAL DATA 19

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ELECTRICAL SPECIFICATIONS

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage

Input Voltage V
Operating Temperature Range

Minimum Ambient Temperature
Maximum Ambient Temperature

Storage Temperature Range T

THERMAL CHARACTERISTICS-- PGA PACKAGE

V

CC -0.3 to +7.0 V

-0.5 to +7.0 V

0

70

-55 to 150 °C

T
T

stg

in

A
A

°C

The device contains circuitry to
protect the inputs against damage
due to high static voltages or
electric fields; however, normal
precautions should be taken to
avoid application of voltages higher
than maximum-rated voltages to
these high-impedance circuits.
Tying unused inputs to the
appropriate logic voltage level (e.g.,
either GND or VCC) enhances

reliability of operation.

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Characteristic Symbol Value Rating

Thermal Resistance - Plastic

Junction to Ambient
Junction to case

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in oC can be obtained from:

where:

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T

θ

P
P
P

For most applications, P

= Ambient Temperature, oC

A
J

= Package Thermal Resistance, Junction-to-Ambient, oC/W

A

= P

D

= I

INT

= Power Dissipation on Input and Output Pins — User Determined

I/O

+ P

INT

CC

I/O

X

VCC, Watts — Chip Internal Power

I/O<PINT

o

C/W

θ

JA

θ

JC

and can be neglected.

32

TBD

TJ=TA+(PD •

θ

JA)

(1)

The following is an approximate relationship between PD and TJ (if P

PD=K ÷ (TJ+273oC) (2)

Solving Equations (1) and (2) for K gives:

K=PD • (TA + 273oC) +

where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring PD (at thermal equilibrium) for a known TA. Using this value of K, the values of PD and TJ can
be obtained by solving equations (1) and (2) iteratively for any value of TA.

20 MC68EC030 TECHNICAL DATA MOTOROLA

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is neglected):

I/O

JA•PD

2

θ

(3)

Freescale Semiconductor, Inc.

The total thermal resistance of a package (
representing the barrier to heat flow from the semiconductor junction to the package (case) surface (
and from the case to the outside ambient air (

is device related and cannot be influenced by the user. However,

θ

JC

be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal
convection. Thus, good thermal management on the part of the user can significantly reduce

approximately equals;

θ

JA

semiconductor junction temperature.
Values for thermal resistance presented in this document, unless estimated, were derived using the

procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for
MC68XX Microcomponent Devices,” and are provided for design purposes only. Thermal measurements
are complex and dependent on procedure and setup. User derived values for thermal resistance may

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differ.

. Substitution of

θ

JC

) can be separated into two components,

θ

JA

). These terms are related by the equation:

θ

CA

=

θ

JA

+

θ

θ

JC

θ

JC

CA

for

AC ELECTRICAL SPECIFICATION DEFINITIONS

The AC specifications presented consist of output delays, input setup and hold times, and signal skew
times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more
other signals.

and

θ

JC

is user dependent and can

θ

CA

θ

CA

in equation (1) results in a lower

θ

JA

θ

CA

θ

JC

(4)

so that

,
)

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The measurement of the AC specifications is defined by the waveforms shown in Figure 9. To test th e
parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in Figure 9.
Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in
Figure 9. Inputs are specified with minimum setup and hold times, and are measured as shown. Finally,
the measurement for signal-to-signal specifications is also shown.

Note that the testing levels used to verify conformance to the AC specifications does not affect the
guaranteed DC operation of the device as specified in the DC electrical specifications.

MOTOROLA MC68EC030 TECHNICAL DATA 21

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DRIVE

TO 2.4 V

2.0 V

0.8 V

2.0 V

0.8 V

A

B

2.0 V

0.8 V

2.0 V

0.8 V

VALID

OUTPUT n + 1

C

VALID

INPUT

VALID

OUTPUT n

D

2.0 V

0.8 V

C

2.0 V

0.8 V

CLK

DRIVE TO

0.5 V

OUTPUTS(1) CLK

OUTPUTS(2) CLK

I

INPUTS(3) CLK

INPUTS(4) CLK

VALID

OUTPUT n

DRIVE TO

2.4 V

DRIVE TO

0.5 V

2.0 V

0.8 V

VALID
INPUT

2.0 V

B

0.8 V

D

2.0 V

0.8 V

A

2.0 V

0.8 V

VALID
OUTPUT n+1

DRIVE
TO 2.4 V

DRIVE
TO 0.5 V

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2.0 V

ALL SIGNALS(5)

0.8 V

E

F

2.0 V

0.8 V

NOTES:

1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.

2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.

3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.

4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.

5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.

LEGEND:

A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).

F. Signal valid to signal invalid specification (maximum or minimum).

Figure 9. Drive Levels and Test Points for AC Specifications

22 MC68EC030 TECHNICAL DATA MOTOROLA

Freescale Semiconductor, Inc.

DC ELECTRICAL SPECIFICATIONS

(VCC=5.0 Vdc ± 5%; GND=0Vdc; temperature in defined ranges)

Characteristics Symbol Min M a x Unit

Input High Voltage V
Input Low Voltage V

Input Leakage Current

GND≤Vin,≤V

Hi-Z (Off-State) Leakage

Current
@ 2.4 V/0.5 V

Output High Voltage

I

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OH = 400 µA

Output Low Voltage

I

OL = 3.2 mA

I

OL = 5.3 mA

I

OL = 2.0 mA

I

OL = 10.7 mA

Power Dissipation (TA=0C) P
Capacitance (see Note)

V

= 0 V, TA=25C, f=1 MHz

in

Load Capacitance

NOTE: Capacitance is periodically sampled rather than 100% tested.

CC

BERR,BR, BGACK, CLK,.IPL0–IPL2,

CDIS, DSACK0, DSACK1

HALT, RESET

A0-A31,

A0–A31, FC0–FC2, SIZ0–SIZ1,

AS, DBEN, DS, D0-D31, FC0-FC2,

R/

W, RMC, SIZ0-SIZ1

A0–A31,

CBREQ, AS, DS, R/W, RMC, DBEN,

STATUS, REFILL, CIOUT, ECS, OCS

AS, BG, D0–D31, DBEN, DS,

ECS, R/W, IPEND

OCS, RMC

CBREQ, CIOUT, STATUS, REFILL

, SIZ0–SIZ1, FC0–FC2

BG, D0–D31

HALT,RESET

ECS, OCS

CIOUT, STATUS, REFILL

All Other

AVEC,

IPEND

I

V

V

IH

IL

I

in

TSI

OH

OL

D

C

in

C

L

2.0 V

GND

-0.5

-2.5

-20

-20 20 µA

2.4 — V

—
—
—
—

— 2.6 W
—

—50

cale Semiconductor,

AC ELECTRICAL SPECIFICATIONS — CLOCK INPUT (see Figure 10)

Frees

Num. Characteristic 25MHz 40 MHz

Min Max Min Max

Frequency of Operation 12.5 25 25 40 MHz

1 Cycle Time Clock 40 80 25 40 ns
2,3 Clock Pulse Width Measured from 1.5 V to 1.5 V 19 61 11.5 29 n s
4,5 Clock Rise and Fall Times — 4 — 2 ns

CC

0.8 V

2.5
20

0.5

0.5

0.5

0.5

20 pF

70

130

Unit

V

µA

V

pF

MOTOROLA MC68EC030 TECHNICAL DATA 23

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0.8 V

2.0 V

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1

2

3

4

NOTE:

Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.

Figure 10. Clock Input Timing Diagram

5

AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES

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(VCC=5.0Vdc ± 5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)

Num. Characterstics 25MHz 40 MHz Unit

Min Max Min Max

Clock High to Function Code, Size,

6

6A Clock High to ECS, OCS Asserted 0 15 0 10 ns
6B

7

8

9 Clock Low to AS, DS Asserted, CBREQ Valid 3 18 2 10 ns

1

9A

14

9B

10 ECS Width Asserted 10 — 5 — ns

10A OCS Width Asserted 10 — 5 — ns

7

10B

11

12 Clock Low to AS, DS, CBREQ Negated 0 18 0 10 ns

12A Clock Low to ECS/OCS Negated 0 18 0 12 ns

13

14 AS (and DS Read) Width Asserted (Asynchronous Cycle) 70 — 30 — ns

11

14A

14B AS (and DS, Read) Width Asserted (Synchronous Cycle) 30 — 18 — ns

15 AS, DS Width Negated 30 — 18 — ns

Address Valid

Function Code, Size,

Negating Edge of

Clock High to Function Code Size,
High Impedance

Clock High to Function Code Size,

Invalid

AS to DS Assertion Skew (Read) -10 10 -6 6 ns
AS Asserted to DS Asserted (Write) 27 — 16 — ns

ECS, OCS Width Negated 5 — 5 — ns

Function Code, Size,
(and

DS Asserted, Read)

AS, DS Negated to Function Code, Size, RMC CIOUT, Address

Invalid

DS Width Asserted (Write) 30 — 18 — ns

RMC, IPEND, CIOUT, Address Valid to

ECS

RMC, CIOUT, Address Valid to AS Asserted

RMC, IPEND,CIOUT,

RMC, CIOUT, Address Data

RMC, IPEND, CIOUT, Address

020014ns

3—3—ns

040025ns

0—0—ns

7—5—ns

7—3—ns

24 MC68EC030 TECHNICAL DATA MOTOROLA

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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES

(Continued)

Num. Characterstics 25MHz 40 MHz Unit

Min Max Min Max

8

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15A

25

25A

26

27A Late BERR/HALT Asserted to Clock Low (Setup) 5 — 3 — ns

28

28A

29

29A

30

30A

31

31A

37A

39A BG Width Asserted 60 — 30 — ns

DS Negated to AS Asserted 25 — 16 — ns

16 Clock High to AS, DS, R/W, DBEN, CBREQ High Impedance — 40 — 25 ns
17 AS, DS Negated to R/W Invalid 7 — 3 — ns
18 Clock High to R/W High 0 20 0 14 ns
20 Clock High to R/W Low 0 20 0 14 ns
21 R/W High to AS Asserted 7 — 5 — ns
22 R/W Low to DS Asserted (Write) 47 — 24 — ns
23 Clock High to Data-Out Valid — 20 — 14 ns
24 Data-Out Valid to Negating Edge of AS 5—3—ns

11

AS, DS Negated to Data-Out Invalid 7 — 3 — ns

9,11

DS Negated to DBEN Negated (Write) 7 — 3 — ns

11

Data-Out Valid to DS Asserted (Write) 7 — 3 — ns

27 Data-In Valid to Clock Low (Setup) 2 — 1 — ns

AS, DS Negated to DSACKx, BERR, HALT, AVEC Negated

12

(Asynchronous Hold)
Clock Low to DSACKx, BERR, HALT, AVEC Negated

12

(Synchronous Hold)

12

AS, DS Negated to Data-In Invalid (Asynchronous Hold) 0 — 0 — ns

12

AS, DS Negated to Data-In High Impedance — 40 — 25 ns

12

Clock Low to Data-In Invalid (Synchronous Hold) 8 — 6 — ns

12

Clock Low to Data-In High Impedance (Read followed by Write) — 60 — 30 ns

2

DSACKx Asserted to Data-In Valid (Asynchronous Data Setup) — 28 — 14 ns

3

DSACKx Asserted to DSACKx Valid (Skew) — 7 — 3 ns

32 RESET Input Transition Time — 1.5 — 1.5 Clks
33 Clock Low to BG Asserted 0 20 0 14 ns
34 Clock Low to BG Negated 0 20 0 14 Clks
35 BR Asserted to BG Asserted (RMC Not Asserted) 1.5 3.5 1.5 3.5 Clks
37 BGACK Asserted to BG Negated 1.5 3.5 1.5 3.5 Clks

6

BGACK Asserted to BR Negated 0 1.5 0 1.5 ns

39 BG Width Negated 60 — 30 — ns

40 Clock High to DBEN Asserted (Read) 0 20 0 16 ns
41 Clock Low to DBEN Negated (Read) 0 20 0 16 ns
42 Clock Low to DBEN Asserted (Write) 0 20 0 16 ns
43 Clock High to DBEN Negated (Write) 0 20 0 16 ns

040020ns

870640

ns

MOTOROLA MC68EC030 TECHNICAL DATA 25

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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES

(Concluded)

Num. Characterstics 25 MHz 40 MHz Unit

Min Max Min Max

44 R/W Low to DBEN Asserted (Write) 7 — 5 — ns

45

DBEN Width Asserted Synchronous Read

9

45A

46 R/W Width Asserted (Asynchronous Write or Read) 100 — 50 — ns
46A R/W Width Asserted (Synchronous Write or Read) 60 — 30 — ns
47A Asynchronous Input Setup Time to Clock Low 2 — 2 — ns
47B Asynchronous Input Hold Time from Clock Low 8 — 6 — ns

4

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48

58
59
60
61

DSACKx Asserted to BERR, HALT Asserted — 25 — 14 ns

53 Data-Out Hold from Clock High 3 — 2 — ns

55 R/W Asserted to Data Bus Impedance Change 20 — 11 — ns

56 RESET Pulse Width (Reset Instruction) 512 — 512 — Clks

57 BERR Negated to HALT Negated (Rerun) 0 — 0 — ns

10

BGACK Negated to Bus Driven 1 — 1 — Clks

10

BG Negated to Bus Driven 1 — 1 — Clks

13

Synchronous Input Valid to Clock High (Setup Time) 2 — 2 — ns

13

Clock High to Synchronous Input Invalid (Hold Time) 8 — 6 — ns
62 Clock Low to STATUS, REFILL Asserted 0 20 0 15 ns
63 Clock Low to STATUS, REFILL Negated 0 20 0 15 ns

Asynchronous Write4080——

5

Synchronous Write

40——

DBEN Width Asserted Asynchronous Read

5

2245—

5

22——

cale Semiconductor,

—

ns

ns

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26 MC68EC030 TECHNICAL DATA MOTOROLA

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NOTES:

1. This number can be reduced to 5 ns if strobes have equal loads.

2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx low to data setup time
(#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy th e
data-in clock low setup time (#27) for the following clock cycle and BERR must only satisfy the late

BERR low to clock low setup time (#27A) for the following clock cycle.

3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or

DSACK1 to DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1.

4. This specification applies to the first (DSACK0 or DSACK1) DSACKx signal asserted. In the absence o f

DSACKx, BERR is an asynchronous input using the asynchronous input setup time (#47A).

5. DBEN may stay asserted on consecutive write cycles.

6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded,

BG may be reasserted.

7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit
followed immediately by another cache hit, a cache miss, or an operand cycle.

8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time
for DS negated to AS asserted (specification #13A in the

nc...

I

Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that
the MC68EC030 does not meet the MC68881/MC68882 requirements.

9. This specification allows a system designer to guarantee data hold times on the output side of data
buffers that have output enable signals generated with DBEN. The timing on DBEN precludes its u s e

for synchronous READ cycles with no wait states.

10. These specifications allow system designers to guarantee that an alternate bus master has stopped
driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence.

11. DS will not be asserted for synchronous write cycles with no wait states.

12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock
(synchronous). The designer is free to use either time.

13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for
the clock while AS is asserted. These values are specified relative to the high level of the rising clock

edge. The values originally published were specified relative to the low level of the rising clock edge.

14. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS
(allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (spec 8B of the

MC68881/MC68882 User's Manual)

cale Semiconductor,

.

MC68881/MC68882 User's Manual

all

rising edges of

).

Frees

MOTOROLA MC68EC030 TECHNICAL DATA 27

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A31-A0

FC2-FC0

SIZ1-SIZ0

RMC

CLK

ECS

S0 S1 S2 S3 S4 S5

6

6A

12A

10A

6A

10

8

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cale Semiconductor,

Frees

OCS

AS

DS

R/W

DBEN

DSACK0

DSACK1

D31-D0

BERR

HALT

ASYNCHRONOUS

ALL

INPUTS

11

9

11

18

9

21

40

31A

31

47A

14

9A

14

46

41

45

27

48

60

27A

13

12

20

17

28

29

29A

CIIN

61

CBREQ

47B

12

Figure 11. Asynchronous Read Cycle Timing Diagram

28 MC68EC030 TECHNICAL DATA MOTOROLA

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CLK

S0 S1 S2 S3 S4 S5

S0

A31-A0, FC2-FC0

SIZ1-SIZ0

RMC

ECS

OCS

AS

DS

R/W

6A

20

6

12A

22

9

42

46

8

15

12

17

25A

DBEN

DSACK0

DSACK1

D31-D0

BERR

HALT

CIOUT

44

23

31A

55

48

45

28

26

6

27A

43

53

25

8

MOTOROLA MC68EC030 TECHNICAL DATA 29

Freescale Semiconductor, Inc.

nc...

I

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Frees

CLK

A31-A0, FC2-FC0

SIZ1-SIZ0

RMC

ECS

OCS

AS

DS

R/W

DBEN

CIOUT

CBREQ

DSACK0/DSACK1

STERM

S0 S1 S2 S3 S0 S1

6

6A

18

60

12A

14B

9

S2

8

46A

40

41

45A

12

61

CIIN

30A

CBACK

30

D31-D0

27

Figure 13. Synchronous Read Cycle Timing Diagram

30 MC68EC030 TECHNICAL DATA MOTOROLA

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S0 S1 S2 S3 S0 S1

CLK

A31-A0, FC2-FC0

SIZ1-SIZ0

6

RMC

12A

ECS

6A

OCS

12

nc...

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AS

DS

20

9

14B

46A

S2

8

18

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Frees

R/W

DBEN

D31-D0

DSACK0/DSACK1

STERM

BERR

HALT

CBREQ

42

45A

23

24

60

61

28A

28A

27A

43

53

Figure 14. Synchronous Write Cycle Timing Diagram

MOTOROLA MC68EC030 TECHNICAL DATA 31

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CLK

A31-A0

D31-D0

FC2-FC0

SIZ1-SIZ0

Freescale Semiconductor, Inc.

S0 S1 S2 S3 S4 S5

nc...

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ECS

OCS

AS

DS

R/W

DBEN

DSACK0

DSACK1

BR

7

16

33

37A

35

34

BG

39

37

BGACK

39A

NOTE:

32 MC68EC030 TECHNICAL DATA MOTOROLA

Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.

Figure 15. Bus Arbitration Timing Diagram

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CLK

Freescale Semiconductor, Inc.

6

IPEND

47A

CDIS

STATUS

62

REFILL

nc...

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Figure 16. Other Signal Timings

cale Semiconductor,

8

63

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MOTOROLA MC68EC030 TECHNICAL DATA 33

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MECHANICAL DATA

PIN ASSIGNMENTS — PIN GRID ARRAY (RC SUFFIX)

N

D31 D28 D26 D25 D23 D21 D19 D16 D15 D13 D11

M

DBEN ECS D29 D27 D24 D22 D20 D14 D12 D9 D6 D3

L

CIIN SIZ0 R/W D30 GND V GND GND GND D10 D7 D4 D2

K

CBREQ

DS

SIZ1

VVD5

J

CBACK AS

H

G

F

E

D

C

B

A

HALT V

BERR

STERM

DSACK1

V

DSACK0

CLK

AVEC

FC2 FC0 V V A6

FC1

CIOUT BGACK

BG

RMC

BR

A0

12345678910

CC CC

GND

GND

GND

GND GND

OCS

A31

A29

A30

A28

CC

MC68EC030

CC

A27

A25

A26

A24

NOTE

The MC68030 has four additional guide pins not present on the
MC68EC030. Therefore, an MC68EC030 fits in a socket designed
for the MC68030, but the MC68030 does not necessary fit in a
socket intended for the MC68EC030.

The Vcc and GND pins are separated into three groups to provide individual power
supply connections for the address bus buffers, data bus buffers, and all other output
buffers and internal logic

Pin Group VCC GND

Address Bus C6, D10 C5, C7, C9, E11
Data Bus L6, K10 J11, L9, L7, L5
ECS, SIZx, DS, AS, DBEN, CBREQ, R/W K 4 J 3
FC0–FC2, RMS, OCS, CIOUT, BG D 4 E 3
Internal Logic, RESET, STATUS, REFILL,
Misc

D18 D8

D17

D1 D0

STATUS REFILL

GND

CDIS IPL0

V

CCCC

BOTTOM

VIEW

GNDVGNDA1

A22

A23

A18 GND

A20

A16

A21

A19

CCCC

A11

A14

A17

IPL2

GND

RESET

V

CCCC

NC IPEND

A3 A2

A9 A5 A4

A12 A8 A7

A15 A13 A10

11 12 13

IPL1

NC

H3, F2, F11, H11 L8, G3, F3, G11

34 MC68EC030 TECHNICAL DATA MOTOROLA

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PACKAGE DIMENSIONS

MC68EC030

RP SUFFIX PACKAGE

CASE 789F-01

A

nc...

I

B

MILLIMETERS

MIN MAX MIN MAX

DIM

A

34.04 35.05

B
C
D
G
K
L
M
V

2.92

0.44

4.32 4.95

1.02 1.52

2.79

3.18

0.55 0.017 0.022

3.81

INCHES

1.340 1.380

1.340 1.38034.04 35.05

0.115 0.135

0.100 BSC2.54 BSC

0.170

0.195

0.040

0.110 0.150

0.060

1.200 BSC30.48 BSC

cale Semiconductor,

K

T

X

V

M

N

M

L
K
J
H

G

F
E
D

C

B
A

L

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

2.

3.

12345678910111213

D 124 PL

0.76 (0.030)

0.76 (0.030)

0.17(0.007)

ANSI Y14.5M, 1982.
CONTROLLING DIMENSION: INCH
DIMENSION D INCLUDES LEAD FINISH.

M
M

M

T

TASB
X

G

S

G

Frees

MOTOROLA MC68EC030 TECHNICAL DATA 35

For More Information On This Product,

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nc...

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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or

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design. Motorola does not assume any liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

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unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution: P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive Blakelands, Milton Keynes, MK14 5BP,
England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial
Estate, Tai Po, N.T., Hong Kong.

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