Freescale Semiconductor, Inc.
M68300 Family
MC68332
User’s Manual
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of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and
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all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including
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© MOTOROLA, INC. 1995
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TABLE OF CONTENTS
Paragraph Title Page
SECTION 1 INTRODUCTION
SECTION 2NOMENCLATURE
2.1 Symbols and Operators ..................................................................................2-1
2.2 CPU32 Registers ............................................................................................2-2
2.3 Pin and Signal Mnemonics .............................................................................2-3
2.4 Register Mnemonics .......................................................................................2-4
2.5 Conventions ...................................................................................................2-5
SECTION 3OVERVIEW
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3.1 MC68332 Features .........................................................................................3-1
3.1.1 System Integration Module (SIM) ...........................................................3-1
3.1.2 Central Processing Unit (CPU) ...............................................................3-1
3.1.3 Time Processor Unit (TPU) ....................................................................3-1
3.1.4 Queued Serial Module (QSM) ................................................................3-2
3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM) .............3-2
3.2 System Block Diagram and Pin Assignment Diagrams ..................................3-2
3.3 Pin Descriptions .............................................................................................3-5
3.4 Signal Descriptions .........................................................................................3-7
3.5 Intermodule Bus .............................................................................................3-9
3.6 System Memory Map .....................................................................................3-9
3.6.1 Internal Register Map ...........................................................................3-10
3.6.2 Address Space Maps ...........................................................................3-10
3.7 System Reset ...............................................................................................3-15
3.7.1 SIM Reset Mode Selection ...................................................................3-15
3.7.2 MCU Module Pin Function During Reset .............................................3-16
SECTION 4 SYSTEM INTEGRATION MODULE
4.1 General ...........................................................................................................4-1
4.2 System Configuration and Protection .............................................................4-2
4.2.1 Module Mapping .....................................................................................4-3
4.2.2 Interrupt Arbitration .................................................................................4-3
4.2.3 Show Internal Cycles ..............................................................................4-4
4.2.4 Factory Test Mode .................................................................................4-4
4.2.5 Register Access .....................................................................................4-4
4.2.6 Reset Status ...........................................................................................4-4
4.2.7 Bus Monitor ............................................................................................4-5
4.2.8 Halt Monitor ............................................................................................4-5
4.2.9 Spurious Interrupt Monitor ......................................................................4-5
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4.2.10 Software Watchdog ................................................................................4-5
4.2.11 Periodic Interrupt Timer ..........................................................................4-7
4.2.12 Low-Power Stop Operation ....................................................................4-8
4.2.13 Freeze Operation ...................................................................................4-9
4.3 System Clock .................................................................................................4-9
4.3.1 Clock Sources ......................................................................................4-10
4.3.2 Clock Synthesizer Operation ................................................................4-10
4.3.3 External Bus Clock ...............................................................................4-15
4.3.4 Low-Power Operation ...........................................................................4-15
4.3.5 Loss of Reference Signal .....................................................................4-16
4.4 External Bus Interface ..................................................................................4-17
4.4.1 Bus Signals ..........................................................................................4-18
4.4.1.1 Address Bus .................................................................................4-18
4.4.1.2 Address Strobe ............................................................................4-18
4.4.1.3 Data Bus ......................................................................................4-18
4.4.1.4 Data Strobe ..................................................................................4-18
4.4.1.5 Read/Write Signal ........................................................................4-18
4.4.1.6 Size Signals .................................................................................4-19
4.4.1.7 Function Codes ............................................................................4-19
4.4.1.8 Data and Size Acknowledge Signals ...........................................4-19
4.4.1.9 Bus Error Signal ...........................................................................4-20
4.4.1.10 Halt Signal ....................................................................................4-20
4.4.1.11 Autovector Signal .........................................................................4-20
4.4.2 Dynamic Bus Sizing .............................................................................4-20
4.4.3 Operand Alignment ..............................................................................4-21
4.4.4 Misaligned Operands ...........................................................................4-22
4.4.5 Operand Transfer Cases ......................................................................4-22
4.5 Bus Operation ..............................................................................................4-22
4.5.1 Synchronization to CLKOUT ................................................................4-23
4.5.2 Regular Bus Cycles ..............................................................................4-23
4.5.2.1 Read Cycle ...................................................................................4-24
4.5.2.2 Write Cycle ...................................................................................4-25
4.5.3 Fast Termination Cycles .......................................................................4-26
4.5.4 CPU Space Cycles ...............................................................................4-27
4.5.4.1 Breakpoint Acknowledge Cycle ....................................................4-28
4.5.4.2 LPSTOP Broadcast Cycle ............................................................4-31
4.5.5 Bus Exception Control Cycles ..............................................................4-31
4.5.5.1 Bus Errors ....................................................................................4-33
4.5.5.2 Double Bus Faults ........................................................................4-33
4.5.5.3 Retry Operation ............................................................................4-34
4.5.5.4 Halt Operation ..............................................................................4-34
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4.5.6 External Bus Arbitration ........................................................................4-35
4.5.6.1 Slave (Factory Test) Mode Arbitration .........................................4-36
4.5.6.2 Show Cycles ................................................................................4-36
4.6 Reset ............................................................................................................ 4-37
4.6.1 Reset Exception Processing ................................................................4-37
4.6.2 Reset Control Logic ..............................................................................4-38
4.6.3 Reset Mode Selection ..........................................................................4-38
4.6.3.1 Data Bus Mode Selection .............................................................4-39
4.6.3.2 Clock Mode Selection ..................................................................4-41
4.6.3.3 Breakpoint Mode Selection ..........................................................4-41
4.6.4 MCU Module Pin Function During Reset .............................................4-41
4.6.5 Pin State During Reset .........................................................................4-42
4.6.5.1 Reset States of SIM Pins .............................................................4-42
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules ...............4-43
4.6.6 Reset Timing ........................................................................................4-43
4.6.7 Power-On Reset ...................................................................................4-44
4.6.8 Reset Processing Summary .................................................................4-45
4.6.9 Reset Status Register ..........................................................................4-46
4.7 Interrupts ...................................................................................................... 4-46
4.7.1 Interrupt Exception Processing ............................................................4-46
4.7.2 Interrupt Priority and Recognition .........................................................4-46
4.7.3 Interrupt Acknowledge and Arbitration .................................................4-47
4.7.4 Interrupt Processing Summary .............................................................4-48
4.7.5 Interrupt Acknowledge Bus Cycles .......................................................4-49
4.8 Chip Selects .................................................................................................4-49
4.8.1 Chip-Select Registers ...........................................................................4-51
4.8.1.1 Chip-Select Pin Assignment Registers ........................................4-52
4.8.1.2 Chip-Select Base Address Registers ...........................................4-53
4.8.1.3 Chip-Select Option Registers .......................................................4-53
4.8.1.4 PORTC Data Register ..................................................................4-55
4.8.2 Chip-Select Operation ..........................................................................4-55
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge ..........................4-55
4.8.4 Chip-Select Reset Operation ................................................................4-56
4.9 Parallel Input/Output Ports ...........................................................................4-58
4.9.1 Pin Assignment Registers ....................................................................4-58
4.9.2 Data Direction Registers ......................................................................4-58
4.9.3 Data Registers ......................................................................................4-58
4.10 Factory Test .................................................................................................4-58
SECTION 5 CENTRAL PROCESSING UNIT
5.1 General ...........................................................................................................5-1
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5.2 CPU32 Registers ............................................................................................5-2
5.2.1 Data Registers ........................................................................................5-3
5.2.2 Address Registers ..................................................................................5-5
5.2.3 Program Counter ....................................................................................5-5
5.2.4 Control Registers ....................................................................................5-5
5.2.4.1 Status Register ...............................................................................5-5
5.2.4.2 Alternate Function Code Registers ................................................5-6
5.2.5 Vector Base Register (VBR) ...................................................................5-6
5.3 Memory Organization .....................................................................................5-6
5.4 Virtual Memory ...............................................................................................5-8
5.5 Addressing Modes ..........................................................................................5-8
5.6 Processing States ..........................................................................................5-8
5.7 Privilege Levels ..............................................................................................5-9
5.8 Instructions ..................................................................................................... 5-9
5.8.1 M68000 Family Compatibility ...............................................................5-12
5.8.2 Special Control Instructions ..................................................................5-13
5.8.2.1 Low Power Stop (LPSTOP) .........................................................5-13
5.8.2.2 Table Lookup and Interpolate (TBL) ............................................5-13
5.9 Exception Processing ...................................................................................5-13
5.9.1 Exception Vectors ................................................................................5-13
5.9.2 Types of Exceptions .............................................................................5-14
5.9.3 Exception Processing Sequence ..........................................................5-15
5.10 Development Support ...................................................................................5-15
5.10.1 M68000 Family Development Support .................................................5-15
5.10.2 Background Debugging Mode ..............................................................5-16
5.10.2.1 Enabling BDM ..............................................................................5-17
5.10.2.2 BDM Sources ...............................................................................5-17
5.10.2.3 Entering BDM ...............................................................................5-18
5.10.2.4 BDM Commands ..........................................................................5-19
5.10.2.5 Background Mode Registers ........................................................5-20
5.10.2.6 Returning from BDM ....................................................................5-20
5.10.2.7 Serial Interface .............................................................................5-20
5.10.3 Recommended BDM Connection .........................................................5-22
5.10.4 Deterministic Opcode Tracking ............................................................5-22
5.10.5 On-Chip Breakpoint Hardware .............................................................5-23
5.11 Loop Mode Instruction Execution .................................................................5-23
SECTION 6QUEUED SERIAL MODULE
6.1 General ...........................................................................................................6-1
6.2 QSM Registers and Address Map ..................................................................6-2
6.2.1 QSM Global Registers ...........................................................................6-2
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6.2.1.1 Low-Power Stop Operation ...........................................................6-2
6.2.1.2 Freeze Operation ..........................................................................6-3
6.2.1.3 QSM Interrupts ..............................................................................6-3
6.2.2 QSM Pin Control Registers ...................................................................6-3
6.3 Queued Serial Peripheral Interface ................................................................6-4
6.3.1 QSPI Registers ......................................................................................6-6
6.3.1.1 Control Registers ...........................................................................6-7
6.3.1.2 Status Register ..............................................................................6-7
6.3.2 QSPI RAM .............................................................................................6-7
6.3.2.1 Receive RAM .................................................................................6-7
6.3.2.2 Transmit RAM ................................................................................6-8
6.3.2.3 Command RAM .............................................................................6-8
6.3.3 QSPI Pins ...............................................................................................6-8
6.3.4 QSPI Operation ......................................................................................6-9
6.3.5 QSPI Operating Modes ........................................................................6-10
6.3.5.1 Master Mode ................................................................................6-17
6.3.5.2 Master Wraparound Mode ...........................................................6-20
6.3.5.3 Slave Mode ..................................................................................6-20
6.3.5.4 Slave Wraparound Mode .............................................................6-22
6.3.6 Peripheral Chip Selects ........................................................................6-22
6.4 Serial Communication Interface ...................................................................6-22
6.4.1 SCI Registers .......................................................................................6-22
6.4.1.1 Control Registers .........................................................................6-22
6.4.1.2 Status Register .............................................................................6-25
6.4.1.3 Data Register ...............................................................................6-25
6.4.2 SCI Pins ..............................................................................................6-25
6.4.3 SCI Operation .......................................................................................6-25
6.4.3.1 Definition of Terms .......................................................................6-25
6.4.3.2 Serial Formats ..............................................................................6-26
6.4.3.3 Baud Clock ...................................................................................6-26
6.4.3.4 Parity Checking ............................................................................6-27
6.4.3.5 Transmitter Operation ..................................................................6-27
6.4.3.6 Receiver Operation ......................................................................6-28
6.4.3.7 Idle-Line Detection .......................................................................6-29
6.4.3.8 Receiver Wakeup .........................................................................6-30
6.4.3.9 Internal Loop ................................................................................6-30
6.5 QSM Initialization .........................................................................................6-31
SECTION 7TIME PROCESSOR UNIT
7.1 General ...........................................................................................................7-1
7.2 TPU Components ...........................................................................................7-2
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7.2.1 Time Bases ............................................................................................7-2
7.2.2 Timer Channels ......................................................................................7-2
7.2.3 Scheduler ............................................................................................... 7-2
7.2.4 Microengine ............................................................................................7-2
7.2.5 Host Interface .........................................................................................7-2
7.2.6 Parameter RAM ......................................................................................7-3
7.3 TPU Operation ...............................................................................................7-3
7.3.1 Event Timing ..........................................................................................7-3
7.3.2 Channel Orthogonality ............................................................................7-4
7.3.3 Interchannel Communication ..................................................................7-4
7.3.4 Programmable Channel Service Priority ................................................7-4
7.3.5 Coherency .............................................................................................. 7-4
7.3.6 Emulation Support ..................................................................................7-4
7.3.7 TPU Interrupts ........................................................................................7-5
7.4 Standard and Enhanced Standard Time Functions .......................................7-6
7.4.1 Discrete Input/Output (DIO) ....................................................................7-6
7.4.2 Input Capture/Input Transition Counter (ITC) .........................................7-6
7.4.3 Output Compare (OC) ............................................................................7-6
7.4.4 Pulse-Width Modulation (PWM) .............................................................7-7
7.4.5 Synchronized Pulse-Width Modulation (SPWM) ....................................7-7
7.4.6 Period Measurement with Additional Transition Detect (PMA) ..............7-7
7.4.7 Period Measurement with Missing Transition Detect (PMM) .................7-7
7.4.8 Position-Synchronized Pulse Generator (PSP) ......................................7-7
7.4.9 Stepper Motor (SM) ................................................................................7-8
7.4.10 Period/Pulse-Width Accumulator (PPWA) ..............................................7-8
7.4.11 Quadrature Decode (QDEC) ..................................................................7-9
7.5 Motion Control Time Functions ......................................................................7-9
7.5.1 Table Stepper Motor (TSM) ....................................................................7-9
7.5.2 New Input Capture/Transition Counter (NITC) .......................................7-9
7.5.3 Queued Output Match (QOM) ..............................................................7-10
7.5.4 Programmable Time Accumulator (PTA) .............................................7-10
7.5.5 Multichannel Pulse-Width Modulation (MCPWM) ................................7-10
7.5.6 Fast Quadrature Decode (FQD) ...........................................................7-10
7.5.7 Universal Asynchronous Receiver/Transmitter (UART) .......................7-11
7.5.8 Brushless Motor Commutation (COMM) ..............................................7-11
7.5.9 Frequency Measurement (FQM) ..........................................................7-11
7.5.10 Hall Effect Decode (HALLD) .................................................................7-11
7.6 Host Interface Registers ...............................................................................7-11
7.6.1 System Configuration Registers ...........................................................7-12
7.6.1.1 Prescaler Control for TCR1 ..........................................................7-12
7.6.1.2 Prescaler Control for TCR2 ..........................................................7-12
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7.6.1.3 Emulation Control .........................................................................7-13
7.6.1.4 Low-Power Stop Control ..............................................................7-13
7.6.2 Channel Control Registers ...................................................................7-14
7.6.2.1 Channel Interrupt Enable and Status Registers ...........................7-14
7.6.2.2 Channel Function Select Registers ..............................................7-14
7.6.2.3 Host Sequence Registers ............................................................7-14
7.6.2.4 Host Service Registers .................................................................7-14
7.6.2.5 Channel Priority Registers ...........................................................7-14
7.6.3 Development Support and Test Registers ...........................................7-15
SECTION 8STANDBY RAM WITH TPU EMULATION
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8.1 General ...........................................................................................................8-1
8.2 TPURAM Register Block ................................................................................8-1
8.3 TPURAM Array Address Mapping ..................................................................8-1
8.4 TPURAM Privilege Level ................................................................................8-2
8.5 Normal Operation ...........................................................................................8-2
8.6 Standby Operation .........................................................................................8-2
8.7 Low-Power Stop Operation ............................................................................8-3
8.8 Reset .............................................................................................................. 8-3
8.9 TPU Microcode Emulation ..............................................................................8-3
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
C.1 M68MMDS1632 Modular Development System ........................................... C-1
C.2 M68MEVB1632 Modular Evaluation Board ................................................... C-2
APPENDIX D REGISTER SUMMARY
D.1 Central Processing Unit ................................................................................. D-1
D.1.1 CPU32 Register Model .......................................................................... D-2
D.1.2 SR — Status Register ........................................................................... D-3
D.2 System Integration Module ............................................................................ D-3
D.2.1 SIMCR — Module Configuration Register .............................$YFFA00 D-5
D.2.2 SIMTR — System Integration Test Register..........................$YFFA02 D-6
D.2.3 SYNCR — Clock Synthesizer Control Register .................... $YFFA04 D-6
D.2.4 RSR — Reset Status Register ..............................................$YFFA07 D-7
D.2.5 SIMTRE — System Integration Test Register (ECLK)........... $YFFA08 D-7
D.2.6 PORTE0/PORTE1 — Port E Data Register..........$YFFA11, $YFFA13 D-8
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D.2.7 DDRE — Port E Data Direction Register ............................... $YFFA15 D-8
D.2.8 PEPAR — Port E Pin Assignment Register...........................$YFFA17 D-8
D.2.9 PORTF0/PORTF1 — Port F Data Register...........$YFFA19, $YFFA1B D-9
D.2.10 DDRF — Port F Data Direction Register................................$YFFA1D D-9
D.2.11 PFPAR — Port F Pin Assignment Register............................$YFFA1F D-9
D.2.12 SYPCR — System Protection Control Register...................$YFFA21 D-10
D.2.13 PICR — Periodic Interrupt Control Register.........................$YFFA22 D-11
D.2.14 PITR — Periodic Interrupt Timer Register ........................... $YFFA24 D-11
D.2.15 SWSR — Software Service Register ................................... $YFFA27 D-11
D.2.16 TSTMSRA — Master Shift Register A..................................$YFFA30 D-11
D.2.17 TSTMSRB — Master Shift Register B..................................$YFFA32 D-11
D.2.18 TSTSC — Test Module Shift Count ..................................... $YFFA34 D-12
D.2.19 TSTRC — Test Module Repetition Count............................$YFFA36 D-12
D.2.20 CREG — Test Submodule Control Register .......................$YFFA38 D-12
D.2.21 DREG — Distributed Register..............................................$YFFA3A D-12
D.2.22 PORTC — Port C Data Register.......................................... $YFFA41 D-12
D.2.23 CSPAR0 — Chip Select Pin Assignment Register 0............$YFFA44 D-12
D.2.24 CSPAR1 — Chip Select Pin Assignment Register 1............$YFFA46 D-13
D.2.25 CSBARBT — Chip Select Base Address Register Boot ROM $YFFA48 D13
D.2.26 CSBAR[0:10] — Chip Select Base Address Registers $YFFA4C–$YFFA74
D-13
D.2.27 CSORBT — Chip Select Option Register Boot ROM...........$YFFA4A D-14
D.2.28 CSOR[0:10] — Chip Select Option Registers.....$YFFA4E–$YFFA76 D-14
D.3 Standby RAM Module with TPU Emulation ................................................. D-16
D.3.1 TRAMMCR — TPURAM Module Configuration Register..... $YFFB00 D-16
D.3.2 TRAMTST — TPURAM Test Register.................................$YFFB02 D-16
D.3.3 TRAMBAR — TPURAM Base Address and Status Register $YFFB04 D-16
D.4 Queued Serial Module ................................................................................. D-18
D.4.1 QSMCR — QSM Configuration Register .............................$YFFC00 D-18
D.4.2 QTEST — QSM Test Register.............................................$YFFC02 D-19
D.4.3 QILR — QSM Interrupt Level Register..........................................$YFFC04
QIVR — QSM Interrupt Vector Register$YFFC05 .................................................... D-19
D.4.4 SCCR0 — SCI Control Register 0 .......................................$YFFC08 D-20
D.4.5 SCCR1 — SCI Control Register 1........................................$YFFC0A D-20
D.4.6 SCSR — SCI Status Register............................................. $YFFC0C D-22
D.4.7 SCDR — SCI Data Register.................................................$YFFC0E D-23
D.4.8 PORTQS — Port QS Data Register.....................................$YFFC15 D-23
D.4.9 PQSPAR — PORT QS Pin Assignment Register.........................$YFFC16
DDRQS — PORT QS Data Direction Register$YFFC17 .......................................... D-23
D.4.10 SPCR0 — QSPI Control Register 0.....................................$YFFC18 D-25
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D.4.11 SPCR1 — QSPI Control Register 1 ....................................$YFFC1A D-26
D.4.12 SPCR2 — QSPI Control Register 2 ................................... $YFFC1C D-27
D.4.13 SPCR3 — QSPI Control Register 3 ............................................ $YFFC1E
SPSR — QSPI Status Register $YFFC1F ................................................................ D-27
D.4.14 RR[0:F] — Receive Data RAM...........................$YFFD00–$YFFD0E D-28
D.4.15 TR[0:F] — Transmit Data RAM .........................$YFFD20–$YFFD3E D-28
D.4.16 CR[0:F] — Command RAM................................ $YFFD40–$YFFD4F D-29
D.5.1 TPUMCR — TPU Module Configuration Register................ $YFFE00 D-30
D.5.2 TCR — Test Configuration Register.....................................$YFFE02 D-32
D.5.3 DSCR — Development Support Control Register................$YFFE04 D-32
D.5.4 DSSR — Development Support Status Register ................. $YFFE06 D-33
D.5.5 TICR — TPU Interrupt Configuration Register..................... $YFFE08 D-33
D.5.6 CIER — Channel Interrupt Enable Register.........................$YFFE0A D-34
D.5.7 CFSR0 — Channel Function Select Register 0 ...................$YFFE0C D-34
D.5.8 CFSR1 — Channel Function Select Register 1 ...................$YFFE0E D-34
D.5.9 CFSR2 — Channel Function Select Register 2 ................... $YFFE10 D-34
D.5.10 CFSR3 — Channel Function Select Register 3 ................... $YFFE12 D-34
D.5.11 HSQR0 — Host Sequence Register 0 ................................. $YFFE14 D-35
D.5.12 HSQR1 — Host Sequence Register 1 ................................. $YFFE16 D-35
D.5.13 HSRR0 — Host Service Request Register 0 ....................... $YFFE18 D-35
D.5.15 CPR0 — Channel Priority Register 0 ..................................$YFFE1C D-36
D.5.16 CPR1 — Channel Priority Register 1.................................. $YFFE1E D-36
D.5.17 CISR — Channel Interrupt Status Register..........................$YFFE20 D-36
D.5.18 LR — Link Register..............................................................$YFFE22 D-36
D.5.19 SGLR — Service Grant Latch Register................................$YFFE24 D-36
D.5.20 DCNR — Decoded Channel Number Register .................... $YFFE26 D-37
D.5.21 TPU Parameter RAM .......................................................................... D-37
SUMMARY OF CHANGES
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TABLE OF CONTENTS
(Continued)
Paragraph Title Page
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LIST OF ILLUSTRATIONS
Figure Title Page
3-1 MCU Block Diagram ....................................................................................... 3-3
3-2 Pin Assignments for 132-Pin Package ........................................................... 3-4
3-3 Pin Assignments for 144-Pin Package ........................................................... 3-5
3-4 Internal Register Memory Map ..................................................................... 3-10
3-5 Overall Memory Map .................................................................................... 3-11
3-6 Separate Supervisor and User Space Map .................................................. 3-12
3-7 Supervisor Space (Separate Program/Data Space) Map ............................ 3-13
3-8 User Space (Separate Program/Data Space) Map ...................................... 3-14
4-1 System Integration Module Block Diagram ....................................................4-2
4-2 System Configuration and Protection ............................................................. 4-3
4-3 Periodic Interrupt Timer and Software Watchdog Timer ................................4-7
4-4 System Clock Block Diagram ......................................................................... 4-9
4-5 System Clock Oscillator Circuit ....................................................................4-10
4-6 System Clock Filter Networks ...................................................................... 4-11
4-7 MCU Basic System ...................................................................................... 4-17
4-8 Operand Byte Order ..................................................................................... 4-21
4-9 Word Read Cycle Flowchart .........................................................................4-25
4-10 Write Cycle Flowchart .................................................................................. 4-26
4-11 CPU Space Address Encoding .................................................................... 4-27
4-12 Breakpoint Operation Flowchart ................................................................... 4-30
4-13 LPSTOP Interrupt Mask Level ......................................................................4-31
4-14 Bus Arbitration Flowchart for Single Request ...............................................4-36
4-15 Data Bus Mode Select Conditioning .............................................................4-40
4-16 Power-On Reset ........................................................................................... 4-45
4-17 Basic MCU System ...................................................................................... 4-50
4-18 Chip-Select Circuit Block Diagram ...............................................................4-51
4-19 CPU Space Encoding for Interrupt Acknowledge .........................................4-56
5-1 CPU32 Block Diagram ................................................................................... 5-2
5-2 User Programming Model .............................................................................. 5-3
5-3 Supervisor Programming Model Supplement .................................................5-3
5-4 Data Organization in Data Registers .............................................................. 5-4
5-5 Address Organization in Address Registers ...................................................5-5
5-6 Memory Operand Addressing ........................................................................ 5-7
5-7 Common in-Circuit Emulator Diagram ..........................................................5-16
5-8 Bus State Analyzer Configuration ................................................................ 5-17
5-9 Debug Serial I/O Block Diagram .................................................................. 5-21
5-10 BDM Serial Data Word ................................................................................. 5-22
5-11 BDM Connector Pinout .................................................................................5-22
5-12 Loop Mode Instruction Sequence .................................................................5-23
6-1 QSM Block Diagram ....................................................................................... 6-1
6-2 QSPI Block Diagram ..................................................................................... 6-6
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LIST OF ILLUSTRATIONS
(Continued)
Figure Title Page
6-3 QSPI RAM ...................................................................................................... 6-8
6-4 Flowchart of QSPI Initialization Operation ....................................................6-11
6-5 Flowchart of QSPI Master Operation (Part 1) .............................................. 6-12
6-5 Flowchart of QSPI Master Operation (Part 2) .............................................. 6-13
6-5 Flowchart of QSPI Master Operation (Part 3) .............................................. 6-14
6-6 Flowchart of QSPI Slave Operation (Part 1) ................................................ 6-15
6-6 Flowchart of QSPI Slave Operation (Part 2) ................................................ 6-16
6-7 SCI Transmitter Block Diagram .................................................................... 6-23
6-8 SCI Receiver Block Diagram ........................................................................ 6-24
7-1 TPU Block Diagram ........................................................................................ 7-1
7-2 TCR1 Prescaler Control ...............................................................................7-12
7-3 TCR2 Prescaler Control ...............................................................................7-13
A-1 CLKOUT Output Timing Diagram .................................................................A-14
A-2 External Clock Input Timing Diagram ...........................................................A-14
A-3 ECLK Output Timing Diagram ......................................................................A-14
A-4 Read Cycle Timing Diagram ........................................................................A-15
A-5 Write Cycle Timing Diagram .........................................................................A-16
A-6 Fast Termination Read Cycle Timing Diagram ............................................A-17
A-7 Fast Termination Write Cycle Timing Diagram .............................................A-18
A-8 Bus Arbitration Timing Diagram —Active Bus Case ....................................A-19
A-9 Bus Arbitration Timing Diagram — Idle Bus Case .......................................A-20
A-10 Show Cycle Timing Diagram ........................................................................A-20
A-11 Chip Select Timing Diagram .........................................................................A-21
A-12 Reset and Mode Select Timing Diagram ......................................................A-21
A-13 Background Debugging Mode Timing Diagram — Serial Communication ...A-23
A-14 Background Debugging Mode Timing Diagram — Freeze Assertion ...........A-23
A-15 ECLK Timing Diagram ..................................................................................A-25
A-16 QSPI Timing — Master, CPHA = 0 ..............................................................A-27
A-17 QSPI Timing — Master, CPHA = 1 ..............................................................A-27
A-18 QSPI Timing — Slave, CPHA = 0 ................................................................A-28
A-19 QSPI Timing — Slave, CPHA = 1 ................................................................A-28
A-20 TPU Timing Diagram ....................................................................................A-29
B-1 132-Pin Plastic Surface Mount Package Pin Assignments ............................B-2
B-2 144-Pin Plastic Surface Mount Package Pin Assignments ............................B-3
D-1 User Programming Model ..............................................................................D-2
D-2 Supervisor Programming Model Supplement .................................................D-2
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LIST OF TABLES
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Table Title Page
3-1 MCU Driver Types........................................................................................... 3-6
3-2 MCU Pin Characteristics.................................................................................3-6
3-3 MCU Power Connections................................................................................3-7
3-4 MCU Signal Characteristics............................................................................ 3-7
3-5 MCU Signal Function...................................................................................... 3-8
3-6 SIM Reset Mode Selection............................................................................ 3-15
3-7 Module Pin Functions.................................................................................... 3-16
4-1 Show Cycle Enable Bits..................................................................................4-4
4-2 Bus Monitor Period.......................................................................................... 4-5
4-3 MODCLK Pin and SWP Bit During Reset....................................................... 4-6
4-4 Software Watchdog Ratio................................................................................4-6
4-5 MODCLK Pin and PTP Bit at Reset................................................................4-7
4-6 Periodic Interrupt Priority................................................................................. 4-8
4-7 Clock Control Multipliers................................................................................4-12
4-8 System Frequencies from 32.768–kHz Reference........................................4-14
4-9 Clock Control................................................................................................. 4-16
4-10 Size Signal Encoding ....................................................................................4-19
4-11 Address Space Encoding.............................................................................. 4-19
4-12 Effect of DSACK Signals............................................................................... 4-21
4-13 Operand Transfer Cases............................................................................... 4-22
4-14 DSA
4-15 Reset Source Summary................................................................................ 4-38
4-16 Reset Mode Selection................................................................................... 4-39
4-17 Module Pin Functions.................................................................................... 4-42
4-18 SIM Pin Reset States.................................................................................... 4-43
4-19 Chip-Select Pin Functions.............................................................................4-52
4-20 Pin Assignment Field Encoding..................................................................... 4-52
4-21 Block Size Encoding...................................................................................... 4-53
4-22 Option Register Function Summary.............................................................. 4-54
4-23 Chip Select Base and Option Register Reset Values ...................................4-57
4-24 CSBOOT Base and Option Register Reset Values....................................... 4-58
5-1 Instruction Set Summary............................................................................... 5-10
5-2 Exception Vector Assignments......................................................................5-14
5-3 BDM Source Summary..................................................................................5-17
5-4 Polling the BDM Entry Source....................................................................... 5-18
5-5 Background Mode Command Summary.......................................................5-19
5-6 CPU Generated Message Encoding.............................................................5-22
6-1 QSM Pin Function...........................................................................................6-4
6-2 QSPI Pin Function........................................................................................... 6-9
6-3 BITS Encoding.............................................................................................. 6-19
6-4 SCI Pin Function........................................................................................... 6-25
CK, BERR, and HALT Assertion Results ............................................... 4-32
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LIST OF TABLES
(Continued)
Table Title Page
6-5 Serial Frame Formats....................................................................................6-26
6-6 Effect of Parity Checking on Data Size......................................................... 6-27
7-1 TCR1 Prescaler Control................................................................................7-12
7-2 TCR2 Prescaler Control................................................................................7-13
7-3 Channel Priority Encodings........................................................................... 7-15
A-1 Maximum Ratings............................................................................................A-1
A-2 Typical Ratings, 16.78 MHz Operation............................................................A-2
A-2 a. Typical Ratings, 20.97 MHz Operation............................................................A-2
A-3 Thermal Characteristics ..................................................................................A-3
A-4 16.78 MHz Clock Control Timing.....................................................................A-4
A-4 a. 20.97 MHz Clock Control Timing.....................................................................A-5
A-5 16.78 MHz DC Characteristics........................................................................A-6
A-5 a. 20.97 MHz DC Characteristics........................................................................A-7
A-6 16.78 MHz AC Timing.....................................................................................A-9
A-6 a. 20.97 MHz AC Timing...................................................................................A-11
A-7 Background Debugging Mode Timing...........................................................A-22
A-8 16.78 MHz ECLK Bus Timing........................................................................A-24
A-8 a. 20.97 MHz ECLK Bus Timing........................................................................A-24
A-9 QSPI Timing..................................................................................................A-26
A-10 16.78 MHz Time Processor Unit Timing........................................................A-29
A-11 20.97 MHz Time Processor Unit Timing........................................................A-29
B-1 MCU Ordering Information..............................................................................B-5
B-2 Quantity Order Suffix.......................................................................................B-7
C-1 MC68332 Development Tools.........................................................................C-1
D-1 Module Address Map......................................................................................D-1
D-2 SIM Address Map............................................................................................D-4
D-3 TPURAM Address Map.................................................................................D-16
D-4 QSM Address Map........................................................................................D-18
D-5 TPU Address Map.........................................................................................D-30
D-6 Parameter RAM Address Map......................................................................D-37
D-7 MC68332 Module Address Map....................................................................D-38
D-8 Register Bit and Field Mnemonics.................................................................D-41
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SECTION 1 INTRODUCTION
The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance
data manipulation capabilities with powerful peripheral subsystems. The MCU is built
up from standard modules that interface through a common intermodule bus (IMB).
Standardization facilitates rapid development of devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a
time processor unit (TPU), a queued serial module (QSM), and a 2-Kbyte static RAM
module with TPU emulation capability (TPURAM).
The MCU can either synthesize an internal clock signal from an external reference or
use an external clock input directly. Operation with a 32.768-kHz reference frequency
is standard. System hardware and software allow changes in clock rate during operation. Because MCU operation is fully static, register and memory contents are not affected by clock rate changes.
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High-density complementary metal-oxide semiconductor (HCMOS) architecture
makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 instruction set includes a low-power
stop (LPSTOP) command that efficiently implements this capability.
Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each microcontroller has a comprehensive user's manual that provides sufficient information for normal operation of the device. The
user's manual is supplemented by module reference manuals that provide detailed information about module operation and applications. Refer to Motorola publication
vanced Microcontroller Unit (AMCU) Literature
documentation.
(BR1116/D) for a complete listing of
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INTRODUCTION
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±
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SECTION 2 NOMENCLATURE
The following nomenclature is used throughout the manual. Nomenclature used only
in certain sections, such as register bit mnemonics, is defined in those sections.
2.1 Symbols and Operators
+ — Addition
- — Subtraction or negation (two's complement)
* — Multiplication
/ — Division
> — Greater
< — Less
= — Equal
— Equal or greater
— Equal or less
- — Not equal
— AND
; — Inclusive OR (OR)
— Exclusive OR (EOR)
NOT
— Complementation
: — Concatenation
— Transferred
— Exchanged
— Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
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2.2 CPU32 Registers
A6–A0 — Address registers (Index registers)
A7 (SSP) — Supervisor Stack Pointer
A7 (USP) — User Stack Pointer
CCR — Condition code register (user portion of SR)
D7–D0 — Data Registers (Index registers)
DFC — Alternate function code register
PC — Program counter
SFC — Alternate function code register
SR — Status register
VBR — Vector base register
X — Extend indicator
N — Negative indicator
Z — Zero indicator
V — Two's complement overflow indicator
C — Carry/borrow indicator
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2.3 Pin and Signal Mnemonics
ADDR[23:0] — Address Bus
AS
— Address Strobe
AVEC
BERR
BGACK
BKPT
CLKOUT — System Clock
CS[10:0]
CSBOOT
DATA[15:0] — Data Bus
DSACK[1:0]
DSCLK — Development Serial Clock
DSO — Development Serial Output
EXTAL — External Crystal Oscillator Connection
FC[2:0] — Function Codes
FREEZE — Freeze
HALT
IFETCH
IPIPE
IRQ[7:1]
MISO — Master In Slave Out
MODCLK — Clock Mode Select
MOSI — Master Out Slave In
PC[6:0] — SIM I/O Port C
PCS[3:0] — Peripheral Chip Selects
PE[7:0] — SIM I/O Port E
PF[7:0] — SIM I/O Port F
PQS[7:0] — QSM I/O Port
QUOT — Quotient Out
R/W
RESET
RMC
RXD — SCI Receive Data
SCK — QSPI Serial Clock
SIZ[1:0] — Size
T2CLK — TPU Clock In
TPUCH[15:0] — TPU Channel Signals
TSC — Three-State Control
TXD — SCI Transmit Data
XFC — External Filter Capacitor
XTAL — External Crystal Oscillator Connection
— Autovector
— Bus Error
BG
— Bus Grant
— Bus Grant Acknowledge
— Breakpoint
BR
— Bus Request
— Chip Selects
— Boot ROM Chip Select
DS
— Data Strobe
— Data and Size Acknowledge
DSI — Development Serial Input
— Halt
— Instruction Fetch
— Instruction Pipeline
— Interrupt Request
— Read/Write
— Reset
— Read-Modify-Write Cycle
SS
— Slave Select
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2.4 Register Mnemonics
CFSR[0:3] — Channel Function Select Registers [0:3]
CIER — Channel Interrupt Enable Register
CISR — Channel Interrupt Status Register
CPR[0:1] — Channel Priority Registers [0:1]
CREG — Test Control Register C
CR[0:F] — QSM Command RAM
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[0:10] — Chip-Select Base Address Registers [0:10]
CSORBT — Chip-Select Option Register Boot ROM
CSOR[0:10] — Chip-Select Option Registers [0:10]
CSPAR[0:1] — Chip-Select Pin Assignment Registers [0:1]
DCNR — Decoded Channel Number Register
DDRE — Port E Data Direction Register
DDRF — Port F Data Direction Register
DDRQS — Port QS Data Direction Register
DREG — SIM Test Module Distributed Register
DSCR — Development Support Control Register
DSSR — Development Support Status Register
HSQR[0:1] — Host Sequence Registers [0:1]
HSRR[0:1] — Host Service Request Registers [0:1]
LR — Link Register
PEPAR — Port E Pin Assignment Register
PFPAR — Port F Pin Assignment Register
PICR — Periodic Interrupt Control Register
PITR — Periodic Interrupt Timer Register
PORTC — Port C Data Register
PORTE — Port E Data Register
PORTF — Port F Data Register
PORTQS — Port QS Data Register
PQSPAR — Port QS Pin Assignment Register
QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
QSMCR — QSM Configuration Register
QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SGLR — Service Grant Latch Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
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SWSR — Software Watchdog Service Register
SYNCR — Clock Synthesizer Control Register
SYPCR — System Protection Control Register
TCR — TPU Test Configuration Register
TICR — TPU Interrupt Configuration Register
TPUMCR — TPU Module Configuration Register
TRAMBAR — TPURAM Base Address/Status Register
TRAMMCR — TPURAM Module Configuration Register
TRAMTST — TPURAM Test Register
TR[0:F] — QSM Transmit Data RAM
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
TSTRC — Test Module Repetition Counter
TSTSC — Test Module Shift Count Register
2.5 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
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Clear refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.
A specific mnemonic within a range is referred to by mnemonic and number. A15 is
bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0.
that define the range. AM[35:30] are bits 35 to 30 of accumulator M; CSOR[0:5] are
the first six option registers
Parentheses are used to indicate the content of a register or memory location, rather
than the register or memory location itself. (A) is the content of accumulator A. (M
1) is the content of the word at address M.
LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-
ences to low and high bytes are spelled out.
LSW means least significant word or words. MSW means most significant word or
words.
A range of mnemonics is referred to by mnemonic and the numbers
ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus.
DATA is the data bus. DATA[15:8] are the eight MSB of the data bus.
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SECTION 3 OVERVIEW
This section contains information about the entire modular microcontroller. It lists the
features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system
memory maps. Timing and electrical specifications for the entire microcontroller and
for individual modules are provided in
. Comprehensive module register descriptions and memory maps are provided
TICS
APPENDIX D REGISTER SUMMARY .
in
3.1 MC68332 Features
The following paragraphs highlight capabilities of each of the microcontroller modules.
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Each module is discussed separately in a subsequent section of this user's manual.
APPENDIX A ELECTRICAL CHARACTERIS-
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3.1.1 System Integration Module (SIM)
• External Bus Support
• Programmable Chip-Select Outputs
• System Protection Logic
• Watchdog Timer, Clock Monitor, and Bus Monitor
• System Protection Logic
• System Clock Based on 32.768-kHz Crystal for Low Power Operation
• Test/Debug Submodule for Factory/User Test and Development
3.1.2 Central Processing Unit (CPU)
• Upward Object Code Compatible
• New Instructions for Controller Applications
• 32-Bit Architecture
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Table Lookup and Interpolate Instruction
• Improved Exception Handling for Controller Applications
• Trace on Change of Flow
• Hardware Breakpoint Signal, Background Mode
• Fully Static Operation
3.1.3 Time Processor Unit (TPU)
• Dedicated Microengine Operating Independently of CPU32
• 16 Independent, Programmable Channels and Pins
• Any Channel can Perform any Time Function
• Two Timer Count Registers with Programmable Prescalers
• Selectable Channel Priority Levels
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3.1.4 Queued Serial Module (QSM)
• Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmitter (UART): Modulus Baud Rate, Parity
• Queued Serial Peripheral Interface (SPI): 80-Byte RAM, Up to 16 Automatic
Transfers
• Dual Function I/O Ports
• Continuous Cycling, 8–16 Bits per Transfer
3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM)
• 2-Kbytes of Static RAM
• May be Used as Normal RAM or TPU Microcode Emulation RAM
3.2 System Block Diagram and Pin Assignment Diagrams
Figure 3-1 is a functional diagram of the MCU. Although diagram blocks represent the
relative size of the physical modules, there is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integratedcircuit modules. Figure 3-2 shows the pin assignments of the 132-pin plastic surfacemount package. Figure 3-3 shows the pin assignments of the 144-pin plastic surfacemount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN-
FORMATION for package dimensions. All pin functions and signal names are shown
in this drawing. Refer to subsequent paragraphs in this section for pin and signal descriptions.
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MOTOROLA OVERVIEW MC68332
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TPUCH[15:0] TPUCH[15:0]
T2CLK T2CLK
RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
BKPT/DSCLK
IFETCH
/DSI
IPIPE/DSO
PORT QS
CONTROL
TXD
PCS3
PCS2
PCS1
SCK
MOSI
MISO
QSM
TPU
IMB
IFETCH
BKPT
2 KBYTES
RAM
CPU 32
DSI
IPIPE
DSO
FREEZE
DSCLK
CHIP
SELECTS
BR
BG
BGACK
[10:0]
CS
FC2
FC1
FC0
ADDR[23:0]
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
EBI
DS PE5/DS
AS
RMC
AVEC PE2/AVEC
DSACK1 PE1/DSACK1
DSACK0 PE0/DSACK0
IRQ[7:1]
MODCLK
CLOCK
TSC
TEST
QUOT
CONTROL
ADDR[23:19]
CONTROL
CONTROL
CONTROL
PORT E
PORT F PORT C
CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[18:0]
PE4/AS
PE3/RMC
DATA[15:0]DATA[15:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
XFC
V
TSC
FREEZE/QUOT
DDSYN
CONTROL
332 BLOCK
Figure 3-1 MCU Block Diagram
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V
DD
V
STBY
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
V
DD
V
SS
ADDR9
ADDR10
ADDR11
ADDR12
V
SS
ADDR13
ADDR14
ADDR15
ADDR16
V
DD
V
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
DD
SS
TPUCH0
TPUCH1
TPUCH2
TPUCH3
TPUCH4
TPUCH5
V
17
16151413121110
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52535455565758596061626364656667686970717273747576777879808182
TPUCH6
DD
TPUCH7
9876543
VSSV
TPUCH8
TPUCH9
TPUCH10
DD
TPUCH11
VSSV
2
1
MC68332
TPUCH13
TPUCH14
TPUCH12
131
130
132
TPUCH15
T2CLK
V
129
128
SS
127
V
126
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
125
124
123
122
PC2/FC2/CS5
PC3/ADDR19/CS6
121
120
DD
SS
V
PC0/FC0/CS3
PC1/FC1/CS4
117
119
118
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
V
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
V
DD
V
SS
DATA4
DATA5
DATA6
DATA7
V
SS
DATA8
DATA9
DATA10
DATA11
V
DD
V
SS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
V
DD
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PE7/SIZ1
PE6/SIZ0
AS
SS
V
332 132-PIN QFP
SS
V
PQS7/TXD
RXD
IPIPE/DSO
IFETCH/DSI
TSC
BKPT/DSCLK
SS
V
XTAL
DDSYN
V
FREEZE/QUOT
XFC
VDDVDDV
EXTAL
SS
CLKOUT
HALT
RESET
BERR
PF7/IRQ7
PF5/IRQ5
PF6/IRQ6
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
R/W
PF1/IRQ1
PF0/MODCLK
Figure 3-2 Pin Assignments for 132-Pin Package
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NC
V
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
V
DD
V
SS
T2CLK
TPUCH15
TPUCH14
TPUCH13
TPUCH12
NC
V
DD
V
SS
TPUCH11
TPUCH10
TPUCH9
TPUCH8
V
DDE
V
SSE
TPUCH7
TPUCH6
TPUCH5
TPUCH4
TPUCH3
TPUCH2
TPUCH1
TPUCH0
V
SS
NC
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
142
141
ADDR1
ADDR2
DATA0
140
139
ADDR3
ADDR4
V
143
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
383940414243444546474849505152535455565758596061626364
DD
V
STBY
V
DATA1
DATA2
138
137
ADDR5
ADDR6
DD
DATA3
136
135
ADDR7
ADDR8
VSSV
134
DD
V
DATA4
DATA5
133
132
SS
V
ADDR9
SS
DATA6
DATA7NCDATA8NCDATA9
V
131
130
129
128
127
126
MC68332
SS
NC
NC
V
ADDR10
ADDR11
ADDR12
DATA10NCDATA11
125
124
123
ADDR13
ADDR14
ADDR15NCADDR16
122
DD
VSSDATA12
V
121
120
DD
V
119
SS
V
DATA13
DATA14
DATA15
118
117
116
65
ADDR17
ADDR18
PQS0/MISO
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
115
114
113
112
111
68
6667697071
PQS2/SCK
PQS1/MOSI
PQS4/PCS1
PQS5/PCS2
PQS3/PCS0/SS
DD
PE5/DS
V
109
110
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
DD
V
PQS6/PCS3
NC
V
SS
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
V
SS
CLKOUT
V
DD
NC
XFC
V
DD
EXTAL
V
DD
XTAL
V
SS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PQS7/TXD
V
SS
NC
332 144-PIN QFP
Figure 3-3 Pin Assignments for 144-Pin Package
3.3 Pin Descriptions
The following tables summarize functional characteristics of MCU pins. Table 3-1
shows types of output drivers. Table 3-2 shows all inputs and outputs. Digital inputs
and outputs use CMOS logic levels. An entry in the Discrete I/O column indicates that
a pin can also be used for general-purpose input, output, or both. The I/O port designation is given when it applies. Table 3-3 shows characteristics of power pins. Refer
to Figure 3-1 for port organization.
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Table 3-1 MCU Driver Types
Type I/O Description
A O Output-only signals that are always driven; no external pull-up required
Aw O Type A output with weak P-channel pull-up during reset
B O Three-state output that includes circuitry to pull up output before high impedance is
Bo O Type B output that can be operated in an open-drain mode
established, to ensure rapid rise time. An external holding resistor is required to
maintain logic level while the pin is in the high-impedance state.
Table 3-2 MCU Pin Characteristics
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Pin
Mnemonic
ADDR23/CS10
ADDR[22:19]/CS[9:6]
ADDR[18:0] A Y N — —
BG
BGACK
BKPT
BR
CLKOUT A — — — —
CSBOOT
DATA[15:0]
DSACK1
DSACK0
DSI/IFETCH
DSO/IPIPE
EXTAL
FC[2:0]/CS[5:3]
FREEZE/QUOT A — — — —
IRQ[7:1]
MODCLK
PCS0/SS
PCS[3:1] Bo Y Y I/O PQS[6:4]
RESET
SIZ[1:0] B Y N I/O PE[7:6]
T2CLK — Y Y — —
TPUCH[15:0] A Y Y — —
/ECLK A Y N O —
AS
AVEC
BERR
/CS1 B — — — —
/CS2 B Y N — —
/DSCLK — Y Y — —
/CS0 B Y N — —
1
DS
2
HALT
B Y Y I/O PF[7:1]
MISO Bo Y Y I/O PQS0
1
MOSI Bo Y Y I/O PQS1
R/W
RMC
RXD — N N — —
SCK Bo Y Y I/O PQS2
TSC — Y Y — —
Output
Driver
A Y N O PC[6:3]
B Y N I/O PE5
B Y N I/O PE2
B Y N — —
B — — — —
Aw Y N — —
B Y N I/O PE4
B Y N I/O PE1
B Y N I/O PE0
A Y Y — —
A — — — —
— — Special — —
A Y N O PC[2:0]
Bo Y N — —
B Y N I/O PF0
Bo Y Y I/O PQS3
A Y N — —
Bo Y Y — —
B Y N I/O PE3
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Designation
Port
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Table 3-2 MCU Pin Characteristics (Continued)
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Pin
Mnemonic
TXD Bo Y Y I/O PQS7
2
XFC
2
XTAL
NOTES:
1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.
2. EXTAL, XFC, and XTAL are clock reference connections.
Output
Driver
— — — Special —
— — — Special —
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Designation
Port
Table 3-3 MCU Power Connections
Pin Mnemonic Description
V
STBY
V
DDSYN
V
SSE/VDDE
V
SSI/VDDI
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
Standby RAM Power
Clock Synthesizer Power
3.4 Signal Descriptions
The following tables define MCU signals. Table 3-4 shows signal origin, type, and active state. Table 3-5 describes signal functions. Both tables are sorted alphabetically
by mnemonic. MCU pins often have multiple functions. More than one description can
apply to a pin.
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Table 3-4 MCU Signal Characteristics
Signal
Name
ADDR[23:0] SIM Bus —
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT SIM Output —
CS[10:0]
CSBOOT
DATA[15:0] SIM Bus —
DS
DSACK[1:0]
DSCLK CPU32 Input Serial Clock
DSI CPU32 Input (Serial Data)
DSO CPU32 Output (Serial Data)
EXTAL SIM Input —
FC[2:0] SIM Output —
FREEZE SIM Output 1
HALT
MCU
Module
SIM Output 0
SIM Input 0
SIM Input 0
SIM Output 0
SIM Input 0
CPU32 Input 0
SIM Input 0
SIM Output 0
SIM Output 0
SIM Output 0
SIM Input 0
SIM Input/Output 0
Signal
Type
Active
State
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Table 3-4 MCU Signal Characteristics (Continued)
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Signal
Name
IFETCH CPU32 Output —
IPIPE
IRQ[7:1]
MISO QSM Input/Output —
MODCLK SIM Input —
MOSI QSM Input/Output —
PC[6:0] SIM Output (Port)
PCS[3:0] QSM Input/Output —
PE[7:0] SIM Input/Output (Port)
PF[7:0] SIM Input/Output (Port)
PQS[7:0] QSM Input/Output (Port)
QUOT SIM Output —
RESET
RMC
R/W
RXD QSM Input —
SCK QSM Input/Output —
SIZ[1:0] SIM Output —
SS
T2CLK TPU Input —
TPUCH[15:0] TPU Input/Output 1
TSC SIM Input —
TXD QSM Output —
XFC SIM Input —
XTAL SIM Output —
MCU
Module
CPU32 Output —
SIM Input 0
SIM Input/Output 0
SIM Output 0
SIM Output 1/0
QSM Input 0
Signal
Type
Table 3-5 MCU Signal Function
Signal Name Mnemonic Function
Address Bus ADDR[23:0] 24-bit address bus
Address Strobe AS
Autovector AVEC
Bus Error BERR
Bus Grant BG
Bus Grant Acknowledge BGACK
Breakpoint BKPT
Bus Request BR
System Clockout CLKOUT System clock output
Chip Selects CS[10:0]
Boot Chip Select CSBOOT
Data Bus DATA[15:0] 16-bit data bus
Data Strobe DS
Data and Size Acknowledge DSACK[1:0]
Development Serial In, Out,
Clock
Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference;
DSI, DSO,
DSCLK
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
Select external devices at programmed addresses
Chip select for external boot start-up ROM
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
a crystal or an external oscillator can be used
Active
State
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Table 3-5 MCU Signal Function (Continued)
Signal Name Mnemonic Function
Function Codes FC[2:0] Identify processor state and current address space
Freeze FREEZE Indicates that the CPU has entered background mode
Halt HALT
Instruction Pipeline IPIPE
Interrupt Request Level IRQ[7:1]
Master In Slave Out MISO Serial input to QSPI in master mode;
Clock Mode Select MODCLK Selects the source and type of system clock
Master Out Slave In MOSI Serial output from QSPI in master mode;
Port C PC[6:0] SIM digital output port signals
Auxiliary Timer Clock Input PCLK External clock dedicated to the GPT
Peripheral Chip Select PCS[3:0] QSPI peripheral chip selects
Port E PE[7:0] SIM digital I/O port signals
Port F PF[7:0] SIM digital I/O port signals
Port QS PQS[7:0] QSM digital I/O port signals
Quotient Out QUOT Provides the quotient bit of the polynomial divider
Reset RESET
Read-Modify-Write Cycle RMC
Read/Write R/W
SCI Receive Data RXD Serial input to the SCI
QSPI Serial Clock SCK Clock output from QSPI in master mode;
Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle
Slave Select SS
TCR2 Clock T2CLK External clock source for TCR2 counter
TPU Channel Pins TPUCH[15:0] Bidirectional pins associated with TPU channels
Three-State Control TSC Places all output drivers in a high-impedance state
SCI Transmit Data TXD Serial output from the SCI
External Filter Capacitor XFC Connection for external phase-locked loop filter capacitor
, IFETCH Indicate instruction pipeline activity
Suspend external bus activity
Provides an interrupt priority level to the CPU
serial output from QSPI in slave mode
serial input to QSPI in slave mode
System reset
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
clock input to QSPI in slave mode
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
3.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design
and operation of modular microcontrollers. It contains circuitry to support exception
processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with
external components through the IMB. The IMB in the MCU uses 24 address and 16
data lines.
3.6 System Memory Map
Figure 3-4 through Figure 3-8 are MCU memory maps. Figure 3-4 shows IMB ad-
dresses of internal registers. Figure 3-5 through Figure 3-8 show system memory
maps that use different external decoding schemes.
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3.6.1 Internal Register Map
In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent-
ed by Y determines the base address of MCU module control registers. In M68300 microcontrollers, Y is equal to M111, where M is the logic state of the module mapping
(MM) bit in the system integration module configuration register (SIMCR).
$YFF000
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$YFFA00
$YFFA80
$YFFB00
$YFFB40
$YFFC00
$YFFE00
$YFFFFF
SIM
RESERVED
TPURAM CONTROL
RESERVED
QSM
TPU
2-KBYTE
TPURAM ARRAY
332 ADDRESS MAP
Figure 3-4 Internal Register Memory Map
3.6.2 Address Space Maps
Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded
externally so that separate user/supervisor or program/data spaces are not provided.
In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces.
FC[1:0] are not decoded, so that separate program and data spaces are not provided.
In Figure 3-7 and Figure 3-8, FC[2:0] are decoded, resulting in four separate memory
spaces: supervisor/program, supervisor/data, user/program and user/data.
All exception vectors are located in supervisor data space, except the reset vector,
which is located in supervisor program space. Only the initial reset vector is fixed in
the processor's memory map. Once initialization is complete, there are no fixed assignments. Since the vector base register (VBR) provides the base address of the vector table, the vector table can be located anywhere in memory. Refer to SECTION 5
CENTRAL PROCESSING UNIT for more information concerning memory management, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM
INTEGRATION MODULE for more information concerning function codes and address space types.
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$000000
COMBINED
SUPERVISOR
AND USER
SPACE
0040–005C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
VECTOR
OFFSET
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
006C
0064
0068
006C
0070
0074
0078
007C
VECTOR
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
14
FORMAT ERROR AND UNINITIALIZED INTERRUPT
15
16–23
32–47
48–58
59–63
64–255
FORMAT ERROR AND UNINITIALIZED INTERRUPT
24
25
26
27
28
29
30
31
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
TYPE OF
EXCEPTION
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$YFF000
$YFFA00
$7FF000
INTERNAL REGISTERS (MM = 0)
SIM
RESERVED
TPURAM CTL
RESERVED
$YFFA80
$YFFB00
$YFFB40
$YFFC00
QSM
$YFFE00
TPU
$FF0000
$FFFFFF
INTERNAL REGISTERS (MM = 1)
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
$XX0000RESET — INITIAL STACK POINTER
$XX03FC
332 S/U COMB MAP
Figure 3-5 Overall Memory Map
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$000000
SUPERVISOR
SPACE
0040–005C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
VECTOR
OFFSET
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
006C
0064
0068
006C
0070
0074
0078
007C
VECTOR
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
14
FORMAT ERROR AND UNINITIALIZED INTERRUPT
15
16–23
32–47
48–58
59–63
64–255
FORMAT ERROR AND UNINITIALIZED INTERRUPT
24
25
26
27
28
29
30
31
TAP INSTRUCTION VECTORS (0–15)
TYPE OF
EXCEPTION
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX0000RESET — INITIAL STACK POINTER
USER
SPACE
$XX03FC
$YFF000
$YFFA00
$7FF000
INTERNAL REGISTERS
SIM
RESERVED
TPURAM CTL
RESERVED
INTERNAL REGISTERS
$YFFA80
$YFFB00
$YFFB40
$YFFC00
QSM
$YFFE00
TPU
$FF0000
$FFFFFF
INTERNAL REGISTERS
$YFFFFF
INTERNAL REGISTERS
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
332 S/U SEP MAP
$000000
$7FF000
$FF0000
$FFFFFF
4
4
Figure 3-6 Separate Supervisor and User Space Map
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$000000
SUPERVISOR
DATA
SPACE
Freescale Semiconductor, Inc.
VECTOR
OFFSET
0000
0004
VECTOR
OFFSET
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0040–005C
006C
0064
0068
006C
0070
0074
0078
007C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
VECTOR
NUMBER
0
1
VECTOR
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
EXCEPTION VECTORS LOCATED
IN SUPERVISOR PROGRAM SPACE
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
EXCEPTION VECTORS LOCATED
IN SUPERVISOR DATA SPACE
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
HARDWARE BREAKPOINT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX0000
$XX0004
$XX0000RESET — INITIAL STACK POINTER
$XX03FC
$000000
SUPERVISOR
PROGRAM
SPACE
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$YFF000
$YFFA00
$7FF000
INTERNAL REGISTERS
SIM
RESERVED
TPURAM CTL
RESERVED
$YFFA80
$YFFB00
$YFFB40
$YFFC00
QSM
$YFFE00
TPU
$FF0000
$FFFFFF
INTERNAL REGISTERS
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
332 SUPER P/D MAP
$FFFFFF
Figure 3-7 Supervisor Space (Separate Program/Data Space) Map
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$000000
$FFFFFF
USER
PROGRAM
SPACE
$000000
$7FF000
$FF0000
$FFFFFF
USER
DATA
SPACE
INTERNAL REGISTERS
INTERNAL REGISTERS
SIM
RESERVED
TPURAM CTL
RESERVED
QSM
TPU
$YFF000
$YFFA00
$YFFA80
$YFFB00
$YFFB40
$YFFC00
$YFFE00
$YFFFFF
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NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
3. Some internal registers are not available in user space.
332 USER P/D MAP
Figure 3-8 User Space (Separate Program/Data Space) Map
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3.7 System Reset
The following information is a concise reference only. MC68332 system reset is a complex operation. To understand operation during and after reset, refer to SECTION 4
SYSTEM INTEGRATION MODULE, paragraph 4.6 Reset for more complete discussion of the reset function.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT
pin determines what happens during subsequent breakpoint as-
sertions. Table 3-6 is a summary of reset mode selection options.
Table 3-6 SIM Reset Mode Selection
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Mode Select Pin Default Function
(Pin Left High)
DATA0 CSBOOT
DATA1 CS0
DATA2 CS3
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8 DSACK0
AVEC
DATA9 IRQ[7:1]
DATA11 Test Mode Disabled Test Mode Enabled
MODCLK VCO = System Clock EXTAL = System Clock
BKPT
Background Mode Disabled Background Mode Enabled
16-Bit CSBOOT 8-Bit
CS1
CS2
CS4
CS5
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
, DSACK1,
, DS, AS,
SIZ[1:0]
MODCLK
Alternate Function
(Pin Pulled Low)
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
PORTF
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3.7.2 MCU Module Pin Function During Reset
Generally, pins associated with modules other than the SIM default to port functions,
and input/output ports are set to input state. This is accomplished by disabling pin
functions in the appropriate control registers, and by clearing the appropriate port data
direction registers. Refer to individual module sections in this manual for more information. Table 3-7 is a summary of module pin function out of reset.
Table 3-7 Module Pin Functions
Module Pin Mnemonic Function
CPU32 DSI/IFETCH
DSO/IPIPE DSO/IPIPE
BKPT/DSCLK BKPT/DSCLK
TPU TPUCH[15:0] TPU Input
T2CLK TCR2 Clock
QSM PQS7/TXD Discrete Input
PQS[6:4]/PCS[3:1] Discrete Input
PQS3/PCS0/SS
PQS2/SCK Discrete Input
PQS1/MOSI Discrete Input
PQS0/MISO Discrete Input
RXD RXD
DSI/IFETCH
Discrete Input
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SECTION 4 SYSTEM INTEGRATION MODULE
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This section is an overview of SIM function. Refer to the
RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D
REGISTER SUMMARY for information concerning the SIM address map and register
structure.
4.1 General
The system integration module (SIM) consists of five functional blocks. Figure 4-1 is
a block diagram of the SIM.
The system configuration and protection block controls configuration parameters and
provides bus and software watchdog monitors. In addition, it provides a periodic interrupt generator to support execution of time-critical control routines.
The system clock generates clock signals used by the SIM, other IMB modules, and
external devices.
The external bus interface handles the transfer of information between IMB modules
and external address space. EBI pins can also be configured for use as general-purpose I/O ports E and F.
The chip-select block provides 12 chip-select signals. Each chip-select signal has an
associated base register and option register that contain the programmable characteristics of that chip select. Chip-select pins can also be configured for use as generalpurpose output port C.
The system test block incorporates hardware necessary for testing the MCU. It is used
to perform factory tests, and its use in normal applications is not supported.
SIM Reference Manual
(SIM-
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SYSTEM CONFIGURATION
CLOCK SYNTHESIZER
AND PROTECTION
CLKOUT
EXTAL
MODCLK
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CHIP SELECTS
EXTERNAL BUS INTERFACE
FACTORY TEST
CHIP SELECTS
EXTERNAL BUS
RESET
TSC
FREEZE/QUOT
S(C)IM BLOCK
Figure 4-1 System Integration Module Block Diagram
4.2 System Configuration and Protection
The system configuration and protection functional block controls module configuration, preserves reset status, monitors internal activity, and provides periodic interrupt
generation. Figure 4-2 is a block diagram of the submodule.
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MODULE CONFIGURATION
AND TEST
RESET STATUS
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CLOCK
9
2
PRESCALER
HALT MONITOR
BUS MONITOR
SPURIOUS INTERRUPT MONITOR
SOFTWARE WATCHDOG TIMER
PERIODIC INTERRUPT TIMER
RESET REQUEST
BERR
RESET
REQUEST
IRQ [7:1]
SYS PROTECT BLOCK
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Figure 4-2 System Configuration and Protection
4.2.1 Module Mapping
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping bit (MM) in the SIM configuration register
(SIMCR) determines where the control register block is located in the system memory
map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM
= 1, register addresses range from $FFF000 to $FFFFFF.
4.2.2 Interrupt Arbitration
Each module that can generate interrupt requests has an interrupt arbitration (IARB)
field. Arbitration between interrupt requests of the same priority is performed by serial
contention between IARB field bit values. Contention must take place whenever an in-
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terrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized,
the CPU32 processes a spurious interrupt exception.
Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same priority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all
other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to 4.7 Interrupts for a discussion of interrupt arbitration.
4.2.3 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in the SIMCR determines what the external bus interface does during internal transfer
operations. Table 4-1 shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to 4.5.6.2 Show Cycles for more information.
Table 4-1 Show Cycle Enable Bits
SHEN Action
00 Show cycles disabled, external arbitration enabled
01 Show cycles enabled, external arbitration disabled
10 Show cycles enabled, external arbitration enabled
11 Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
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4.2.4 Factory Test Mode
The internal IMB can serve as slave to an external master for direct module testing.
This test mode is reserved for factory test. Slave mode is enabled by holding DATA11
low during reset. The slave enabled (SLVEN) bit is a read-only bit that shows the reset
state of DATA11.
4.2.5 Register Access
The CPU32 can operate at either of two privilege levels. Supervisor level is more privileged than user level — all instructions and system resources are available at supervisor level, but access is restricted at user level. Effective use of privilege level can
protect system resources from uncontrolled access. The state of the S bit in the CPU
status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, registers with controlled access are restricted to supervisor access only.
4.2.6 Reset Status
The reset status register (RSR) latches internal MCU status during reset. Refer to
4.6.9 Reset Status Register for more information.
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4.2.7 Bus Monitor
The internal bus monitor checks data and size acknowledge (DSACK) or autovector
(AVEC
ternal bus error (BERR
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT) field in the system protection control register (SYPCR). Table 4-2 shows the periods allowed.
) signal response times during normal bus cycles. The monitor asserts the in-
) signal when the response time is excessively long.
Table 4-2 Bus Monitor Period
BMT Bus Monitor Time-out Period
00 64 System Clocks
01 32 System Clocks
10 16 System Clocks
11 8 System Clocks
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The monitor does not check DSACK
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.
4.2.8 Halt Monitor
The halt monitor responds to an assertion of the HALT
to 4.5.5.2 Double Bus Faults for more information. Halt monitor reset can be inhibited
by the halt monitor (HME) bit in SYPCR.
4.2.9 Spurious Interrupt Monitor
During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, recognizes the highest priority source, and then acquires a vector or responds to a request for autovectoring. The spurious interrupt monitor asserts the internal bus error signal (BERR
exception processing. The assertion of BERR
interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 4.7 Interrupts for further information. For detailed information about interrupt exception processing, refer to SECTION 5 CENTRAL PRO-
CESSING UNIT.
response on the external bus unless the CPU32
signal on the internal bus. Refer
) if no interrupt arbitration occurs during interrupt
causes the CPU32 to load the spurious
4.2.10 Software Watchdog
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
software service register SWSR on a periodic basis. If servicing does not take place,
the watchdog times out and asserts the reset signal.
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Perform a software watchdog service sequence as follows:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and software watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be selected. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
Table 4-3 MODCLK Pin and
SWP Bit During Reset
MODCLK SWP
0 (External Clock) 1 (÷ 512)
1 (Internal Clock) 0 (÷ 1)
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The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
Time-out Period
------------------------------------------------------------------------------------ -=
1
EXTAL Frequency Divide Ratio⁄
or
Time-out Period
Divide Ratio
------------------------------------------------ -=
EXTAL Frequency
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new timeout period can take effect.
Table 4-4 Software Watchdog Ratio
SWP SWT Ratio
000
001
010
011
100
101
110
111
9
2
11
2
13
2
15
2
18
2
20
2
22
2
24
2
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the periodic interrupt timer.
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SWP
PTP
FREEZE
EXTAL
LPSTOP
SWT1
SWT0
SWE
CLOCK
DISABLE
PRESCALER (29)
PRECLK
CLOCK
MUX
PITCLK
÷ 4
SWCLK
2
PITR
8-BIT MODULUS
COUNTER
15 STAGE
DIVIDER CHAIN (2
9
11213215
2
15
)
Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer
4.2.11 Periodic Interrupt Timer
The periodic interrupt timer allows the generation of interrupts of specific priority at predetermined intervals. This capability is often used to schedule control system tasks
that must be performed within time constraints. The timer consists of a prescaler, a
modulus counter, and registers that determine interrupt timing, priority and vector assignment. Refer to SECTION 5 CENTRAL PROCESSING UNIT for further information
about interrupt exception processing.
The periodic interrupt modulus counter is clocked by a signal derived from the buffered
crystal oscillator (EXTAL) input pin unless an external frequency source is used. The
value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register
(PITR) determines system clock prescaling for the watchdog timer. One of two options, either no prescaling, or prescaling by a factor of 512, can be selected. The value
of PTP is affected by the state of the MODCLK pin during reset, as shown in Table 4-
5. System software can change PTP value.
PIT
INTERRUPT
RESET
PIT BLOCK
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Table 4-5 MODCLK Pin and
PTP Bit at Reset
MODCLK PTP
0 (External Clock) 1 (÷ 512)
1 (Internal Clock) 0 (÷ 1)
Either clock signal (EXTAL or EXTAL ÷ 512) is divided by four before driving the modulus counter (PITCLK). The modulus counter is initialized by writing a value to the periodic timer modulus (PITM) field in the PITR. A zero value turns off the periodic timer.
When the modulus counter value reaches zero, an interrupt is generated. The modulus counter is then reloaded with the value in PITM and counting repeats. If a new value is written to PITR, it is loaded into the modulus counter when the current count is
completed.
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Use the following expression to calculate timer period.
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PIT Period
Interrupt priority and vectoring are determined by the values of the periodic interrupt
request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt
control register (PICR).
Content of PIRQL is compared to the CPU32 interrupt priority mask to determine
whether the interrupt is recognized. Table 4-6 shows priority of PIRQL values. Because of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority. The periodic timer continues to run when the
interrupt is disabled.
Table 4-6 Periodic Interrupt Priority
PIRQL Priority Level
000 Periodic Interrupt Disabled
001 Interrupt Priority Level 1
010 Interrupt Priority Level 2
011 Interrupt Priority Level 3
100 Interrupt Priority Level 4
101 Interrupt Priority Level 5
110 Interrupt Priority Level 6
111 Interrupt Priority Level 7
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number used to calculate the address
of the appropriate exception vector in the exception vector table. Reset value of the
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
4.2.12 Low-Power Stop Operation
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSIM bit in the SIMCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop.
PIT Modulus()Prescaler Value()4()
----------------------------------------------------------------------------------------------=
EXTAL Frequency
During low-power stop, the clock input to the software watchdog timer is disabled and
the timer stops. The software watchdog begins to run again on the first rising clock
edge after low-power stop ends. The watchdog is not reset by low-power stop. A service sequence must be performed to reset the timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external
interrupt request, can bring the MCU out of the low-power stop condition if it has a
higher priority than the interrupt mask value stored in the clock control logic when lowpower stop is initiated. LPSTOP can be terminated by a reset.
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4.2.13 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted internally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt
timer are affected. The halt monitor and spurious interrupt monitor continue to operate
normally. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus
monitor when FREEZE is asserted, and setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted. When FRZSW is set, FREEZE assertion must be at least two
times the PIT clock source period to ensure an accurate number of PIT counts.
4.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
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support changes in clock rate during operation.
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The system clock signal can be generated in one of three ways. An internal phaselocked loop can synthesize the clock from either an internal reference or an external
reference, or the clock signal can be input from an external frequency source. Keep
these clock sources in mind while reading the rest of this section. Figure 4-4 is a block
diagram of the system clock. Refer to APPENDIX A ELECTRICAL CHARACTERIS-
TICS for clock specifications.
EXTAL XTAL XFC
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
LOW-PASS
FILTER
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
V
DDSYN
VCO
W
Y
X
SYSTEM
CLOCK
CLKOUT
32 PLL BLOCK
Figure 4-4 System Clock Block Diagram
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4.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source.
When MODCLK is held high during reset, the clock synthesizer generates a clock signal from either an internal or an external reference frequency — the clock synthesizer
control register (SYNCR) determines operating frequency and mode of operation.
When MODCLK is held low during reset, the clock synthesizer is disabled and an external system clock signal must be applied — SYNCR control bits have no effect.
To generate a reference frequency using the internal oscillator a reference crystal
must be connected between the EXTAL and XTAL pins. Figure 4-5 shows a recommended circuit.
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C1
22 pF*
C2
22 pF*
V
SSI
Resistance and capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
*
Specific components must be based on crystal type. Contact crystal vendor for exact circuit.
R1
330k
XTAL
R2
10M
EXTAL
32 OSCILLATOR
Figure 4-5 System Clock Oscillator Circuit
If an external reference signal or an external system clock signal is applied via the EXTAL pin, the XTAL pin must be left floating. External reference signal frequency must
be less than or equal to maximum specified reference frequency. External system
clock signal frequency must be less than or equal to maximum specified system clock
frequency.
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during
reset), the duty cycle of the input is critical, especially at operating frequencies close
to maximum. The relationship between clock signal duty cycle and clock signal period
is expressed:
Minimum External Clock Period =
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Minimum External Clock High Low Time⁄
50% Percentage Variation of External Clock Input Duty Cycle–
4.3.2 Clock Synthesizer Operation
V
DDSYN
is used to power the clock circuits when either an internal or an external reference frequency is applied. A separate power source increases MCU noise immunity
and can be used to run the clock when the MCU is powered down. A quiet power sup-
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ply must be used as the V
DDSYN
be placed as close as possible to the V
cy. When an external system clock signal is applied and the PLL is disabled, V
should be connected to the VDD supply. Refer to the
source. Adequate external bypass capacitors should
DDSYN
pin to assure stable operating frequen-
DDSYN
SIM Reference Manual
(SIMRM/
AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain
a 50% clock duty cycle, VCO frequency is either two or four times system clock frequency, depending on the state of the X bit in SYNCR. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a
phase comparator. The other phase comparator input is a reference signal, either from
the crystal oscillator or from an external source. The comparator generates a control
signal proportional to the difference in phase between the two inputs. The signal is lowpass filtered and used to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock
stability. Figure 4-6 shows two recommended filters. XFC pin leakage must be as
specified in APPENDIX A ELECTRICAL CHARACTERISTICS to maintain optimum
stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled. The XFC pin must be left floating in this case.
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C3
0.1µF
C4
0.01µF
V
SSI
NORMAL OPERATING
ENVIRONMENT
1. Maintain low-leakage on the XFC node. See Appendix A electrical characteristics for more information.
2. Recommended loop filter for reduced sensitivity to low-frequency noise.
C1
0.1µF
XFC
V
DDSYN
C3
0.1µF
1
C4
0.01µF
V
SSI
HIGH-STABILITY OPERATING
C1
0.1µF
C2
0.01µF
ENVIRONMENT
R1
18kΩ
XFC
V
DDSYN
1, 2
16/32 XFC CONN
Figure 4-6 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time
is affected by the filter time constant and by the amount of difference between the two
comparator inputs. Whenever comparator input changes, the synthesizer must relock.
Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does
not come out of reset state until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time.
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When the clock synthesizer is used, control register SYNCR determines operating frequency and various modes of operation. The SYNCR W bit controls a three-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four. The
SYNCR Y field determines the count modulus for a modulo 64 down counter, causing
it to divide by a value of Y + 1. When W or Y values change, VCO frequency changes,
and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit that
is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is enabled, and system clock frequency is one-fourth VCO frequency; setting X disables
the divider, doubling clock speed without changing VCO speed. There is no relock delay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
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F
SYSTEM
F
REFERENCE
4Y 1+()2
()[]=
2W X+
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by
the W, X, and Y bits must be within the limits specified for the MCU. Do not use a combination of bit values that selects either an operating frequency or a VCO frequency
greater than the maximum specified values in APPENDIX A ELECTRICAL CHARAC-
TERISTICS.
Table 4-7 shows clock control multipliers for all possible combinations of SYNCR bits.
Table 4-8 shows clock frequencies available with a 32.768-kHz reference and a max-
imum specified clock frequency of 20.97 MHz.
Table 4-7 Clock Control Multipliers
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus Prescalers
Y [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
000000 4 8 16 32
000001 8 16 32 64
000010 12 24 48 96
011111 16 32 64 128
000011 20 40 80 160
000100 24 48 96 192
000101 28 56 112 224
000110 32 64 128 256
000111 36 72 144 288
001000 40 80 160 320
001001 44 88 176 352
001010 48 96 192 384
001011 52 104 208 416
001100 56 112 224 448
001101 60 120 240 480
001110 64 128 256 512
001111 68 136 272 544
010000 72 144 288 576
010001 76 152 304 608
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Table 4-7 Clock Control Multipliers (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus Prescalers
Y [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
010010 80 160 320 640
010011 84 168 336 672
010100 88 176 352 704
010101 92 184 368 736
010110 96 192 384 768
010111 100 200 400 800
011000 104 208 416 832
011001 108 216 432 864
011010 112 224 448 896
011011 116 232 464 928
011100 120 240 480 960
011101 124 248 496 992
011110 128 256 512 1024
100000 132 264 528 1056
100001 136 272 544 1088
100010 140 280 560 1120
100011 144 288 576 1152
100100 148 296 592 1184
100101 152 304 608 1216
100110 156 312 624 1248
100111 160 320 640 1280
101000 164 328 656 1312
101001 168 336 672 1344
101010 172 344 688 1376
101011 176 352 704 1408
101100 180 360 720 1440
101101 184 368 736 1472
101110 188 376 752 1504
101111 192 384 768 1536
110000 196 392 784 1568
110001 200 400 800 1600
110010 204 408 816 1632
110011 208 416 832 1664
110100 212 424 848 1696
110101 216 432 864 1728
110110 220 440 880 1760
110111 224 448 896 1792
111000 228 456 912 1824
111001 232 464 928 1856
111010 236 472 944 1888
111011 240 480 960 1920
111100 244 488 976 1952
111101 248 496 992 1984
111110 252 504 1008 2016
111111 256 512 1024 2048
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Table 4-8 System Frequencies from 32.768–kHz Reference
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus Prescaler
Y [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
000000 131 262 524 1049
000001 262 524 1049 2097
000010 393 786 1573 3146
000011 524 1049 2097 4194
000100 655 1311 2621 5243
000101 786 1573 3146 6291
000110 918 1835 3670 7340
000111 1049 2097 4194 8389
001000 1180 2359 4719 9437
001001 1311 2621 5243 10486
001010 1442 2884 5767 11534
001011 1573 3146 6291 12583
001100 1704 3408 6816 13631
001101 1835 3670 7340 14680
001110 1966 3932 7864 15729
001111 2097 4194 8389 16777
010000 2228 4456 8913 17826
010001 2359 4719 9437 18874
010010 2490 4981 9961 19923
010011 2621 5243 10486 20972
010100 2753 5505 11010
010101 2884 5767 11534
010110 3015 6029 12059
010111 3146 6291 12583
011000 3277 6554 13107
011001 3408 6816 13631
011010 3539 7078 14156
011011 3670 7340 14680
011100 3801 7602 15204
011101 3932 7864 15729
011110 4063 8126 16253
011111 4194 8389 16777
100000 4325 8651 17302
100001 4456 8913 17826
100010 4588 9175 18350
100011 4719 9437 18874
100100 4850 9699 19399
100101 4981 9961 19923
100110 5112 10224 20447
100111 5243 10486 20972
101000 5374 10748
101001 5505 11010
101010 5636 11272
101011 5767 11534
101100 5898 11796
21496 42992
22020 44040
22544 45089
23069 46137
23593 47186
22020
23069
24117
25166
26214
27263
28312
29360
30409
31457
32506
33554
34603
35652
36700
37749
38797
39846
40894
41943
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Table 4-8 System Frequencies from 32.768–kHz Reference (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus Prescaler
Y [W:X] = 00 [W:X] = 01 [W:X] = 10 [W:X] = 11
101101 6029 12059 24117 48234
101110 6160 12321
101111 6291 12583
110000 6423 12845
110001 6554 13107
110010 6685 13369
110011 6816 13631
110100 6947 13894
110101 7078 14156
110110 7209 14418
110111 7340 14680
111000 7471 14942
111001 7602 15204
111010 7733 15466
111011 7864 15729
111100 7995 15991
111101 8126 16253
111110 8258 16515
111111 8389 16777
24642 49283
25166 50332
25690 51380
26214 52428
26739 53477
27263 54526
27787 55575
28312 56623
28836 57672
29360 58720
2988 59769
30409 60817
30933 61866
31457 62915
31982 63963
32506 65011
33030 66060
33554 67109
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4.3.3 External Bus Clock
The state of the external clock division bit (EDIV) in SYNCR determines clock rate for
the external bus clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock
for MC6800 devices and peripherals. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The clock is enabled by the CS10
field in chip select pin assignment register 1 (CSPAR1). ECLK
operation during low-power stop is described in the following paragraph. Refer to 4.8
Chip Selects for more information about the external bus clock.
4.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selectively, the CPU can set the STOP bits in each module configuration register. To minimize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SIM brings the MCU out of
low-power operation when either an interrupt of higher priority than the stored mask or
a reset occurs. Refer to 4.5.4.2 LPSTOP Broadcast Cycle and SECTION 5 CEN-
TRAL PROCESSING UNIT for more information.
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During a low-power stop, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET
and IRQ pins are clocked by SIMCLK. The SIM can also continue to generate
the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external
clock (STEXT) bits in SYNCR determine clock operation during low-power stop. Table
4-9 is a summary of the effects of STSIM and STEXT. MODCLK value is the logic level
on the MODCLK pin during the last reset before LPSTOP execution. Any clock in the
off state is held low. If the synthesizer VCO is turned off during LPSTOP, there is a
PLL relock delay after the VCO is turned back on.
Table 4-9 Clock Control
Mode Pins SYNCR Bits Clock Status
LPSTOP MODCLK EXTAL STSIM STEXT SIMCLK CLKOUT ECLK
No 0 External
Clock
Yes 0 External
Clock
Yes 0 External
Clock
Yes 0 External
Clock
Yes 0 External
Clock
No 1 Crystal or
Reference
Yes 1 Crystal or
Reference
Yes 1 Crystal or
Reference
Yes 1 Crystal or
Reference
Yes 1 Crystal or
Reference
X X External
Clock
0 0 External
Clock
0 1 External
Clock
1 0 External
Clock
1 1 External
Clock
X X VCO VCO VCO
0 0 Crystal or
Reference
0 1 Crystal or
Reference
1 0 VCO Off Off
1 1 VCO VCO VCO
External
Clock
Off Off
External
Clock
Off Off
External
Clock
Off Off
Crystal/
Reference
External
Clock
External
Clock
External
Clock
Off
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4.3.5 Loss of Reference Signal
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when
clock logic detects a reference failure.
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced
into an operating condition referred to as limp mode. Limp mode frequency varies
from device to device, but maximum limp frequency does not exceed one half maximum system clock when X = 0, or maximum system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a reference signal. It is set when a reference failure is detected.
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4.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 4-7 shows a basic system with external memory and peripherals.
ASYNC BUS
FC
SIZ
CLKOUT
AS
DSACK
DS
CS3
CS5
IRQ
ADDR[23:0]
DATA[15:0]
MCU
CSBOOT
R/W
1
PERIPHERAL
SIZ
CLK
AS
DSACK
DS
CS
IACK
IRQ
ADDR[15:0]
DATA[15:0]
MEMORY
ADDR[23:0]
DATA[15:8]
CS
R/W
2
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MEMORY
ADDR[23:0]
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
2
32 EXAMPLE SYS BLOCK
Figure 4-7 MCU Basic System
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic
sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word
transfers. Ports are accessed through the use of asynchronous cycles controlled by
the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1
DSACK0
). Multiple bus cycles may be required for a transfer to or from an 8-bit port.
and
The maximum number of bits transferred during an access is referred to as port width.
Widths of eight and sixteen bits can be accessed by asynchronous bus cycles controlled by the data size (SIZ[1:0]) and the data and size acknowledge (DSACK[1:0]
signals. Multiple bus cycles may be required for a dynamically-sized transfer.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
can be synchronized with EBI transfers. Refer to 4.8 Chip Selects for more information.
)
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4.4.1 Bus Signals
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space it is to take
place in, the size of the transfer, and the type of cycle. External devices decode these
signals and respond to transfer data and terminate the bus cycle. The EBI operates in
an asynchronous mode for any port width.
4.4.1.1 Address Bus
Bus signals ADDR[23:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS
is asserted.
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4.4.1.2 Address Strobe
Address strobe (AS) is a timing signal that indicates the validity of an address on the
address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle.
4.4.1.3 Data Bus
Signals DATA[15:0] form a bidirectional, nonmultiplexed parallel bus that transfers
data to or from the MCU. A read or write operation can transfer eight or sixteen bits of
data in one bus cycle. During a read cycle, the data is latched by the MCU on the last
falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus
are driven, regardless of the port width or operand size. The MCU places the data on
the data bus one-half clock cycle after AS
4.4.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS
a read cycle. For a write cycle, DS
valid. The MCU asserts DS
cycle.
one full clock cycle after the assertion of AS during a write
signals an external device that data on the bus is
is asserted in a write cycle.
is asserted at the same time as AS during
4.4.1.5 Read/Write Signal
The read/write signal (R/W
This signal changes state, when required, at the beginning of a bus cycle, and is valid
while AS
cycle or vice versa. The signal may remain low for two consecutive write cycles.
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4-18 USER’S MANUAL
is asserted. R/W only transitions when a write cycle is preceded by a read
) determines the direction of the transfer during a bus cycle.
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4.4.1.6 Size Signals
Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while the address strobe (AS
) is asserted. Table 4-
10 shows SIZ0 and SIZ1 encoding.
Table 4-10 Size Signal Encoding
SIZ1 SIZ0 Transfer Size
0 1 Byte
1 0 Word
1 1 3 Byte
0 0 Long Word
4.4.1.7 Function Codes
The CPU generates function code output signals FC[2:0] to indicate the type of activity
occurring on the data or address bus. These signals can be considered address extensions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle.
Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
is asserted.
AS
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Table 4-11 shows address space encoding.
Table 4-11 Address Space Encoding
FC2 FC1 FC0 Address Space
0 0 0 Reserved
0 0 1 User Data Space
0 1 0 User Program Space
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Supervisor Data Space
1 1 0 Supervisor Program Space
1 1 1 CPU Space
The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed determine whether a memory access is to program or data space.
4.4.1.8 Data and Size Acknowledge Signals
During normal bus transfers, external devices assert the data and size acknowledge
signals (D
SACK[1:0]) to indicate port width to the MCU. During a read cycle, these signals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0]
can also be supplied internally by chip-select logic. Refer
to 4.8 Chip Selects for more information.
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4.4.1.9 Bus Error Signal
The bus error signal (BERR) is asserted when a bus cycle is not properly terminated
by DSACK
DSACK
ception Control Cycles for more information.
or AVEC assertion. BERR can also be asserted at the same time as
, provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Ex-
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The internal bus monitor can generate the BERR
ternal transfers. An external bus master must provide its own BERR
drive the BERR
transfers initiated by an external bus master. Refer to 4.5.6 External Bus Arbitration
for more information.
4.4.1.10 Halt Signal
The halt signa (HALT
to cause single bus cycle operation or (in combination with BERR
cle in error. The HALT
ing the use of external bus may continue executing, unaffected by the HALT
When the MCU completes a bus cycle with the HALT
placed in the high-impedance state, and bus control signals are driven inactive; the address, function code, size, and read/write signals remain in the same state. If HALT
still asserted once bus mastership is returned to the MCU, the address, function code,
size, and read/write signals are again driven to their previous states. The MCU does
not service interrupt requests while it is halted. Refer to 4.5.5 Bus Exception Control
Cycles for further information.
4.4.1.11 Autovector Signal
The autovector signal (AVEC
edge cycles. Assertion of AVEC
cate an interrupt handler routine. If it is continuously asserted, autovectors are
generated for all external interrupt requests. AVEC
cles. Refer to 4.7 Interrupts for more information. AVEC
quests can also be supplied internally by chip-select logic. Refer to 4.8 Chip Selects
for more information. The autovector function is disabled when there is an external bus
master. Refer to 4.5.6 External Bus Arbitration for more information.
pin, because the internal BERR monitor has no information about
) can be asserted by an external device for debugging purposes
signal affects external bus cycles only, so a program not requir-
) can be used to terminate external interrupt acknowl-
causes the CPU32 to generate vector numbers to lo-
signal for internal and internal-to-ex-
generation and
) a retry of a bus cy-
signal asserted, DATA[15:0] is
is ignored during all other bus cy-
for external interrupt re-
signal.
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4.4.2 Dynamic Bus Sizing
The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During an operand transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK
shown in Table 4-12. Chip-select logic can generate data and size acknowledge signals for an external device. Refer to 4.8 Chip Selects for further information.
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Table 4-12 Effect of DSACK
DSACK1 DSACK0 Result
1 1 Insert Wait States in Current Bus Cycle
1 0 Complete Cycle — Data Bus Port Size is 8 Bits
0 1 Complete Cycle — Data Bus Port Size is 16 Bits
0 0 Reserved
Signals
If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK
instance, a 16-bit device always returns DSACK
signals to indicate the port width. For
for a 16-bit port (regardless of wheth-
er the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins.
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Operand bytes are designated as shown in Figure 4-8. OP[0:3] represent the order of
access. For instance, OP0 is the most significant byte of a long-word operand, and is
accessed first, while OP3, the least significant byte, is accessed last. The two bytes of
a word-length operand are OP0 (most significant) and OP1. The single byte of a bytelength operand is OP0.
Operand Byte Order
31 24 23 16 15 8 7 0
Long Word OP0 OP1 OP2 OP3
Three Byte OP0 OP1 OP2
Word OP0 OP1
Byte OP0
Figure 4-8 Operand Byte Order
4.4.3 Operand Alignment
The EBI data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit
bus and routes them to their required positions. Positioning of bytes is determined by
the size and address outputs. SIZ1 and SIZ0 indicate the remaining number of bytes
to be transferred during the current bus cycle. The number of bytes transferred is equal
to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base.
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4.4.4 Misaligned Operands
CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned
when it overlaps a word boundary. This is determined by the value of ADDR0. When
ADDR0 = 0 (an even address), the address is on a word and byte boundary. When
ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand
is aligned at any address; a word or long-word operand is misaligned at an odd address.
The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word is transferred on a following bus cycle.
4.4.5 Operand Transfer Cases
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
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cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.
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Table 4-13 Operand Transfer Cases
Read Cycles Write Cycles
Nu
m
1 Byte to 8-Bit Port (Even/Odd) 01 X 10 OP0 — OP0 (OP0) —
2 Byte to 16-Bit Port (Even) 01 0 01 OP0 — OP0 (OP0) —
3 Byte to 16-Bit Port (Odd) 01 1 01 — OP0 (OP0) OP0 —
4 Word to 8-Bit Port (Aligned) 10 0 10 OP0 — OP0 (OP1) 1
5 Word to 8-Bit Port (Misaligned)
6 Word to 16-Bit Port (Aligned) 10 0 11 OP0 OP1 OP0 OP1 —
7 Word to 16-Bit Port (Misaligned)
8 Long Word to 8-Bit Port (Aligned) 00 0 10 OP0 — OP0 (OP1) 13
9 Long Word to 8-Bit Port (Misaligned)
10 Long Word to 16-Bit Port (Aligned) 00 0 01 OP0 OP1 OP0 OP1 6
11 Long Word to 16-Bit Port
(Misaligned)
12 3 Byte to 8-Bit Port (Aligned)
13 3 Byte to 8-Bit Port (Misaligned)
NOTES:
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
Transfer Case SIZ
1
1
1
2
2
[1:0]
10 1 10 OP0 — OP0 (OP0) 1
10 1 01 — OP0 (OP0) OP0 2
1
10 1 10 OP0 — OP0 (OP0) 12
10 1 01 — OP0 (OP0) OP0 2
11 0 10 OP0 — OP0 (OP1) 5
11 1 10 OP0 — OP0 (OP0) 4
ADDR0 DSACK
[1:0]
DATA
[15:8]
DATA
[7:0]
DATA
[15:8]
DATA
[7:0]
Next
Cycle
4.5 Bus Operation
Internal microcontroller modules are typically accessed in two system clock cycles,
with no wait states. Regular external bus cycles use handshaking between the MCU
and external peripherals to manage transfer size and data. These accesses take three
system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
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Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Chip-select logic can
also be used to insert wait states before internal generation of handshaking signals.
Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the
RM/AD) for more information about each type of bus cycle.
The MCU is responsible for de-skewing signals it issues at both the start and the end
of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data
signals from peripheral devices.
4.5.1 Synchronization to CLKOUT
External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
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interpreted relative to the MCU system clock output (CLKOUT).
SIM Reference Manual
(SIM-
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Descriptions are made in terms of individual system clock states, labeled {S0, S1,
S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and
does not correspond to any implemented machine state. A clock cycle consists of two
successive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
more information.
Bus cycles terminated by DSACK
OUT cycles. To support systems that use CLKOUT to generate DSACK
puts, asynchronous input setup time and asynchronous input hold times are specified.
When these specifications are met, the MCU is guaranteed to recognize the appropriate signal on a specific edge of the CLKOUT signal.
For a read cycle, when assertion of DSACK
of the clock, valid data is latched into the MCU on the next falling clock edge, provided
that the data meets the data setup time. In this case, the parameter for asynchronous
operation can be ignored.
When a system asserts DSACK
and obeys the bus protocol by maintaining DSACK
throughout the clock edge that negates AS
runs at the maximum speed of three clocks per cycle.
assertion normally require a minimum of three CLK-
and other in-
is recognized on a particular falling edge
for the required window around the falling edge of S2
and BERR or HALT until and
, no wait states are inserted. The bus cycle
To ensure proper operation in a system synchronized to CLKOUT, when either BERR
or BERR
must satisfy the appropriate data-in setup and hold times before the falling edge of the
clock cycle after DSACK
4.5.2 Regular Bus Cycles
The following paragraphs contain a discussion of cycles that use external bus control
logic. Refer to 4.5.3 Fast Termination Cycles for information about fast cycles.
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-23
and HALT is asserted after DSACK, BERR (or BERR and HALT) assertion
is recognized.
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To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ
signals and ADDR0 are externally decoded to select the active portion of the data bus
(refer to 4.4.2 Dynamic Bus Sizing). When AS
device either places data on the bus (read cycle) or latches data from the bus (write
cycle), then asserts a DSACK[1:0]
The DSACK[1:0] signals can be asserted before the data from a peripheral device is
valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period
between DSACK
There is no specified maximum for the period between the assertion of AS and
DSACK
the cycle is terminated with DSACK
ments until either DSACK
. Although the MCU can transfer data in a minimum of three clock cycles when
assertion and DS assertion is specified.
, DS, and R/W are valid, a peripheral
combination that indicates port size.
, the MCU inserts wait cycles in clock period incre-
signal goes low.
NOTE
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The SIM bus monitor asserts BERR
predetermined limit. Bus monitor period is determined by the BMT
field in SYPCR. The bus monitor cannot be disabled; maximum monitor period is 64 system clock cycles.
If no peripheral responds to an access, or if an access is invalid, external logic should
assert the BERR
asserted simultaneously, the CPU32 acts as though only BERR
mination signals are not asserted within a specified period, the bus monitor terminates
the cycle.
4.5.2.1 Read Cycle
During a read cycle, the MCU transfers data from an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
read two bytes at once. For a byte operation, the MCU reads one byte. The portion of
the data bus from which each byte is read depends on operand size, peripheral address, and peripheral port size. Figure 4-9 is a flowchart of a word read cycle. Refer
to 4.4.2 Dynamic Bus Sizing, 4.4.4 Misaligned Operands, and the
Manual
(SIMRM/AD) for more information.
or HALT signals to abort the bus cycle (when BERR and HALT are
when response time exceeds a
is asserted). If bus ter-
SIM Reference
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4-24 USER’S MANUAL
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MCU PERIPHERAL
ADDRESS DEVICE (S0)
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1) SET R/W
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
TO READ
ASSERT AS AND DS (S1)
DECODE DSACK (S3)
LATCH DATA (S4)
NEGATE AS
START NEXT CYCLE (S0)
AND DS (S5)
Figure 4-9 Word Read Cycle Flowchart
PRESENT DATA (S2)
1) DECODE ADDR, R/W, SIZ[1:0], DS
2) PLACE DATA ON DATA[15:0] OR
DATA[15:8] IF 8-BIT DATA
3) DRIVE DSACK SIGNALS
TERMINATE CYCLE (S5)
1) REMOVE DATA FROM DATA BUS
2) NEGATE DSACK
RD CYC FLOW
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4.5.2.2 Write Cycle
During a write cycle, the MCU transfers data to an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to
write two bytes at once. For a byte operation, the MCU writes one byte. The portion of
the data bus upon which each byte is written depends on operand size, peripheral address, and peripheral port size.
Refer to 4.4.2 Dynamic Bus Sizing and 4.4.4 Misaligned Operands for more information. Figure 4-10 is a flowchart of a write-cycle operation for a word transfer. Refer
to the
SIM Reference Manual
(SIMRM/AD) for more information.
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-25
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MCU PERIPHERAL
ADDRESS DEVICE (S0)
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1) SET R/W
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
1) NEGATE DS
2) REMOVE DATA FROM DATA BUS
TO WRITE
ASSERT AS (S1)
PLACE DATA ON DATA[15:0] (S2)
ASSERT DS AND WAIT FOR DSACK (S3)
OPTIONAL STATE (S4)
NO CHANGE
TERMINATE OUTPUT TRANSFER (S5)
AND AS
START NEXT CYCLE
Figure 4-10 Write Cycle Flowchart
ACCEPT DATA (S2 + S3)
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
TERMINATE CYCLE
1) NEGATE DSACK
WR CYC FLOW
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4.5.3 Fast Termination Cycles
When an external device has a fast access time, the chip-select circuit fast-termination
option can provide a two-cycle external bus transfer. Because the chip-select circuits
are driven from the system clock, the bus cycle termination is inherently synchronized
with the system clock.
If multiple chip selects are to be used to select the same device that can support fast
termination, and match conditions can occur simultaneously, program the DSACK
field in each associated chip-select option register for fast termination. Alternately, program one DSACK
field for fast termination and the remaining DSACK fields for exter-
nal termination.
Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
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4-26 USER’S MANUAL
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When AS, DS, and R/W are valid, a peripheral device either places data on the bus
(read cycle) or latches data from the bus (write cycle). At the appropriate time, chipselect logic asserts data and size acknowledge signals.
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The DSACK
nally generated DSACK
option fields in the chip-select option registers determine whether inter-
or externally generated DSACK are used. For fast termination
cycles, the F-term encoding (%1110) must be used. Refer to 4.8.1 Chip-Select Reg-
isters for information about fast-termination setup.
To use fast-termination, an external device must be fast enough to have data ready,
within the specified setup time, by the falling edge of S4. Refer to APPENDIX A ELEC-
TRICAL CHARACTERISTICS for tabular information about fast termination timing.
When fast termination is in use, DS
is asserted during read cycles but not during write
cycles. The STRB field in the chip-select option register used must be programmed
with the address strobe encoding to assert the chip select signal for a fast-termination
write.
4.5.4 CPU Space Cycles
Function code signals FC[2:0] designate which of eight external address spaces is accessed during a bus cycle. Address space 7 is designated CPU space. CPU space is
used for control information not normally associated with read or write bus cycles.
Function codes are valid only while AS
is asserted. Refer to 4.4.1.7 Function Codes
for more information on codes and encoding.
During a CPU space access, ADDR[19:16] are encoded to reflect the type of access
being made. Figure 4-11 shows the three encodings used by 68300 family microcontrollers. These encodings represent breakpoint acknowledge (Type $0) cycles, low
power stop broadcast (Type $3) cycles, and interrupt acknowledge (Type $F) cycles.
Refer to 4.7 Interrupts for information about interrupt acknowledge bus cycles.
CPU SPACE CYCLES
BREAKPOINT
ACKNOWLEDGE
LOW POWER
STOP BROADCAST
FUNCTION
CODE
20
111
20
111
1923 16
0000000000000000000 T0BKPT#
19 1623
000000111111111111111110
ADDRESS BUS
0
241
0
INTERRUPT
ACKNOWLEDGE
20
11111111111111111111 1111 LEVEL
19 1623
CPU SPACE
TYPE FIELD
0
CPU SPACE CYC TIM
Figure 4-11 CPU Space Address Encoding
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-27
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4.5.4.1 Breakpoint Acknowledge Cycle
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with the background debugging
mode. The following paragraphs discuss breakpoint processing when background debugging mode is not enabled. See SECTION 5 CENTRAL PROCESSING UNIT for
more information on exception processing and the background debugging mode.
In M68300 microcontrollers, both hardware and software can initiate breakpoints.
4.5.4.1.1 Software Breakpoints
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The CPU32 B
The CPU responds to this instruction by initiating a breakpoint-acknowledge read cycle in CPU space. It places the breakpoint acknowledge (%0000) code on ADDR[19:16], the breakpoint number (bits [2:0] of the BKPT opcode) in ADDR[4:2], and
%0 (indicating a software breakpoint) on ADDR1.
The external breakpoint circuitry decodes the function code and address lines and responds by either asserting BERR
asserting DSACK
If the bus cycle is terminated by DSACK, the CPU32 reads the instruction on the data
bus and inserts the instruction into the pipeline. (For 8-bit ports, this instruction fetch
may require two read cycles.)
If the bus cycle is terminated by BERR
exception processing: it acquires the number of the illegal-instruction exception vector,
computes the vector address from this number, loads the content of the vector address
into the PC, and jumps to the exception handler routine at that address.
4.5.4.1.2 Hardware Breakpoints
Assertion of the BKPT
tiating a breakpoint-acknowledge read cycle in CPU space. It places $00001E on the
address bus. (The breakpoint acknowledge code of %0000 is placed on ADDR[19:16],
the breakpoint number value of %111 is placed on ADDR[4:2], and ADDR1 is set to
one, indicating a hardware breakpoint.)
KPT instruction allows the user to insert breakpoints through software.
or placing an instruction word on the data bus and
.
, the CPU32 then performs illegal-instruction
input initiates a hardware breakpoint. The CPU responds by ini-
Fr
The external breakpoint circuitry decodes the function code and address lines, places
an instruction word on the data bus, and asserts BERR
ware breakpoint exception processing: it acquires the number of the hardware breakpoint exception vector, computes the vector address from this number, loads the
content of the vector address into the PC, and jumps to the exception handler routine
at that address. If the external device asserts DSACK
nores the breakpoint and continues processing.
When BKPT
breakpoint exception occurs at the end of that instruction. The prefetched instruction
is “tagged” with the breakpoint when it enters the instruction pipeline, and the breakpoint exception occurs after the instruction executes. If the pipeline is flushed before
MOTOROLA SYSTEM INTEGRATION MODULE MC68332
4-28 USER’S MANUAL
assertion is synchronized with an instruction prefetch, processing of the
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. The CPU then performs hard-
rather than BERR, the CPU ig-
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the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is synchronized with an operand fetch, exception processing occurs at the end of the instruction during which BKPT
is latched.
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Refer to the
(SIMRM/AD) for additional information.
ual
CPU32 Reference Manual
(CPU32RM/AD) and the
SIM Reference Man-
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MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-29
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CPU32 PERIPHERAL
ACKNOWLEDGE BREAKPOINT
IF BREAKPOINT INSTRUCTION EXECUTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS
IF BKPT PIN ASSERTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
BREAKPOINT OPERATION FLOW
IF BKPT INSTRUCTION EXECUTED:
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
OR:
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
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IF BREAKPOINT INSTRUCTION EXECUTED AND
DSACK IS ASSERTED:
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
IF BKPT PIN ASSERTED AND
DSACK IS ASSERTED:
1) NEGATE AS AND DS
2) GO TO (A)
IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO (B)
(A)
IF BKPT INSTRUCTION EXECUTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
IF BKPT PIN ASSERTED:
1) CONTINUE PROCESSING
IF BKPT INSTRUCTION EXECUTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
(B)
IF BKPT ASSERTED:
1) ASSERT DSACK
OR:
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) NEGATE DSACK or BERR
IF BKPT PIN ASSERTED:
1) INITIATE HARDWARE BREAKPOINT PROCESSING
1110A
Figure 4-12 Breakpoint Operation Flowchart
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4.5.4.2 LPSTOP Broadcast Cycle
Low-power stop is initiated by the CPU32. Individual modules can be stopped by setting the STOP bits in each module configuration register, or the SIM can turn off system clocks after execution of the LPSTOP instruction. When the CPU executes
LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power mode when either an interrupt of higher priority than the stored mask or a
reset occurs. Refer to and SECTION 5 CENTRAL PROCESSING UNIT for more information.
During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address
$3FFFE. This write puts a copy of the interrupt mask value in the clock control logic.
The mask is encoded on the data bus as shown in Figure 4-13. The LPSTOP CPU
space cycle is shown externally (if the bus is available) as an indication to external devices that the MCU is going into low-power stop mode. The SIM provides an internally
generated DSACK
for a fast write cycle.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 IP MASK
response to this cycle. The timing of this bus cycle is the same as
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Figure 4-13 LPSTOP Interrupt Mask Level
4.5.5 Bus Exception Control Cycles
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing occurs when bus cycles are not terminated in the expected manner. The internal bus
monitor can be used to generate BERR
taken. Bus cycles can also be terminated by assertion of the external BERR
signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 4-5, which indicates the results of each type of bus cycle termination.
Normal Termination
DSACK
Halt Termination
HALT
(case 2).
is asserted; BERR and HALT remain negated (case 1).
is asserted at the same time or before DSACK, and BERR remains negated
internally, causing a bus error exception to be
or HALT
Bus Error Termination
BERR
DSACK
DSACK
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-31
is asserted in lieu of, at the same time as, or before DSACK, or after
, and HALT remains negated; BERR is negated at the same time or after
.
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Retry Termination
HALT
after DSACK
negated at the same time or after BERR
and BERR are asserted in lieu of, at the same time as, or before DSACK or
; BERR is negated at the same time or after DSACK; HALT may be
.
Table 4-14 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
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Table 4-14 DSACK
Case
Number
1 DSACK
2 DSACK
3 DSACK
4 DSACK
5 DSACK
6 DSACK
NOTES:
N = The number of current even bus state (S2, S4, etc.).
A = Signal is asserted in this bus state.
NA = Signal is not asserted in this state
X = Don't care.
S = Signal was asserted in previous state and remains asserted in this state.
Control Signal Asserted on Rising
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
, BERR, and HALT Assertion Results
Edge of State
N N + 2
A
NA
NA
A
NA
A/S
NA/A
A
NA
A
A
NA
NA/A
A
A/S
A
NA
NA
S
NA
X
S
NA
S
X
S
X
X
S
NA
X
S
S
X
A
A
Normal termination.
Halt termination: normal cycle terminate and halt.
Continue when HALT
Bus error termination: terminate and take bus error
exception, possibly deferred.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Retry termination: terminate and retry when HALT is
negated.
Retry termination: terminate and retry when HALT is
negated.
Result
is negated.
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK
, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the required setup time and hold time for both of them are met for the same falling edge of
the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing
requirements.) External circuitry that provides these signals must be designed with
these constraints in mind, or else the internal bus monitor must be used.
DSACK
, BERR, and HALT may be negated after AS is negated.
WARNING
If DSACK
or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.
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4.5.5.1 Bus Errors
The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU detects assertion of the IMB BERR
monitor or an external source) while the HALT
BERR assertions do not force immediate exception processing. The signal is synchronized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR
tors:
signal (by the internal bus
signal remains negated.
detection/acknowledge is dependent upon several fac-
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• Which bus cycle of an instruction is terminated by assertion of BERR
• The number of bus cycles in the instruction during which BERR
• The number of bus cycles in the instruction following the instruction in which
BERR
• Whether BERR
cess.
Because of these factors, it is impossible to predict precisely how long after occurrence of a bus error the bus error exception is processed.
4.5.5.2 Double Bus Faults
Exception processing for bus error exceptions follows the standard exception processing sequence. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information about exceptions. However, a special case of bus error, called double bus fault,
can abort exception processing.
is asserted.
is asserted during a program space access or a data space ac-
CAUTION
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an instruction prefetch, the IMB precharge state (bus pulled high, or $FF)
is latched into the CPU32 instruction register, with indeterminate results.
.
is asserted.
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BERR
cleared by the first instruction of the BERR
in two ways:
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-33
assertion is not detected until an instruction is complete. The BERR latch is
exception handler. Double bus fault occurs
1. When bus error exception processing begins and a second BERR
before the first instruction of the first exception handler is executed.
2. When one or more bus errors occur before the first instruction after a RESET
exception is executed.
3. A bus error occurs while the CPU32 is loading information from a bus error
stack frame during a return from exception (RTE) instruction.
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Immediately after assertion of a second BERR, the MCU halts and drives the HALT
line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur
(refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after
exception processing has been completed (during the execution of the exception handler routine, or later) does not cause a double bus fault. The MCU continues to retry
the same bus cycle as long as the external hardware requests it.
4.5.5.3 Retry Operation
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When an external device asserts BERR
the retry sequence. A delayed retry can also occur. The MCU terminates the bus cycle,
places the AS
cycle until the BERR
nization delay, the MCU retries the previous cycle using the same address, function
codes, data (for a write), and control signals. The BERR
fore S2 of the read cycle to ensure correct operation of the retried cycle.
, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun
If BR
sequence but first relinquishes the bus to an external master. Once the external master returns the bus and negates BERR
This feature allows an external device to correct the problem that caused the bus error
and then try the bus cycle again.
The MCU retries any read or write cycle of an indivisible read-modify-write operation
separately; RMC
relinquish the bus while RMC
the bus and retry a bus cycle during a read-modify-write cycle must assert BERR
only (HALT must remain negated). The bus error handler software should examine
BR
the read-modify-write bit in the special status word and take the appropriate action to
resolve this type of fault when it occurs.
4.5.5.4 Halt Operation
When HALT
tivity after negation of DSACK
progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to
byte transfer, activity ceases after S2.
Negating and reasserting HALT
(bus cycle to bus cycle) operation. The HALT
so that a program that does not use external bus can continue executing. During dynamically-sized 8-bit transfers, external bus activity may not stop at the next cycle
boundary. Occurrence of a bus error while HALT
tiate a retry sequence.
and DS signals in their inactive state, and does not begin another bus
and HALT signals are negated by external logic. After a synchro-
remains asserted during the entire retry sequence. The MCU will not
is asserted. Any device that requires the MCU to give up
is asserted while BERR is not asserted, the MCU halts external bus ac-
. The MCU may complete the current word transfer in
according to timing requirements provides single-step
and HALT during a bus cycle, the MCU enters
signal should be negated be-
and HALT, the EBI runs the previous bus cycle.
signal affects external bus cycles only,
is asserted causes the CPU32 to ini-
and
When the MCU completes a bus cycle while the HALT
goes to high-impedance state and the AS
states. Address, function code, size, and read/write signals remain in the same state.
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signal is asserted, the data bus
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The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbitration). However, when external bus arbitration occurs while the MCU is halted, ad-
dress and control signals go to high-impedance state. If HALT
the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states. The MCU cannot service interrupt requests
while halted.
4.5.6 External Bus Arbitration
MCU bus design provides for a single bus master at any one time. Either the MCU or
an external device can be master. Bus arbitration protocols determine when an external device can become bus master. Bus arbitration requests are recognized during
normal processing, HALT
bus fault.
The bus controller in the MCU manages bus arbitration signals so that the MCU has
the lowest priority. External devices that need to obtain the bus must assert bus arbi-
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tration signals in the sequences described in the following paragraphs.
is still asserted when
assertion, and when the CPU has halted due to a double
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Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The protocol sequence is:
A. An external device asserts bus request signal (BR
B. The MCU asserts the bus grant signal (BG
C. An external device asserts the bus grant acknowledge (BGACK
cate that it has assumed bus mastership.
can be asserted during a bus cycle or between cycles. BG is asserted in response
BR
to BR
transfer. Additionally, BG
write operation (when RMC
If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG
when it assumes mastership, and must maintain BGACK assertion as long as it is bus
master.
Two conditions must be met for an external device to assume bus mastership. The device must receive BG
indicating that no other bus master is active. This technique allows the processing of
bus requests during data transfer cycles.
. To guarantee operand coherency, BG is only asserted at the end of operand
is not asserted until the end of an indivisible read-modify-
is negated).
through the arbitration process, and BGACK must be inactive,
) to indicate that the bus is available;
. An external device must assert BGACK
);
) signal to indi-
is negated a few clock cycles after BGACK transition. However, if bus requests are
BG
still pending after BG
This additional BG
master before the current master has released the bus.
Refer to Figure 4-14, which shows bus arbitration for a single device. The flowchart
shows BR
MC68332 SYSTEM INTEGRATION MODULE MOTOROLA
USER’S MANUAL 4-35
negated at the same time BGACK is asserted.
is negated, the MCU asserts BG again within a few clock cycles.
assertion allows external arbitration circuitry to select the next bus
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MCU REQUESTING DEVICE
REQUEST THE BUS
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GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG
TERMINATE ARBITRATION
1) NEGATE BG
BGACK TO BE NEGATED)
RE-ARBITRATE OR RESUME PROCESSOR
(AND WAIT FOR
OPERATION
)
1) ASSERT BUS REQUEST (BR
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
)
BUS ARB FLOW
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Figure 4-14 Bus Arbitration Flowchart for Single Request
State changes occur on the next rising edge of CLKOUT after the internal signal is valid. The BG
signal transitions on the falling edge of the clock after a state is reached
during which G changes. The bus control signals (controlled by T) are driven by the
MCU immediately following a state change, when bus mastership is returned to the
MCU. State 0, in which G and T are both negated, is the state of the bus arbiter while
the MCU is bus master. Request R and acknowledge A keep the arbiter in state 0 as
long as they are both negated.
4.5.6.1 Slave (Factory Test) Mode Arbitration
This mode is used for factory production testing of internal modules. It is not supported
as a user operating mode. Slave mode is enabled by holding DATA11 low during reset. In slave mode, when BG
is asserted, the MCU is slaved to an external master that
has full access to all internal registers.
4.5.6.2 Show Cycles
The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS
is not asserted exter-
nally during show cycles.
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Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show Internal Cycles). This field is cleared by reset. When show cycles are disabled, the
address bus, function codes, size, and read/write signals reflect internal bus activity,
but AS
pedance state during internal accesses.
and DS are not asserted externally and external data bus pins are in high-im-
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When show cycles are enabled, DS
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN encoding halts internal
bus activity while there is an external master.
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus conditions, and is indeterminate. During a byte write to an external address, the data multiplexer in the SIM causes the value of the byte that is written to be driven out on both
bytes of the data bus.
4.6 Reset
Reset occurs when an active low logic level on the RESE
The RESET
SET is asserted, reset does not occur until the clock starts. Resets are clocked to allow
completion of write cycles in progress at the time RESET
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The system
integration module determines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware modeselect inputs, then passes control to the CPU32.
4.6.1 Reset Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
vector base register (VBR). The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. The CPU32 uses vector
numbers to calculate displacement into the table. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information concerning exceptions.
input is synchronized to the system clock. If there is no clock when RE-
is asserted externally during internal cycles, and
T pin is clocked into the SIM.
is asserted.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset occurs at the end of a bus cycle, and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential reset tasks are performed during exception processing. Other initialization tasks must be accomplished by the exception
handler routine. 4.6.8 Reset Processing Summary contains details of exception processing.
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4.6.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate reset lines. Reset control logic can drive four different internal signals.
1. EXTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU has executed
a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchronous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure; thus the reset
control logic responds by asserting reset to the system immediately. (A system reset,
however, caused by the CPU32 RESET instruction, is asynchronous but does not indicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The internal bus monitor is automatically enabled for synchronous resets. When a bus cycle
does not terminate normally, the bus monitor terminates it.
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Refer to Table 4-15 for a summary of reset sources.
Table 4-15 Reset Source Summary
Type Source Timing Cause Reset Lines Asserted by
External External Synch External Signal MSTRST CLKRST EXTRST
Power Up EBI Asynch V
Software Watchdog Monitor Asynch Time Out MSTRST CLKRST EXTRST
HALT
Loss of Clock Clock Synch Loss of Reference MSTRST CLKRST EXTRST
Test Test Synch Test Mode MSTRST — EXTRST
System CPU32 Asynch RESET Instruction — — EXTRST
Monitor Asynch Internal HALT Assertion
(e.g. Double Bus Fault)
DD
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
Controller
Internal single byte or aligned word writes are guaranteed valid for synchronous resets. External writes are also guaranteed to complete, provided the external configuration logic on the data bus is conditioned as shown in Figure 4-13.
4.6.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT
pin determines what happens during subsequent breakpoint as-
sertions. Table 4-16 is a summary of reset mode selection options.
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Table 4-16 Reset Mode Selection
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Mode Select Pin Default Function
DATA0 CSBOOT
DATA1 CS0
DATA2 CS3
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8 DSACK[1:0]
DATA9 IRQ[7:1]
DATA11 Test Mode Disabled Test Mode Enabled
MODCLK VCO = System Clock EXTAL = System Clock
BKPT
Background Mode Disabled Background Mode Enabled
4.6.3.1 Data Bus Mode Selection
(Pin Left High)
16-Bit CSBOOT 8-Bit
CS1
CS2
CS4
CS5
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
,
AVEC
, DS, AS,
SIZE
MODCLK
Alternate Function
(Pin Pulled Low)
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
PORTF
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All data lines have weak internal pull-up drivers. When pins are held high by the internal drivers, the MCU uses a default operating configuration. However, specific lines
can be held low externally to achieve an alternate configuration.
NOTE
External bus loading can overcome the weak internal pull-up drivers
on data bus lines, and hold pins low during reset.
Use an active device to hold data bus lines low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET
is released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven lines may be required. Figure 4-15 shows a recommended method
for conditioning the mode select signals.
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LINES
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DATA15
•
•
•
•
•
DATA1
•
DATA0
VDDV
DD
•
•
•
•
•
•
* * *
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DS
R/W
*Optional, to prevent conflict on RESET negation.
•••••
•
DATA BUS MODE DECODE
Figure 4-15 Data Bus Mode Select Conditioning
Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARACTERISTICS. Do not confuse pin function with pin electrical state. Refer to 4.6.5 Pin
State During Reset for more information.
DATA0 determines the function of the boot ROM chip-select signal (CSBOOT
other chip-select signals, C
SBOOT is active at the release of reset. During reset ex-
). Unlike
ception processing, the MCU fetches initialization vectors beginning at address
$000000 in supervisor program space. An external memory device containing vectors
located at these addresses can be enabled by CSBOOT
after a reset. The logic level
of DATA0 during reset selects boot ROM port size for dynamic bus allocation. When
DATA0 is held low, port size is eight bits; when DATA0 is held high, either by the weak
internal pull-up driver or by an external pull-up, port size is 16 bits. Refer to 4.8.4 Chip-
Select Reset Operation for more information.
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DATA1 and DATA2 determine the functions of CS[2:0]
and CS[5:3], respectively. DATA[7:3] determine the functions of an associated chip select and all lower-numbered
chip-selects down through CS6
CS[8:6]
are assigned alternate function as ADDR[21:19], and CS[10:9] remain chip-
. For example, if DATA5 is pulled low during reset,
selects. Refer to 4.8.4 Chip-Select Reset Operation for more information.
DATA8 determines the function of the DSACK[1:0]
, AVEC, DS, AS, and SIZE pins. If
DATA8 is held low during reset, these pins are assigned to I/O port E.
DATA9 determines the function of interrupt request pins IRQ[7:0]
and the clock mode
select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned
to I/O port F.
DATA11 determines whether the SIM operates in test mode out of reset. This capability is used for factory testing of the MCU.
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4.6.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency. When MODCLK is held low during reset, the clock synthesizer is disabled, and an external system clock signal must be applied. Refer to 4.3
System Clock for more information.
The MODCLK pin can also be used as parallel I/O pin PF0. To prevent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
4.6.3.3 Breakpoint Mode Selection
NOTE
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The MCU uses internal and external breakpoint (BKPT
tion processing, at the release of the R
to determine how to handle breakpoints.
If either BKPT
and the CPU32 enters background debugging mode whenever either BKPT
subsequently asserted.
If both BKPT
cessing begins whenever either BKPT
Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information on background debugging mode and exceptions. Refer to 4.5.4 CPU Space Cycles for information concerning breakpoint acknowledge bus cycles.
4.6.4 MCU Module Pin Function During Reset
Usually, module pins default to port functions, and input/output ports are set to input
state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 4-17 is a summary of module pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
signal is at logic level zero when sampled, an internal BDM flag is set,
inputs are at logic level one when sampled, breakpoint exception pro-
ESET signal, the CPU32 samples these signals
signal is subsequently asserted.
) signals. During reset excep-
input is
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Table 4-17 Module Pin Functions
Module Pin Mnemonic Function
CPU32 DSI/IFETCH
DSO/IPIPE DSO/IPIPE
BKPT/DSCLK BKPT/DSCLK
GPT PGP7/IC4/OC5 Discrete Input
PGP[6:3]/OC[4:1] Discrete Input
PGP[2:0]/IC[3:1] Discrete Input
PAI Discrete Input
PCLK Discrete Input
PWMA, PWMB Discrete Output
QSM PQS7/TXD Discrete Input
PQS[6:4]/PCS[3:1] Discrete Input
PQS3/PCS0/SS
PQS2/SCK Discrete Input
PQS1/MOSI Discrete Input
PQS0/MISO Discrete Input
RXD RXD
DSI/IFETCH
Discrete Input
4.6.5 Pin State During Reset
It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin
driver can be active, inactive or in high-impedance state while reset occurs. During
power-up reset, pin state is subject to the constraints discussed in 4.6.7 Power-On
Reset.
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NOTE
Pins that are not used should either be configured as outputs, or (if
configured as inputs) pulled to the appropriate inactive state. This decreases additional I
caused by digital inputs floating near mid-sup-
DD
ply level.
4.6.5.1 Reset States of SIM Pins
Generally, while RESET
state or are driven to their inactive states. After RESET
is asserted, SIM pins either go to an inactive high-impedance
is released, mode selection
occurs, and reset exception processing begins. Pins configured as inputs during reset
become active high-impedance loads after RESET
is released. Inputs must be driven
to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins configured as outputs begin to function after RESET
is released. Table 4-18 is a summary
of SIM pin states during reset.
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Table 4-18 SIM Pin Reset States
State While Pin State After RESET Released
Mnemonic RESET
Asserted
/ADDR23 1 CS10 1 ADDR23 Unknown
CS10
CS[9:6]
/ADDR[22:19]/PC[6:3] 1 CS[9:6] 1 ADDR[22:19] Unknown
ADDR[18:0] High-Z Output ADDR[18:0] Unknown ADDR[18:0] Unknown
AS
/PE5 High-Z Output AS Output PE5 Input
AVEC
/PE2 Disabled AVEC Input PE2 Input
BERR
CSM
/BG 1 CSM 1BG1
CSE
/BGACK 1 CSE 1 BGACK Input
CS0
/BR 1 CS0 1BRInput
CLKOUT Output CLKOUT Output CLKOUT Output
CSBOOT
DATA[15:0] Mode Select DATA[15:0] Input DATA[15:0] Input
DS
/PE4 Disabled DS Output PE4 Input
DSACK0
DSACK1
CS5
CS3
IRQ[7:1]
MODCLK/PF0 Mode Select MODCLK Input PF0 Input
SIZ[1:0]/PE[7:6] Disabled SIZ[1:0] Unknown PE[7:6] Input
/PE0 Disabled DSACK0 Input PE0 Input
/PE1 Disabled DSACK1 Input PE1 Input
/FC2/PC2 1 CS5 1 FC2 Unknown
FC1/PC1 1 FC1 1 FC1 Unknown
/FC0/PC0 1 CS3 1 FC0 Unknown
HALT
/PF[7:1] Disabled IRQ[7:1] Input PF[7:1] Input
R/W
RESET
RMC
TSC Mode Select TSC Input TSC Input
Disabled BERR Input BERR Input
Disabled HALT Input HALT Input
Disabled R/W Output R/W Output
Asserted RESET Input RESET Input
Disabled RMC Output PE3 Input
1 CSBOOT 0 CSBOOT 0
Pin
Function
Pin State Pin
Function
Pin State
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
As a rule, module pins that are assigned to general-purpose I/O ports go to active highimpedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
4.6.6 Reset Timing
The RESE
External RESET
T input must be asserted for a specified minimum period for reset to occur.
assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET
is asserted, SIM pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET
an additional 512 CLKOUT cycles after it detects that the RESET
signal is no longer
pin low for
being externally driven, to guarantee this length of reset to the entire system.
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If an internal source asserts a reset signal, the reset control logic asserts RESET for
a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles,
the control logic continues to assert RESET
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the reset input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the reset
input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for ten cycles, then it is tested again. The process repeats until RESET
4.6.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to clock synthesizer power input pin V
V
DDSYN
When V
rameters and by oscillator circuit design. V
ing reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and
timing specifications.
DDSYN
is applied before and during reset, which minimizes crystal start-up time.
DDSYN
for the MCU to operate. The following discussion assumes that
is applied at power-on, start-up time is affected by specific crystal pa-
until the internal reset signal is negated.
is released.
ramp-up time also affects pin state dur-
DD
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During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The circuit releases MSTRST as V
the minimum specified value, and SIM pins are initialized as shown in Table 4-19. As
reaches specified minimum value, the clock synthesizer VCO begins operation
V
DD
and clock frequency ramps up to specified limp mode frequency. The external RESET
line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles
elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 4-16 is a timing diagram of power-up reset. It shows the relationships between
RESET
ramp time and VCO frequency ramp time determine how long the four cy-
DD
, VDD, and bus signals.
ramps up to
DD
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CLKOUT
VCO
LOCK
V
DD
RESET
BUS
CYCLES
NOTES:
BUS STATE
UNKNOWN
1. Internal start-up time.
2. SSP fetched.
3. PC fetched.
4. First instruction fetched.
CONTROL SIGNALS
THREE-STATED
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512 CLOCKS
ADDRESS AND
10 CLOCKS
1
32
4
32 POR TIM
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Figure 4-16 Power-On Reset
4.6.8 Reset Processing Summary
To prevent write cycles in progress from being corrupted, a reset is recognized at the
end of a bus cycle, and not at an instruction boundary. Any processing in progress at
the time a reset occurs is aborted. After SIM reset control logic has synchronized an
internal or external reset request, it asserts the MSTRST signal.
The following events take place when MSTRST is asserted.
A. Instruction execution is aborted.
B. The status register is initialized.
1. The T0 and T1 bits are cleared to disable tracing.
2. The S bit is set to establish supervisor privilege level.
3. The interrupt priority mask is set to $7, disabling all interrupts below priority
7.
C. The vector base register is initialized to $000000.
The following events take place when MSTRST is negated after assertion.
A. The CPU32 samples the BKPT
input.
B. The CPU32 fetches the reset vector:
1. The first long word of the vector is loaded into the interrupt stack pointer.
2. The second long word of the vector is loaded into the program counter.
Vectors can be fetched from internal RAM or from external ROM enabled by the
CSBOOT
signal.
C. The CPU32 fetches and begins decoding the first instruction to be executed.
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4.6.9 Reset Status Register
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when the RESET
to APPENDIX D REGISTER SUMMARY.
4.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the system integration module, the central processing unit, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process.
Chip-select logic can also be used to respond to interrupt requests. Refer to 4.8 Chip
Selects for more information.
4.7.1 Interrupt Exception Processing
signal is released. Refer
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The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing. Each exception has an assigned vector in
an exception vector table that points to an associated handler routine. The CPU uses
vector numbers to calculate displacement into the table. During exception processing,
the CPU fetches the appropriate vector and executes the exception handler routine to
which the vector points.
Out of reset, the exception vector table is located beginning at address $000000. This
value can be changed by programming the vector base register (VBR) with a new value, and multiple vector tables can be used. Refer to SECTION 5 CENTRAL PRO-
CESSING UNIT for more information concerning exceptions.
4.7.2 Interrupt Priority and Recognition
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less
than seven can be masked by the interrupt priority (IP) field in status register.
There are seven interrupt request signals (IRQ[7:1]
on the IMB, and are corresponding pins for external interrupt service requests. The
CPU treats all interrupt requests as though they come from internal modules — external interrupt requests are treated as interrupt service requests from the SIM. Each of
the interrupt request signals corresponds to an interrupt priority level. IRQ1
lowest priority and IRQ7
the highest.
). These signals are used internally
has the
Interrupt recognition is determined by interrupt priority level and interrupt priority mask
value. The interrupt priority mask consists of three bits in the CPU32 status register.
Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt
request of a priority less than or equal to the mask value from being recognized and
processed. IRQ7
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted
until an interrupt acknowledge cycle corresponding to that level is detected.
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IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected
unless a falling edge transition is detected on the IRQ7
servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7
asserted as well as each time the priority mask changes from %111 to a lower number
while IRQ7
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause
immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt
source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request with a priority equal
to or lower than the current IP mask value is made, the CPU32 does not recognize the
occurrence of the request. If simultaneous interrupt requests of different priorities are
made, and both have a priority greater than the mask value, the CPU32 recognizes
the higher-level request.
is asserted.
line. This prevents redundant
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4.7.3 Interrupt Acknowledge and Arbitration
When the CPU32 detects one or more interrupt requests of a priority higher than the
interrupt priority mask value, it places the interrupt request level on the address bus
and initiates a CPU space read cycle. The request level serves two purposes: it is decoded by modules or external devices that have requested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them, and it is
latched into the interrupt priority mask field in the CPU32 status register, to preclude
further interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the interrupt priority mask value placed on the address bus during the interrupt acknowledge
cycle and respond if the priority of the service request corresponds to the mask value.
However, before modules or external devices respond, interrupt arbitration takes
place.
Arbitration is performed by means of serial contention between values stored in individual module interrupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register.
IARB fields can be assigned values from %0000 to %1111. In order to implement an
arbitration scheme, each module that can initiate an interrupt service request must be
assigned a unique, non-zero IARB field value during system initialization. Arbitration
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an
interrupt service request from a source that has an IARB field value of %0000, a spurious interrupt exception is processed.
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Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
CPU32 interprets multiple vector numbers at the same time, with unpredictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for
arbitration between internal and external interrupt requests. The reset value of IARB
for the SIM is %1111, and the reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same priority, it always takes place, even when a single source is requesting service. This is important for two reasons: the EBI does not transfer the interrupt acknowledge read cycle
to the external bus unless the SIM wins contention, and failure to contend causes the
interrupt acknowledge bus cycle to be terminated early, by a bus error.
WARNING
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When arbitration is complete, the module with the highest arbitration priority must terminate the bus cycle. Internal modules place an interrupt vector number on the data
bus and generate appropriate internal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowledge cycle is transferred to the external bus, the appropriate external device must decode the mask value and respond
with a vector number, then generate data and size acknowledge (D
signals, or it must assert the autovector (A
respond in time, the EBI bus monitor asserts the bus error signal B
ous interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC
sponse to interrupt requests from external devices (refer to 4.8.3 Using Chip-Select
Signals for Interrupt Acknowledge). Chip-select address match logic functions only
after the EBI transfers an interrupt acknowledge cycle to the external bus following
IARB contention. If a module makes an interrupt request of a certain priority, and the
appropriate chip-select registers are programmed to generate AVEC
nals in response to an interrupt acknowledge cycle for that priority level, chip-select
logic does not respond to the interrupt acknowledge cycle, and the internal module
supplies a vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PICR) determines PIT priority level. A PIRQ value of %000 means that PIT interrupts are
inactive. By hardware convention, when the CPU32 receives simultaneous interrupt
requests of the same level from more than one SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed by the IRQ
VEC) request signal. If the device does not
SACK) termination
ERR, and a spuri-
or DSACK signals in re-
or DSACK sig-
pins.
4.7.4 Interrupt Processing Summary
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction
boundary.
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B. The processor state is stacked. The S bit in the status register is set, establish-
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]
= %1111, which indicates that the cycle is an interrupt acknowledge CPU
space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of
the interrupt request being acknowledged; and ADDR0 = %1.
3. The request level is latched from the address bus into the interrupt priority
mask field in the status or condition code register.
D. Modules that have requested interrupt service decode the priority value in AD-
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by
IARB contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR
number.
2. The dominant interrupt source supplies a vector number and DSACK
nals appropriate to the access. The CPU acquires the vector number.
3. The AVEC
interrupt source or the pin can be tied low), and the CPU generates an autovector number corresponding to interrupt priority.
4. The bus monitor asserts BERR
terrupt vector number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor
transfers control to the exception handler routine.
4.7.5 Interrupt Acknowledge Bus Cycles
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC
CHARACTERISTICS and the
signal is asserted (the signal can be asserted by the dominant
, and the CPU generates the spurious interrupt vector
and the CPU32 generates the spurious in-
or DSACK, refer to APPENDIX A ELECTRICAL
SIM Reference Manual
(SIMRM/AD).
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Fr
4.8 Chip Selects
Typical microcontrollers require additional hardware to provide external chip-select
and address decode signals. The MCU includes 12 programmable chip-select circuits
that can provide 2- to 20-clock-cycle access to external memory and peripherals. Address block sizes of two Kbytes to one Mbyte can be selected. Figure 4-17 is a diagram of a basic system that uses chip selects.
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CLKOUT
DSACK
ADDR[23:0]
DATA[15:0]
FC
SIZ
AS
DS
CS3
CS5
IRQ
ASYNC BUS
1
PERIPHERAL
SIZ
CLK
AS
DSACK
DS
CS
IACK
IRQ
ADDR[15:0]
DATA[15:0]
2
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MCU
CSBOOT
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
MEMORY
ADDR[23:0]
DATA[15:8]
CS
R/W
MEMORY
ADDR[23:0]
DATA[7:0]
CS
R/W
2
2
32 EXAMPLE SYS BLOCK
Figure 4-17 Basic MCU System
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also
generate DSACK
and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, ad-
dress, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. If all parameters match, the
appropriate chip-select signal is asserted. Select signals are active low. If a chip-select
function is given the same address as a microcontroller module or an internal memory
array, an access to that address goes to the module or array, and the chip-select signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits are configured for operation out of reset. However, all chip-select signals except CSBOOT
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in the corresponding option register is programmed to a nonzero value, selecting a
transfer size. The chip-select option must not be written until a base address has been
written to a proper base address register. CSBOOT
is automatically asserted out of
reset. Alternate functions for chip-select pins are enabled if appropriate data bus pins
are held low at the release of the reset signal (refer to 4.6.3.1 Data Bus Mode Selec-
tion for more information). Figure 4-18 is a functional diagram of a single chip-select
circuit.
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INTERNAL
SIGNALS
ADDRESS
BUS CONTROL
AVEC
DSACK
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
AVEC
GENERATOR
OPTION COMPARE
OPTION REGISTER
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
TIMING
AND
CONTROL
REGISTER
PIN
PIN
DATA
CHIP SEL BLOCK
Figure 4-18 Chip-Select Circuit Block Diagram
4.8.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment registers (CSPAR[0:1]) determine functions of the pins. Pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC)
latches data for chip-select pins that are used for discrete output.
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Blocks of addresses are assigned to each chip-select function. Block sizes of two
Kbytes to one Mbyte can be selected by writing values to the appropriate base address
register (CSBAR[0:10], CSBARBT). Address blocks for separate chip-select functions
can overlap.
Chip select option registers (CSOR[0:10], CSORBT) determine timing of and conditions for assertion of chip-select signals. Eight parameters, including operating mode,
access size, synchronization, and wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the
chip-select circuits. A set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap operation.
Comprehensive address maps and register diagrams are provided in APPENDIX D
REGISTER SUMMARY.
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4.8.1.1 Chip-Select Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that
determine the functions of the chip-select pins. Each pin has two or three possible
functions, as shown in Table 4-19.
Table 4-19 Chip-Select Pin Functions
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16-Bit
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
8-Bit
Chip Select
CSBOOT CSBOOT —
CS0 BR —
CS1 BG —
CS2 BGACK —
CS3 FC0 PC0
CS4 FC1 PC1
CS5 FC2 PC2
CS6 ADDR19 PC3
CS7 ADDR20 PC4
CS8 ADDR21 PC5
CS9 ADDR22 PC6
CS10 ADDR23 ECLK
Alternate
Function
Discrete Output
Table 4-20 shows pin assignment field encoding. Pins that have no discrete output
function do not use the %00 encoding.
Table 4-20 Pin Assignment Field Encoding
Bit Field Description
00 Discrete Output
01 Alternate Function
10 Chip Select (8-Bit Port)
11 Chip Select (16-Bit Port)
Port size determines the way in which bus transfers to an external address are allocated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as
a chip select. Port size and transfer size affect how the chip-select signal is asserted.
Refer to 4.8.1.3 Chip-Select Option Registers for more information.
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Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin. These pins have weak internal pull-up drivers, but can be held low
by external devices. (Refer to 4.6.3.1 Data Bus Mode Selection for more information.) Either 16-bit chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the boot ROM select pin (CSBOOT
) are disabled out
of reset. There are twelve chip-select functions and only eight associated data bus
pins. There is not a one-to-one correspondence. Refer to 4.8.4 Chip-Select Reset
Operation for more detailed information.
The CSBOOT
ing reset determines what port width CSBOOT
signal is normally enabled out of reset. The state of the DATA0 line dur-
uses. If DATA0 is held high (either by
the weak internal pull-up driver or by an external pull-up device), 16-bit width is selected. If DATA0 is held low, 8-bit port size is selected.
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A pin programmed as a discrete output drives an external signal to the value specified
in the pin data register. No discrete output function is available on pins CSB
G, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.
B
When a pin is programmed for discrete output or alternate function, internal chip-select
logic still functions and can be used to generate DSA
dress and control signal match.
4.8.1.2 Chip-Select Base Address Registers
Each chip select has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. Block size is the extent
of the address block above the base address. Block size is determined by the value
contained in a BLKSZ field. Block addresses for different chip selects can overlap.
The BLKSZ field determines which bits in the base address field are compared to corresponding bits on the address bus during an access. Provided other constraints de-
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termined by option register fields are also satisfied, when a match occurs, the
associated chip-select signal is asserted. Table 4-21 shows BLKSZ encoding.
OOT, BR,
CK or AVEC internally on an ad-
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Table 4-21 Block Size Encoding
BLKSZ[2:0] Block Size Address Lines Compared
000 2 Kbyte ADDR[23:11]
001 8 Kbyte ADDR[23:13]
010 16 Kbyte ADDR[23:14]
011 64 Kbyte ADDR[23:16]
100 128 Kbyte ADDR[23:17]
101 256 Kbyte ADDR[23:18]
110 512 Kbyte ADDR[23:19]
111 1 Mbyte ADDR[23:20]
The chip-select address compare logic uses only the most significant bits to match an
address within a block. The value of the base address must be a multiple of block size.
Base address register diagrams show how base register bits correspond to address
lines.
After reset, the MCU fetches the initialization routine from the address contained in the
reset vector, located beginning at address $000000 of program space. To support
bootstrap operation from reset, the base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros. A memory device containing the
reset vector and initialization routine can be automatically enabled by CSBOOT
a reset. The block size field in CSBARBT has a reset value of 512 Kbytes. Refer to
4.8.4 Chip-Select Reset Operation for more information.
after
4.8.1.3 Chip-Select Option Registers
Option register fields determine timing of and conditions for assertion of chip-select
signals. To assert a chip-select signal, and to provide DSACK
other constraints set by fields in the option register and in the base address register
must also be satisfied. Table 4-22 is a summary of option register functions.
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Table 4-22 Option Register Function Summary
MODE BYTE R/W STRB DSACK SPACE IPL AVEC
0 = ASYNC* 00 = Disable 00 = Rsvd 0 = AS
1 = SYNC 01 = Lower 01 = Read 1 = DS
10 = Upper 10 = Write 0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
*11 = Both 11 = Both 0011 = 3 WAIT 11 = S/U SP* 011 = Priority 3
*Use this value when function is not required for chip-select operation.
0000 = 0 WAIT 00 = CPU SP 000 = All* 0 = Off*
0001 = 1 WAIT 01 = User SP 001 = Priority 1 1 = On
0100 = 4 WAIT 100 = Priority 4
0101 = 5 WAIT 101 = Priority 5
0110 = 6 WAIT 110 = Priority 6
0111 = 7 WAIT 111 = Priority 7
1000 = 8 WAIT
1001 = 9 WAIT
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1110 = F term
1111 = External
The MODE bit determines whether chip-select assertion simulates an asynchronous
bus cycle, or is synchronized to the M6800-type bus clock signal (ECLK) available on
ADDR23 (refer to 4.3 System Clock for more information on ECLK).
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The BYTE field controls bus allocation for chip-select transfers. Port size, set when a
chip select is enabled by a pin assignment register, affects signal assertion. When an
8-bit port is assigned, any BYTE field value other than %00 enables the chip select
signal. When a 16-bit port is assigned, however, BYTE field value determines when
the chip select is enabled. The BYTE fields for CS[10:0]
are cleared during reset. However, both bits in the boot ROM option register (CSORBT) BYTE field are set (%11)
when the reset signal is released.
The R/W field causes a chip-select signal to be asserted only for a read, only for a
write, or for both read and write. Use this field in conjunction with the STRB bit to generate asynchronous control signals for external devices.
The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Se-
lecting address strobe causes a chip-select signal to be asserted synchronized with
the address strobe. Selecting data strobe causes a chip-select signal to be asserted
synchronized with the data strobe. This bit has no effect in synchronous mode.
The DSACK field specifies the source of data strobe acknowledge signals used in
asynchronous mode. It also allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted.
The SPACE field determines the address space in which a chip select is asserted. An
access must have the space type represented by SPACE encoding in order for a chipselect signal to be asserted.
The IPL field contains an interrupt priority mask that is used when chip-select logic is
set to trigger on external interrupt acknowledge cycles. When the SPACE field is set
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to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the values are the same, and other option register constraints are satisfied, a chip select signal is asserted. This field only affects the response of chip selects and does not affect
interrupt recognition by the CPU. Encoding %000 causes a chip-select signal to be asserted regardless of interrupt acknowledge cycle priority, provided all other constraints
are met.
The AVEC bit selects one of two methods of acquiring an interrupt vector during an
external interrupt acknowledge cycle. The internal autovector signal is generated only
in response to interrupt requests from the SIM IRQ
4.8.1.4 PORTC Data Register
The PORTC data register latches data for PORTC pins programmed as discrete outputs. When a pin is assigned as a discrete output, the value in this register appears at
the output. PC[6:0] correspond to CS[9:3]
effect, and it always reads zero.
4.8.2 Chip-Select Operation
When the MCU makes an access, enabled chip-select circuits compare the following
items:
pins.
. Bit 7 is not used. Writing to this bit has no
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1. Function codes to SPACE fields, and to the IPL field if the SPACE field encoding is not for CPU32 space.
2. Appropriate ADDR bits to base address fields.
3. Read/write status to R/W
4. ADDR0 and/or SIZ bits to the BYTE field (16-bit ports only).
5. Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the
access is an interrupt acknowledge cycle).
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same
time as AS
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK
termines whether DSACK
of wait states inserted before internal DSACK
The speed of an external device determines whether internal wait states are needed.
Normally, wait states are inserted into the bus cycle during S3 until a peripheral asserts DSACK
must be selected and a predetermined number of wait states can be programmed into
the chip-select option register.
Refer to the
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge
or DS assertion in asynchronous mode. Assertion is synchronized with
is generated internally.DSACK also determines the number
. If a peripheral does not generate DSACK, internal DSACK generation
SIM Reference Manual
fields.
field de-
assertion.
(SIMRM/AD) for further information.
Ordinary I/O bus cycles use supervisor space access, but interrupt acknowledge bus
cycles use CPU space access. Refer to 4.5.4 CPU Space Cycles and 4.7 Interrupts
for more information. There are no differences in flow for chip selects in each type of
space, but base and option registers must be properly programmed for each type of
external bus cycle.
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During a CPU space cycle, bits [15:3] of the appropriate base register must be configured to match ADDR[23:11], as the address is compared to an address generated by
the CPU.
Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority,
and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge
code. The rest of the address lines are set to one.
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INTERRUPT
ACKNOWLEDGE
FUNCTION
CODE
20 0
11111111111111111111 1111
19 1623
CPU SPACE
TYPE FIELD
ADDRESS BUS
LEVEL
CPU SPACE IACK TIM
Figure 4-19 CPU Space Encoding for Interrupt Acknowledge
Because address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external address bus following IARB contention, chip-select
logic generates AVEC
external IRQ
pins. If an internal module makes an interrupt request of a certain priority,
or DSACK signals only in response to interrupt requests from
and the chip-select base address and option registers are programmed to generate
AVEC
or DSACK signals in response to an interrupt acknowledge cycle for that priority
level, chip-select logic does not respond to the interrupt acknowledge cycle, and the
internal module supplies a vector number and generates an internal DSACK
signal to
terminate the cycle.
Perform the following operations before using a chip select to generate an interrupt ac-
knowledge signal.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator
checks ADDR[19:16] against the corresponding bits in the base address register. (The CPU32 places the CPU32 space type on ADDR[19:16].)
3. Set the R/W
field to read only. An interrupt acknowledge cycle is performed as
a read cycle.
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector
for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte
when using an 8-bit port.
If an interrupting device does not provide a vector number, an autovector acknowledge
must be generated. Asserting AVEC
ing AVEC
internally using the chip-select option register, terminates the bus cycle.
, either by asserting the AVEC pin or by generat-
4.8.4 Chip-Select Reset Operation
The least significant bits of each of the 2-bit CS[10:0] pin assignment fields in CSPAR0
and CSPAR1 each have a reset value of one. The reset values of the most significant
bits of each field are determined by the states of DATA[7:1] during reset. There are
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weak internal pull-up drivers for each of the data lines, so that chip-select operation
will be selected by default out of reset. However, the internal pull-up drivers can be
overcome by bus loading effects — to insure a particular configuration out of reset, use
an active device to put the data lines in a known state during reset. The base address
fields in chip-select base address registers CSBAR[0:10] and chip select option registers CSOR[0:10] have the reset values shown in Table 4-23. The BYTE fields of
CSOR[0:10] have a reset value of “disable”, so that a chip-select signal cannot be asserted until the base and option registers are initialized.
Table 4-23 Chip Select Base and Option
Register Reset Values
Fields Reset Values
Base Address $000000
Block Size 2 Kbyte
Async/Sync Mode Asynchronous Mode
Upper/Lower Byte Disabled
Read/Write Reserved
AS
/DS AS
DSACK No Wait States
Address Space CPU Space
IPL Any Level
Autovector External Interrupt Vector
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Following reset, the MCU fetches initial stack pointer and program counter values from
the exception vector table, beginning at $000000 in supervisor program space. The
BOOT chip-select signal is used to select an external boot ROM mapped to a base
CS
address of $000000. In order to do this, the reset values of the fields that control CSBOOT must be different from those of other chip select signals.
The MSB of the CSBOOT field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in option register CSORBT
has a reset value of “both bytes” so that the select signal is enabled out of reset. The
LSB value of the CSBOOT
field, determined by the logic level of DATA0 during reset,
selects boot ROM port size. When DATA0 is held low during reset, port size is eight
bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a weak
internal pull-up driver, so that a 16-bit port will be selected by default out of reset. However, the internal pull-up driver can be overcome by bus loading effects —to insure a
particular configuration out of reset, use an active device to put DATA0 in a known
state during reset.
The base address field in chip-select base address register boot (CSBARBT) has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT
CSBARBT has a reset value of 1 Mbyte. Table 4-24 shows CSBOOT
signal is asserted. The block size field in
reset values.
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Table 4-24 CSBOOT
Base Address $000000
Block Size 1 Mbyte
Async/Sync Mode Asynchronous Mode
Upper/Lower Byte Both Bytes
Read/Write Read/Write
Address Space Supervisor/User Space
Autovector Interrupt Vector Externally
Base and Option Register Reset Values
Fields Reset Values
AS
/DS AS
DSACK 13 Wait States
IPL Any Level
4.9 Parallel Input/Output Ports
Fifteen SIM pins can be configured for general-purpose discrete input and output. Although these pins are organized into two ports, port E and port F, function assignment
is by individual pin. Pin assignment registers, data direction registers, and data registers are used to implement discrete I/O.
4.9.1 Pin Assignment Registers
Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the
functions of the pins in each port. Any bit set to one defines the corresponding pin as
a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O
pin.
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4.9.2 Data Direction Registers
Bits in the port E and port F data direction registers (DDRE and DDRF) control the direction of the pin drivers when the pins are configured as I/O. Any bit in a register set
to one configures the corresponding pin as an output. Any bit in a register cleared to
zero configures the corresponding pin as an input. These registers can be read or written at any time. Writes have no effect.
4.9.3 Data Registers
A write to the port E and port F data registers (PORTE and PORTF) is stored in an
internal data latch, and if any pin in the corresponding port is configured as an output,
the value stored for that bit is driven out on the pin. A read of a data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value
read is the value stored in the register. Both data registers can be accessed in two locations. Registers can be read or written at any time.
4.10 Factory Test
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the SIM to support production test. Test submodule registers are intended for Motorola use only. Register names and addresses are provided in APPENDIX
D REGISTER SUMMARY to show the user that these addresses are occupied. The
QUOT pin is also used for factory test.
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SECTION 5 CENTRAL PROCESSING UNIT
The CPU32, the instruction processing module of the M68300 family, is based on the
industry-standard MC68000 processor. It has many features of the MC68010 and
MC68020, as well as unique features suited for high-performance controller applications. This section is an overview of the CPU32. For detailed information concerning
CPU operation, refer to the
5.1 General
Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a philosophy emphasizing register-memory interaction. There are eight multifunction data registers and seven general-purpose address-
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ing registers.
CPU32 Reference Manual
(CPU32RM/AD).
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All data resources are available to all operations requiring those resources. The data
registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand
lengths for all operations. Word and long-word operations support address manipulation. Although the program counter (PC) and stack pointers (SP) are special-purpose
registers, they are also available for most data addressing activities. Ease of program
checking and diagnosis is further enhanced by trace and trap capabilities at the instruction level.
A block diagram of the CPU32 is shown in Figure 5-1. The major blocks operate in a
highly independent fashion that maximizes concurrence of operation while managing
the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and
control unit provide overall chip control, managing the internal buses, registers, and
functions of the execution unit.
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CONTROL STORE
CONTROL LOGIC
MICROSEQUENCER AND CONTROL
DECODE
STAGE STAGE
CB
INSTRUCTION PIPELINE
PROGRAM
COUNTER
SECTION
EXECUTION UNIT
WRITE PENDING
BUFFER
MICROBUS
CONTROLLER
PREFETCH
CONTROLLER
BUFFER
STAGE
A
DATA
SECTION
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ADDRESS
BUS
BUS CONTROL
SIGNALS
DATA
BUS
Figure 5-1 CPU32 Block Diagram
5.2 CPU32 Registers
The CPU32 programming model consists of two groups of registers that correspond
to the user and supervisor privilege levels. User programs can use only the registers
of the user model. The supervisor programming model, which supplements the user
programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of the
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit
program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status
register, two alternate function code registers, and a 32-bit vector base register (see
Figure 5-2 and Figure 5-3).
1127A
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