Freescale MC68331 User Manual
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Technical Summary
32-Bit Modular Microcontroller
1 Introduction
The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that
interface through a common intermodule bus (IMB). Standardization facilitates rapid development of
devices tailored for specific applications.
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MC68331
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The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a general-purpose
timer (GPT), and a queued serial module (QSM).
The MCU can either synthesize an internal clock signal from an external reference or use an external
clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum system clock speed is 20.97 MHz. Because MCU operation is fully static, register and memory contents
are not affected by a loss of clock.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this
capability.
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Table 1 Ordering Information
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Package Type Temperature Frequency
(MHz)
132-Pin PQFP –40 to +85 ° C 16 MHz 2 pc tray SPAKMC331CFC16
20 MHz 2 pc tray SPAKMC331CFC20
–40 to +105 ° C 16 MHz 2 pc tray SPAKMC331VFC16
20 MHz 2 pc tray SPAKMC331VFC20
–40 to +125 ° C 16 MHz 2 pc tray SPAKMC331MFC16
20 MHz 2 pc tray SPAKMC331MFC20
144-Pin QFP –40 to +85 ° C 16 MHz 2 pc tray SPAKMC331CFV16
20 MHz 2 pc tray SPAKMC331CFV20
–40 to +105 ° C 16 MHz 2 pc tray SPAKMC331VFV16
20 MHz 2 pc tray SPAKMC331VFV20
–40 to +125 ° C 16 MHz 2 pc tray SPAKMC331MFV16
20 MHz 2 pc tray SPAKMC331MFV20
Package Order
Quantity
36 pc tray MC68331CFC16
36 pc tray MC68331CFC20
36 pc tray MC68331VFC16
36 pc tray MC68331VFC20
36 pc tray MC68331MFC16
36 pc tray MC68331MFC20
44 pc tray MC68331CFV16
44 pc tray MC68331CFV20
44 pc tray MC68331VFV16
44 pc tray MC68331VFV20
44 pc tray MC68331MFV16
44 pc tray MC68331MFV20
Order Number
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Section Page
1 Introduction 1
1.1 Features ......................................................................................................................................4
1.2 Block Diagram .............................................................................................................................5
1.3 Pin Assignments ..........................................................................................................................6
1.4 Address Map ...............................................................................................................................8
1.5 Intermodule Bus ..........................................................................................................................8
2 Signal Descriptions 9
2.1 Pin Characteristics ......................................................................................................................9
2.2 MCU Power Connections ..........................................................................................................10
2.3 MCU Driver Types .....................................................................................................................10
2.4 Signal Characteristics ................................................................................................................10
2.5 Signal Function ..........................................................................................................................11
3 System Integration Module 14
3.1 Overview ...................................................................................................................................14
3.2 System Configuration and Protection ........................................................................................16
3.3 System Clock ............................................................................................................................21
3.4 External Bus Interface ...............................................................................................................24
3.5 Chip Selects ..............................................................................................................................28
3.6 General-Purpose Input/Output ..................................................................................................35
3.7 Resets .......................................................................................................................................37
3.8 Interrupts ...................................................................................................................................39
3.9 Factory Test Block .....................................................................................................................41
4 Central Processor Unit 43
4.1 Overview ...................................................................................................................................43
4.2 Programming Model ..................................................................................................................43
4.3 Status Register ..........................................................................................................................45
4.4 Data Types ................................................................................................................................45
4.5 Addressing Modes .....................................................................................................................45
4.6 Instruction Set Summary ...........................................................................................................46
4.7 Background Debugging Mode ...................................................................................................50
5 Queued Serial Module 51
5.1 Overview ...................................................................................................................................51
5.2 Pin Function ..............................................................................................................................52
5.3 QSM Registers ..........................................................................................................................53
5.4 QSPI Submodule .......................................................................................................................56
5.5 SCI Submodule .........................................................................................................................64
6 General-Purpose Timer Module 70
6.1 Overview ...................................................................................................................................70
6.2 Capture/Compare Unit ..............................................................................................................71
6.3 Pulse-Width Modulator ..............................................................................................................74
6.4 GPT Registers ...........................................................................................................................75
7 Summary of Changes 82
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TABLE OF CONTENTS
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1.1 Features
• Modular Architecture
• Central Processing Unit (CPU32)
— Upward Object Code Compatible
— New Instructions for Controller Applications
— 32-Bit Architecture
— Virtual Memory Implementation
— Loop Mode of Instruction Execution
— Table Lookup and Interpolate Instruction
— Improved Exception Handling for Controller Applications
— Trace on Change of Flow
— Hardware Breakpoint Signal, Background Mode
— Fully Static Operation
• System Integration Module (SIM)
— External Bus Support
— Programmable Chip-Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— System Protection Logic
— System Clock Based on 32.768-kHz Crystal for Low Power Operation
— Test/Debug Submodule for Factory/User Test and Development
• Queued Serial Module (QSM)
— Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmit-
— Queued Serial Peripheral Interface (QSPI): 80-Byte RAM, Up to 16 Automatic Transfers
— Dual Function I/O Ports
— Continuous Cycling, 8 to 16 Bits per Transfer
• General-Purpose Timer (GPT)
— Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler
— Three Input Capture Channels
— Four Output Compare Channels
— One Input Capture/Output Compare Channel
— One Pulse Accumulator/Event Counter Input
— Two Pulse-Width Modulation Outputs
— Optional External Clock Input
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ter (UART): Modulus Baud Rate, Parity
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1.2 Block Diagram
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PWMA PWMA
PWMB PWMB
PCLK PCLK
PAI PAI
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
PORT GP
CONTROL
PORTQS
CONTROL
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
TXD
PCS3
PCS2
PCS1
PCS0/SS
SCK
MOSI
MISO
GPT
IMB
CHIP
SELECTS
BR
BG
BGACK
CS[10:0]
FC2
FC1
FC0
ADDR[23:19]
ADDR[23:0]
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
DS
AS PE4/AS
RMC PE3/RMC
AVEC PE2/AVEC
DSACK1 PE1/DSACK1
DSACK0
PORT C
CONTROL
PORT E
CONTROL
CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[18:0]
PE5/DS
PE0/DSACK0
EBI
DATA[15:0]DATA[15:0]
R/W
RESET
HALT
CPU32QSM
IRQ[7:1]
PORT F
CONTROL
MODCLK
CLOCK
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
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BKPT/DSCLK
/DSI
IFETCH
/DSO
IPIPE
CONTROL
BKPT
TEST
TSC
QUOT
TSC
FREEZE/QUOT
CONTROL
331 BLOCK
FREEZE
DSI
DSO
DSCLK
IPIPE
IFETCH
Figure 1 MCU Block Diagram
MC68331TS/D 5
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1.3 Pin Assignments
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V
DD
NC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
V
DD
V
SS
ADDR9
ADDR10
ADDR11
ADDR12
V
SS
ADDR13
ADDR14
ADDR15
ADDR16
V
DD
V
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
DD
SS
V
NC
PGP0/IC1
PGP1/IC2
PGP2/IC3
PGP3/OC1
PGP4/OC2/OC1
PGP5/OC3/OC1NCPGP6/OC4/OC1
17
16151413121110
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52535455565758596061626364656667686970717273747576777879808182
DD
VSSV
9876543
PGP7/IC4/OC5/OC1
PAI
VSSV
NC
2
MC68331
DD
1
NC
132
NC
131
PWMA
130
PWMB
PCLK
129
128
SS
V
127
V
DD
126
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
125
124
123
122
SS
PC0/FC0/CS3
V
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
83
121
120
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
V
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
V
DD
V
SS
DATA4
DATA5
DATA6
DATA7
V
SS
DATA8
DATA9
DATA10
DATA11
V
DD
V
SS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
V
DD
PE4/AS
PE6/SIZ0
SS
V
331 132-PIN QFP
SS
V
PQS7/TXD
RXD
/DSO
IPIPE
/DSI
/DSCLK
IFETCH
BKPT
SS
V
TSC
FREEZE/QUOT
XTAL
EXTAL
DDSYN
V
XFC
VDDVDDV
CLKOUT
SS
HALT
RESET
BERR
PF7/IRQ7
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
R/W
PE7/SIZ1
PF0/MODCLK
Figure 2 MC68331 132-Pin QFP Pin Assignments
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/CS2
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NC
V
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
PGP7/IC4/OC5/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
V
DD
V
SS
PCLK
PWMB
PWMA
NC
NC
NC
V
DD
V
SS
NC
PAI
PGP6/OC4
V
DD
V
SS
NC
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
NC
V
SS
NC
DD
BGACK
BG/CS1
BR/CS0
CSBOOT
142
141
ADDR1
ADDR2
DATA0
140
139
ADDR3
ADDR4
V
143
144
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
383940414243444546474849505152535455565758596061626364
DD
NC
V
DATA1
DATA2
138
137
ADDR5
ADDR6
DD
DATA3
136
135
ADDR7
ADDR8
VSSV
134
V
DD
DATA4
DATA5
133
132
SS
V
ADDR9
SS
DATA6
DATA7NCDATA8NCDATA9
V
131
130
129
128
127
126
MC68331
SS
NC
NC
V
ADDR10
ADDR11
ADDR12
DATA10NCDATA11
125
124
123
ADDR13
ADDR14
ADDR15NCADDR16
122
V
121
DD
VSSDATA12
120
119
SS
DD
V
V
DATA13
DATA14
118
117
ADDR17
ADDR18
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
116
115
114
113
65
68
6667697071
PQS2/SCK
PQS0/MISO
PQS1/MOSI
PQS3/PCS0/SS
DD
PE2/AVEC
PE3/RMC
PE5/DS
V
109
112
111
110
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
DD
V
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
NC
V
SS
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
V
SS
CLKOUT
V
DD
NC
XFC
V
DD
EXTAL
V
DD
XTAL
V
SS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PQS7/TXD
V
SS
NC
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331 144-PIN QFP
Figure 3 MC68331 144-Pin QFP Pin Assignments
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1.4 Address Map
The following figure is a map of the MCU internal addresses. Unimplemented blocks are mapped externally.
$YFF000
$YFF900
$YFF93F
GPT
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Freescale Semiconductor, I
$YFFA00
SIM
$YFFA7F
$YFFA80
$YFFAFF
$YFFC00
$YFFDFF
$YFFFFF
1.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with external components through the IMB. The IMB in the MCU uses 24
address and 16 data lines.
RESERVED
QSM
331 ADDRESS MAP
Figure 4 MCU Address Map
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2 Signal Descriptions
2.1 Pin Characteristics
The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All
inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin
function. Refer to Table 4 , for a description of output drivers. An entry in the discrete I/O column of Ta-
ble 2 indicates that a pin has an alternate I/O function. The port designation is given when it applies.
Refer to the MCU Block Diagram for information about port organization.
Table 2 MCU Pin Characteristics
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Freescale Semiconductor, I
Pin
Mnemonic
ADDR23/CS10
ADDR[22:19]/CS[9:6]
ADDR[18:0] A Y N — —
BG
BGACK
BKPT
BR
CLKOUT A — — — —
CSBOOT
DATA[15:0]
DSACK1
DSACK0
DSI/IFETCH
DSO/IPIPE
EXTAL
FC[2:0]/CS[5:3] A Y N O PC[2:0]
FREEZE/QUOT A — — — —
IC4/OC5 A Y Y I/O GP4
IC[3:1] A Y Y I/O GP[7:5]
IRQ[7:1]
MODCLK
OC[4:1] A Y Y I/O GP[3:0]
PCLK
PCS0
PCS[3:1]
PWMA, PWMB A — — O —
RESET
/ECLK A Y N O —
AS
AVEC
BERR
/CS1 B — — — —
/CS2 B Y N — —
/DSCLK — Y Y — —
/CS0 BY N ——
1
DS
2
HALT
B Y Y I/O PF[7:1]
MISO Bo Y Y I/O PQS0
1
MOSI Bo Y Y I/O PQS1
3
PAI
3
/SS Bo Y Y I/O PQS3
R/W
RMC
Output
Driver
A Y N O PC[6:3]
B Y N I/O PE5
B Y N I/O PE2
BY N — —
B — — — —
Aw Y N — —
B Y N I/O PE4
B Y N I/O PE1
B Y N I/O PE0
AY Y ——
A— — ——
— — Special — —
Bo Y N — —
B Y N I/O PF0
— Y Y I —
— Y Y I —
Bo Y Y I/O PQS[6:4]
AY N — —
Bo Y Y — —
B Y N I/O PE3
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Designation
Port
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Table 2 MCU Pin Characteristics (Continued)
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Pin
Mnemonic
RXD — N N — —
SCK Bo Y Y I/O PQS2
SIZ[1:0] B Y N I/O PE[7:6]
TSC — Y Y — —
TXD Bo Y Y I/O PQS7
2
XFC
2
XTAL
NOTES:
1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port
pin.
2. EXTAL, XFC, and XTAL are clock reference connections.
3. PAI and PCLK can be used for discrete input, but are not part of an I/O port.
2.2 MCU Power Connections
V
DDSYN
V
/V
SSE
DDE
V
/V
SSI
DDI
Output
Driver
— — — Special —
— — — Special —
Table 3 MCU Power Connections
Input
Synchronized
Input
Hysteresis
Clock Synthesizer Power
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
Discrete
I/O
Designation
Port
2.3 MCU Driver Types
Table 4 MCU Driver Types
Type I/O Description
A O Output-only signals that are always driven; no external pull-up required
Aw O Type A output with weak P-channel pull-up during reset
B O Three-state output that includes circuitry to pull up output before high impedance is es-
Bo O Type B output that can be operated in an open-drain mode
2.4 Signal Characteristics
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Signal Name MCU Module Signal Type Active State
ADDR[23:0] SIM Bus —
CLKOUT SIM Output —
CS[10:0]
CSBOOT
DATA[15:0] SIM Bus —
tablished, to ensure rapid rise time. An external holding resistor is required to
maintain logic level while the pin is in the high-impedance state.
Table 5 MCU Signal Characteristics
AS
AVEC
BERR
BG
BGACK
BKPT
BR
DS
SIM Output 0
SIM Input 0
SIM Input 0
SIM Output 0
SIM Input 0
CPU32 Input 0
SIM Input 0
SIM Output 0
SIM Output 0
SIM Output 0
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Signal Name MCU Module Signal Type Active State
DSACK[1:0]
PWMA, PWMB GPT Output —
2.5 Signal Function
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Table 5 MCU Signal Characteristics (Continued)
DSCLK CPU32 Input Serial Clock
DSI CPU32 Input (Serial Data)
DSO CPU32 Output (Serial Data)
EXTAL SIM Input —
FC[2:0] SIM Output —
FREEZE SIM Output 1
HALT
IC[4:1] GPT Input —
IFETCH
IPIPE
IRQ[7:1]
MISO QSM Input/Output —
MODCLK SIM Input —
MOSI QSM Input/Output —
OC[5:1] GPT Output —
PAI GPT Input —
PC[6:0] SIM Output (Port)
PCS[3:0] QSM Input/Output —
PE[7:0] SIM Input/Output (Port)
PF[7:0] SIM Input/Output (Port)
PQS[7:0] QSM Input/Output (Port)
PCLK GPT Input —
QUOT SIM Output —
RESET
RMC
R/W
RXD QSM Input —
SCK QSM Input/Output —
SIZ[1:0] SIM Output —
SS
TSC SIM Input —
TXD QSM Output —
XFC SIM Input —
XTAL SIM Output —
SIM Input 0
SIM Input/Output 0
CPU32 Output —
CPU32 Output —
SIM Input 0
SIM Input/Output 0
SIM Output 0
SIM Output 1/0
QSM Input 0
Freescale Semiconductor, I
Signal Name Mnemonic Function
Address Bus ADDR[23:0] 24-bit address bus
Address Strobe AS
Autovector AVEC
Bus Error BERR
Bus Grant BG
Bus Grant Acknowledge BGACK
Breakpoint BKPT
Bus Request BR
System Clockout CLKOUT System clock output
Chip Selects CS[10:0]
Table 6 MCU Signal Function
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
Select external devices at programmed addresses
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Table 6 MCU Signal Function (Continued)
Signal Name Mnemonic Function
Boot Chip Select CSBOOT
Data Bus DATA[15:0] 16-bit data bus
Data Strobe DS
Data and Size Acknowledge DSACK[1:0]
Development Serial In, Out,
Clock
Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference;
Function Codes FC[2:0] Identify processor state and current address space
Freeze FREEZE Indicates that the CPU has entered background mode
Halt HALT
Input Capture IC[3:1] When a specified transition is detected on an input capture pin, the
Input Capture 4/Output Compare 5IC4/OC5 Can be configured for either an input capture or output compare
Instruction Pipeline IPIPE
Interrupt Request Level IRQ[7:1]
Master In Slave Out MISO Serial input to QSPI in master mode;
Clock Mode Select MODCLK Selects the source and type of system clock
Master Out Slave In MOSI Serial output from QSPI in master mode;
Output Compare OC[5:1] Change state when the value of an internal GPT counter matches
Pulse Accumulator Input PAI Signal input to the pulse accumulator
Port C PC[6:0] SIM digital output port signals
Auxiliary Timer Clock Input PCLK External clock dedicated to the GPT
Peripheral Chip Select PCS[3:0] QSPI peripheral chip selects
Port E PE[7:0] SIM digital I/O port signals
Port F PF[7:0] SIM digital I/O port signals
Port QS PQS[7:0] QSM digital I/O port signals
Pulse-Width Modulation PWMA, PWMB Output for PWM
Quotient Out QUOT Provides the quotient bit of the polynomial divider
Reset RESET
Read-Modify-Write Cycle RMC
Read/Write R/W
SCI Receive Data RXD Serial input to the SCI
QSPI Serial Clock SCK Clock output from QSPI in master mode;
Size SIZ[1:0] Indicates the number of bytes to be transferred during a bus cycle
Slave Select SS
Three-State Control TSC Places all output drivers in a high-impedance state
SCI Transmit Data TXD Serial output from the SCI
External Filter Capacitor XFC Connection for external phase-locked loop filter capacitor
Chip select for external boot startup ROM
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indicates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
DSI, DSO,
DSCLK
, IFETCH Indicate instruction pipeline activity
Serial I/O and clock for background debugging mode
a crystal or an external oscillator can be used
Suspend external bus activity
value in an internal GPT counter is latched
Provides an interrupt priority level to the CPU
serial output from QSPI in slave mode
serial input to QSPI in slave mode
a value stored in a GPT control register
System reset
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
clock input to QSPI in slave mode
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
12 MC68331TS/D
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3 System Integration Module
The system integration module (SIM) consists of five functional blocks that control system start-up, initialization, configuration, and external bus.
SYSTEM CONFIGURATION
XTAL
CLOCK SYNTHESIZER
SYSTEM PROTECTION
CHIP SELECTS
CLKOUT
EXTAL
MODCLK
CHIP SELECTS
EXTERNAL BUS
EXTERNAL BUS INTERFACE
RESET
FACTORY TEST
Figure 5 SIM Block Diagram
3.1 Overview
The system configuration and protection block controls MCU configuration and operating mode. The
block also provides bus and software watchdog monitors.
The system clock generates clock signals used by the SIM, other IMB modules, and external devices.
In addition, a periodic interrupt generator supports execution of time-critical control routines.
The external bus interface handles the transfer of information between IMB modules and external address space.
TSC
FREEZE/QUOT
300 S(C)IM BLOCK
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The chip-select block provides eleven general-purpose chip-select signals and a boot ROM chip-select
signal. Both general-purpose and boot ROM chip-select signals have associated base address registers and option registers.
The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported.
The SIM control register address map occupies 128 bytes. Unused registers within the 128-byte address space return zeros when read. The “Access” column in the SIM address map below indicates
which registers are accessible only at the supervisor privilege level and which can be assigned to either
the supervisor or user privilege level, according to the value of the SUPV bit in the SIMCR.
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Access Address 15 8 7 0
S $YFFA00 SIM CONFIGURATION (SIMCR)
S $YFFA02 FACTORY TEST (SIMTR)
S $YFFA04 CLOCK SYNTHESIZER CONTROL (SYNCR)
S $YFFA06 NOT USED RESET STATUS REGISTER (RSR)
S $YFFA08 MODULE TEST E (SIMTRE)
S $YFFA0A NOT USED NOT USED
S $YFFA0C NOT USED NOT USED
S $YFFA0E NOT USED NOT USED
S/U $YFFA10 NOT USED PORT E DATA (PORTE0)
S/U $YFFA12 NOT USED PORT E DATA (PORTE1)
S/U $YFFA14 NOT USED PORT E DATA DIRECTION (DDRE)
S $YFFA16 NOT USED PORT E PIN ASSIGNMENT (PEPAR)
S/U $YFFA18 NOT USED PORT F DATA (PORTF0)
S/U $YFFA1A NOT USED PORT F DATA (PORTF1)
S/U $YFFA1C NOT USED PORT F DATA DIRECTION (DDRF)
S $YFFA1E NOT USED PORT F PIN ASSIGNMENT (PFPAR)
S $YFFA20 NOT USED SYSTEM PROTECTION CONTROL
S $YFFA22 PERIODIC INTERRUPT CONTROL (PICR)
S $YFFA24 PERIODIC INTERRUPT TIMING (PITR)
S $YFFA26 NOT USED SOFTWARE SERVICE (SWSR)
S $YFFA28 NOT USED NOT USED
S $YFFA2A NOT USED NOT USED
S $YFFA2C NOT USED NOT USED
S $YFFA2E NOT USED NOT USED
S $YFFA30 TEST MODULE MASTER SHIFT A (TSTMSRA)
S $YFFA32 TEST MODULE MASTER SHIFT B (TSTMSRB)
S $YFFA34 TEST MODULE SHIFT COUNT (TSTSC)
S $YFFA36 TEST MODULE REPETITION COUNTER (TSTRC)
S $YFFA38 TEST MODULE CONTROL (CREG)
S/U $YFFA3A TEST MODULE DISTRIBUTED REGISTER (DREG)
$YFFA3C NOT USED NOT USED
$YFFA3E NOT USED NOT USED
S/U $YFFA40 NOT USED PORT C DATA (PORTC)
$YFFA42 NOT USED NOT USED
S $YFFA44 CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
S $YFFA46 CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
S $YFFA48 CHIP-SELECT BASE BOOT (CSBARBT)
S $YFFA4A CHIP-SELECT OPTION BOOT (CSORBT)
S $YFFA4C CHIP-SELECT BASE 0 (CSBAR0)
S $YFFA4E CHIP-SELECT OPTION 0 (CSOR0)
S $YFFA50 CHIP-SELECT BASE 1 (CSBAR1)
S $YFFA52 CHIP-SELECT OPTION 1 (CSOR1)
S $YFFA54 CHIP-SELECT BASE 2 (CSBAR2)
S $YFFA56 CHIP-SELECT OPTION 2 (CSOR2)
S $YFFA58 CHIP-SELECT BASE 3 (CSBAR3)
S $YFFA5A CHIP-SELECT OPTION 3 (CSOR3)
S $YFFA5C CHIP-SELECT BASE 4 (CSBAR4)
Table 7 SIM Address Map
(SYPCR)
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Access Address 15 8 7 0
S $YFFA5E CHIP-SELECT OPTION 4 (CSOR4)
S $YFFA60 CHIP-SELECT BASE 5 (CSBAR5)
S $YFFA62 CHIP-SELECT OPTION 5 (CSOR5)
S $YFFA64 CHIP-SELECT BASE 6 (CSBAR6)
S $YFFA66 CHIP-SELECT OPTION 6 (CSOR6)
S $YFFA68 CHIP-SELECT BASE 7 (CSBAR7)
S $YFFA6A CHIP-SELECT OPTION 7 (CSOR7)
S $YFFA6C CHIP-SELECT BASE 8 (CSBAR8)
S $YFFA6E CHIP-SELECT OPTION 8 (CSOR8)
S $YFFA70 CHIP-SELECT BASE 9 (CSBAR9)
S $YFFA72 CHIP-SELECT OPTION 9 (CSOR9)
S $YFFA74 CHIP-SELECT BASE 10 (CSBAR10)
S $YFFA76 CHIP-SELECT OPTION 10 (CSOR10)
$YFFA78 NOT USED NOT USED
$YFFA7A NOT USED NOT USED
$YFFA7C NOT USED NOT USED
$YFFA7E NOT USED NOT USED
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
Table 7 SIM Address Map (Continued)
3.2 System Configuration and Protection
This functional block provides configuration control for the entire MCU. It also performs interrupt arbitration, bus monitoring, and system test functions. MCU system protection includes a bus monitor, a
HALT monitor, a spurious interrupt monitor, and a software watchdog timer. These functions have been
made integral to the microcontroller to reduce the number of external components in a complete control
system.
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RESET STATUS
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HALT MONITOR
BUS MONITOR
SPURIOUS INTERRUPT MONITOR
CLOCK
PRESCALER
9
2
Figure 6 System Configuration and Protection Block
3.2.1 System Configuration
The SIM controls MCU configuration during normal operation and during internal testing.
SIMCR —SIM Configuration Register
15
EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB
RESET:
0 0 0 0 DATA11 0 0 0 1 1 0 0 1 1 1 1
EXOFF —External Clock Off
14 13 12 11 10 9 8 7 6 5 4 3 0
The SIM configuration register controls system configuration. It can be read or written at any time, except for the module mapping (MM) bit, which can be written only once.
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
SOFTWARE WATCHDOG TIMER
PERIODIC INTERRUPT TIMER
RESET REQUEST
BERR
RESET REQUEST
IRQ[7:1]
300 SYS PROTECT BLOCK
$YFFA00
FRZSW —Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts during software debug.
FRZBM —Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
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SLVEN —Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DATA11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] —Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SHEN Action
00 Show cycles disabled, external arbitration enabled
01 Show cycles enabled, external arbitration disabled
10 Show cycles enabled, external arbitration enabled
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SUPV —Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-
visor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
MM —Module Mapping
0 = Internal modules are addressed from $7FF000 –$7FFFFF.
1 = Internal modules are addressed from $FFF000 –$FFFFFF.
IARB[3:0] —Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU processes a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same priority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
3.2.2 System Protection Control Register
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
SYPCR —System Protection Control Register
15
NOT USED SWE SWP SWT HME BME BMT
RESET:
SWE —Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
8 7 6 5 4 3 2 1 0
1 MODCLK 0 0 0 0 0 0
$YFFA21
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SWP —Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] —Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following table gives the ratio for each combination of SWP and SWT bits.
SWP SWT Ratio
000
001
010
011
100
101
110
111
9
2
11
2
13
2
15
2
18
2
20
2
22
2
24
2
HME —Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME —Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] —Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
BMT Bus Monitor Time-out Period
00 64 System Clocks
01 32 System Clocks
10 16 System Clocks
11 8 System Clocks
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
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monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
response times during normal bus cycles
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cycle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhibited by the HME bit in the SYPCR.
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3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR
knowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog times out and issues a reset. This register can be written at any time, but returns zeros when read.
if no interrupt arbitration occurs during an interrupt-ac-
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SWSR —Software Service Register
15
NOT USED 0 0 0 0 0 0 0 0
RESET:
Register shown with read value
Perform a software watchdog service sequence as follows:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be executed between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
MODCLK SWP
3.2.7 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
PICR — Periodic Interrupt Control Register
15
0 0 0 0 0 PIRQL PIV
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
14 13 12 11 10 8 7 0
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
01
10
$YFFA27
$YFFA22
PIRQL[2:0] —Periodic Interrupt Request Level
The following table shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT interrupt and an external IRQ
terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
signal of the same priority occur simultaneously, the PIT in-
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PIV[7:0] —Periodic Interrupt Vector
The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
When the SIM responds, the periodic interrupt vector is placed on the bus.
PIRQL Interrupt Request Level
000 Periodic Interrupt Disabled
001 Interrupt Request Level 1
010 Interrupt Request Level 2
011 Interrupt Request Level 3
100 Interrupt Request Level 4
101 Interrupt Request Level 5
110 Interrupt Request Level 6
111 Interrupt Request Level 7
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PITR —Periodic Interrupt Timer Register $YFFA24
15 14 13 12 11 10 9 8 7 0
0 0 0 0 0 0 0 PTP PITM
RESET:
0 0 0 0 0 0 0 MODCLK 0 0 0 0 0 0 0 0
The PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This
register can be read or written at any time.
PTP —Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by a value of 512
The reset state of PTP is the complement of the state of the MODCLK signal during reset.
PITM[7:0] —Periodic Interrupt Timing Modulus Field
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
PIT Period = [(PITM)(Prescaler)(4)]/EXTAL
where
PIT Period = Periodic interrupt timer period
PITM = Periodic interrupt timer register modulus (PITR[7:0])
EXTAL Frequency = Crystal frequency
Prescale = 512 or 1 depending on the state of the PTP bit in the PITR
3.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral
bus. Because MCU operation is fully static, register and memory contents are not affected when the
clock rate changes. System hardware and software support changes in the clock rate during operation.
The system clock signal can be generated in three ways. An internal phase-locked loop can synthesize
the clock from an internal or external frequency source, or the clock signal can be input from an external
source.
Following is a block diagram of the clock submodule.
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32.768 KHz
22
22 pF 22 pF
V
SSI
EXTAL
1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 MΩ OR GREATER).
2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
R4
330K
R3
10M
CRYSTAL
OSCILLATOR
V
SSI
XTAL XFC PIN
PHASE
COMPARATOR
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
LOW-PASS
FILTER
V
DDSYN
1
XFC
0.1µF
V
DDSYN
0.1µF
0.01µF
VCO
W
Y
X
V
SSI
SYSTEM
CLOCK
CLKOUT
SYS CLOCK
BLOCK 32KHZ
Figure 7 System Clock Block Diagram
3.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines the clock source. When MODCLK
is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator
or an external reference input. Clock synthesizer control register SYNCR determines operating frequency and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied. When the synthesizer is disabled, SYNCR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins to use the internal oscillator.
Use of a 32.768-kHz crystal is recommended. These crystals are inexpensive and readily available. If
an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
Freescale Semiconductor, I
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is
critical, especially at near maximum operating frequencies. The relationship between clock signal duty
cycle and clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% — percentage variation of external clock input duty cycle
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3.3.2 Clock Synthesizer Operation
A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.
The other phase comparator input is a reference signal, either from the internal oscillator or from an
external source. The comparator generates a control signal proportional to the difference in phase between its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.
The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by
the filter time constant and by the amount of difference between the two comparator inputs. Whenever
comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYNCR.
The MCU does not come out of reset state until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time.
The low-pass filter requires an external low-leakage capacitor, typically 0.1 µF, connected between the
XFC and V
V
and can be used to run the clock when the MCU is powered down. Use a quiet power supply as the
V
ternal bypass capacitors as close as possible to the V
is used to power the clock circuits. A separate power source increases MCU noise immunity
DDSYN
source, since PLL stability depends on the VCO, which uses this supply. Place adequate ex-
DDSYN
DDSYN
pins.
pin to ensure stable operating frequency.
DDSYN
When the clock synthesizer is used, control register SYNCR determines operating frequency and various modes of operation. SYNCR can be read only when the processor is operating at the supervisor
privilege level.
The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting
X doubles clock speed without changing VCO speed. There is no VCO relock delay. The SYNCR W bit
controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.
The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide
by a value of Y + 1. When either W or Y value changes, there is a VCO relock delay.
Clock frequency is determined by SYNCR bit settings as follows:
F
SYSTEM
In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU. The VCO frequency is twice the system clock frequency if X
= 1 or four times the system clock frequency if X = 0.
The reset state of SYNCR ($3F00) produces a modulus-64 count.
= F
REFERENCE
[4(Y + 1)(2
2W +X
)]
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3.3.3 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circumstances, such as following loss of synthesizer reference or during low-power operation. Clock source is
determined by the logic state of the MODCLK pin during reset.
SYNCR —Clock Synthesizer Control Register $YFFA04
15 14 13 8 7 6 5 4 3 2 1 0
W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT
RESET:
0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0
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When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level.
W —Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X —Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit
doubles clock speed without changing the VCO speed. There is no VCO relock delay.
Y[5:0] —Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.
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EDIV —E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.5 Chip Selects for more information.
SLIMP —Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency causes SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
SLOCK —Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
RSTEN —Reset Enable
0 = Loss of crystal causes the MCU to operate in limp mode.
1 = Loss of crystal causes system reset.
STSIM —Stop Mode SIM Clock
0 = When LPSTOP is executed, the SIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIM clock is driven from the VCO.
STEXT —Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SIM clock, as determined by
the state of the STSIM bit.
3.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external devices. The external bus has 24 address lines and 16 data lines.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1
may be required for a transfer to or from an 8-bit port.
and DSACK0). Multiple bus cycles
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Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchronized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5 Chip Selects for more information.
3.4.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only changes state when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
Table 8 Size Signal Encoding
SIZ1 SIZ0 Transfer Size
0 1 Byte
1 0 Word
1 1 Three Byte
0 0 Long Word
3.4.2 Function Codes
The CPU32 automatically generates function code signals FC[2:0]. The function codes can be considered address extensions that automatically select one of eight address spaces to which an address applies. These spaces are designated as either user or supervisor, and program or data spaces. Address
space 7 is designated CPU space. CPU space is used for control information not normally associated
with read or write bus cycles. Function codes are valid while AS is asserted.
Table 9 CPU32 Address Space Encoding
FC2 FC1 FC0 Address Space
0 0 0 Reserved
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0 0 1 User Data Space
0 1 0 User Program Space
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Supervisor Data Space
1 1 0 Supervisor Program Space
1 1 1 CPU Space
3.4.3 Address Bus
Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted.
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3.4.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.4.5 Data Bus
Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During
a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For
a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.4.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.4.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1
and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.
During a write cycle, the signals indicate that an external device has successfully stored data and that
the cycle can end. These signals also indicate to the MCU the size of the port for the bus cycle just completed. (Refer to 3.4.9 Dynamic Bus Sizing.)
is asserted at the same time as AS during a read cycle. For a write cycle,
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT
are asserted simultaneously, the CPU takes a bus error exception.
Autovector signal (AVEC) can terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates
that the MCU will internally generate a vector number to locate an interrupt handler routine. If it is continuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored
during all other bus cycles.
3.4.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1 and DSACK0).
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3.4.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
Table 10 Effect of DSACK Signals
DSACK1 DSACK0 Result
1 1 Insert Wait States in Current Bus Cycle
1 0 Complete Cycle —Data Bus Port Size is 8 Bits
0 1 Complete Cycle —Data Bus Port Size is 16 Bits
0 0 Reserved
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