Freescale MC68160A User Manual
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Freescale Semiconductor, Inc.
Enhanced Ethernet Transceiver
The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device
which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE–T
Twisted Pair (TP) Interface media connections through external isolation
transformers. It encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via 10BASE–T or AUI
interfaces. The MC68160A gluelessly interface to the Ethernet controller
contained in the MC68360 Quad Integrated Communications Controller
(QUICC) device. The MC68160A also interfaces easily to most other
industry–standard IEEE 802.3 LAN controllers. Prior to twisted pair data
reception, Smart Squelch circuitry qualifies input signals for correct
amplitude, pulse width, and sequence requirements.
• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction
Option
• Automatic Port Selection Option with Status Output
Order this document by MC68160A/D
MC68160A
ENHANCED ETHERNET
INTERFACE TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Driver Pre–emphasis for Twisted Pair Output Data
• Crystal Controlled Clock Oscillator or External Clock Generator Option
• Digital Phase–Locked–Loop (DPLL) Timing Recovery and Data Decoding
• Standby Mode with Reduced Power Consumption
• Twisted Pair Signal Quality Error (Heartbeat) Test Option
• Diagnostic Local Loop Back Option
• Transmit, Receive and Collision Detection Status Output
• Full–Duplex Operation Option on Twisted Pair Port
• Twisted Pair Jabber Detection and Status Output
• Link Integrity Testing and Status Output
The sale and use of this product is licensed under technology covered by one
or more Digital Equipment Corporation patents.
52 1
FB SUFFIX
PLASTIC PACKAGE
CASE 848D
(LQFP–52)
ORDERING INFORMATION
Operating
Device
MC68160AFB TA = 0° to + 70°C LQFP
Temperature Range
Package
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Rev 1
Freescale Semiconductor, Inc.
MC68160A
Figure 1. 10Base–T Interface Block Diagram
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RX
RCLK
MFILT
RXLED
RENA
CLLED
CLSN
TXLED
TENA
TX
X1
SIA INTERFACE
X2
TCLK
CS0
CS1
CS2
TPEN
APORT
TPAPCE
TPSQEL
TPFULDL
LOOP
Pulse Conditioner
Pulse Conditioner
Pulse
Conditioner
Mode
Select
Manchester
Encoder
20 MHz
Osc
÷2
Jabber
Control
TPJABB
Manchester
Decoder
Carrier
Detect
Mux
Mux
Driver
Pre–emphasis
Control
This device contains 20,000 active transistors.
Link
Pulse
Control
Mux
Collision
Detect
Collision
Detector
Control
Squelch
Test
Circuit
Mux
Receiver
Mux
TPRX– TPRX+TPSQELTPLILTPTX–TPTX+
Receiver
Squelch
Data
Receiver
Noise
Reject
Filter
Noise
Reject
Filter
ARX+
ARX–
ACX+
ACX–
ATX–
ATX+
Twisted
Pair
Polarity
Error
Control
TPPLR
AUI INTERFACE
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ANALOG IC DEVICE DATA
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Freescale Semiconductor, I
Freescale Semiconductor, Inc.
MC68160A
Enhanced Ethernet Serial Transceiver
Table 1. Pin Descriptions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface Pins 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator and Frequency Multiplier Pins 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Select Pins 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Indicator Pins 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply and Ground Pins 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. Controller Interface Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. Controller Independent Mode Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply DC Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TTL/CMOS Input and Output DC Characteristics 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Input and Output DC Characteristics 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Input and Output DC Characteristics 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Input (X1) Switching Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Phase Locked Loop Switching Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Transmit Switching Characteristics (Motorola Mode) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Receive Switching Characteristics (Motorola Mode) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Transmit Switching Characteristics (Intel Mode) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Receive Switching Characteristics (Intel Mode) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Transmit Switching Characteristics (Fujitsu Mode) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Receive Switching Characteristics (Fujitsu Mode) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Transmit Switching Characteristics (National Mode) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Receive Switching Characteristics (National Mode) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Transmit Switching Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Transmit Jabber Switching Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Transmit Signal Quality Error Test Switching Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Receive Switching Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Receive Link Integrity Switching Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Collision Switching Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Full Duplex Switching Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Transmit Switching Characteristics 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Receive Switching Characteristics 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmission 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Reception 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jabber 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Duplex 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Port Selection 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Polarity Selection 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Back Mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of Crystal and External Components 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Filter Components 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE–T Filter and Transformer Choice 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Transformer Choice 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG IC DEVICE DATA
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Pin(s) Symbol Type Name/Function
CONTROLLER INTERFACE
1 RENA O
2 RX O
48 TCLK O
49 TENA I
50 RCLK O
51 CLSN O
52 TX I
AUI INTERFACE
21
22
23
24
25
26
ACX–
ACX+
ARX–
ARX+
ATX–
ATX+
TTL/CMO
TTL/CMOS
TTL/CMOS
TTL
TTL/CMOS
TTL/CMOS
TTL
I AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased
I AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased
O AUI Differential Transmit Outputs : This line pair is intended to operate into terminated
MC68160A
T able 1. Pin Function Descriptiont
Receive Enable Output: Indication of the presence of network activity , synchronous to
RCLK. In the standby mode, RENA is driven to the high impedance state.
Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,
100 ms should be allowed before attempting to read data processed by the MC68160A, B
and C. This delay is needed to insure that the receive phase locked loop is properly
synchronized with incoming data. In the standby mode, RX is driven to the high impedance
state.
Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at
10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to
the high impedance state.
Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission
on the active port. An internal pull–down resistor is provided so that the input is low under no
connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at
the conclusion of a reset operation, it must first be deasserted and then reasserted before
data transmission can occur. In the standby mode, TENA is driven to the high impedance
state.
Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high
impedance state.
Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and
ACX– terminals which meet threshold and pulse width requirements. In the TP mode,
indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was
generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high
impedance state.
Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to
be Manchester encoded. In the standby mode, TX is driven to the high impedance state.
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity. Signals at ACX+/– have no ef fect on data path functions.
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity, and a data receiver with no of fset for Manchester Data reception.
transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is
previously asserted, Manchester encoded data is outputted at ATX+/–. When operating into a
78 Ω terminated transmission line, signaling meets the required output levels and skew for
IEEE–802.3 drop cables. When the 10BASE–T port is automatically or manually selected,
the AUI outputs are driven to a low power standby state in which the outputs deliver a
balanced high state voltage.
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TWISTED PAIR INTERFACE
31
32
36
37
NOTE: The sense of the controller interface pins will change, depending on the controller selected.
TPRX–
TPRX+
TPTX–
TPTX+
I Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with
Smart Squelch capability which only allows differential receive data to pass as long as the
input amplitude is greater than a minimum signal threshold level and a specific pulse
sequence is received. This assures a good signal to noise ratio while the signal pair is active
by preventing crosstalk and impulse noise conditions from activating the receive function.
O Twisted Pair Differential Transmitter Outputs: These lines have pre–distortion drive
capability and are intended to drive terminated twisted pair transmission lines. When the AUI
port is manually selected, the 10BASE–T outputs are driven to a low power standby state in
which the outputs deliver a balanced high state voltage. However, when the AUI port is
automatically selected, the 10BASE–T outputs remain active.
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Pin(s) Symbol Type Name/Function
OSCILLATOR AND FREQUENCY MULTIPLIER
12 MFILT C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be
16 X1 I/C
17 X2 O/C
MODE SELECT
3
4
5
6 LOOP I
9 APORT I
27 TPSQEL I
28 TPFULDL I
29 TPAPCE I
46 TPEN I/O
CS0
CS1
CS2
CMOS
CMOS
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
(TTL/CMOS)
MC68160A
T able 1. Pin Function Description (continued)
attached to this pin.
Oscillator Inverter Input and Crystal Connection Point: When connected for crystal
oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an
external 20 MHz CMOS compatible clock generator.
Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by
an external CMOS Clock generator.
Mode Select: The logic states applied to these pins select the appropriate interface for the
desired IEEE–802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.
Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SQE test.
Automatic Port Selection Enable: When high, MC68160A will automatically select the TP
or AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port is automatically selected, the MC68160A will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for
the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.
Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160A collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SQE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16–bit times after the
last transition of a transmitted signal and continues for 5 to 15–bit times. (When the AUI port
is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160A ACX+/– receive inputs)
Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
and receive operation on the twisted pair port without an indicated collision. This pin is not to
be asserted with LOOP as a test mode is enabled that disrupts normal operation.
Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.
Twisted Pair Port Enable: If APOR T is low, TPEN is an input which determines whether the
AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
manually selected, the MC68160A will not produce link pulses for the TP port.
If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)
Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the circuitry associated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.
ANALOG IC DEVICE DATA
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Pin(s) Symbol Type Name/Function
STATUS INDICATOR
40 TXLED O
41 RXLED O
42 CLLED O
43 TPLIL O
44 TPPLR O
45 TPJABB O
POWER SUPPLY AND GROUND
10 VDDDIV Frequency Divider Supply Pin
11
13
14
15
20 GNDSUB Substrate Ground Pin
7
8
18
19
30
33
34
35
38
39
47 GNDCTL Controller Interface Ground Pin
NOTE: Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.
VDDFM
GNDFM
GNDVCO
VDDVCO
VDDDIG
GNDDIG
VDDDIG
GNDDIG
VDDANA
GNDANA
GNDPWR
VDDPWR
VDDPWR
GNDPWR
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
MC68160A
T able 1. Pin Function Description (continued)
Transmit Status LED Driver Output: This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pull–up takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns
on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
Receive Status LED Driver Output: This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pull–up takes
this pin to its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
Collision Status LED Driver Output: This pin indicates the collision status of the currently
selected TP or AUI port. When there is no collision activity detected, an internal pull–up takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.
Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low
logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has
automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this
output will be driven to the high logic state. When the AUI mode is selected this output is
driven to the high impedance state. In the standby mode, this output is also driven to the high
impedance state.
Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the
TPTX+/– outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present. When the AUI mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.
Frequency Multiplier Supply and Ground Pins
Voltage Controlled Oscillator Ground and Supply Pins
Digital Supply and Ground Pins
Analog Supply and Ground Pins
Power Supply and Ground Pins
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ANALOG IC DEVICE DATA
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Freescale Semiconductor, Inc.
Motorola
Transceiver
MC68160A
(EEST)
CS0
CS1
CS2
Pin Pin Sense Pin Sense Pin Sense Pin Sense
TCLK TCLK High TXC Low TCKN Low TXC High
TX TX High TXD High TXD High TXD High
TENA TENA High RTS Low TEN High TXE High
RCLK RCLK High RXC Low RCN Low RXC High
RX RX High RXD High RXD High RXD High
RENA RENA High CRS Low XCD High CRS High
CLSN CLSN High CDT Low XCOL Low COL High
1
LOOP
NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used.
2. The Motorola controller interface contained in the MC68360 (QUICC
3. The pin sense is shown from the perspective of the identified controller pin.
4. Supported only by MC68160A.
Motorola
Controller
MC68360
(QUICC)
N.A. High LPBK Low LBC High LPBK High
2
1
1
0
MC68160A
T able 2. Controller Interface Selection
4
Intel
Controllers
82586, 82590,
82593, 82596
0
1
0
) is compatible with the AMD 7990 (LANCE) and 79C900 (ILACC) controllers.
Fujitsu
Controllers
86950 (Etherstar)
86960 (NICE)
4
1
0
0
National
Controllers
8390, 83C690,
83932B (SONIC)
4
0
0
0
T able 3. Controller Independent Mode Selection
Pin Standby Mode Reserved Reserved Reserved
CS0
CS1
CS2
NOTE: In standby mode, the MC68160A consumes less power supply current than in any other
mode. Additionally, in the standby mode, all of the controller inputs and outputs are
driven to the high impedance state. When the standby mode is deasserted, an internal
reset pulse of approximately 6.0 µs duration is generated.
Following a period of operation in the standby mode, the time required to insure stable
data reception is approximately 100 ms.
Freescale Semiconductor, I
LAN
Controller
TCLK
TX
TENA
RCLK
RX
1
1
1
Figure 2. Applications Block Diagram
MC68160A
0
1
1
ATX+
ATX–
ARX+
ARX–
ACX+
ACX–
1
0
1
Pulse
Transformers
0
0
1
ATX+
ATX–
ARX+
ARX–
ACX+
ACX–
DB–15
Connector
RENA
CLSN
ANALOG IC DEVICE DATA
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TPTX+
TPTX–
TPRX+
TPRX–
Filters
and
Pulse
Transformers
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TPTX+
TPTX–
TPRX+
TPRX–
RJ–45
Connector
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Freescale Semiconductor, I
Freescale Semiconductor, Inc.
MC68160A
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Characteristic Symbol Min Max Unit
Storage Temperature Range T
Power Supply Voltage Range
Analog
Digital
Voltage on any TTL compatible input pin with
respect to Ground
Voltage on TPRX, ARX, or ACX input pins with
respect to Ground
Differential Voltage on TPRX, ARX, or ACX Input
Pins
NOTE: Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the
device. Functional operation of the device is not implied at these or any other conditions in
excess of those indicated in the operation sections of this data sheet. Exposure to Absolute
Maximum Ratings conditions for extended periods can adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Max Unit
Power Supply Voltage Range V
Power Supply Ripple (20 kHz to 100 kHz) – – 50 mV
Power Supply Impulse Noise (Either Polarity) – – 100 mV
Ambient Operating Temperature Range T
ARX/ACX Input Differential Rise and Fall Time (see Figure 39) t
ARX Pair Idle Time after Transmission (see Figure 39) t
ESD
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge
(ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD–susceptibility
testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 Ω capacitance –
100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using
the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model.
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges.)
Characteristic
POWER SUPPLY
Undervoltage Shutdown Threshold – – – – 4.4 V
Power Supply Current I
Symbol Test Conditions Min Typ Max Unit
DD
V
V
V
stg
DDA
DDD
DIFF
–65 150 °C
–
–
V –0.5
–0.5
–6.0 6.0 V
Standby Mode
7.0
7.0
VDD + 0.5
6.0
–
V
V
DD
A
260
265
–
–
4.75 5.25 V
0 70 °C
2.0 10 ns
8.0 – µs
145
–
200
5.0
mA
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OROLA ANALOG IC DEVICE DATA
Freescale Semiconductor, Inc.
MC68160A
..
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DC ELECTRICAL CHARACTERISTICS (T
limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)
Characteristic
TTL COMPATIBLE INPUTS
TTL Compatible Input Voltage
Low State
High State
Input Current TTL Compatible Input Pins (Note 1)
Input Current TENA TTL Compatible Input Pin:
with Pull–Down Resistor
I
IH
I
IL
with Pull–Down Resistor removed in Standby Mode
CMOS COMPATIBLE INPUTS
CMOS Compatible Input Voltage
Low State
High State
Input Current (Pin X1) IIH & I
TTL/CMOS COMPATIBLE OUTPUTS
TTL/CMOS Compatible Output Voltage
Low State (Note 2)
Low State (Note 3)
TTL/CMOS Compatible Output Voltage
High State (Note 4)
High State (Note 5)
High State (Note 2)
Three State Output Leakage Current I
= 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum
A
Symbol Test Conditions Min Max Unit
VIL(TTL)
VIH(TTL)
I
IH
I
IL
IIH & I
IL
VIL(CMOS)
VIH(CMOS)
IL
V
OL
V
OH
OZ
–
0 V < VI < V
–
0 V < VI < V
IOL = 4.0 mA
IOL = 10 mA
IOH = –500 µA
IOH = –10 mA
IOH = –4.0 mA
0 V ≤ VOZ ≤ V
DD
DD
DD
–
2.0
–
–
–
–
–
3.0
– ±100 µA
–
–
3.9
3.9
2.4
– ±10 µA
0.8
±10
+200
–20
±10
1.0
0.45
0.45
V
–
µA
V
–
V
V
–
–
–
Characteristic Symbol Test Conditions Min Max Unit
TWISTED PAIR RECEIVER INPUTS
Input Voltage Range (DC + AC) V
Differential Input Squelch Threshold Voltage V
Common Mode Bias Generator Voltage V
Common Mode Input Resistance R
Differential Input Resistance R
TWISTED PAIR TRANSMITTER OUTPUTS
Differential Output Voltage
Pre–Emphasis Level
Signal Level
Common Mode Output Voltage Range V
Common Mode Output Voltage in Standby Mode V
Freescale Semiconductor, I
NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).
2. TCLK, RX, RCLK, RENA and CLSN.
3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).
4. TPPLR, TPLIL, CLLED, TXLED and RXLED.
5. TPJABB and TPEN (In Output Mode).
6. Measured with T est Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.
7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.
8. Measured directly on the TPTX+/– pins of the device.
9. Measured with T est Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.
10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.
ITP
ITPSQ
BCMTP
CMTP
DIFFTP
V
ODFTPP
V
ODFTPS
OCMTP
OCMTPSB
– 1.5 4.3 V
Note 10 270 390 mV
Note 9 1.8 3.2 V
– 1000 – Ω
– 2.5 – kΩ
Note 7
Note 6 0 4.0 V
IOH = –100 µA VDD – 1.0 V
±2.2
±1.56
±2.8
±1.98
DD
V
V
ANALOG IC DEVICE DATA
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Freescale Semiconductor, I
DC ELECTRICAL CHARACTERISTICS
limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)
Characteristic
TWISTED PAIR TRANSMITTER OUTPUTS
Differential Output Voltage
IDLE Mode
Open Circuit
Differential Output Impedance
TRANSMISSION Mode
IDLE Mode
Common Mode Output Impedance
TRANSMISSION Mode
IDLE Mode
NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).
2. TCLK, RX, RCLK, RENA and CLSN.
3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).
4. TPPLR, TPLIL, CLLED, TXLED and RXLED.
5. TPJABB and TPEN (In Output Mode).
6. Measured with T est Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.
7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.
8. Measured directly on the TPTX+/– pins of the device.
9. Measured with T est Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.
10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges.)
Characteristic
AUI RECEIVER INPUTS
Input Voltage Range (DC + AC) V
Differential Mode Input Voltage Range V
Differential Input Squelch Threshold Voltage V
Common Mode Input Resistance R
Differential Input Resistance (ARX, ACX Inputs) R
AUI TRANSMITTER OUTPUTS
Common Mode Output Voltage
IDLE Mode
ACTIVE Mode
STANDBY Mode
Differential Output Voltage
IDLE Mode
ACTIVE Mode
Differential Output Load Current
IDLE Mode
Output Short Circuit Current I
(continued) (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum
Symbol Test Conditions Min Max Unit
V
ODFTPI
V
ODFTPO
R
ODFTPT
R
ODFTPI
R
OCMTPT
R
OCMTPI
Symbol Test Conditions Min Max Unit
IA
IDFA
IASQ
ICMA
IDFA
V
OCMIA
V
OCMAA
V
OCMSA
V
ODFIA
V
ODFAA
I
ODFIA
ODSA
1.0 V < V
1.0 V < V
318 mV < V
Output Short Circuited to
Note 6
Note 8
Note 8
Note 8
– 1.0 4.2 V
– ±318 ±1315 mV
– –275 –175 mV
< 4.2 V 1.5 – kΩ
ICMA
< 4.2 V
ICMA
< 1315 mV
IDMA
Figure 6
IO = –100 µA
Figure 6
Figure 7
VDD or GND
–
–
12
8.0
3.0
1.0
5.0 – kΩ
1.0
1.0
VDD – 2.0
–
±600
– ±4.0
– ±150 mA
±50
5.25
28
29
7.0
10
4.2
4.2
VDD – 1.2
±40
±1315
mV
V
Ω
Ω
V
mV
mA
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