Freescale MC68060, MC68LC060, MC68EC060 User Manual

M68060 User’s Manual

Including the

MC68060,

MC68LC060,

and

MC68EC060

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M68060 USER’S MANUAL

MOTOROLA

PREFACE

The complete documentation package for the MC68060, MC68LC060, and MC68EC060
(collectively called M68060) consists of the M68060UM/AD,
the M68000PM/AD,

Manual

32-bit microprocessors. The
complete instruction set for the M68000 family.

The introduction of this manual includes general information concerning the MC68060 and
summarizes the differences among the M68060 family devices. Additionally, appendices
provide detailed information on how these M68060 derivatives operate differently from the
MC68060.

When reading this manual, disregard information concerning the floating-point unit in refer­ence to the MC68LC060, and disregard information concerning the floating-point unit and
memory management unit in reference to the MC68EC060.

describes the capabilities, operation, and programming of the M68060 superscalar

M68000 Family Programmer’s Reference Manual

M68000 Family Programmer’s Reference Manual

M68060 User’s Manual

. The

M68060 User’s

contains the

, and

The organization of this manual is as follows:

Section 1 Introduction
Section 2 Signal Description
Section 3 Integer Unit
Section 4 Memory Management Unit
Section 5 Caches
Section 6 Floating-Point Unit
Section 7 Bus Operation
Section 8 Exception Processing
Section 9 IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
Section 10 Instruction Timings
Section 11 Applications
Section 12 Electrical and Thermal Characteristics
Section 13 Ordering Information and Mechanical Data
Appendix A MC68LC060
Appendix B MC68EC060
Appendix C MC68060 Software Package
Appendix D M68060 Instructions

MOTOROLA

M68060 USER’S MANUAL

v

MC68060 ACRONYM LIST

AGU—address generation unit
ALU—arithmetic logic unit
ATC—address translation cache
BUSCR—bus control register
CACR—cache control register
CCR—condition code register
CM—cache mode
CPU—central processing unit
DFC—destination function code
DTTx—data transparent translation register
DRAM—dynamic random access memory
FPIAR—floating-point instruction address register
FPCR—floating-point control register
FPSP—floating-point software package
FPSR—floating-point status register
FPU—floating-point unit
FP7–FP0—floating-point data registers 7–0
FSLW—fault status long word
IEE—integer execute unit
IFP—instruction fetch pipeline
IFU—instruction fetch unit
IPU—instruction pipe unit
ISP—interrupt stack pointer
ITTR—instruction transparent translation register
IU—integer unit
JTAG—Joint Test Action Group
MMU—memory management unit

MOTOROLA

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MC68060 Acronym List

MMUSR—memory management unit status register
M68060SP—M68060 software package
NANs—not-a-numbers
NOP—no operation
OEP—operand execution pipeline
OPU—operand pipe unit
PC—program counter
PCR—processor configuration register
PGI—page index field
PI—pointer index field
PLL—phase-locked loop
pOEP—primary operand execution pipeline
RI—root index field
SFC—source function code
SNAN—signaling not-a-number
sOEP—secondary operand execution pipeline
SP—stack pointer
SR—status register
SRP—supervisor root pointer register
SSP—supervisor stack pointer
TAP—test access port
TCR—translation control register
TTL—transistor-transistor logic
TTR—transparent translation register
UPA—user page attribute
URP—user root pointer register
USP—user stack pointer
VBR—vector base register
VLSI—very large-scale integration

viii

M68060 USER’S MANUAL

MOTOROLA

TABLE OF CONTENTS

Section 1

Introduction

1.1 Differences Among M68060 Family Members..............................................1-3

1.1.1 MC68LC060................................................................................................1-3

1.1.2 MC68EC060...............................................................................................1-3

1.1.2.1 Address Translation Differences ..............................................................1-3

1.1.2.2 Instruction Differences..............................................................................1-3

1.2 Features........................................................................................................1-4

1.3 Architecture...................................................................................................1-4

1.4 Processor Overview......................................................................................1-5

1.4.1 Functional Blocks........................................................................................1-5

1.4.2 Integer Unit.................................................................................................1-7

1.4.2.1 Instruction Fetch Unit................................................................................1-7

1.4.2.2 Integer Unit...............................................................................................1-8

1.4.2.3 Floating-Point Unit....................................................................................1-8

1.4.2.4 Memory Units ...........................................................................................1-9

1.4.2.5 Address Translation Caches ....................................................................1-9

1.4.2.6 Instruction and Data Caches ....................................................................1-9

1.4.2.6.1 Cache Organization..............................................................................1-10

1.4.2.6.2 Cache Coherency.................................................................................1-10

1.4.3 Bus Controller...........................................................................................1-10

1.5 Processing States.......................................................................................1-10

1.6 Programming Model....................................................................................1-11

1.7 Data Format Summary................................................................................1-14

1.8 Addressing Capabilities Summary..............................................................1-14

1.9 Instruction Set Overview.............................................................................1-15

1.10 Notational Conventions...............................................................................1-21

Section 2

Signal Description

2.1 Address and Control Signals ........................................................................2-3

2.1.1 Address Bus (A31–A0)...............................................................................2-3

2.1.2 Cycle Long-Word Address (CLA

) ...............................................................2-4

2.2 Data Bus (D31–D0).......................................................................................2-4

2.3 Transfer Attribute Signals .............................................................................2-4

2.3.1 Transfer Cycle Type (TT1, TT0).................................................................2-4

2.3.2 Transfer Cycle Modifier (TM2–TM0)...........................................................2-4

2.3.3 Transfer Line Number (TLN1, TLN0)..........................................................2-5

2.3.4 User-Programmable Page Attributes (UPA1, UPA0)..................................2-5

2.3.5 Read/Write (R/W

MOTOROLA

) .......................................................................................2-6

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x

Table of Contents

2.3.6 Transfer Size (SIZ1, SIZ0)..........................................................................2-6

2.3.7 Bus Lock (LOCK

2.3.8 Bus Lock End (LOCKE

2.3.9 Cache Inhibit Out (CIOUT

2.3.10 Byte Select Lines (BS3

)........................................................................................ 2-6

)..............................................................................2-6

)......................................................................... 2-7

–BS0).....................................................................2-7

2.4 Master Transfer Control Signals................................................................... 2-7

2.4.1 Transfer Start (TS

2.4.2 Transfer in Progress (TIP

2.4.3 Starting Termination Acknowledge Signal Sampling (SAS

)...................................................................................... 2-8

).......................................................................... 2-8

)....................... 2-8

2.5 Slave Transfer Control Signals..................................................................... 2-8

2.5.1 Transfer Acknowledge (TA

2.5.2 Transfer Retry Acknowledge (TRA

)........................................................................2-8

)............................................................ 2-8

2.5.3 Transfer Error Acknowledge (TEA) ............................................................2-9

2.5.4 Transfer Burst Inhibit (TBI

2.5.5 Transfer Cache Inhibit (TCI

2.6 Snoop Control (SNOOP

)......................................................................... 2-9

)....................................................................... 2-9

) ..............................................................................2-9

2.7 Arbitration Signals....................................................................................... 2-10

2.7.1 Bus Request (BR

2.7.2 Bus Grant (BG

2.7.3 Bus Grant Relinquish Control (BGR

2.7.4 Bus Tenure Termination (BTT

2.7.5 Bus Busy (BB

)..................................................................................... 2-10

).........................................................................................2-10

)........................................................2-10

).................................................................2-10

)..........................................................................................2-11

2.8 Processor Control Signals.......................................................................... 2-11

2.8.1 Cache Disable (CDIS

2.8.2 MMU Disable (MDIS

2.8.3 Reset In (RSTI

)......................................................................................... 2-12

2.8.4 Reset Out (RSTO

).............................................................................. 2-11

)................................................................................ 2-12

).................................................................................... 2-12

2.9 Interrupt Control Signals............................................................................. 2-12

2.9.1 Interrupt Priority Level (IPL2

2.9.2 Interrupt Pending Status (IPEND

2.9.3 Autovector (AVEC

)................................................................................... 2-13

–IPL0)..........................................................2-12

) ............................................................2-12

2.10 Status and Clock Signals............................................................................2-13

2.10.1 Processor Status (PST4–PST0)...............................................................2-13

2.10.2 MC68060 Processor Clock (CLK) ............................................................2-14

2.10.3 Clock Enable (CLKEN

)............................................................................. 2-14

2.11 Test Signals................................................................................................2-15

2.11.1 JTAG Enable (JTAG

)................................................................................ 2-15

2.11.2 Test Clock (TCK)...................................................................................... 2-15

2.11.3 Test Mode Select (TMS)........................................................................... 2-15

2.11.4 Test Data In (TDI).....................................................................................2-16

2.11.5 Test Data Out (TDO)................................................................................ 2-16

2.11.6 Test Reset (TRST) ...................................................................................2-16

2.12 Thermal Sensing Pins (THERM1, THERM0)..............................................2-16

2.13 Power Supply Connections.........................................................................2-16

2.14 Signal Summary .........................................................................................2-16

M68060 USER’S MANUAL

MOTOROLA

Table of Contents

Section 3

Integer Unit

3.1 Integer Unit Execution Pipelines...................................................................3-1

3.2 Integer Unit Register Description..................................................................3-2

3.2.1 Integer Unit User Programming Model.......................................................3-2

3.2.1.1 Data Registers (D7–D0) ...........................................................................3-2

3.2.1.2 Address Registers (A6–A0)......................................................................3-2

3.2.1.3 User Stack Pointer (A7)............................................................................3-2

3.2.1.4 Program Counter......................................................................................3-3

3.2.1.5 Condition Code Register ..........................................................................3-3

3.2.2 Integer Unit Supervisor Programming Model..............................................3-3

3.2.2.1 Supervisor Stack Pointer..........................................................................3-4

3.2.2.2 Status Register.........................................................................................3-4

3.2.2.3 Vector Base Register................................................................................3-4

3.2.2.4 Alternate Function Code Registers...........................................................3-5

3.2.2.5 Processor Configuration Register.............................................................3-5

Section 4

Memory Management Unit

4.1 Memory Management Programming Model..................................................4-3

4.1.1 User and Supervisor Root Pointer Registers..............................................4-3

4.1.2 Translation Control Register.......................................................................4-4

4.1.3 Transparent Translation Registers .............................................................4-6

4.2 Logical Address Translation..........................................................................4-7

4.2.1 Translation Tables......................................................................................4-7

4.2.2 Descriptors................................................................................................4-12

4.2.2.1 Table Descriptors....................................................................................4-12

4.2.2.2 Page Descriptors....................................................................................4-12

4.2.2.3 Descriptor Field Definitions.....................................................................4-13

4.2.3 Translation Table Example.......................................................................4-15

4.2.4 Variations in Translation Table Structure..................................................4-16

4.2.4.1 Indirect Action.........................................................................................4-16

4.2.4.2 Table Sharing Between Tasks................................................................4-17

4.2.4.3 Table Paging ..........................................................................................4-17

4.2.4.4 Dynamically Allocated Tables.................................................................4-17

4.2.5 Table Search Accesses............................................................................4-19

4.2.6 Address Translation Protection.................................................................4-20

4.2.6.1 Supervisor and User Translation Tables ................................................4-21

4.2.6.2 Supervisor Only......................................................................................4-22

4.2.6.3 Write Protect...........................................................................................4-22

4.3 Address Translation Caches.......................................................................4-24

4.4 Transparent Translation..............................................................................4-27

4.5 Address Translation Summary....................................................................4-28

4.6 RSTI

4.6.1 Effect of RSTI

and MDIS Effect on the MMU............................................................4-28

on the MMUs.....................................................................4-28

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Table of Contents

4.6.2 Effect of MDIS on Address Translation .................................................... 4-30

4.7 MMU Instructions........................................................................................4-30

4.7.1 MOVEC ....................................................................................................4-30

4.7.2 PFLUSH ...................................................................................................4-30

4.7.3 PLPA ........................................................................................................4-30

Section 5

Caches

5.1 Cache Operation........................................................................................... 5-1

5.2 Cache Control Register ................................................................................5-5

5.3 Cache Management .....................................................................................5-6

5.4 Caching Modes.............................................................................................5-7

5.4.1 Cachable Accesses.................................................................................... 5-7

5.4.1.1 Writethrough Mode...................................................................................5-7

5.4.1.2 Copyback Mode .......................................................................................5-8

5.4.2 Cache-Inhibited Accesses.......................................................................... 5-8

5.4.3 Special Accesses .......................................................................................5-9

5.5 Cache Protocol.............................................................................................5-9

5.5.1 Read Miss...................................................................................................5-9

5.5.2 Write Miss...................................................................................................5-9

5.5.3 Read Hit......................................................................................................5-9

5.5.4 Write Hit....................................................................................................5-10

5.6 Cache Coherency....................................................................................... 5-10

5.7 Memory Accesses for Cache Maintenance................................................ 5-11

5.7.1 Cache Filling.............................................................................................5-11

5.7.2 Cache Pushes..........................................................................................5-13

5.8 Push Buffer................................................................................................. 5-13

5.9 Store Buffer................................................................................................. 5-13

5.10 Push Buffer and Store Buffer Bus Operation..............................................5-14

5.11 Branch Cache.............................................................................................5-14

5.12 Cache Operation Summary ........................................................................ 5-15

5.12.1 Instruction Cache...................................................................................... 5-15

5.12.2 Data Cache............................................................................................... 5-16

Section 6

Floating-Point Unit

6.1 Floating-Point User Programming Model...................................................... 6-2

6.1.1 Floating-Point Data Registers (FP7–FP0).................................................. 6-3

6.1.2 Floating-Point Control Register (FPCR).....................................................6-3

6.1.2.1 Exception Enable Byte ............................................................................. 6-3

6.1.2.2 Mode Control Byte.................................................................................... 6-3

6.1.3 Floating-Point Status Register (FPSR).......................................................6-4

6.1.3.1 Floating-Point Condition Code Byte ......................................................... 6-5

6.1.3.2 Quotient Byte............................................................................................ 6-5

6.1.3.3 Exception Status Byte .............................................................................. 6-5

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MOTOROLA

Table of Contents

6.1.3.4 Accrued Exception Byte ...........................................................................6-6

6.1.4 Floating-Point Instruction Address Register (FPIAR) .................................6-7

6.2 Floating-Point Data Formats and Data Types...............................................6-7

6.3 Computational Accuracy.............................................................................6-11

6.3.1 Intermediate Result...................................................................................6-12

6.3.2 Rounding the Result.................................................................................6-13

6.4 Postprocessing Operation...........................................................................6-15

6.4.1 Underflow, Round, and Overflow..............................................................6-15

6.4.2 Conditional Testing...................................................................................6-16

6.5 Floating-Point Exceptions...........................................................................6-19

6.5.1 Unimplemented Floating-Point Instructions..............................................6-19

6.5.2 Unsupported Floating-Point Data Types...................................................6-21

6.5.3 Unimplemented Effective Address Exception...........................................6-22

6.6 Floating-Point Arithmetic Exceptions..........................................................6-22

6.6.1 Branch/Set on Unordered (BSUN)............................................................6-24

6.6.1.1 Trap Disabled Results (FPCR BSUN Bit Cleared) .................................6-24

6.6.1.2 Trap Enabled Results (FPCR BSUN Bit Set) .........................................6-24

6.6.2 Signaling Not-a-Number (SNAN)..............................................................6-25

6.6.2.1 Trap Disabled Results (FPCR SNAN Bit Cleared) .................................6-25

6.6.2.2 Trap Enabled Results (FPCR SNAN Bit Set) .........................................6-26

6.6.3 Operand Error...........................................................................................6-26

6.6.3.1 Trap Disabled Results (FPCR OPERR Bit Cleared)...............................6-27

6.6.3.2 Trap Enabled Results (FPCR OPERR Bit Set).......................................6-27

6.6.4 Overflow....................................................................................................6-28

6.6.4.1 Trap Disabled Results (FPCR OVFL Bit Cleared)..................................6-29

6.6.4.2 Trap Enabled Results (FPCR OVFL Bit Set)..........................................6-29

6.6.5 Underflow..................................................................................................6-30

6.6.5.1 Trap Disabled Results (FPCR UNFL Bit Cleared)..................................6-31

6.6.5.2 Trap Enabled Results (FPCR UNFL Bit Set)..........................................6-31

6.6.6 Divide-by-Zero..........................................................................................6-32

6.6.6.1 Trap Disabled Results (FPCR DZ Bit Cleared).......................................6-33

6.6.6.2 Trap Enabled Results (FPCR DZ Bit Set)...............................................6-33

6.6.7 Inexact Result...........................................................................................6-33

6.6.7.1 Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared...........6-34

6.6.7.2 Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set)..........6-34

6.7 Floating-Point State Frames.......................................................................6-35

Section 7

Bus Operation

7.1 Bus Characteristics.......................................................................................7-1

7.2 Full-, Half-, and Quarter-Speed Bus Operation and BCLK...........................7-3

7.3 Acknowledge Termination Ignore State Capability.......................................7-4

7.4 Bus Control Register.....................................................................................7-4

7.5 Data Transfer Mechanism.............................................................................7-5

7.6 Misaligned Operands....................................................................................7-9

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Table of Contents

7.7 Processor Data Transfers...........................................................................7-12

7.7.1 Byte, Word, and Long-Word Read Transfer Cycles.................................7-12

7.7.2 Line Read Transfer...................................................................................7-15

7.7.3 Byte, Word, and Long-Word Write Cycles................................................7-20

7.7.4 Line Write Cycles.....................................................................................7-25

7.7.5 Locked Read-Modify-Write Cycles..........................................................7-28

7.7.6 Emulating CAS2 and CAS Misaligned......................................................7-31

7.7.7 Using CLA

to Increment A3 and A2.......................................................... 7-32

7.8 Acknowledge Cycles................................................................................... 7-32

7.8.1 Interrupt Acknowledge Cycles................................................................. 7-32

7.8.1.1 Interrupt Acknowledge Cycle (Terminated Normally).............................7-35

7.8.1.2 Autovector Interrupt Acknowledge Cycle ...............................................7-35

7.8.1.3 Spurious Interrupt Acknowledge Cycle ..................................................7-35

7.8.2 Breakpoint Acknowledge Cycle................................................................ 7-36

7.8.2.1 LPSTOP Broadcast Cycle......................................................................7-38

7.9 Bus Exception Control Cycles ....................................................................7-46

7.9.1 Bus Errors.................................................................................................7-46

7.9.2 Retry Operation........................................................................................7-48

7.9.3 Double Bus Fault...................................................................................... 7-51

7.10 Bus Synchronization...................................................................................7-52

7.11 Bus Arbitration ............................................................................................ 7-52

7.11.1 MC68040-Arbitration Protocol (BB Protocol)............................................7-53

7.11.2 MC68060-Arbitration Protocol (BTT Protocol)..........................................7-58

7.11.3 External Arbiter Considerations................................................................7-65

7.12 Bus Snooping Operation............................................................................7-68

7.13 Reset Operation.........................................................................................7-71

7.14 Special Modes of Operation .......................................................................7-74

7.14.1 Acknowledge Termination Ignore State Capability...................................7-74

7.14.2 Acknowledge Termination Protocol.......................................................... 7-76

7.14.3 Extra Data Write Hold Time Mode............................................................7-76

Section 8

Exception Processing

8.1 Exception Processing Overview...................................................................8-1

8.2 Integer Unit Exceptions................................................................................. 8-4

8.2.1 Access Error Exception..............................................................................8-5

8.2.2 Address Error Exception.............................................................................8-7

8.2.3 Instruction Trap Exception..........................................................................8-7

8.2.4 Illegal Instruction and Unimplemented Instruction Exceptions...................8-8

8.2.5 Privilege Violation Exception....................................................................8-10

8.2.6 Trace Exception........................................................................................8-10

8.2.7 Format Error Exception ............................................................................8-11

8.2.8 Breakpoint Instruction Exception.............................................................. 8-11

8.2.9 Interrupt Exception ...................................................................................8-12

8.2.10 Reset Exception .......................................................................................8-14

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8.3 Exception Priorities.....................................................................................8-17

8.4 Return from Exceptions ..............................................................................8-19

8.4.1 Four-Word Stack Frame (Format $0) .......................................................8-19

8.4.2 Six-Word Stack Frame (Format $2)..........................................................8-20

8.4.3 Floating-Point Post-Instruction Stack Frame (Format $3) ........................8-20

8.4.4 Eight-Word Stack Frame (Format $4).......................................................8-21

8.4.4.1 Program Counter (PC)............................................................................8-21

8.4.4.2 Fault Address .........................................................................................8-22

8.4.4.3 Fault Status Long Word (FSLW).............................................................8-22

8.4.5 Recovering from an Access Error.............................................................8-25

8.4.6 Bus Errors and Pending Memory Writes .................................................8-27

8.4.7 Branch Prediction Error ............................................................................8-29

Section 9

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes

9.1 IEEE 1149.1 Test Access Port (Normal JTAG) Mode ..................................9-1

9.1.1 Overview.....................................................................................................9-2

9.1.2 JTAG Instruction Shift Register ..................................................................9-3

9.1.2.1 EXTEST....................................................................................................9-4

9.1.2.2 LPSAMPLE...............................................................................................9-5

9.1.2.3 Private Instructions...................................................................................9-5

9.1.2.4 SAMPLE/PRELOAD.................................................................................9-5

9.1.2.5 IDCODE....................................................................................................9-5

9.1.2.6 CLAMP .....................................................................................................9-6

9.1.2.7 HIGHZ.......................................................................................................9-6

9.1.2.8 BYPASS ...................................................................................................9-6

9.1.3 JTAG Test Data Registers..........................................................................9-7

9.1.3.1 Idcode Register ........................................................................................9-7

9.1.3.2 Boundary Scan Register...........................................................................9-7

9.1.3.3 Bypass Register .....................................................................................9-15

9.1.4 Restrictions...............................................................................................9-15

9.1.5 Disabling the IEEE 1149.1 Standard Operation .......................................9-15

9.1.6 Motorola MC68060 BSDL Description......................................................9-17

9.2 Debug Pipe Control Mode...........................................................................9-24

9.2.1 Debug Command Interface.......................................................................9-25

9.2.2 Debug Pipe Control Mode Commands.....................................................9-27

9.2.3 Emulator Mode .........................................................................................9-31

9.3 Switching between JTAG and Debug Pipe ControlModes of Operation.....9-33

Section 10

Instruction Execution Timing

10.1 Superscalar Operand Execution Pipelines .................................................10-1

10.1.1 Dispatch Test 1: sOEP Opword and Required

Extension Words Are Valid.......................................................................10-2

10.1.2 Dispatch Test 2: Instruction Classification................................................10-2

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10.1.3 Dispatch Test 3: Allowable Effective Addressing Mode in the sOEP.......10-8

10.1.4 Dispatch Test 4: Allowable Operand Data Memory Reference................ 10-8

10.1.5 Dispatch Test 5: No Register Conflicts on sOEP.AGU Resources ..........10-8

10.1.6 Dispatch Test 6: No Register Conflicts on sOEP.IEE Resources ............10-9

10.2 Timing Assumptions .................................................................................10-10

10.3 Cache and ATC Performance Degradation Times ................................... 10-12

10.3.1 Instruction ATC Miss ..............................................................................10-12

10.3.2 Data ATC Miss .......................................................................................10-13

10.3.3 Instruction Cache Miss...........................................................................10-13

10.3.4 Data Cache Miss....................................................................................10-13

10.4 Effective Address Calculation Times ........................................................ 10-14

10.5 Move Instruction Execution Times............................................................10-14

10.6 Standard Instruction Execution Times......................................................10-16

10.7 Immediate Instruction Execution Times....................................................10-17

10.8 Single-Operand Instruction Execution Times ...........................................10-18

10.9 Shift/Rotate Execution Times ...................................................................10-19

10.10 Bit Manipulation and Bit Field Execution Times........................................ 10-19

10.11 Branch Instruction Execution Times.........................................................10-21

10.12 LEA, PEA, and MOVEM Execution Times................................................ 10-22

10.13 Multiprecision Instruction Execution Times............................................... 10-22

10.14 Status Register, MOVES, and Miscellaneous

Instruction Execution Times...................................................................... 10-22

10.15 FPU Instruction Execution Times .............................................................10-24

10.16 Exception Processing Times ....................................................................10-26

Section 11

Applications Information

11.1 Guidelines for Porting Software to the MC68060 .......................................11-1

11.1.1 User Code ................................................................................................11-1

11.1.2 Supervisor Code.......................................................................................11-1

11.1.2.1 Initialization Code (Reset Exception Handler)........................................11-2

11.1.2.1.1 Processor Configuration Register (PCR) (MOVEC of PCR)................11-2

11.1.2.1.2 Default Transparent Translation Register (MOVEC of TCR) ............... 11-2

11.1.2.1.3 MC68060 Software Package (M68060SP). ......................................... 11-2

11.1.2.1.4 Cache Control Register (CACR) (MOVEC of CACR)..........................11-3

11.1.2.1.5 Resource Checking (Access Error Handler) ........................................ 11-3

11.1.2.2 Virtual Memory Software........................................................................11-3

11.1.2.2.1 Translation Control Register (MOVEC of TCR)....................................11-3

11.1.2.2.2 Descriptors in Cacheable Copyback Pages Prohibited........................11-4

11.1.2.2.3 Page and Descriptor Faults (Access Error Handler)............................11-4

11.1.2.2.4 PTEST, MOVEC of MMUSR, and PLPA..............................................11-4

11.1.2.3 Context Switch Interrupt Handlers.......................................................... 11-5

11.1.2.4 Trace Handlers.......................................................................................11-5

11.1.2.5 I/O Device Driver Software.....................................................................11-5

11.1.3 Precise Vs. Imprecise Exception Mode.................................................... 11-6

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11.1.4 Other Considerations................................................................................11-6

11.2 Using an MC68060 in an Existing MC68040 System .................................11-6

11.2.1 Power Considerations...............................................................................11-6

11.2.1.1 DC to DC Voltage Conversion................................................................11-6

11.2.1.1.1 Linear Voltage Regulator Solution........................................................11-7

11.2.1.1.2 Switching Regulator Solution................................................................11-7

11.2.1.2 Input Signals During Power-Up Requirement.......................................11-11

11.2.2 Output Hold Time Differences ................................................................11-11

11.2.3 Bus Arbitration........................................................................................11-13

11.2.4 Snooping.................................................................................................11-13

11.2.5 Special Modes........................................................................................11-13

11.2.6 Clocking..................................................................................................11-14

11.2.7 PSTx Encoding.......................................................................................11-14

11.2.8 Miscellaneous Pullup Resistors..............................................................11-15

11.3 Example DRAM Access............................................................................11-15

11.4 Thermal Management..............................................................................11-17

11.5 Support Devices.......................................................................................11-20

Section 12

Electrical and Thermal Characteristics

12.1 Maximum Ratings .......................................................................................12-1

12.2 Thermal Characteristics..............................................................................12-1

12.3 Power Dissipation .......................................................................................12-1

12.4 DC Electrical Specifications (Vcc = 3.3 Vdc ± 5%).....................................12-2

12.5 Clock Input Specifications (Vcc = 3.3 Vdc ± 5%)........................................12-3

12.6 Output AC Timing Specifications (Vcc = 3.3 Vdc ± 5%).............................12-4

12.7 Input AC Timing Specifications (Vcc = 3.3 Vdc ± 5%)................................12-6

Section 13

Ordering Information and Mechanical Data

13.1 Ordering Information...................................................................................13-1

13.2 Pin Assignments .........................................................................................13-1

13.2.1 MC68060, MC68LC060, and MC68EC060 Pin Grid Array (RC Suffix) ....13-2

13.2.2 MC68060, MC68LC060, and MC68EC060 Quad Flat Pack (FE Suffix)...13-3

13.3 Mechanical Data .........................................................................................13-4

Appendix A

MC68LC060

Appendix B

MC68EC060

B.1 Address Translation Differences...................................................................B-1

B.2 Instruction Differences..................................................................................B-1

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Appendix C

MC68060 Software Package

C.1 Module Format..............................................................................................C-2

C.2 Unimplemented Integer Instructions.............................................................C-4

C.2.1 Integer Emulation Results ..........................................................................C-5

C.2.2 Module 1: Unimplemented Integer Instruction Exception

(MC68060ISP)............................................................................................C-5

C.2.2.1 Unimplemented Integer Instruction Exception Module Entry Points ........C-6

C.2.2.2 Unimplemented Integer Instruction Exception Module Call-Outs.............C-6

C.2.2.3 CAS Misaligned Address and CAS2

Emulation-Related Call-Outs and Entry Points ........................................C-6

C.2.3 Module 2: Unimplemented Integer Instruction Library (MC68060ILSP).....C-9

C.3 Floating-Point Emulation Package (MC68060FPSP) .................................C-11

C.3.1 Floating-Point Emulation Results .............................................................C-13

C.3.2 Module 3: Full Floating-Point Kernel ........................................................C-14

C.3.2.1 Full Floating-Point Kernel Module Entry Points......................................C-14

C.3.2.2 Full Floating-Point Kernel Module Call-Outs..........................................C-14

C.3.2.2.1 The F-Line Exception Call-Outs...........................................................C-14

C.3.2.2.2 System-Supplied Floating-Point Arithmetic

Exception Handler Call-Outs................................................................C-15

C.3.2.2.3 Exception-Related Call-Outs...............................................................C-15

C.3.2.2.4 Exit Point Call-Outs..............................................................................C-15

C.3.2.3 Bypassing Module-Supplied Floating-Point Arithmetic Handlers...........C-15

C.3.2.3.1 Overflow/Underflow..............................................................................C-16

C.3.2.3.2 Signalling Not-A-Number, Operand Error.............................................C-17

C.3.2.3.3 Inexact Exception.................................................................................C-18

C.3.2.3.4 Divide-by-Zero Exception.....................................................................C-19

C.3.2.3.5 Branch/Set on Unordered Exception....................................................C-19

C.3.2.4 Exceptions During Emulation.................................................................C-20

C.3.2.4.1 Trap-Disabled Operation......................................................................C-20

C.3.2.4.2 Trap-Enabled Operation.......................................................................C-21

C.3.3 Module 4: Partial Floating-Point Kernel....................................................C-21

C.3.4 Module 5: Floating-Point Library (M68060FPLSP)...................................C-22

C.4 Operating System Dependencies...............................................................C-23

C.4.1 Instruction and Data Fetches....................................................................C-23

C.4.2 Instructions Not Recommended...............................................................C-26

C.5 Installation Notes ........................................................................................C-27

C.5.1 Installing the Library Modules...................................................................C-27

C.5.2 Installing the Kernel Modules ...................................................................C-27

C.5.3 Release Notes and Module Offset Assignments......................................C-28

C.5.4 AESOP Electronic Bulletin Board.............................................................C-29

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Appendix D

MC68060 Instructions

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MOTOROLA

LIST OF ILLUSTRATIONS

1-1 MC68060 Block Diagram ...................................................................................1-6

1-2 Programming Model.........................................................................................1-12

2-1 Functional Signal Groups...................................................................................2-3

3-1 MC68060 Integer Unit Pipeline ..........................................................................3-1

3-2 Integer Unit User Programming Model...............................................................3-2

3-3 Integer Unit Supervisor Programming Model.....................................................3-3

3-4 Status Register...................................................................................................3-4

3-5 Processor Configuration Register ......................................................................3-5

4-1 Memory Management Unit.................................................................................4-2

4-2 Memory Management Programming Model.......................................................4-3

4-3 URP and SRP Register Formats........................................................................4-3

4-4 Translation Control Register Format..................................................................4-4

4-5 Transparent Translation Register Format ..........................................................4-6

4-6 Translation Table Structure................................................................................4-8

4-7 Logical Address Format .....................................................................................4-8

4-8 Detailed Flowchart of Table Search Operation ................................................4-10

4-9 Detailed Flowchart of Descriptor Fetch Operation ...........................................4-11

4-10 Table Descriptor Formats.................................................................................4-12

4-11 Page Descriptor Formats .................................................................................4-12

4-12 Example Translation Table...............................................................................4-15

4-13 Translation Table Using Indirect Descriptors ...................................................4-16

4-14 Translation Table Using Shared Tables...........................................................4-18

4-15 Translation Table with Nonresident Tables......................................................4-19

4-16 Translation Table Structure for Two Tasks ......................................................4-21

4-17 Logical Address Map with Shared Supervisor and User Address Spaces.......4-22

4-18 Translation Table Using S-Bit and W-Bit To Set Protection.............................4-23

4-19 ATC Organization.............................................................................................4-24

4-20 ATC Entry and Tag Fields................................................................................4-25

4-21 Address Translation Flowchart.........................................................................4-29

5-1 MC68060 Instruction and Data Caches .............................................................5-2

5-2 Instruction Cache Line Format...........................................................................5-2

5-3 Data Cache Line Format....................................................................................5-2

5-4 Caching Operation .............................................................................................5-3

5-5 Cache Control Register......................................................................................5-5

5-6 Instruction Cache Line State Diagram..............................................................5-16

5-7 Data Cache Line State Diagrams.....................................................................5-18

6-1 Floating-Point Unit Block Diagram .....................................................................6-2

6-2 Floating-Point User Programming Model...........................................................6-3

6-3 Floating-Point Control Register Format..............................................................6-4

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List of Illustrations

6-4 Floating-Point Condition Code (FPSR)..............................................................6-5

6-5 Floating-Point Quotient Byte (FPSR).................................................................6-5

6-6 Floating-Point Exception Status Byte (FPSR)....................................................6-6

6-7 Floating-Point Accrued Exception Byte (FPSR).................................................6-6

6-8 Intermediate Result Format.............................................................................. 6-12

6-9 Rounding Algorithm Flowchart......................................................................... 6-14

6-10 Floating-Point State Frame..............................................................................6-35

6-11 Status Word Contents...................................................................................... 6-36

7-1 Signal Relationships to Clocks...........................................................................7-2

7-2 Full-Speed Clock................................................................................................7-2

7-3 Half-Speed Clock...............................................................................................7-2

7-4 Quarter-Speed Clock .........................................................................................7-3

7-5 Bus Control Register Format.............................................................................. 7-4

7-6 Internal Operand Representation.......................................................................7-5

7-7 Data Multiplexing................................................................................................ 7-6

7-8 Byte Select Signal Generation and PAL Equation.............................................7-8

7-9 Example of a Misaligned Long-Word Transfer.................................................7-10

7-10 Example of Misaligned Word Transfer............................................................. 7-10

7-11 Misaligned Long-Word Read Bus Cycle Timing............................................... 7-11

7-12 Byte, Word, and Long-Word Read Cycle Flowchart ........................................7-13

7-13 Byte, Word, and Long-Word Read Bus Cycle Timing...................................... 7-14

7-14 Line Read Cycle Flowchart..............................................................................7-17

7-15 Line Read Transfer Timing............................................................................... 7-18

7-16 Burst-Inhibited Line Read Cycle Flowchart...................................................... 7-20

7-17 Burst-Inhibited Line Read Bus Cycle Timing.................................................... 7-21

7-18 Byte, Word, and Long-Word Write Transfer Flowchart....................................7-22

7-19 Long-Word Write Bus Cycle Timing................................................................. 7-23

7-20 Line Write Cycle Flowchart ..............................................................................7-26

7-21 Line Write Burst-Inhibited Cycle Flowchart......................................................7-27

7-22 Line Write Bus Cycle Timing............................................................................ 7-28

7-23 Locked Bus Cycle for TAS Instruction Timing..................................................7-30

7-24 Using CLA

in a High-Speed DRAM Design .....................................................7-33

7-25 Interrupt Pending Procedure............................................................................ 7-33

7-26 Assertion of IPEND

..........................................................................................7-34

7-27 Interrupt Acknowledge Cycle Flowchart...........................................................7-36

7-28 Interrupt Acknowledge Bus Cycle Timing ........................................................7-37

7-29 Autovector Interrupt Acknowledge Bus Cycle Timing......................................7-38

7-30 Breakpoint Interrupt Acknowledge Cycle Flowchart......................................... 7-39

7-31 Breakpoint Interrupt Acknowledge Bus Cycle Timing......................................7-40

7-32 LPSTOP Broadcast Cycle Flowchart...............................................................7-41

7-33 LPSTOP Broadcast Bus Cycle Timing, BG Negated....................................... 7-42

7-34 LPSTOP Broadcast Bus Cycle Timing, BG Asserted ......................................7-43

7-35 Exiting LPSTOP Mode Flowchart..................................................................... 7-44

7-36 Exiting LPSTOP Mode Timing Diagram...........................................................7-45

7-37 Word Write Access Bus Cycle Terminated with TEA

Timing........................... 7-48

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List of Illustrations

7-38 Line Read Access Bus Cycle Terminated with TEA Timing.............................7-49

7-39 Retry Read Bus Cycle Timing..........................................................................7-50

7-40 Line Write Retry Bus Cycle Timing...................................................................7-51

7-41 MC68040-Arbitration Protocol State Diagram..................................................7-57

7-42 MC68060-Arbitration Protocol State Diagram..................................................7-64

7-43 Processor Bus Request Timing........................................................................7-67

7-44 Arbitration During Relinquish and Retry Timing...............................................7-68

7-45 Implicit Bus Ownership Arbitration Timing........................................................7-69

7-46 Effect of BGR

on Locked Sequences...............................................................7-70

7-47 Snooped Bus Cycle..........................................................................................7-71

7-48 Initial Power-On Reset Timing..........................................................................7-72

7-49 Normal Reset Timing........................................................................................7-73

7-50 Data Bus Usage During Reset.........................................................................7-74

7-51 Acknowledge Termination Ignore State Example ............................................7-75

7-52 Extra Data Write Hold Example........................................................................7-77

8-1 General Exception Processing Flowchart ..........................................................8-2

8-2 General Form of Exception Stack Frame...........................................................8-3

8-3 Interrupt Recognition Examples.......................................................................8-13

8-4 Interrupt Exception Processing Flowchart........................................................8-15

8-5 Reset Exception Processing Flowchart............................................................8-16

8-6 Fault Status Long-Word Format.......................................................................8-22

9-1 JTAG Test Logic Block Diagram........................................................................9-3

9-2 JTAG Idcode Register Format............................................................................9-7

9-3 Output Pin Cell (O.Pin).......................................................................................9-8

9-4 Observe-Only Input Pin Cell (I.Obs)...................................................................9-8

9-5 Input Pin Cell (I.Pin) ...........................................................................................9-9

9-6 Output Control Cell (IO.Ctl)................................................................................9-9

9-7 General Arrangement of Bidirectional Pin Cells...............................................9-10

9-8 JTAG Bypass Register.....................................................................................9-15

9-9 Circuit Disabling IEEE Standard 1149.1...........................................................9-16

9-10 Debug Command Interface Schematic ............................................................9-25

9-11 Interface Timing................................................................................................9-26

9-12 Transition from JTAG to Debug Mode Timing Diagram...................................9-34

9-13 Transition from Debug to JTAG Mode Timing Diagram...................................9-35

11-1 Linear Voltage Regulator Solution....................................................................11-7

11-2 LTC1147 Voltage Regulator Solution...............................................................11-8

11-3 LTC1148 Voltage Regulator Solution...............................................................11-9

11-4 MAX767 Voltage Regulator Solution..............................................................11-10

11-5 MC68040 Address Hold Time........................................................................11-11

11-6 MC68060 Address Hold Time........................................................................11-12

11-7 MC68060 Address Hold Time Fix ..................................................................11-12

11-8 Simple CLK Generation..................................................................................11-14

11-9 Generic CLK Generation................................................................................11-14

11-10 MC68040 BCLK to CLKEN

Relationship........................................................11-15

11-11 DRAM Timing Analysis...................................................................................11-15

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12-12 Clock Input Timing Diagram.............................................................................12-3

12-13 Drive Levels and Test Points for AC Specifications......................................... 12-7

12-14 Reset Configuration Timing.............................................................................. 12-8

12-15 Read/Write Timing ...........................................................................................12-9

12-16 Bus Arbitration Timing....................................................................................12-10

12-17 Bus Arbitration Timing (Continued)................................................................ 12-11

12-18 CLA

Timing ....................................................................................................12-12

12-19 Snoop Timing................................................................................................. 12-13

12-20 Other Signals Timing...................................................................................... 12-14

13-1 PGA Package Dimensions (RC Suffix)............................................................13-4

13-2 QFP Package Dimensions (FE Suffix)............................................................. 13-5

C-1 Call-Out Dispatch Table Example......................................................................C-2

C-2 Example Pseudo-Assembly File ........................................................................C-3

C-3 Module Call-In, Call-Out Example......................................................................C-4

C-4 CAS and CAS2 Call-Outs and Entry Points.......................................................C-9

C-5 C-Code Representation of Integer Library Routines........................................C-10

C-6 MUL Instruction Call Example..........................................................................C-11

C-7 CMP2 Instruction Call Example .......................................................................C-11

C-8 SNAN/OPERR Exception Handler Pseudo-Code............................................C-18

C-9 Disabled vs. Enabled Exception Actions..........................................................C-20

C-10 _mem_read Pseudo-Code...............................................................................C-23

C-11 Register Usage of {i,d}mem_{read,write}_{b,w,l}.............................................C-25

C-12 Vector Table and M68060SP Relationship......................................................C-28

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LIST OF TABLES

1-1 Data Formats....................................................................................................1-14

1-2 Effective Addressing Modes.............................................................................1-15

1-3 Instruction Set Summary..................................................................................1-16

1-4 Notational Conventions....................................................................................1-21

2-1 Signal Index........................................................................................................2-1

2-2 Transfer-Type Encoding.....................................................................................2-4

2-3 Normal and MOVE16 Access TMx Encoding.....................................................2-5

2-4 Alternate Access TMx Encoding ........................................................................2-5

2-5 SIZx Encoding....................................................................................................2-6

2-6 Data Bus Byte Select Signals.............................................................................2-7

2-7 PSTx Encoding.................................................................................................2-14

2-8 Signal Summary...............................................................................................2-17

4-1 Updating U-Bit and M-Bit for Page Descriptors................................................4-20

4-2 SFC and DFC Values.......................................................................................4-20

5-1 TLNx Encoding.................................................................................................5-11

5-2 Instruction Cache Line State Transitions..........................................................5-15

5-3 Data Cache Line State Transitions...................................................................5-18

6-1 RND Encoding....................................................................................................6-4

6-2 PREC Encoding .................................................................................................6-4

6-3 MC68060 FPU Data Formats and Data Types ..................................................6-7

6-4 Single-Precision Real Format Summary............................................................6-8

6-5 Double-Precision Real Format Summary...........................................................6-9

6-6 Extended-Precision Real Format Summary.....................................................6-10

6-7 Packed Decimal Real Format Summary..........................................................6-11

6-8 Floating-Point Condition Code Encoding .........................................................6-16

6-9 Floating-Point Conditional Tests ......................................................................6-18

6-10 Floating-Point Exception Vectors.....................................................................6-19

6-11 Unimplemented Instructions.............................................................................6-20

6-12 Possible Operand Errors Exceptions ...............................................................6-27

6-13 Overflow Rounding Mode Values.....................................................................6-29

6-14 Underflow Rounding Mode Values...................................................................6-31

6-15 Possible Divide-by-Zero Exceptions.................................................................6-33

6-16 Rounding Mode Values....................................................................................6-34

7-1 Data Bus Requirements for Read and Write Cycles..........................................7-7

7-2 Summary of Access Types vs. Bus Signal Encoding.........................................7-9

7-3 Memory Alignment Influence on Noncachable and

Writethrough Bus Cycles..................................................................................7-12

7-4 Interrupt Acknowledge Termination Summary.................................................7-34

7-5 Termination Result Summary...........................................................................7-46

7-6 MC68040-Arbitration Protocol Transition Conditions.......................................7-55

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7-7 MC68040-Arbitration Protocol State Description .............................................7-56

7-8 MC68060-Arbitration Protocol State Transition Conditions.............................. 7-62

7-9 MC68060-Arbitration Protocol State Description .............................................7-63

7-10 Special Mode vs. IPLx

Signals.........................................................................7-74

8-1 Exception Vector Assignments ..........................................................................8-4

8-2 Interrupt Levels and Mask Values....................................................................8-12

8-3 Exception Priority Groups ................................................................................8-17

9-1 JTAG States.......................................................................................................9-2

9-2 JTAG Instructions............................................................................................... 9-4

9-3 Boundary Scan Bit Definitions.......................................................................... 9-10

9-4 Debug Command Interface Pins...................................................................... 9-25

9-5 Command Summary........................................................................................9-28

10-1 Superscalar OEP Dispatch Test Algorithm......................................................10-4

10-2 MC68060 Superscalar Classification of M680x0 Integer Instructions..............10-4

10-3 Superscalar Classification of M680x0 Privileged Instructions..........................10-7

10-4 Superscalar Classification of M680x0 Floating-Point Instructions ...................10-7

10-5 Effective Address Calculation Times.............................................................. 10-14

10-6 Move Byte and Word Execution Times.......................................................... 10-15

10-7 Move Long Execution Times..........................................................................10-15

10-8 MOVE16 Execution Times............................................................................. 10-15

10-9 Standard Instruction Execution Time.............................................................10-16

10-10 Immediate Instruction Execution Times.........................................................10-17

10-11 Single-Operand Instruction Execution Times.................................................10-18

10-12 Clear (CLR) Execution Times ........................................................................10-18

10-13 Shift/Rotate Execution Times.........................................................................10-19

10-14 Bit Manipulation (Dynamic Bit Count) Execution Times.................................10-19

10-15 Bit Manipulation (Static Bit Count) Execution Times......................................10-20

10-16 Bit Field Execution Times............................................................................... 10-20

10-17 Branch Execution Times................................................................................10-21

10-18 JMP, JSR Execution Times............................................................................ 10-21

10-19 Return Instruction Execution Times...............................................................10-21

10-20 LEA, PEA, and MOVEM Instruction Execution Times ...................................10-22

10-21 Multiprecision Instruction Execution Times.................................................... 10-22

10-22 Status Register (SR) Instruction Execution Times......................................... 10-23

10-23 MOVES Execution Times............................................................................... 10-23

10-24 Miscellaneous Instruction Execution Times...................................................10-23

10-25 Floating-Point Instruction Execution Times....................................................10-24

10-26 Exception Processing Times..........................................................................10-26

11-1 With Heat Sink, No Air Flow...........................................................................11-18

11-2 With Heat Sink, with Air Flow......................................................................... 11-18

11-3 No Heat Sink.................................................................................................. 11-19

11-4 Support Devices and Products....................................................................... 11-20

C-1 Call-Out Dispatch Table and Module Size.........................................................C-4

C-2 FPU Comparison..............................................................................................C-12

C-3 Unimplemented Instructions.............................................................................C-13

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List of Tables

C-4 Unimplemented Data Formats and Data Types.............................................. C-13

C-5 UNIX Operating System Calls......................................................................... C-23

C-6 Instructions Not Handled by the M68060SP ................................................... C-26

C-7 Files Provided in an M68060SP Release........................................................ C-27

D-1 M68000 Family Instruction Set and Processor Cross-Reference ..................... D-1

D-2 M68000 Family Instruction Set.......................................................................... D-6

D-3 Exception Vector Assignments for the M68000 Family................................... D-10

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SECTION 1
INTRODUCTION

The superscalar MC68060 represents a new line of Motorola microprocessor products. The
first generation of the M68060 product line consists of the MC68060, MC68LC060, and
MC68EC060. All three microprocessors offer superscalar integer performance of over 100
MIPS at 66 MHz. The MC68060 comes fully equipped with both a floating-point unit (FPU)
and a memory management unit (MMU) for high-performance embedded control and desk­top applications. For cost-sensitive embedded control and desktop applications where an
MMU is required, but the additional cost of a FPU is not justified, the MC68LC060 offers
high-performance at a low cost. Specifically designed for low-cost embedded control appli­cations, the MC68EC060 eliminates both the FPU and MMU, permitting designers to lever­age MC68060 performance while avoiding the cost of unnecessary features. Throughout
this product brief, all references to the MC68060 also refer to the MC68LC060 and the
MC68EC060, unless otherwise noted.

Leveraging many of the same performance enhancements used by RISC designs as well
as providing innovative architectural techniques, the MC68060 harnesses new levels of per­formance for the M68000 family. Incorporating 2.5 million transistors on a single piece of sil­icon, the MC68060 employs a deep pipeline, dual issue superscalar execution, a branch
cache, a high-performance floating-point unit (MC68060 only), eight Kbytes each of on-chip
instruction and data caches, and dual on-chip demand paging MMUs (MC68060 and
MC68LC060 only). The MC68060 allows simultaneous execution of two integer instructions
(or an integer and a float instruction) and one branch instruction during each clock.

The MC68060 features a full internal Harvard architecture. The instruction and data caches
are designed to support concurrent instruction fetch, operand read and operand write refer­ences on every clock. Separate 8-Kbyte instruction and 8-Kbyte data caches can be frozen
to prevent allocation over time-critical code or data. The independent nature of the caches
allows instruction stream fetches, data-stream fetches, and external accesses to occur
simultaneously with instruction execution. The operand data cache is four-way banked to
permit simultaneous read and write access each clock.

A very high bandwidth internal memory system coupled with the compact nature of the
M68000 family code allows the MC68060 to achieve extremely high levels of performance,
even when operating from low-cost memory such as a 32-bit wide dynamic random access
memory system.

Instructions are fetched from the internal cache or external memory by a four-stage instruc­tion fetch pipeline. The MC68060 variable-length instruction system is internally decoded
into a fixed-length representation and channeled into an instruction buffer. The instruction
buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetch

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Introduction

unit and the operand execution units. Fixed format instructions are dispatched to dual four­stage pipelined RISC operand execution engines where they are then executed.

The branch cache also plays a major role in achieving the high performance levels of the
MC68060. It has been implemented such that most branches are executed in zero cycles.
Using a technique known as branch folding, the branch cache allows the instruction fetch
pipeline to detect and change the instruction prefetch stream before the change of flow
affects the instruction execution engines, minimizing the need for pipeline refill.

In addition to substantial cost and performance benefits, the MC68060 also offers advan­tages in power consumption and power management. The MC68060 automatically mini­mizes power dissipation by using a fully-static design, dynamic power management, and
low-voltage operation. It automatically powers-down internal functional blocks that are not
needed on a clock-by-clock basis. Explicitly the MC68060 power consumption can be con­trolled from the operating system. Although the MC68060 operates at a lower operating volt­age, it directly interfaces to both 3-V and 5-V peripherals and logic.

Complete code compatibility with the M68000 family allows the designer to draw on existing
code and past experience to bring products to market quickly. There is also a broad base of
established development tools, including real-time kernels, operating systems, languages,
and applications, to assist in product design. The functionality provided by the MC68060
makes it the ideal choice for a range of high-performance embedded applications and com­puting applications. With M68000 family code compatibility, the MC68060 provides a range
of upgrade opportunities to virtually any existing MC68040 application.

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Introduction

1.1 DIFFERENCES AMONG M68060 FAMILY MEMBERS

Because the functionality of individual M68060 family members are similar, this manual is
organized so that the reader will take the following differences into account while reading
the rest of this manual. Unless otherwise noted, all references to MC68060, with the excep­tion of the differences outlined below, will apply to the MC68060, MC68LC060, and
MC68EC060. The following paragraphs describe how the MC68LC060 and the
MC68EC060 differ from the MC68060.

1.1.1 MC68LC060

The MC68LC060 is a derivative of the MC68060. The MC68LC060 has the same execution
unit and MMU as the MC68060, but has no FPU. The MC68LC060 is 100% pin compatible
with the MC68060. Disregard all information concerning the FPU when reading this manual.
The following difference exists between the MC68LC060 and the MC68060:

• The MC68LC060 does not contain an FPU. When floating-point instructions are
encountered, a floating-point disabled exception is taken.

1.1.2 MC68EC060

The MC68EC060 is a derivative of the MC68060. The MC68EC060 has the same execution
unit as the MC68060, but has no FPU or paged MMU, which embedded control applications
generally do not require. Disregard information concerning the FPU and MMU when reading
this manual. The MC68EC060 is pin compatible with the MC68060. The following differ­ences exist between the MC68EC060 and the MC68060:

• The MC68EC060 does not contain an FPU. When floating-point instructions are
encountered, a floating-point disabled exception is taken.

• The MDIS
purposes only.

1.1.2.1 ADDRESS TRANSLATION DIFFERENCES. Although the MC68EC060 has no

paged MMU, the four transparent translation registers (ITT0, ITT1, DTT0, and DTT1) and
the default transparent translation (defined by certain bits in the translation control register
(TCR)) operate normally and can still be used to assign cache modes and supervisor and
write protection for given address ranges. All addresses can be mapped by the four trans­parent translation registers (TTRs) and the default transparent translation.

1.1.2.2 INSTRUCTION DIFFERENCES. The PFLUSH and PLPA instructions, the supervi-

sor root pointer (SRP) and user root pointer (URP) registers, and the E- and P-bits of the
TCR are not supported by the MC68EC060 and must not be used. Use of these instructions
and registers in the MC68EC060 exhibits poor programming practice since no useful results
can be achieved. Any functional anomalies that may result from their use will require system
software modification (to remove offending instructions) to achieve proper operation.

pin name has been changed to the JS0 pin and is included for boundary scan

The PLPA instruction operates normally except that when an address misses in the four
TTRs, instead of performing a table search operation, the access cache mode and write pro­tection properties are defined by the default transparent translation bits in the TCR. The
address register contents are never changed since all addresses are always transparently

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Introduction

translated. The PLPA instruction can only generate an access error exception only on super­visor or write protection violation cases. The PFLUSH instruction operates as a virtual NOP
instruction.

When the MOVEC instruction is used to access the SRP and URP registers and the E- and
P-bits in the TCR, no exceptions are reported. However, those bits are undefined for the
MC68EC060 and must not be used.

1.2 FEATURES

The main features of the MC68060 are as follows:

• 1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Com­pliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.

• Harvard Architecture with Independent, Decoupled Fetch and Execution Pipelines.

• Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped
Branch Cache for Improved Branch Instruction Performance.

• A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but
not Out-of-Order Instruction Execution.

• An IEEE Standard, MC68040- and MC68881-/MC68882-Compatible FPU.

• An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry
Address Translation Caches

• Dual 8-Kbyte Caches (Instruction Cache and Data Cache)

• A Flexible, High-Bandwidth Synchronous Bus Interface

• User Object-Code Compatible with All Earlier M68000 Microprocessors

1.3 ARCHITECTURE

The instruction fetch unit (IFU) is a four-stage pipeline for prefetching instructions. The dual
operand execution pipelines (OEPs) (named primary” (pOEP) and secondary (sOEP)) are
four-stage pipelines for decoding the instructions, fetching the required operand(s), and then
performing the actual execution of the instructions. Since the IFU and OEP are decoupled
by a first-in-first-out (FIFO) instruction buffer, the IFU is able to prefetch instructions in
advance of their actual use by the OEPs.

The MC68060 is designed to maximize the OEP’s efficiency through the use of a supersca­lar pipeline architecture. This architectural advance improves processor performance dra­matically by exploiting instruction-level parallelism. The term superscalar denotes the ability
to detect, dispatch, execute, and return results from more than one instruction during each
machine cycle from an otherwise conventional instruction stream.

As a result, multiple instructions may be executed in a single machine cycle. Since the dual
OEPs perform in a lock-step mode of operation, the multiple instruction execution is per­formed simultaneously, but not out-of-order. The net effect is a software-invisible pipeline
architecture capable of sustained execution rates of < 1 machine cycle per instruction of the
M68000 instruction set.

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Architectural highlights of the MC68060 include:

• Four-Stage Instruction Fetch Unit (IFU)
— 64-Entry Instruction Address Translation Cache (ATC), Organized as 4-Way Set-

Associative, for Fast Virtual-to-Physical Address Translations
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache
—256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache, Which Predicts

the Direction of Branches Based on Their Past Execution History
—96-Byte FIFO Instruction Buffer to Allow Decoupling of the IFP and OEPs

• Four-Stage Execution Pipelines Featuring Primary Pipeline (pOEP), Secondary Pipe­line (sOEP), and Register File (RGF) Containing Program-Visible General Registers
— 64-Entry Operand Data ATC, Organized as 4-Way Set-Associative, for Fast Virtual-

to-Physical Address Translations
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Operand Data Cache
— The Operand Data Cache Is Organized in a Banked Structure to Allow Simultaneous

Read/Write Accesses
— Integer Execute Engines Optimized to Perform Most Instruction Executions in a

Single Machine Cycle
—Floating-Point Execute Engine, with Floating-Point Register File, Optimized for Per-

formance with Extended-Precision-Wide Internal Datapaths.
—Four-Entry Store Buffer and One-Entry Push Buffer That Provide the Performance

Feature of Decoupling the Processor Pipeline from External Memory for Certain

Cache Modes of Operation.

This pipeline architecture supports extremely high data transfer rates within the MC68060
processor. The on-chip instruction and operand data caches provide 600 MBytes/sec @ 50
MHz to the pipelines, while the integer execute engines can support sustained transfer rates
of 1.2 GBytes/sec.

1.4 PROCESSOR OVERVIEW

The following paragraphs provide a general description of the MC68060.

1.4.1 Functional Blocks

Figure 1-1 illustrates a simplified block diagram of the MC68060.

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Introduction

The architecture of the MC68060 processor is implemented in the following major blocks:

• Execution Unit
—Instruction Fetch Unit
—Integer Unit
—FPU

• Memory Units
—Instruction Memory Unit

• Instruction ATC

• Instruction Cache

• Instruction Cache Controller

—Data Memory Unit

• Data ATC

• Data Cache

• Data Cache Controller

• Bus Controller

These major units execute concurrently to maximize sustained performance. Note that the
caches reside on separate buses allowing concurrent instruction fetch, data read, and data
write operations (internal Harvard architecture).

EXECUTION UNIT

FLOATING-

POINT

UNIT

OC

EA

FETCH

EXECUTE

FP

EX

INSTRUCTION FETCH UNIT

BRANCH

CACHE

INSTRUCTION

BUFFER

pOEP sOEP

DECODE

CALCULATE

FETCH

EXECUTE

DATA AVAILABLE

WRITE-BACK

DS DS

EA

OC OC

EA

EX

INT

INTEGER UNIT

IA

CALCULATE

INSTRUCTION

FETCH
EARLY

DECODE

DECODE

EA

CALCULATE

EA

FETCH

INT

EXECUTE

AGAG

EX

IB

IAG

IC

IED

DA

WB

INSTRUCTION

ATC

INSTRUCTION
CONTROLLER

INSTRUCTION MEMORY UNIT

CONTROLLER

DATA

ATC

DATA MEMORY UNIT

CACHE

DATA

CACHE

INSTRUCTION

CACHE

DATA

CACHE

B
U
S

C
O
N
T
R
O
L
L
E
R

ADDRESS

DATA

CONTROL

1-6

OPERAND DATA BUS

Figure 1-1. MC68060 Block Diagram

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