Freescale MC33991 Technical Data

Freescale Semiconductor

Technical Data

Gauge Driver Integrated Circuit

This 33991 is a single packaged, Serial Peripheral Interface (SPI)
controlled, dual stepper motor gauge driver Integrated Circuit (IC).
This monolithic IC consists of four dual output H-Bridge coil drivers
and the associated control logic. Each pair of H-Bridge drivers is used
to automatically control the speed, direction and magnitude of current
through the two coils of a two-phase instrumentation stepper motor,
similar to an MMT licensed AFIC 6405.

This device is ideal for use in automotive instrumentation systems
requiring distributed and flexible stepper motor gauge driving. The
device also eases the transition to stepper motors from air core
motors by emulating the air core pointer movement with little
additional processor bandwidth utilization.

The device has many attractive features including:

Features

• MMT-Licensed Two-Phase Stepper Motor Compatible

• Minimal Processor Overhead Required

• Fully Integrated Pointer Movement and Position State Machine
with Air Core Movement Emulation

• 4096 Possible Steady State Pointer Positions

• 340° Maximum Pointer Sweep

• Linear 4500° 2

• Maximum Pointer Velocity of 400°

• Analog Microstepping (12 Steps/Degree of Pointer Movement)

• Pointer Calibration and Return to Zero

• SPI Controlled 16-Bit Word

• Calibratable Internal Clock

• Low Sleep Mode Current

• Pb-Free Packaging Designated by Suffix Code EG

Document Number: MC33991

Rev. 2.0, 11/2006

33991

GAUGE DRIVER INTEGRATED CIRCUIT

DW SUFFIX

EG SUFFIX (PB-FREE)

98ASB42344B
24-PIN SOICW

ORDERING INFORMATION

Device

MC33991DW/R2

MCZ33991EG/R2

Temperature

Range (T

-40 to 125°C SOICW

)

A

Package

V

PWR

5.0 V

Regulator

MCU

VPWR

VDD

RT
RS
CS

SCLK
SI
SO

33991

SIN1+

SIN1-

COS1+

COS1-

SIN2+

SIN2-

COS2+

COS2-

GND

Motor 1

Motor 2

Figure 1. 33991 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2006. All rights reserved.

INTERNAL BLOCK DIAGRAM

VDD

INTERNAL BLOCK DIAGRAM

VPWR

Internal

Reference

CS

SCLK

SO

RST

SI

COS0

SIN0

SPI

COS1

H-BRIDGE

Logic

Under

ILIM

&

CONTROL

&

Over

Voltage

Detect

Over Temp

SIN1

Oscillator

GND

Figure 2. 33991 Simplified Internal Block Diagram

RTZ

COS0+
COS0-

SIN0+
SIN0-

COS1+
COS1-

RTZ

SIN1+
SIN1-

33991

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

PIN CONNECTIONS

COS0+

COS0
SIN0+

SIN0
GND
GND
GND
GND

CS

SCLK

SO

1
2
3
4
5
6
7
8
9
10
11
12

SI

24

COS1+

23

COS1-

22

SIN1+

21

SIN1-

20

GND

19

GND

18

GND

17

GND

16

PWR

V

15

RST

14

VDD

13

RTZ

Table 1. 33991 Pin Definitions

Pin Number Pin Name Definitions

1 COS0+

2

COS0-

3 SIN0+

4 SIN0-

5 - 8 GND

9 CS

10 SCLK

11 SO

12 SI

13 RTZ
14 VDD

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

Ground. These pins serve as the ground for the source of the low-side output transistors as well as the
logic portion of the device. They also help dissipate heat from the device.

Chip Select. This pin is connected to a chip select output of a LSI IC. This IC controls which device is
addressed by pulling the CS pin of the desire device low, enabling the SPI communication with the device,
while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active
pull-up, requiring CMOS logic levels. This pin is also used to calibrate the internal clock.

Serial Clock. This pin is connected to the SCLK pin of the master device and acts as a bit clock for the
SPI port. It transitions on time per bit transferred at an operating frequency, fSPI, defined in the Coil Output
Timing Table. It is idle between command transfers. The pin is 50 percent duty cycle, with CMOS logic
levels. This signal is used to shift data to and from the device.

Serial Output. This pin is connected to the SPI Serial Data Input pin of the master device, or to the SI pin
of the next device in a daisy chain. This output will remain tri-stated unless the device is selected by a low
CS signal. The output signal generated will have CMOS logic levels and the output will transition on the
rising edges of SCLK. The serial output data provides status feedback and fault information for each output
and is returned MSB first when the device is addressed.

Serial Input. This pin is connected to the SPI Serial Data Output pin of the master device from which it
receives output command data. This input has an internal active pull down requiring CMOS logic levels.
The serial data transmitted on this line is a 16-bit control command sent MSB first, controlling the gauge
functions. The master ensures data is available on the falling edge of SCLK.

Multiplexed Output. This multiplexed output pin of the non-driven coil during an RTZ event.

Voltage. This SPI and logic power supply input will work with 5.0 V supplies.

33991

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

PIN CONNECTIONS

Table 1. 33991 Pin Definitions (continued)

Pin Number Pin Name Definitions

15 RST

16 VPWR

17 - 20 GND

21 SIN1-

22 SIN1+

23 COS1-

24 COS1+

Reset. If the master decides to reset the device, or place it into a sleep state, the RST pin is driven to a
logic 0. A logic 0 on the RST pin will force all internal logic to the known default state. This input has an
internal active pull-up.

Battery Voltage. Power supply.
Ground. These pins serve as the ground for the source of the low-side output transistors as well as the

logic portion of the device. They also help dissipate heat from the device.
H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge

pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

H-Bridge Output. This is the output pin of a half bridge, designed to source or sink current. The H-Bridge
pins linearly drive the sine and cosine coils of two separate stepper motors to provide four-quadrant
operation.

33991

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. 33991 Maximum Ratings

(All voltages are with respect to ground unless otherwise noted)

Rating Symbol Value Limit

Power Supply Voltage

Steady State
Input Pin Voltage
SIN+/- COS +/- Continuous Per Output Current

(1)

(2)

Storage Temperature
Operating Junction Temperature
Thermal Resistance (C/W) Ambient

Junction to Lead

ESD Voltage

(3)

Human Body Model

Machine Model
Peak Package Reflow Temperature During Reflow

(4), (5)

V

PWR(SUS)

V

IN

I

OUTMAX

T

STG

T

JUNC

θ

JA

θ

JL

V

ESD1

V

ESD2

T

PPRT

-0.3 to 41

-0.3 to 7.0 V
40 mA

-55 to 150 °C

-40 to 150 °C
60

20

±2000

±200

Note 5

Notes

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.

2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature
will require maximum output current computation using package thermal resistances

3. VESD1 testing is performed in accordance with the Human Body Model (Czap = 100pF, Rzap = 1500 Ω), All pins are capable of Human
Body Model RSP voltages of ±2000 V with one exception. The SO pin is capable of ± 1900 V, VESD2 testing is performed in accordance
with the Machine Model (Czap = 200pF, Rzap = 0 Ω)

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the cor e ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

V

°C/W
°C/W

V
V

°C

33991

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

(Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

POWER INPUT

Supply Voltage Range

Fully Operational

VPWR Supply Current

V

PWR

I

PWR(ON)

6.5
—

(Gauge 1 & 2 outputs ON, no output loads)

VPWR Supply Current (all Outputs Disabled)

(Reset =logic 0, VDD =5 V)
(Reset =logic 0, VDD =0 V)

Over Voltage Detection Level
Under Voltage Detection Level

(6)

(7)

Logic Supply Voltage Range (5 V nominal supply)
Under VDD Logic Reset
VDD Supply Current (Sleep: Reset logic 0)
VDD Supply Current (Outputs Enabled)

I

PWSLP1

I

PWRSLP2

V

PWROV

V

PWRUV

V

DD

V

DDUV

I

DD(OFF)

I

DD(ON)

—

26 32 38 V

5.0 5.6 6.2 V

4.5 5.0 5.5 V
— — 4.5 V
— 40 65 µA
— 1.0 1.8 mA

Notes

6. Outputs will disable and must be re-enabled via the PECR command.

7. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

—

4.0 6.0

42
15

26.0 V
mA

µA
60
25

33991

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

Table 3. Static Electrical Characteristics (continued)

(Characteristics noted under conditions 4.75 V <

Characteristic Symbol Min Typ Max Unit

POWER OUTPUTS

Microstep Output (measured across coil outputs)
Sin0,1, ± (Cos0,1, ±) (see 33991 Pinout)
Rout = 200 Ω

steps 6,18 (0,12)
steps 5, 7, 17,19 (1,11,13, 23)
steps 4, 8.16, 20 (2,10,14, 22)
steps 3, 9,15, 21 (3, 9,15, 21)
steps 2,10,14, 22 (4, 8,16, 20)
steps 1,11,13, 23 (5, 7,17,19)
steps 0,12 (6,18)

Full step Active Output (measured across coil outputs)
Sin0,1, ± (Cos0,1, ±) (see Figure 4)

steps 1, 3 (0, 2)

Microstep, Full Step Output (measured from coil low side to ground)
Sin0,1, ± (Cos0,1, ±) I

Output Flyback Clamp
Output Current Limit (Out = VSTP6)
Over temperature Shutdown
Over temperature Hysteresis

Notes

8. Not 100 percent tested.

OUT

(8)

= 30mA

(8)

VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

5.3

0.97XVST6

0.87XVST6

0.71XVST6

0.50XVST6

0.26XVST6
0

6.0

1.00XVST6

0.94XVST6

0.79XVST6

0.57XVST6

0.31XVST6

0.1

VST6
VST5
VST4
VST3
VST2
VST1
VST0

STATIC ELECTRICAL CHARACTERISTICS

4.9

0.94XVST6

0.84XVST6

0.69XVST6

0.47XVST6

0.23XVST6

-0.1

VFS 4.9 5.3 6.0

VLS 0 0.1 0.3 V
VFB — VST1+0.5 VST1+1.0 V

I

LIM

40 100 170 mA

OTSD 155 — 180 °C

OT

HYST

8 — 16 °C

V

V

33991

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

(Characteristics noted under conditions 4.75 V <

Characteristic Symbol Min Typ Max Unit

CONTROL I/O

(11)

(9)

(9)

(10)

(11)

Input Logic High Voltage
Input Logic Low Voltage
Input Logic Voltage Hysteresis
Input Logic Pull Down Current (SI, SCLK)
Input Logic Pull-Up Current (CS, RST)
SO High State Output Voltage (IOH = 1.0 mA)
SO Low State Output Voltage (IOL = -1.6 mA)
SO Tri-State Leakage Current (CS ≥ 3.5 V)
Input Capacitance
SO Tri-State Capacitance

Notes

9. VDD = 5 V

10. Not Production Tested. This parameter is guaranteed by design, but it is not production tested.

11. Capacitance not measured. This parameter is guaranteed by design, but it is not production tested.

VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)

V

IH

V

IL

V

IN(HYST)

I

DWN

I

UP

V

SOH

V

SOL

S

OLK

C

IN

C

SO

2.0 — — V
— — 0.8 V
— 100 — mV

3 — 20 µA
5 — 20 µA

0.8VDD — — V
— 0.2 0.4 V

-5 0 5 µA
— 4 12 pF
— — 20 pF

33991

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

(Characteristics noted under conditions 4.75 V <

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT AND CLOCK TIMINGS

SIN, COS Output Turn ON delay Time (time from rising CS enabling
outputs to steady state coil voltages and currents)

SIN, COS Output Turn OFF delay Time (time from rising CS disables
outputs to steady state coil voltages and currents)

Uncalibrated Oscillator Cycle Time
Calibrated Oscillator Cycle Time (Cal pulse = 8 µs, PECR D4 is logic 0)
Calibrated Oscillator Cycle Time (Cal pulse = 8 µs, PECR D4 is logic 1)
Maximum Pointer Speed
Maximum Pointer Acceleration

Notes

12. Maximum specified time for the 33991 is the minimum guaranteed time needed from the micro.

13. The minimum and maximum value will vary proportionally to the internal clock tolerance. These are not 100 percent tested.

(13)

(13)

VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)

(12)

(12)

T

DHY(ON)

T

DHY(OFF)

T

CLU

T

CLC

T

CLC

V

MAX

A

MAX

— — 1.0 mS

— — 1.0 mS

0.65 1.0 1.7 µS

1.0 1.1 1.2 µS

0.9 1.0 1.1 µS
— — 400 °C
— — 4500 °C

2

33991

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

(Characteristics noted under conditions 4.75 V <

Characteristic Symbol Min Typ Max Unit

SPI TIMING INTERFACE

Recommended Frequency of SPI Operation
Falling edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)
SO Rise Time (CL=200pF)
SO Fall Time (CL=200pF)
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
Falling Edge of RST to Rising Edge of RST (Required Setup Time)

14. Rising Edge of CS to Falling Edge of CS (Required Setup

(15) (20)

Time)

Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid

0.2 V

< = SO> = 0.8 VDD, CL = 200 pF

DD

Notes

15. The maximum setup time that is specified for the 33991 is the minimum time needed from the micro controller to guarantee correct
operation.

16. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

17. Time required for output status data to be available for use at SO. 1 K Ohm load on SO

18. Time required for output status data to be terminated at SO. 1 K Ohm load on SO.

19. Time required to obtain valid data out from SO following the rise of SCLK.

20. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.

(16)

(16)

VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)

(15)

(19)

(15)

(17)

(18)

(15)

(15)

(15)

(15)

T

T

TS

TSI

Tr
Tf

Tw

T

T

SO(EN)

T

SO(DIS)

T

f

SPI

LEAD

LAG

LSU

(HOLD)

SO
SO

Tr

SI

Tf

SI
RST
CS

T

EN

VALID

— 1.0 3.0 MHz
— 50 167 ns
— 50 167 ns
— 25 83 ns
— 25 83 ns
— 25 50 ns
— 25 50 ns
— — 50 ns
— — 50 ns
— — 3.0 µs
— — 5.0 µs

— — 5.0 µs
— — 145 ns
— 1.3 4.0 µs
— 65 105 ns

The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range
specified in the environmental requirements section. Digital Interface timing is based on a symmetrical 50% duty cycle SCLK
Clock Period of 333 ns. The device shall be fully functional for slower clock speeds.

33991

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

RSTB

RST

CS

CSB

SCLK

SCLK

SI

SI

TwRSTB

0.7VDD

Don’t Care

0.2 VDD

0.7VDD

0.2VDD

TENBL

Tlead

0.7 VDD

0.2VDD

TIMING DIAGRAMS

TwSCLKh

TSIsu

Valid

TwSCLKl

ELECTRICAL CHARACTERISTICS

0.7VDD

TrSI

Tlag

TSI(hold)

Don’t Care Don’t Care

TfSI

Valid

TIMING DIAGRAMS

VIH

VIL

TCSB

VIH

VIL

VIH

VIL

VIH

VIL

SCLK

SO

Low-to-High

SO

High-to-Low

Figure 3. Input Timing Switching Characteristics

TrSI

3.5V
50%

TdlyLH

0.2 VDD
TrSO

Tvalid

TfSO

0.7 VDD

TdlyHL

TfSI

0.7 VDD

0.2VDD

1.0V

VOH

VOL

VOH

VOL

VOH

VOL

Figure 4. Valid Data Delay Time and Valid Time Waveforms

33991

Analog Integrated Circuit Device Data
Freescale Semiconductor 11