Freescale MC33794 Technical Data

Freescale Semiconductor

Technical Data

Electric Field Imaging Device

Document Number: MC33794

Rev 9, 11/2006

The MC33794 is intended for applications where noncontact sensing of
objects is desired. When connected to external electrodes, an electric field is
created.,The MC33794 is intended for use in detecting objects in this electric
field. The IC generates a low-frequency sine wave. The frequency is adjustable
by using an external resistor and is optimized for 120 kHz. The sine wave has
very low harmonic content to reduce harmonic interference.

The MC33794 also contains support circuits for a microcontroller unit (MCU)
to allow the construction of a two-chip E-field system.

Features

• Supports up to 9 Electrodes and 2 References or Electrodes

• Shield Driver for Driving Remote Electrodes Through Coaxial Cables

• +5.0 V Regulator to Power External Circuit

• ISO-9141 Physical Layer Interface

• Lamp Driver Output

• Watchdog and Power-ON Reset Timer

• Critical Internal Nodes Scaled and Selectable for Measurement

• High-Purity Sine Wave Generator Tunable with External Resistor

Typical Applications

• Occupant Detection Systems

• Appliance Control Panels and Touch Sensors

• Linear and Rotational Sliders

• Spill Over Flow Sensing Measurement

• Refrigeration Frost Sensing

• Industrial Control and Safety Systems Security

• Proximity Detection for Wake-Up Features

• Touch Screens

• Garage Door Safety Sensing

• Liquid Level Sensing

MC33794

ELECTRIC FIELD

IMAGING DEVICE

EK SUFFIX

54-LEAD SOICW-EP

CASE 1390-02

ORDERING INFORMATION

Device Name Temperature Range (TA)

MC33794EK/R2 -40°C to 85°C 1390-02 54 SOICW-EP

© Freescale Semiconductor, Inc., 2006. All rights reserved.

Package
Drawing

Package

INTERNAL BLOCK DIAGRAM

A,B,C,D

TEST

E1–E9

REF_A*, REF_B*

* REF_A and REF_B are
not switched to ground
when not selected.

WD_IN

V

DD

V

CC

RST

2.8 kΩ

2.8 kΩ

4

700 Ω*

700 Ω*

POR/

WD

MUX
OUT

MUX

IN

CONTROL

LOGIC

22 k

Ω (Nominal)

OSC

RECT

LPF

GAIN AND

OFFSET

150

300 Ω

CLK
R_OSC

39 kΩ

SHIELD_EN

Ω

SHIELD

LP_CAP

10 nF

LEVEL

V

V

PWR

AGND

GND and HEAT SINK

PWR_MON

MON

V

DD

_

LAMP_GND

LAMP_CTRL

ISO_OUT

ISO_IN

CC

REG

V

DD

REG

ATTN

LAMP CKT

ISO-9141

SIGNAL

LAMP_SENSE

LAMP_MON

LAMP_OUT

ISO-9141

(Note: All Resistor Values are Nominal)

Figure 1. Simplified Functional Block Diagram

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SOICW-EP TERMINAL CONNECTIONS

RST

WD_IN

NC

LAMP_GND

NC

LAMP_OUT

NC

LAMP_SENSE

LAMP_MON
SHIELD_EN

SIGNAL

LEVEL

PWR_MON

LP_CAP

R_OSC

NC
NC
NC
NC

CLK

MON

V

DD

_

V

DD

V

PWR

1

2

3

4

5

6

7

8

9

10

11

D

12

C

13

B

14

A

15

16

17

18

19

20

21

22

23

24

25

26

27

Figure 2. SOICW-EP Terminal Connections

Table 1. SOICW-EP TERMINAL FUNCTION DESCRIPTION

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

LAMP_CTRL
ISO-9414
NC
ISO_IN
NC
NC
NC
ISO_OUT
REF_B
REF_A
E9
E8
E7
E6
E5
E4
E3
E2
E1
TEST
NC
NC
GND
NC
SHIELD
AGND
V

CC

Terminal

Terminal

Name

Formal Name Definition

1 RST Reset

2 WD_IN Watchdog In

3, 5, 7,

NC No connect

20–23, 31,

33, 34,

48– 50, 52

4 LAMP_GND Lamp Ground

6 LAMP_OUT Lamp Driver

This output is intended to generate the reset function of a typical MCU. It has a
delay for Power-ON Reset, level detectors to force a reset when V
out-of-range high or low, and a watchdog timer that will force a reset if WD_IN

REG is

CC

is not asserted at regular intervals. Timing is derived from the oscillator and will
change with changes in the resistor attached to R_OSC.

This terminal must be asserted and deserted at regular interval in order to
prevent

RST from being asserted. By having the MCU program perform this

operation more often the allowed time, a check that the MCU is running and
executing its program is assured. If this doesn’t occur, the MCU will be reset. If
the watchdog function is not desired, this terminal may be connected to CLK to
prevent a reset from being issued.

These terminals may be used at some future date and should be left open.

This is the ground for the current from the lamp. The current into LAMP_OUT
flows out through this terminal.

This is an active low output capable of sinking current of a typical indicator lamp.
One end of the lamp should be connected to a positive supply (for example,
battery voltage) and the other side to this terminal. The current is limited to
prevent damage to the IC in the case of a short or surge during lamp turn-on or
burn-out.

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Table 1. SOICW-EP TERMINAL FUNCTION DESCRIPTION (continued)

Terminal

Terminal

Name

Formal Name Definition

8 LAMP_SENSE Lamp Sense

9 LAMP_MON Lamp Monitor

10 SHIELD_EN Shield Driver

11–14 A, B, C, D Selector Inputs

15 SIGNAL Undetected Signal

16 LEVEL Detected Level

17 PWR_MON Power Monitor

This terminal is normally connected to the LAMP_OUT terminal. The voltage at
this terminal is reduced and sent to LAMP_MON so the voltage at the lamp
terminal is brought into the range of the analog-to-digital converter (ADC) in the
MCU.

This terminal is connected through a voltage divider to the LAMP_SENSE
terminal. The voltage divider scales the voltage at this terminal so that battery
voltage present when the lamp is off is scaled to the range of the MCU ADC.
With the lamp off, this terminal will be very close to battery voltage if the lamp is
not burned out and the terminal is not shorted to ground. This is useful as a lamp
check.

This terminal is used to enable the shield signal. The shield is disabled when
SHIELD_EN is a logic low (ground)

These input terminals control which electrode or reference is active. Selection
values are shown in Table 5, Electrode Selection, page 10

. These are logic level

inputs.

This is the undetected signal being applied to the detector. It has a DC level with
the low radio frequency signal superimposed on it. Care must be taken to
minimize DC loading of this signal. A shift of DC will change the center point of
the signal and adversely affect the detection of the signal.

This is the detected, amplified, and offset representation of the signal voltage on
the selected electrode. Filtering of the rectified signal is performed by a capacitor
attached to LP_CAP.

This is connected through a voltage divider to V
voltage so it will fall within the range of the ADC on the MCU.

. It allows reduction of the

PWR

18 LP_CAP Low-Pass Filter Capacitor

19 R_OSC Oscillator Resistor

24 CLK Clock

25 V

26 V

27 V

28 V

MON VDDMonitor

DD

_

DD

PWR

CC

VDD Capacitor

Positive Power Supply

5.0 V Regulator Output

29 AGND Analog Ground

30 SHIELD Shield Driver

A capacitor on this terminal forms a low pass filter with the internal series
resistance from the detector to this terminal. This terminal can be used to
determine the detected level before amplification or offset is applied. A 10 nF
capacitor connected to this terminal will smooth the rectified signal. More
capacitance will increase the response time.

A resistor from this terminal to circuit ground determines the operating frequency
of the oscillator. The MC33794 is optimized for operation around 120 kHz.

This terminal provides a square wave output at the same frequency as the
internal oscillator. The edges of the square wave coincide with the peaks
(positive and negative) of the sine wave.

This is connected through an internal voltage divider to V
reduction of the voltage so it will fall within the range of the ADC on the MCU.

REG. It allows

DD

A capacitor is connected to this terminal to filter the internal analog regulated
supply. This supply is derived from V

through internal V

PWR

DD

REG.

12 V power applied to this terminal will be converted to the regulated voltages
needed to operate the part. It is also converted to 5.0 V (internal V

8.5 V (internal V

REG) to power the MCU and external devices.

DD

This output terminal requires a 47 µF capacitor and internal V
a regulated 5.0 V for the MCU and for internal needs of the MC33794.

REG) and

CC

REG provides

CC

This terminal is connected to the ground return of the analog circuitry. This
ground should be kept free of transient electrical noise like that from logic
switching. Its path to the electrical current return point should be kept separate
from the return for GND.

This terminal connects to cable shields to cancel cable capacitance.

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Table 1. SOICW-EP TERMINAL FUNCTION DESCRIPTION (continued)

Terminal

32 GND Ground

35 TEST Test Mode Control

36–44 E1–E9 Electrode Connections

45, 46 REF_A,

47 ISO_OUT ISO-9141 Output

51 ISO_IN ISO-9141 Input

53 ISO-9141 ISO-9141 Bus

54 LAMP_CTRL Lamp Control

Terminal

Name

REF_B

(E10, E11)

Formal Name Definition

Reference Connections

(Or as additional electrodes)

This terminal and metal backing is the IC power return and thermal radiator /
conductor.

This terminal is normally connected to circuit ground. There are special
operating modes associated with this terminal when it is not at ground.

These are the electrode terminals. They are connected either directly or through
coaxial cables to the electrodes for measurements. When not selected, these
outputs are grounded through the internal resistance.

These terminals can be individually selected to measure a known capacitance
value. Unlike E1-E9, these two inputs are not grounded when not selected.

This terminal translates ISO-9141 receive levels to 5.0 V logic levels for the
MCU.

This terminal accepts data from the MCU to be sent over the ISO-9141
communications interface. It translates the 5.0 V logic levels from the MCU to
transmit levels on the ISO-9141 bus.

This terminal connects to the ISO-9141 bus. It provides the drive and detects
signaling on the bus and translates it from the bus level to logic levels for the
MCU.

This signal is used to control the lamp driver. A high logic level turns on the lamp.

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MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating Symbol Value Unit

Peak VPWR Voltage

Double Battery

1 Minute Maximum T

= 30°C

A

V

PWRPK

V

DBLBAT

40 V

26.5

ESD Voltage

Human Body Model

Machine Model

(1)

(2)

Storage Temperature

Operating Ambient Temperature

Operating Junction Temperature

Thermal Resistance

Junction-to-Ambient

Junction-to-Case

Junction-to-Board

(3)

(4)

(5)

Lead Soldering Temperature (for 10 Seconds)

V
V

T

ESD1

ESD2

STG

T

A

±2000

±200

-55 to 150 °C

-40 to 85 °C

TJ -40 to 150 °C

R

θ

R

θ

R

θ

T

SOLDER

JA

JC

JB

260 °C

41

0.2

3.0

°C/W

Notes

1. ESD1 performed in accordance with the Human Body Model (C

2. ESD2 performed in accordance with the Machine Model (C

ZAP

= 200 pF, R

ZAP

= 100 pF, R

ZAP

= 1500 Ω).

ZAP

= 0 Ω).

3. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. In accordance with
SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MILSPEC 883 Method 1012.1) with the cold plate temperature used for the case temperature.

5. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.

V

V

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