Freescale MC14489B Technical Data
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
M u Iti-Character
lED Display/lamp Driver
CMOS
The MC144898 is a flexible light-emitting-diode driver which directly interfaces to individual lamps, 7-segment displays, or various combinations of
both. LEOs wired with common cathodes are driven in a multiplexed-by-5
fashion. Communication with an MCUIMPU is established through a synchronous serial port. The MC 144898 features data retention plus decode and scan
circuitry, thus relieving processor overhead. A single, current-setting resistor
is the only ancillary component required.
A single device can drive anyone of the following: a 5-digit display plus
decimals, a 4-112-digit display plus decimals and sign, or 25 lamps. A special
technique allows driving 5 112 digits; see Figure 16. A configuration register
allows the drive capability to be partitioned off to suit many additional applications. The on-chip decoder outputs 7-segment-format numerals O to 9, hexadecimal characters A to F, plus 151etters and symbols.
The MC144898 is compatible with the Motorola SPI and National MICRO-WIRETM serial data ports. The chip's patented 8itGrabberTM registers
augment the serial interface by allowing random access without steering or
address bits. A 24-bit transfer updates the display register. Changing the configuration register requires an 8-bit transfer.
.Operating Voltage Range of Drive Circuitry: 4.5 to 5.5 V
.Operating Junction Temperature Range: -40° to 130°C
.Current Sources Controlled by Single Resistor Provide Anode Drive
.Low-Resistance FET Switches Provide Direct Common Cathode Interface
.Low-Power Mode (Extinguishes the LEDs) and Brightness Controlled via
Serial Port
.Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI
in Low-Power Mode
.Power-On Reset (POR) Blanks the Display on Power-Up, Independent of
Supply Ramp Up Time
.May Be Used with Double-Heterojunction LEDs for Optimum Efficiency
.Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.)
MC14489B
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BitGrabber is a trademark of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
REVO
November 2000
BLOCK DIAGRAM
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
10
12
D
11
24–1/2–STAGE
SHIFT REGISTER
C
44
DATA IN
CLOCK
ENABLE
DISPLAY REGISTER
BitGrabber
CONFIGURATION REGISTER
8 BITS
NIBBLE MUX AND
DECODER ROM
a TO g
7
POR
OSCILLATOR AND
CONTROL LOGIC
5
BLANK
5
ANODE DRIVERS
BANK SWITCHES (FETs)
913151617
BANK 1BANK 2BANK 3BANK 4BANK 5
MAXIMUM RATINGS* (Voltages Referenced to V
Symbol
V
V
ÁÁ
I
ÁÁ
DC Supply Voltage
DD
V
DC Input Voltage
in
DC Output Voltage
out
I
DC Input Current — per Pin
in
ББББББББББ
(Includes Pin 8)
DC Output Current —
out
ББББББББББ
IDD, ISSDC Supply Current, VDD and VSS Pins
T
Chip Junction Temperature
J
R
ÁÁ
ÁÁ
T
ÁÁ
Device Thermal Resistance,
θJA
stg
T
ББББББББББ
Junction–to–Ambient (see Thermal
Considerations section) Plastic DIP
ББББББББББ
Storage Temperature
Lead Temperature, 1 mm from Case for
L
ББББББББББ
10 Seconds
Parameter
Pins 1, 2, 4 – 7, 19, 20 Sourcing
Sinking
Pins 9, 13, 15, 16, 17 Sinking
Pin 18
SOG Package
)
SS
– 0.5 to + 6.0
– 0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
ÁÁÁÁ
ÁÁÁÁ
– 40 to + 130
ÁÁÁÁ
ÁÁÁÁ
– 65 to + 150
ÁÁÁÁ
Value
±15
– 40
10
320
±15
±350
90
100
260
(CURRENT SOURCES)
ab
Unit
V
V
V
mA
Á
mA
Á
mA
°C
°C/W
Á
Á
°C
°C
Á
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
4
444
BitGrabber
24 BITS
4
44444
h DIM/BRIGHT
220
1
194567
cdefgh
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and V
VSS ≤ (Vin or V
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
18
DATA OUT
PIN 3 = V
DD
PIN 14 = V
8
Rx
SS
should be constrained to the range
) ≤ VDD.
out
MC14489B MOTOROLA
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
Symbol
V
DD
VDD (stby) Minimum Standby Voltage Bits Retained in Display and
V
V
V
Hys
V
OL
V
OH
I
in
i
OL
i
OH
I
OZ
R
on
IDD, I
I
ss
*See Thermal Considerations section.
Power Supply Voltage Range of LED Drive Circuitry — 4.5 to 5.5 V
Maximum Low–Level Input Voltage
IL
IH
SS
(Data In, Clock, Enable
Minimum High–Level Input Voltage
(Data In, Clock, Enable
Minimum Hysteresis Voltage
(Data In, Clock, Enable
Maximum Low–Level Output Voltage
(Data Out)
Minimum High–Level Output Voltage
(Data Out)
Maximum Input Leakage Current
(DataInClockEnable
(Data In, Clock, Enable)
Minimum Sinking Current
(a, b, c, d, e, f, g, h)
Peak Sourcing Current — See Figure 7 for currents up to
35 mA (a, b, c, d, e, f, g, h)
Maximum Output Leakage Current
(Bank1Bank2Bank3Bank4Bank5)
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
Maximum ON Resistance
(Bank 1, Bank 2, Bank 3, Bank 4, Bank 5)
Maximum Quiescent Supply Current
Maximum RMS Operating Supply Current
(The VSS leg does not contain the Rx current component.
See Pin Descriptions.)
Parameter Test Condition
)
)
)
)
, TJ = – 40° to 130°C* unless otherwise indicated)
SS
Configuration Registers, Data
Port Fully Functional
I
= 20 µA 3.0
out
I
= 1.3 mA 4.5 0.4
out
I
= – 20 µA 3.0
out
I
= – 800 µA 4.5 4.1
out
Vin = VDD or V
Vin = VDD or VSS,
TJ = 25°C only
V
= 1.0 V 4.5 0.2 mA
out
Rx = 2.0 kΩ, V
Dimmer Bit = High
Rx = 2.0 kΩ, V
Dimmer Bit = Low
V
= VDD (FET Leakage) 5.5 50
out
V
= VDD (FET Leakage),
out
TJ = 25°C only
V
= VSS (Protection Diode
out
Leakage)
I
= 0 to 200 mA 5.0 10 Ω
out
Device in Low–Power Mode,
Vin = VSS or VDD, Rx in
Place, Outputs Open
Same as Above, TJ = 25°C 5.5 20
Device NOT in Low–Power
Mode, Vin = VSS or VDD,
Outputs Open
SS
out
out
= 3.0 V,
= 3.0 V,
V
Guaranteed
DD
V
— 3.0 V
3.0
5.5
3.0
5.5
3.0
5.5
5.5
5.5
5.5 ± 2.0
5.5 ± 0.1
5.0 13 to 17.5
5.0 6 to 9
5.5 1
5.5 1
5.5 100
5.5 1.5 mA
Limit
0.9
1.65
2.1
3.85
0.2
0.4
0.1
0.1
2.9
5.4
Unit
V
V
V
V
V
µA
mA
µA
µA
MC14489BMOTOROLA
3
AC ELECTRICAL CHARACTERISTICS (T
Symbol
f
clk
t
PLH
t
PHL
t
TLH
t
THL
f
R
C
*See Thermal Considerations section.
Serial Data Clock Frequency, Single Device or Cascaded Devices
NOTE: Refer to Clock tw below
(Figure 1)
,
Maximum Propagation Delay, Clock to Data Out
(Figures 1 and 5)
,
Maximum Output Transistion Time, Data Out
(Figures 1 and 5)
Refresh Rate — Bank 1 through Bank 5
(Figures 2 and 6)
Maximum Input Capacitance — Data In, Clock, Enable — 10 pF
in
= – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns)
J
Parameter
V
DD
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Guaranteed
Limit
dc to 3.0
dc to 4.0
dc to 4.0
140
80
80
70
50
50
NA
700 to 1900
700 to 1900
Unit
MHz
ns
ns
Hz
TIMING REQUIREMENTS (T
Symbol Parameter
tsu, t
tsu, th,
t
rec
t
w(L)
t
w(H)
t
w
tr, t
*See Thermal Considerations section.
**For a high–speed 8–Clock access, th for Enable
where th is in ns and f
NOTES:
Minimum Setup and Hold Times, Data In versus Clock
h
f
VDD = 3 to 4.5 V, f
VDD = 4.5 to 5.5 V, f
1.This restriction does NOT apply for f
2.This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
(Figure 3)
Minimum Setup, Hold, ** and Recovery Times, Enable versus Clock
(Figure 4)
Minimum Active–Low Pulse Width, Enable
(Figure 4)
Minimum Inactive–High Pulse Width, Enable
(Figure 4)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall Times — Data In, Clock, Enable
(Figure 1)
clk
clk
clk
= – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated)
J
> 1.78 MHz: th = 4350 – (7500/f
> 2.34 MHz: th = 3300 – (7500/f
is in MHz.
is determined as follows:
rates less than those listed above. For “slow” f
clk
clk
clk
)
)
V
DD
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
rates, use the th limits in the above table.
clk
Guaranteed
Limit
50
40
40
150
100
100
4.5
3.4
3.4
300
150
150
167
125
125
1
1
1
Unit
ns
ns
µs
ns
ns
ms
MC14489B MOTOROLA
4
CLOCK
DATA OUT
90%
50%
10%
90%
50%
10%
t
f
t
w
t
PLH
t
TLH
1/f
clk
t
r
t
w
t
PHL
t
THL
V
DD
V
SS
BANK
OUTPUT
50%
Figure 1. Figure 2.
1/f
R
D
ATA IN
CLOCK
VALID
50%
t
su
50%
t
h
Figure 3. Figure 4.
TEST POINT
DEVICE
UNDER
TEST
*
C
L
*Includes all probe and fixture capacitance.
Figure 5. Figure 6.
tw(L)
ENABLE
V
DD
V
SS
V
DD
V
SS
CLOCK
50%
CLOCK
t
su
50%
FIRST
t
LAST
CLOCK
TEST POINT
DEVICE
UNDER
TEST
tw(H)
h
56
C
t
rec
V
DD
Ω
*
L
V
DD
V
SS
V
DD
V
SS
*Includes all probe and fixture capacitance.
MC14489BMOTOROLA
5
PIN DESCRIPTIONS
DIGITAL INTERFACE
Data In (Pin 12)
Serial Data Input. The bit stream begins with the MSB and
is shifted in on the low–to–high transition of Clock. When the
device is not cascaded, the bit pattern is either 1 byte (8 bits)
long to change the configuration register or 3 bytes (24 bits)
long to update the display register. For two chips cascaded,
the pattern is either 4 or 6 bytes, respectively. The display
does not change during shifting (until Enable
to–high transition) which allows slow serial data rates, if desired.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the two registers. Random access of either register is provided. That is, the registers may be accessed in any sequence. Data is retained in
the registers over a supply range of 3 to 5.5 V. Formats are
shown in Figures 8 through 14 and summarized in Table 2.
Information on the segment decoder is given in Table 1.
Data In typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. These features combine to
maximize noise immunity for use in harsh environments and
bus applications. This input can be directly interfaced to
CMOS devices with outputs guaranteed to switch near rail–
to–rail. When interfacing to NMOS or TTL devices, either a
level shifter (MC14504B, MC74HCT04A) or pullup resistor of
1 kΩ to 10 kΩ must be used. Parameters to be considered
when sizing the resistor are the worst–case IOL of the driving
device, maximum tolerable power consumption, and maximum data rate.
Clock (Pin 11)
Serial Data Clock Input. Low–to–high transitions on Clock
shift bits available at Data In, while high–to–low transitions
shift bits from Data Out. The chip’s 24–1/2–stage shift register is static, allowing clock rates down to dc in a continuous or
intermittent mode. The Clock input does not need to be synchronous with the on–chip clock oscillator which drives the
multiplexing circuit.
Eight clock cycles are required to access the configuration
register, while 24 are needed for the display register when the
MC14489B is not cascaded. See Figures 8 and 9.
As shown in Figure 10, two devices may be cascaded. In
this case, 32 clock cycles access the configuration register
and 48 access the display register, as depicted in Figure 10.
Cascading of 3, 4, 5, and 6 devices is shown in Figures 11,
12, 13, and 14, respectively. Also, reference Table 2.
Clock typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow Clock rise and fall times
are tolerated. See the last paragraph of Data In for more information.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the Clock pin must NOT be
floated or toggled during power–up. That is, the
Clock pin must be stable until the VDD pin
reaches at least 3 V.
If control of the Clock pin during power–up is not
practical, then the MC14489B must be reset via bit
C0 in the C register. To accomplish this, C0 is reset low, then set high.
makes a low–
(Pin 10)
Enable
Active–Low Enable Input. This pin allows the MC14489B to
be used on a serial bus, sharing Data In and Clock with other
peripherals. When Enable
Out is forced to a known (low) state, shifting is inhibited, and
the port is held in the initialized state. To transfer data to the
device, Enable
low, a serial transfer is made via Data In and Clock, and
is taken high. The low–to–high transition on Enable
Enable
transfers data to either the configuration or display register,
depending on the data stream length.
Every rising edge on Enable
while data is loaded. Thus, continually loading the device with
the same data may cause the LEDs on some banks to appear
dimmer than others.
Transitions on Enable
while Clock is high. This puts the device out of
synchronization with the microcontroller. Resynchronization occurs when Enable
Clock is low.
This input is also Schmitt–triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data in the registers. See the last paragraph of Data In for
more information.
Data Out (Pin 18)
Serial Data Output. Data is transferred out of the shift register through Data Out on the high–to–low transition of Clock.
This output is a no connect, unless used in one of the manners discussed below.
When cascading MC14489B’s, Data Out feeds Data In of the
next device per Figures 10, 11, 12, 13, and 14.
Data Out could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a system check conducted at power–up to test the integrity of the
system’s processor, pc board traces, solder joints, etc.
The pin could be monitored at an in–line Q.A. test during
board manufacturing.
Finally, Data Out facilitates troubleshooting a system.
DISPLAY INTERFACE
Rx (Pin 8)
External Current–Setting Resistor. A resistor tied between
this pin and ground (VSS) determines the peak segment drive
current delivered at pins a through h. Pin 8’s resistor ties into
a current mirror with an approximate current gain of 10 when
bit D23 = high (brighten). With D23 = low, the peak current is
reduced about 50%. Values for Rx range from 700 Ω to infinity. When Rx = ∞ (open circuit), the display is extinguished.
For proper current control, resistors having ±1% tolerance
should be used. See Figure 7.
Small Rx values may cause the chip to overheat
if precautions are not observed. See Thermal
Considerations.
(which initially must be inactive high) is taken
is in an inactive high state, Data
initiates a blanking interval
NOTE
must not be attempted
is high and
CAUTION
MC14489B MOTOROLA
6
a through h (Pins 1, 2, 4 – 7, 19, 20)
Anode–Driver Current Sources. These outputs are closely–matched current sources which directly tie to the anodes
of external discrete LEDs (lamps) or display segment LEDs.
Each output is capable of sourcing up to 35 mA.
When used with lamps, outputs a, b, c, and d are used to
independently control up to 20 lamps. Output h is used to control up to 5 lamps dependently. (See Figure 17.) For lamps,
No Decode
the
mode is selected via the configuration regis-
ter, forcing e, f, and g inactive (low).
When used with segmented displays, outputs a through g
drive segments a through g, respectively. Output h is used to
drive the decimals. Refer to Figure 9. If unused, h must be left
open.
Bank 1 through Bank 5 (Pins 9, 13, 15, 16, 17)
Diode–Bank FET Switches. These outputs are low–resistance switches to ground (VSS) capable of handling currents
of up to 320 mA each. These pins directly tie to the common
cathodes of segmented displays or the cathodes of lamps
(wired with cathodes common).
The display is refreshed at a nominal 1 kHz rate to achieve
optimum brightness from the LEDs. A 20% duty cycle is utilized.
Special design techniques are used on–chip to accommodate the high currents with low EMI (electromagnetic interference) and minimal spiking on the power lines.
POWER SUPPLY
VSS (Pin 14)
Most–negative supply potential. This pin is usually ground.
Resistor Rx is externally tied to ground (VSS). Therefore,
the chip’s VSS pin does not contain the Rx current component.
VDD (Pin 13)
Most–positive supply potential.
To guarantee data integrity in the registers and to ensure
the serial interface is functional, this voltage may range from
3 to 6 volts with respect to VSS. For example, within this voltage range, the chip could be placed in and out of the low–
power mode.
To adequately drive the LEDs, this voltage must be 4.5 to
6 volts with respect to VSS.
The VDD pin contains the Rx current component plus the
chip’s current drain. In the low–power mode, the current mirror and clock oscillator are turned off, thus significantly reducing the VDD current, IDD.
35
30
25
20
15
PEAK DRIVE CURRENT (mA)
OH,
i
10
5
400 800 1.2 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k1.6 k
NOTE:Drive current tolerance is approximately ± 15%.
BIT D23 = HIGH (BRIGHTEN LEDs)
WITH D23 = LOW, iOH IS CUT BY
Rx, EXTERNAL RESISTOR (Ω)
5 V SUPPLY
∼
50%.
Figure 7. a through h Nominal Current per Output versus Rx
MC14489BMOTOROLA
7
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