Freescale MC13211, MC13212, MC13213, MC13214 Technical Data
Freescale Semiconductor
Technical Data
MC13211/212/213/214
Document Number: MC1321x
Rev. 0.0, 03/2006
MC1321x
Package Information
Case 1664-01
71-pin LGA [9x9 mm]
ZigBee™- Compliant Platform -
2.4 GHz Low Power Transceiver
for the IEEE
®
802.15.4 Standard
plus Microcontroller
1 Introduction
The MC1321x family is Freescale’s second-generation
ZigBee platform which incorporates a low power 2.4
GHz radio frequency transceiver and an 8-bit
microcontroller into a single 9x9x1 mm 71-pin LGA
package. The MC1321x solution can be used for wireless
applications from simple proprietary point-to-point
connectivity to a complete ZigBee mesh network. The
combination of the radio and a microcontroller in a small
footprint package allows for a cost-effective solution.
The MC1321x contains an RF transceiver which is an
802.15.4-compliant radio that operates in the 2.4
IEEE
GHz ISM frequency band. The transceiver includes a
low noise amplifier, 1mW nominal output power, PA
with internal voltage controlled oscillator (VCO),
integrated transmit/receive switch, on-board power
supply regulation, and full spread-spectrum encoding
and decoding.
Ordering Information
Device Device Marking Package
MC13211
MC13212
MC13213
MC13214
1
See Table 1 for more details.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 MC1321x Pin Assignment and Connections 8
3 MC1321x Serial Peripheral Interface (SPI) . 14
4 IEEE 802.15.4 Modem . . . . . . . . . . . . . . . . . . 16
5 MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 System Electrical Specification . . . . . . . . . 46
7 Application Considerations . . . . . . . . . . . . . 63
8 Mechanical Diagrams . . . . . . . . . . . . . . . . . . 68
1
1
1
1
13211 LGA
13212 LGA
13213 LGA
13214 LGA
The MC1321x also contains a microcontroller based on
the HCS08 Family of Microcontroller Units (MCU) and
can provide up to 60KB of flash memory and 4KB of
RAM. The onboard MCU allows the communications
Freescale reserves the right to change the detail specificatio ns as may be required to permit improvements in the design of i ts
products.
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
stack and also the application to reside on the same system-in-package (SIP). The MC1321x family is
organized as follows:
• The MC13211 has 16KB of flash and 1KB of RAM and is an ideal solution for low cost,
proprietary applications that require wireless point-to-point or star network connectivity. The
MC13211 combined with the Freescale Simple MAC (SMAC) provides the foundation for
proprietary applications by supplying the necessary source code and application examples to get
users started on implementing wireless connectivity.
• The MC13212 contains 32K of flash and 2KB of RAM and is intended for use with the Freescale
fully compliant 802.15.4 MAC. Custom networks based on the 802.15.4 standard MAC can be
implemented to fit user needs. The 802.15.4 standard supports star, mesh and cluster tree
topologies as well as beaconed networks.
• The MC13213 contains 60K of flash and 4KB of RAM and is also intended for use with the
Freescale fully compliant 802.15.4 MAC where larger memory is required. In addition, this device
can support ZigBee applications that use a stack from 3rd party vendors.
• The MC13214 is a fully compliant ZigBee platform. The MC13214 contains 60K of flash and 4KB
of RAM and uses the Figure 8 Wireless ZigBee Stack (Z-stack) software. Applications can be
added to develop fully certified ZigBee products.
Applications include, but are not limited to, the following:
• Residential and commercial automation
— Lighting control
— Security
— Access control
— Heating, ventilation, air-conditioning (HVAC)
— Automated meter reading (AMR)
• Industrial Control
— Asset tracking and monitoring
— Homeland security
— Process management
— Environmental monitoring and control
—HVAC
— Automated meter reading
• Health Care
— Patient monitoring
— Fitness monitoring
MC13211/212/213/214 Technical Data, Rev. 0.0,
2 Freescale Semiconductor
1.1 Ordering Information
Table 1 provides additional details about the MC1321x family.
Table 1. Orderable Parts Details
Operating
Device
MC13211 -40° to 85° C LGA 1KB RAM,
MC13211R2 -40° to 85° C LGA
MC13212 -40° to 85° C LGA 2KB RAM,
MC13212R2 -40° to 85° C LGA
MC13213 -40° to 85° C LGA 4KB RAM,
MC13213R2 -40° to 85° C LGA
MC13214 -40° to 85° C LGA 4KB RAM,
MC13214R2 -40° to 85° C LGA
Temp Ran ge
(TA.)
Package
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Memory
Options
16KB Flash
1KB RAM,
16KB Flash
32KB Flash
2KB RAM,
32KB Flash
60KB Flash
4KB RAM,
60KB Flash
60KB Flash
4KB RAM,
60KB Flash
Description
Intended for proprietary applications and Freescale
Simple MAC (SMAC)
Intended for proprietary applications and Freescale
Simple MAC (SMAC)
Intended for IEEE 802.15.4 compliant applications and
Freescale 802.15.4 MAC
Intended for IEEE 802.15.4 compliant applications and
Freescale 802.15.4 MAC
Intended for IEEE 802.15.4 compliant applications and
Freescale 802.15.4 MAC.
Also supports ZigBee applications that use a stack from a
3rd party vendor.
Intended for IEEE 802.15.4 compliant applications and
Freescale 802.15.4 MAC.
Also supports ZigBee applications that use a stack from a
3rd party vendor.
Intended for full ZigBee compliant applications using the
F8 Wireless Z-Stack
Intended for full ZigBee compliant applications using the
F8 Wireless Z-Stack
1.2 General Platform Features
• IEEE 802.15.4 standard compliant on-chip transceiver/modem
— 2.4GHz
— 16 selectable channels
— Programmable output power
• Multiple power saving modes
• 2V to 3.4V operating voltage with on-chip voltage regulators
• -40°C to +85°C temperature range
• Low external component count
• Supports single 16 MHz crystal clock source operation or dual crystal operation
• Support for SMAC, IEEE 802.15.4, and ZigBee software
• 9mm x 9mm x 1mm 71-pin LGA
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 3
1.3 Microcontroller Features
• Low voltage MCU with 40 MHz low power HCS08 CPU core
• Up to 60K flash memory with block protection and security and 4K RAM
— MC13211: 16KB Flash, 1KB RAM
— MC13212: 32KB Flash, 2KB RAM
— MC13213: 60KB Flash, 4KB RAM
— MC13214: 60KB Flash, 4KB RAM with ZigBee Z-stack
• Low power modes (Wait plus Stop2 and Stop3 modes)
• Dedicated serial peripheral interface (SPI) connected internally to 802.15.4 modem
• One 4-channel and one 1-channel 16-bit timer/pulse width modulator (TPM) module with
selectable input capture, output capture, and PWM capability.
• 8-bit port keyboard interrupt (KBI)
• 8-channel 8-10-bit ADC
• Two independent serial communication interfaces (SCI)
• Multiple clock source options
— Internal clock generator (ICG) with 243 kHz oscillator that has +/-0.2% trimming resolution
and +/-0.5% deviation across voltage.
— Startup oscillator of approximately 8 MHz
— External crystal or resonator
— External source from modem clock for very high accuracy source or system low-cost option
• Inter-integrated circuit (IIC) interface.
• In-circuit debug and flash programming available via on-chip background debug module (BDM)
— Two comparator and 9 trigger modes
— Eight deep FIFO for storing change-of-flow addresses and event-only data
— Tag and force breakpoints
— In-circuit debugging with single breakpoint
• System protection features
— Programmable low voltage interrupt (LVI)
— Optional watchdog timer (COP)
— Illegal opcode detection
• Up to 32 MCU GPIO with programmable pullups
MC13211/212/213/214 Technical Data, Rev. 0.0,
4 Freescale Semiconductor
1.4 RF Modem Features
• Fully compliant IEEE 802.15.4 transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels
and full spread-spectrum encode and decode
• Operates on one of 16 selectable channels in the 2.4 GHz ISM band
• -1 dBm to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical
• Receive sensitivity of <-92 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE
802.15.4 specification of -85 dBm
• Integrated transmit/receive switch
• Dual PA ouput pairs which can be programmed for full differential single-port or dual-port
operation that supports an external LNA and/or PA.
• Three low power modes for increased battery life
• Programmable frequency clock output for use by MCU
• Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external
variable capacitors and allows for automated production frequency calibration
• Four internal timer comparators available to supplement MCU timer resources
• Supports both packet data mode and streaming data mode
• Seven GPIO to supplement MCU GPIO
1.5 Software Features
Freescale provides a wide range of software functionality to complement the MC1321x hardware. There
are three levels of application solutions:
1. Simple proprietary wireless connectivity.
2. User networks built on the IEEE 802.15.4 MAC standard.
3. ZigBee-compliant network stack.
1.5.1 Simple MAC (SMAC)
• Small memory footprint (about 3 Kbytes typical)
• Supports point-to-point and star network configurations
• Proprietary networks
• Source code and application examples provided
1.5.2 IEEE 802.15.4-Compliant MAC
• Supports star, mesh and cluster tree topologies
• Supports beaconed networks
• Supports GTS for low latency
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 5
1.5.3 ZigBee-Compliant Network Stack
• Supports ZigBee 1.0 specification
• Supports star, mesh and tree networks
• Advanced Encryption Standard (AES) 128-bit security
1.6 System Block Diagram
Figure 1 shows a simplified block diagram of the MC1321x solution.
RIN_P(PAO_P)
RIN_M(PAO_M)
PAO_P
PAO_M
Analog Receiver
Transmit/Receive
Switch
IRQ Arbiter RAM Arbiter
Power Management Voltage Regulators
Frequency
Generator
Analog Transmitter
Buffer RAM
Figure 1. MC1321x System Level Block Diagram
HCS08 CPU
RFIC Timers
16-60 KB
Flash Memory
Digital
Digital Control
Transceiver
Logic
1-4 KB RAM
Dedicated
SPI
Low Voltage Detect
Keyboard Interrupt
Internal Clock
Generator
Background
Debug Module
8 Channel
10 Bit ADC
2x SCI
I2C
1 Channel & 4
Channel 16-bit
Timers
COP
Up to 32 GPIO
802.15.4 M odem H CS08 M CU
MC13211/212/213/214 Technical Data, Rev. 0.0,
6 Freescale Semiconductor
1.7 System Clock Configuration
The MC321x device allows for a wide array of system clock configurations:
• Pins are provided for a separate external clock source for the CPU. The external clock source can
by derived from a crystal oscillator or from an external clock source
• Pins are provided for a 16 MHz crystal for the modem clock source (required)
• The modem crystal oscillator frequency can be trimmed through programming to maintain the tight
tolerances required by IEEE 802.15.4
• The modem provides a CLKO programmable frequency clock output that can be used as an
external source to the CPU. As a result, a single crystal system clock solution is possible
• Out of reset, the MCU uses an internally generated clock (approximately 8-MHz) for start-up. This
allows recovery from stop or reset without a long crystal start-up delay
• The MCU contains an internal clock generator (which can be trimmed) that can be used to run the
MCU for low power operation. This internal reference is approximately 243 kHz
MC 1321X
802.15.4 MODEM HCS08 M CU
XTAL1 XTAL2 CLKO
EXTAL XTAL
27
16MHz
Figure 2. MC1321x Single Crystal System Clock Structure
28 10
98
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 7
2 MC1321x Pin Assignment and Connections
Figure 3 shows the MC1321x pinout.
PTA3/KBI1P3
PTA4/KBI1P4
PTA5/KBI1P5
PTA6/KBI1P6
PTA7/KBI1P7
VDDAD
PTG0/BKGD/MS
PTG1/XTAL
PTG2/EXTAL
CLKO
RESET
PTC0/TXD2
PTC1/RXD2
PTC2/SDA1
PTC3/SCL1
PTC4
PTB6/AD1P6
PTA2/KBI1P2
1
16
63 62 61 60 59 58 57 56 55 54 53 52 51 50
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18 19 20 21 22 23 24 25 26 27 28 29 30 31
17
PTC5
PTC6
VREF L
TEST
65
66
PTC7
PTE0/TXD1
PTA0/KBI1P0
PTA1/KBI1P1
PTB7/AD1P7
VREFH
MC1321x
Flag opening
67 68
VDDD
PTE1/RXD1
PTB5/AD1P5
69
VDDINT
GPIO5
PTB4/AD1P4
PTB3/AD1P3
GPIO6
GPIO7
PTB1/AD1P1
PTB2/AD1P2
PTB0/AD1P0
71 70
TEST
XTAL1
XTAL2
VDDLO2
PTD7/TPM2CH4
VDDLO1
PTD6/TPM2CH3
PTD5/TPM2CH2
4964
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
VDDVCO
VBATT
PTD4/TPM2CH1
PTD2/TPM1CH2
ATTN
VDD
GPIO1
GPIO2
GPIO3
GPIO4
SM
PAO_M
PAO_P
NC
RFIN_P
RFIN_M
CT_Bias
VDDA
Figure 3. Preliminary MC1321x Pinout
MC13211/212/213/214 Technical Data, Rev. 0.0,
8 Freescale Semiconductor
2.1 Pin Definitions
Table 2 details the MC1321x pinout and functionality.
Table 2. Pin Function Description
Pin # Pin Name Type Description Functionality
1 PTA3/KBI1P3 Digital
Input/Output
2 PTA4/KBI1P4 Digital
Input/Output
3 PTA5/KBI1P5 Digital
Input/Output
4 PTA6/KBI1P6 Digital
Input/Output
5 PTA7/KBI1P7 Digital
Input/Output
6 VDDAD Power Input MCU power supply to ATD Decouple to ground.
7 PTG0/BKGND/MS Digital
Input/Output
8 PTG1/XTAL Digital
Input/Output/
Output
9 PTG2/EXTAL Digital
Input/Output/
Input
10 CLKO Digital Output Modem Clock Output Programmable frequencies of:
MCU Port A Bit 3 /
Keyboard Input Bit 3
MCU Port A Bit 4 /
Keyboard Input Bit 4
MCU Port A Bit 5 /
Keyboard Input Bit 5
MCU Port A Bit 6 /
Keyboard Input Bit 6
MCU Port A Bit 7 /
Keyboard Input Bit 7
MCU Port G Bit 0 /
Background / Mode Select
MCU Port G Bit 1 / Crystal
oscillator output
MCU Port G Bit 2 / Crystal
oscillator input
PTG0 is output only . Pin is I/O when used as BDM
function.
Full I/O when not used as clock source.
Full I/O when not used as clock source.
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz,
32.786+ kHz (default),
and 16.393+ kHz.
11 RESET Digital
Input/Output
12 PTC0/TXD2 Digital
Input/Output
13 PTC1/RXD2 Digital
Input/Output
14 PTC2/SDA1 Digital
Input/Output
15 PTC3/SCL1 Digital
Input/Output
16 PTC4 Digital
Input/Output
17 PTC5 Digital
Input/Output
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 9
MCU reset. Active low
MCU Port C Bit 0 / SCI2
TX data out
MCU Port C Bit 1/ SCI2 RX
data in
MCU Port C Bit 1/ IIC bus
data
MCU Port C Bit 1/ IIC bus
clock
MCU Port C Bit 4
MCU Port C Bit 5
18 PTC6 Digital
Input/Output
MCU Port C Bit 6
19 PTC7 Digital
Input/Output
20 PTE0/TXD1 Digital
Input/Output
21 PTE1/RXD1 Digital
Input/Output
22 VDDD Power Output Modem regulated output
23 VDDINT Power Input Modem digital interface
24 GPIO5 Digital
Input/Output
25 GPIO6 Digital
Input/Output
26 GPIO7 Digital
Input/Output
27 XTAL1 Input Modem crystal reference
28 XTAL2 Input/Output Modem crystal reference
MCU Port C Bit 7
MCU Port E Bit 0 / SCI1 TX
data out
MCU Port E Bit 1/ SCI1 RX
data in
supply voltage
supply
Modem General Purpose
Input/Output 5
Modem General Purpose
Input/Output 6
Modem General Purpose
Input/Output 7
oscillator input
oscillator output
Decouple to ground.
2.0 to 3.4 V. Decouple to ground. Connect to
Battery.
Connect to 16 MHz crystal and load capacitor.
Connect to 16 MHz crystal and load capacitor. Do
not load this pin by using it as a 16 MHz source.
Measure 16 MHz output at CLKO, programmed for
16 MHz.
29 VDDLO2 Power Input Modem LO2 VDD supply Connect to VDDA externally.
30 VDDLO1 Power Input Modem LO1 VDD supply Connect to VDDA externally.
31 VDDVCO Power Output Modem VCO regulated
supply bypass
32 VBATT Power Input Modem voltage regulators’
input
33 VDDA Power Output Modem analog regulated
65 RFIN_ RF Input
(Output)
34 CT_Bias RF Control
Output
35 RFIN_M RF Input
(Output)
MC13211/212/213/214 Technical Data, Rev. 0.0,
10 Freescale Semiconductor
Modem RF input/output
supply output
(i).8((i).8ive)]TJET1 sc350.82 132.36ml556.8 132.36 l556.8 033.86 l350.82 033.86 lfBT9 0 0 9 353.82 241.32 Tm0 sc-0.002 Tc-0.0025 Tw[(W)-4.8(hen )-6.7(use)-5.8(d)0.8( w)-6.5(i)0.2(th i)-6.5(n)0.8(ternal)-6.5( T)-4.5(/)2.5(R)-6.5( swi)-6.5(t)2.5(ch, )-6.7(th)-5.8(is i)-6.5(s)-2( a )]TJT*-0.0019 Tc0.0041 Tw[(bi)-6.4(0 Tctioan)-5.7nal(RF)-4.4( )6.7ponted nted Li
Modem bias
voltage/control signal for
RF external components
Modem RF input/output
negative
Decouple to ground.
Decouple to ground. Connect to Battery.
Decouple to ground. Connect to directly VDDLO1
and VDDLO2 externally and to PAO_P and
PAO_M through a bias network.
When used with internal T/R switch, provides
ground reference for RX and VDDA reference for
TX. Can also be used as a control signal with
external LNA, antenna switch, and/or PA.
When used with internal T/R switch, this is a
bi0 TctioanRF ted nted Li
Table 2. Pin Function Description (continued)
Pin # Pin Name Type Description Functionality
37 NC Not used May be grounded or left open
38 PAO_P RF Output Modem power amplifier
RF output positive
39 PAO_M RF Output Modem power amplifier
RF output negative
40 SM Input Test Mode pin Must be grounded for normal operation
41 GPIO4 Digital
Input/Output
42 GPIO3 Digital
Input/Output
43 GPIO2 Test Point MCU Port E Bit 6 / Modem
44 GPIO1 Test Point MCU Port E Bit 7 / Modem
45 VDD Power Input MCU main power supply Decouple to ground.
46 ATTN Test Point MCU Port D Bit 0 / Modem
47 PTD2/TPM1CH2 Digital
Input/Output
Modem General Purpose
Input/Output 4
Modem General Purpose
Input/Output 3
General Purpose
Input/Output 2
General Purpose
Input/Output 1
attention input
MCU Port D Bit 2 / TPM1
Channel 2
Open drain. Connect to VDDA through a bias
network when used with external balun. Not used
when internal T/R switch is used.
Open drain. Connect to VDDA through a bias
network when used with external balun. Not used
when internal T/R switch is used.
Internally connected pins. When gpio_alt_en,
Register 9, Bit 7 = 1, GPIO2 functions as a “CRC
Valid” indicator.
Internally connected pins. When gpio_alt_en,
Register 9, Bit 7 = 1, GPIO1 functions as an “Out of
Idle” indicator.
Internally connected pins.
48 PTD4/TPM2CH1 Digital
Input/Output
49 PTD5/TPM2CH2 Digital
Input/Output
50 PTD6/TPM2CH3 Digital
Input/Output
51 PTD7/TPM2CH4 Digital
Input/Output
52 PTB0/AD1P0 Input/Output MCU Port B Bit 0 / ATD
53 PTB1/AD1P1 Input/Output MCU Port B Bit 1 / ATD
54 PTB2/AD1P2 Input/Output MCU Port B Bit 2 / ATD
55 PTB3/AD1P3 Input/Output MCU Port B Bit 3 / ATD
56 PTB4/AD1P4 Input/Output MCU Port B Bit 4 / ATD
MC13211/212/213/214 Technical Data, Rev. 0.0,
MCU Port D Bit 4 / TPM2
Channel 1
MCU Port D Bit 5 / TPM2
Channel 2
MCU Port D Bit 6 / TPM2
Channel 3
MCU Port D Bit 7 / TPM2
Channel 4
analogChannel 0
analog Channel 1
analog Channel 2
analog Channel 3
analog Channel 4
Freescale Semiconductor 11
Table 2. Pin Function Description (continued)
Pin # Pin Name Type Description Functionality
57 PTB5/AD1P5 Input/Output MCU Port B Bit 5 / ATD
analog Channel 5
58 PTB6/AD1P6 Input/Output MCU Port B Bit 6 / ATD
analog Channel 6
59 PTB7/AD1P7 Input/Output MCU Port B Bit 7 / ATD
analog Channel 7
60 VREFH Input MCU high reference
voltage for ATD
61 VREFL Input MCU low reference
voltage for ATD
62 PTA0/KBI1P0 Digital
Input/Output
63 PTA1/KBI1P1 Digital
Input/Output
64 PTA2/KBI1P2 Digital
Input/Output
65 TEST Test Point For factory test Do not connect
66 TEST Test Point For factory test Do not connect
67 TEST Test Point For factory test Do not connect
68 TEST Test Point For factory test Do not connect
69 TEST Test Point For factory test Do not connect
70 TEST Test Point For factory test Do not connect
71 TEST Test Point For factory test Do not connect
FLAG VSS Power input External package flag.
MCU Port A Bit 0 /
Keyboard Input Bit 0
MCU Port A Bit 1 /
Keyboard Input Bit 1
MCU Port A Bit 2 /
Keyboard Input Bit 2
Connect to ground.
Common VSS
MC13211/212/213/214 Technical Data, Rev. 0.0,
12 Freescale Semiconductor
2.2 Internal Functional Interconnects
The MCU provides control for the 802.15.4 modem. The required interconnects between the devices are
routed onboard the SiP. In addition, the signals are brought out to external pads primarily for use as test
points. These signals can be useful when writing and debugging software.
Table 3. Internal Functional Interconnects
Pin # MCU Signal Modem Signal Description
43 PTE6 GPIO2 Modem GPIO2 output acts as “CRC Valid” status indicator for Stream Data
Mode to MCU.
44 PTE7 GPIO1 Modem GPIO1 output acts as “Out of Idle” status indicator for Stream Data
Mode to MCU.
46 PTD0 ATTN
PTE5/SPSCK1 SPICLK MCU SPI master SPI clock output drives modem SPICLK slave clock input.
PTE4/MOSI1 MOSI MCU SPI master MOSI output drives modem slave MOSI input
PTE3/MISO1 MISO Modem SPI slave MISO output drives MCU master MISO input
PTE2/SS1
IRQ M_IRQ Modem interrupt request M_IRQ output drives MCU IRQ input
PTD1 RXTXEN MCU Port D Bit 1 drives the RXTXEN input to the modem to enable TX or RX
PTD3 M_RST MCU Port D Bit 3 drives the reset M_RST input to the modem.
CE MCU SPI master SS output drives modem slave CE input
MCU Port D Bit 0 drives the attention (ATTN) input of the modem to wake
modem from Hibernate or Doze Mode.
or CCA operations.
NOTE
T o use the MCU and modem signals as described in Table 3, the MCU needs
to be programmed appropriately for the stated function.
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 13
3 MC1321x Serial Peripheral Interface (SPI)
The MC1321x modem and CPU communicate primarily through the onboard SPI command channel.
Figure 4 shows the SiP internal interconnects with the SPI bus highlighted. The MCU has a single SPI
module that is dedicated to the modem SPI interface. The modem is a slave only and the MCU SPI must
be programmed and used as a master only. Further, the SPI performance is limited by the modem
constraints of 8 MHz SPI clock frequency, and use of the SPI must be programmed to meet the modem
SPI protocol.
3.1 SiP Level SPI Pin Connections
The SiP level SPI pin connections are all internal to the device. Figure 4 shows the SiP interconnections
with the SPI bus highlighted.
MC1321x
M_RST PTD3
M_IRQ
ATTN
RXTXEN
MODEM MCU
MCU Signal Modem Signal Description
GPIO1/Out_of_Idle
GPIO2/CRC_Valid
MOSI
MISO
SPICLK
CE PTE2/SS1
Figure 4. MC1321x Internal Interconnects Highlighting SPI Bus
Table 4. MC1321x Internal SPI Connections
474443
IRQ
PT D0
PT D1
PT E7
PT E6
PTE4/MOSI1
PTE3/MISO1
PTE5/SPSCK1
11
RESET
PTE5/SPSCK1 SPICLK MCU SPI master SPI clock output drives modem SPICLK slave clock input.
PTE4/MOSI1 MOSI MCU SPI master MOSI output drives modem slave MOSI input
PTE3/MISO1 MISO Modem SPI slave MISO output drives MCU master MISO input
PTE2/SS1 CE MCU SPI master SS output drives modem slave CE input
MC13211/212/213/214 Technical Data, Rev. 0.0,
14 Freescale Semiconductor
3.2 SPI Features
• MCU bus master
• Modem bus slave
• Programmable SPI clock rate; maximum rate is 8 MHz
• Double-buffered transmit and receive at MCU
• Serial clock phase and polarity must meet modem requirements (MCU control bits
• Slave select programmed to meet modem protocol
3.3 SPI System Block Diagram
Figure 5 shows the SPI system level diagram.
MCU (MASTER)
SPI SHIFTER
7 6 5 4 3 2 1 0
CLOCK
GENERATOR
MOS1
MISO1
SPSCK1
PTE2/SS1
Figure 5. SPI System Block Diagram
MOSI
MISO
SPICLK
CE
MODEM (SLAVE)
SPI SHIFTER
7 6 5 4 3 2 1 0
Figure 5 shows the SPI modules of the MCU and modem in the master-slave arrangement. The MCU
(master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. Although the SPI interface
supports simultaneous data exchange between master and slave, the modem SPI protocol only uses data
exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to
the slave. The slave device must be selected by a low level on the slave select input (SS1 pin).
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 15
4 IEEE 802.15.4 Modem
4.1 Block Diagram
2nd IF Mix er
IF = 1 MHz
RFIN_P
(PAO_P)
RFIN_M
(PAO_M)
T / R
LNA
1st IF Mi x er
IF = 65 MHz
CT_Bias
VDD LO2 ÷4
XTAL1
XTAL2
VDDLO1
PAO_P
PAO_M
256 MHz
Crystal
Oscillator
16 MHz
PA
Phase Shift Modulator
PMA
Decimation
Filter
AGC
Synthesizer
Baseband
Mixer
2.45 GHz
VCO
Matched
Filter
Programmable
Prescaler
MUX
CCA
Transmit
Packet RAM 2
Transmit
Packet RAM 1
FCS
Generation
DCD
Receive
Packet R AM
24 Bit Event Timer
4 Programmable
Timer Com parators
Transmit RAM
Header
Generation
Correlator
Arbiter
Symbol
Synch & Det
Receive RAM
Packet
Processor
Arbiter
Symbol
Generation
Power-Up
Control
Logic
Sequence
Manager
(Control Logic)
Analog
Regulator VBATT
Digital
Regulator L
Digital
Regulator H
Crystal
Regulator
VCO
Regulator
SERIAL
PERIPHERAL
IRQ
Arbiter
INTERFACE
VDDINT
VDDD
VDDVCO
(SPI)
VDDA
RXTXEN
CE
MOSI
MISO
SPICLK
ATTN
RST
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
IRQ
CLKO
Figure 6. 802.15.4 Modem Block Diagram
MC13211/212/213/214 Technical Data, Rev. 0.0,
16 Freescale Semiconductor
4.2 Data Transfer Modes
The 802.15.4 modem has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer . For proprietary
applications, packet mode can be used to conserve MCU resources.
4.3 Packet Structure
Figure 7 shows the packet structure of the 802.15.4 modem. Payloads of up to 125 bytes are supported.
The 802.15.4 modem adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
Preamble SFD FLI P ayload Data FCS
Figure 7. 802.15.4 modem Packet Structure
4.4 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS (which are stored in
RAM in Packet Mode). A two-byte FCS is calculated on the received data and compared to the FCS value
appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. A
parameter of received energy during the reception called the Link Quality Indicator is measured over a 64
µs period after the packet preamble and stored in an SPI register.
If the 802.15.4 modem is in Packet Mode, the data is stored in RAM and processed as an entire packet.
The MCU is notified that an entire packet has been received via an interrupt.
If the 802.15.4 modem is in streaming mode, the MCU is notified by a recurring interrupt on a
word-by-word basis.
Figure 8 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure 9 shows
energy detection/LQI reported level versus input power.
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 17
NOTE
For both graphs, the required IEEE 802.15.4 Standard accuracy and range
limits are shown. A 3.5 dBm offset has been programmed into the CCA
reporting level to center the level over temperature in the graphs.
-50
-60
-70
-80
-90
Reported Power Level (dBm)
-100
-90 -80 -70 -60 -50
Input Power (dBm)
802.15.4 Accura cy
and range Requirements
Figure 8. Reported Power Level versus Input Power in Clear Channel Assessment Mode
-15
-25
-35
-45
-55
-65
Reported Power Level (dBm)
-75
802.15.4 Accur ac y
and Range Requirements
-85
-85 -75 -65 -55 -45 -35 -25 -15
Input Power Level (dBm)
Figure 9. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
4.5 Transmit Path Description
For the transmit path, the TX data that was previously written to the internal RAM is retrieved (packet
mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY,
spread, and then up-converted to the transmit frequency.
If the 802.15.4 modem is in packet mode, data is processed as an entire packet. The data is first loaded into
the TX buffer. The MCU then requests that the modem transmit the data. The MCU is notified via an
interrupt when the whole packet has successfully been transmitted.
MC13211/212/213/214 Technical Data, Rev. 0.0,
18 Freescale Semiconductor
In streaming mode, the data is fed to the 802.15.4 modem on a word-by-word basis with an interrupt
serving as a notification that the 802.15.4 modem is ready for more data. This continues until the whole
packet is transmitted.
In both modes, a two-byte FCS is calculated in hardware from the payload data and appended to the packet.
This done without intervention from the user.
4.6 Functional Description
4.6.1 802.15.4 Modem Operational Modes
The 802.15.4 modem has a number of operational modes that allow for low-current operation. Transition
from the Off to Idle mode occurs when M_RST is negated. Once in Idle, the SPI is active and is used to
control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are
summarized, along with the transition times, in Table 5. Current drain in the various modes is listed in
Table 8, DC Electrical Characteristics.
Table 5. 802.15.4 Modem Mode Definitions and Transition Times
Mode Definition
Off All IC functions Off, Leakage only. M_RST asserted. Digital outputs are tri-stated
including IRQ
Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data
is retained.
Doze Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9
= 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and
can be programmed to enter Idle Mode through an internal timer comparator.
Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive Crystal Reference Oscillator On. Receiver On. 144 µs from Idle
Transmit Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle
Transition Time
To or From Idle
10 - 25 ms to Idle
7 - 20 ms to Idle
(300 + 1/CLKO) µs to Idle
4.6.2 Serial Peripheral Interface (SPI)
The MCU directs the 802.15.4 modem, checks its status, and reads/writes data to the device through the
4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and
the 802.15.4 modem occurs as multiple 8-bit bursts on the SPI. The modem SPI signals are:
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the 802.15.4 modem. Data is clocked
into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out
changes state on the trailing (falling) edge of SPICLK.
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 19
NOTE
For the MCU, the SPI clock format is the clock phase control bit CPHA = 0
and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The 802.15.4 modem presents data to the master on the MISO
output.
Although the SPI port is fully static, internal memory , timer and interrupt arbiters require an internal clock
(CLK
), derived from the crystal reference oscillator, to communicate from the SPI regis ters to internal
core
registers and memory.
4.6.2.1 SPI Burst Operation
The SPI port of the MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master
(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the
master on the MISO line. Although an 802.15.4 modem transaction is three or more SPI bursts long, the
timing of a single SPI burst is shown in Figure 10. The maximum SPI clock rate is 8 Mhz from the MCU
because the modem is limited by this number.
1
Figure 10. SPI Single Burst Timing Diagram
MC13211/212/213/214 Technical Data, Rev. 0.0,
20 Freescale Semiconductor
4.6.2.2 SPI Transaction Operation
Although the SPI port of the MCU transfers data in bursts of 8 bits, the 802.15.4 modem requires that a
complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The
assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to
the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write is data written to the 802.15.4
modem and a read is data written to the SPI master . The following SPI bursts will be either the write data
(MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the 802.15.4
modem never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can
extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high
to signal the end of the transaction.
An example SPI read transaction with a 2-byte payload is shown in Figure 11.
CE
Clock Burst
SPICLK
MISO
MOSI
Valid
Header Read data
Figure 11. SPI Read Transaction Diagram
Valid Valid
4.7 Modem Crystal Oscillator
The modem crystal oscillator uses the following external pins as shown in Figure 12.
1. XTAL1 - reference oscillator input.
2. XTAL2 - reference oscillator output. Note that this pin should not be loaded as a reference source
or to measure frequency; instead use CLKO to measure or supply 16 MHz.
MC1321X
802.15.4 MODEM
XTAL1 XTAL2 CLKO
27
28 10
16MH z
Figure 12. Modem Crystal Oscillator
MC13211/212/213/214 Technical Data, Rev. 0.0,
Freescale Semiconductor 21
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