Freescale DSP56367 DATA SHEET

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR DATA SHEET

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Data Sheet

DSP56367

24-Bit Audio Digital Signal Processor

This document briefly descibes the DSP56367 24-bit digital signal processor (DSP). The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. The DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.5 V.

ESAI

INTER-

FACE

EXPANSION AREA

PIO_EB

INTER-

FACE

ESAI_1

PERIPHERAL

24-BIT

DSP56300

Core

PROGRAM

DECODE

CONTROLLE

SHI

PROGRAM

ADDRESS

GENERATOR

MEMORY EXPANSION AREA

PROGRAM

RAM /INSTR. CACHE 3K x 24

PROGRAM

ROM

40K x 24

Bootstrap

PM_EB

YAB XAB PAB DAB

DDB YDB XDB PDB GDB

24X24+56->56-BIT MAC

TWO 56-BIT ACCUMULATORS

BARREL SHIFTER

X MEMORY

RAM

13K X 24

ROM

32K x 24

DATA ALU

Y MEMORY

7K X 24

8K x 24

XM_EB

RAM

ROM

YM_EB

EXTERNAL ADDRESS

SRAM BUS

INTERFACE

I - CACHE

EXTERNAL DATA BUS

BUS

SWITCH DRAM &

SWITCH

POWER

MNGMNT

JTAG

OnCE™

ADDRESS

CONTROL

DAT A

TRIPLE

TIMER

DAX

(SPDIF Tx.)

INTER-

FACE

ADDRESS

GENERATION

UNIT

SIX CHANNELS

DMA UNIT

INTERNAL

DATA

BUS

PLL

CLOCK

GENERAT

HOST

INTER-

FACE

PROGRAM

INTERRUPT

CONTROLLER

EXTAL

RESET

PINIT/NMI

MODA/IRQA MODB/IRQB MODC/IRQC

MODD/IRQD

24 BITS BUS

Figure 1 DSP56367 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Data Sheet

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TABLE OF CONTENTS

SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . 1-1

SECTION 2 SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

APPENDIX A POWER CONSUMPTION BENCHMARK . . . . . . . . . . .APPENDIX A-1

APPENDIX B IBIS MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .APPENDIX B-1

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FOR TECHNICAL ASSISTANCE:

Telephone: 1-800-521-6274 Email: dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is

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“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is

Examples:

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

active when low.)

low

high

Signal/Symbol Logic State Signal State Voltage

PIN PIN False Deasserted VIH/V PIN True Asserted VIH/V PIN False Deasserted VIL/V

True Asserted VIL/V

OL OH OH OL

1 DSP56367 Data Sheet MOTOROLA

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FEATURES

Core features are described fully in the DSP56300 Family Manual.

DSP56300 MODULAR CHASSIS

• 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal logic supply (QVCCL) of 1.8V.

• 100 Million Instructions Per Second (MIPS) with a 100 MHz clock at internal logic supply (QVCCL) of 1.5V.

• Object Code Compatible with the 56K core.

DSP56367

Features

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• Data ALU wit h a 24 x 24 bit multiplier -accumulator and a 56-bi t barrel shifter . 16-bit arithmeti c support.

• Program Control with position independent code support and instruction cache support.

• Six-channel DMA controller.

• PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2

• Internal address tracing support and OnCE for Hardware/Software debugging.

• JTAG port.

• Very l o w-power CMOS design, fully static design with operating frequencies down to DC.

• STOP and WAIT low-power standby modes.

: i=0 to 7). Reduces clock noise.

ON-CHIP MEMORY CONFIGURATION

• 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.

• 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

• 40Kx24 Bit Progr am ROM.

• 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as Instruction Cache or for Program ROM patching.

• 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10Kx24 Bit of Program RAM.

Data Sheet

MOTOROLA DSP56367 2

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DSP56367 Off-chip memory expansion

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OFF-CHIP MEMORY EXPANSION

• External Memory Expansion Port.

• Off-chip expansion up to two 16M x 24-bit word of Data memory.

• Off-chip expansion up to 16M x 24-bit word of Program memory.

• Simultaneous glueless interface to SRAM and DRAM.

PERIPHERAL MODULES

• Ser ial Audio Inter face (ESAI): up to 4 recei vers and up to 6 transmitter s, master or s lave. I2S, Sony, AC97, network and other programmable protocols.

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• Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmi tters, master or slave.

S, Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks)

• Ser ial Host Interface (SHI): SPI and I FIFO, support for 8, 16 and 24-bit words.

• Byte-wide parallel Host Interface (HDI08) with DMA support.

• Triple Timer module (TEC).

• Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats.

• Pi n s of unused peripherals (except SHI) may be programmed as GPIO lines.

144-PIN PLASTIC LQFP PACKAGE

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C protocols, multi master capability, 10-word receive

Data Sheet

3 DSP56367 MOTOROLA

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DSP56367

Documentation

DOCUMENTATION

Table 1 lists the documents that provide a complete description of the DSP56367 and are required

to design properly with the part. Documentation is avail able from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest inf ormation).

Table 1 DSP56367 Documentation

Document Name Description Order Number

DSP56300 Family Manual Detailed description of the 56000-family

architecture and the 24-bit core processor and instruction set

DSP56367 Product Brief Brief description of the chip DSP56367P/D

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DSP56367 User’s Manual DSP56367 User’s Manual DSP56367UM/AD

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DSP56300FM/AD

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Data Sheet

MOTOROLA DSP56367 4

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DSP56367 Documentation

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Data Sheet

5 DSP56367 MOTOROLA

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SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The input and output signals of the DSP56367 are organized into functional groups, which are listed in Table 1 and illustrated in Figure 1.

The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V. A

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special notice for this feature is added to the signal descriptions of those inputs.

Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.3.3V.

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Table 1 DSP56367 Functional Signal Groupings

Functional Group

Power (V

Ground (GND) 18 Table 3

Clock and PLL 3 Table 4

Address bus

Data bus 24 Table 6

Bus control 10 Table 7

Interrupt and mode control 5 Table 8

HDI08

SHI 5 Table 10

ESAI

ESAI_1

Digital audio transmitter (DAX)

) 20 Table 2

Port A

Port B

Port C

Port E

Port D

Number of

Signals

18 Table 5

16 Table 9

12 Table 11

6 Table 12

2 Table 13

Detailed

Description

Timer 1 Table 14

JTAG/OnCE Port 4 Table 15

MOTOROLA DSP56367 Data Sheet 1-1

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Signal/Connection Descriptions Signal Groupings

Table 1 DSP56367 Functional Signal Groupings (Continued)

Functional Group

Note: 1. Port A is the external memory interface port, including the external address bus, data bus, and

control signals.

2. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

5. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

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Number of

Signals

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Detailed

Description

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1-2 DSP56367 Data Sheet MOTOROLA

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Signal/Connection Descriptions

Signal Groupings

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PORT A ADDRESS BUS

A0-A17

VCCA (3) GNDA (4)

PORT A DATA BUS

D0-D23

VCCD (4) GNDD (4)

PORT A BUS CONTROL

AA0-AA2/RAS0-RAS2

CAS

RD WR TA BR BG

BB VCCC (2) GNDC (2)

INTERRUPT AND MODE CONTROL

MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD

RESET

PLL AND CLOCK

EXTAL

PINIT/NMI

PCAP VCCP GNDP

QUIET POWER

VCCQH (3)

VCCQL (4)

GNDQ (4)

SPDIF TRANSMITTER (DAX)

ADO [PD1] ACI [PD0]

TIMER 0

TIO0 [TIO0]

DSP56367

Port D

Port B

Port C

Port E

OnCE ON-CHIP EMULATION/

TDI

TCK TDO

TMS

JTAG PORT

PARALLEL HOST PORT (HDI08)

HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15]

VCCH GNDH

SERIAL AUDIO INTERFACE (ESAI)

SCKT[PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]

SERIAL AUDIO INTERFACE(ESAI_1)

SCKT_1[PE3] FS

T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2)

SERIAL HOST INTERFACE (SHI)

MOSI/HA0

/HA2

SS MISO/SDA

SCK/SCL

HREQ

Figure 1 Signals Identified by Functional Group

MOTOROLA DSP56367 Data Sheet 1-3

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Signal/Connection Descriptions Power

POWER

Table 2 Power Inputs

Power Name Description

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CCP

(4) Quiet Core (Low) Power— V

CCQL

(3) Quiet External (High) Power—V

CCQH

(3) Address Bus Power—V

CCA

(4) Data Bus Power—V

CCD

(2) Bus Control Power—V

CCC

CCH

(2) SHI, ESAI, ESAI_1, DAX and Timer Power —V

CCS

PLL Power—V provided with an extr emely low impedance path to the V

externally to all other V must provide adequate external decoupling capa ci tors. There are four V

other chip power inputs.The user must provide a dequate decoupling capacitors. There are three V

externally to all ot her chip power inputs. The user must provi de adequate external dec oupling capacitors. There are three V

CCA

externally to all ot her chip power inputs. The user must provi de adequate external dec oupling capacitors. There are four V

all other chip power inputs. The user must provide a d equate external decou pl ing capacitors. There are two V inputs.

Host Power—V chip power inputs . The user must provide adequate external decoupling capacitors. There is one V

Timer. This inpu t must be tied external ly to all other chip power inputs. The user mu s t provide adequate ext ernal decoupling capa citors. There are tw o V

CCD

inputs.

is VCC dedicated for PLL use. The volt age should be well-regulate d and the input should be

CCP

is an isolated power for the int ernal processing logic. This input must be tied

CCQL

power pins and the V

inputs.

CCQL

is a quiet power source for I/O lines. This input must be tied externally to all

CCQH

is an isolated power for sections of the address bus I/O drivers. This input must be tied

CCA

is an isolated power for sections of the data bus I/O drivers. This input must be tied

CCD

is an isolated power for the bus control I/O drivers. This input must be tied externally to

CCC

is an isolated pow er for the HDI08 I/O drivers. This input must be tied externally to all other

CCH

CCS

CCP

inputs.

GROUND

Table 3 Grounds

Ground Name Description

power rail. There is one V

power pin only. Do not tie with other power pins. The user

inputs.

CCQL

is an isolated power for the SHI, ESAI, ESAI_1, DAX and

CCS

CCP

input.

CCQH

CCH

inputs.

input.

CCC

GND

(4) Quiet Ground—GNDQ is an isolated ground for t h e i nternal processing logic. This connection must be ti ed

GND

1-4 DSP56367 Data Sheet MOTOROLA

PLL Ground—GNDP is a ground dedicated for PLL us e. The connection should be provided with an extreme ly low-impedance path to ground. V possible to the chi p package. There is one GND

externally to all other chip ground connections. The user must provi de adequate external decoupling capacitors. There are four GN D

connections.

should be bypassed to GNDP by a 0.47 µF capacitor located as close as

CCP

connection.

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Signal/Connection Descriptions

Clock and PLL

Table 3 Grounds

Ground Name Description

GNDA (4) Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. This conne ction

must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND

GND

(4) Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be

GND

(2) Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This co nne ction must be tied

tied externally to all other chip ground connections. The user must provide adequate external decoupling capaci tors. There are four GN D

externally to all other chip ground connections. The user must provi de adequate external de coupling capacitors. There are two G N D

connections.

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GND

(2) SHI, ESAI, ESAI_1, DAX and Timer Ground—GNDS is an isolated ground for the SHI, ESAI, ESAI_ 1, DAX

Host Ground—GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all other chip ground connec ti ons. The user must provide adequa t e external decoupling capa ci tors. There is one GND connection.

and Timer. This connection must be tied externall y to all other chip ground connec ti ons. The user must provide adequate ext ernal decoupling ca p acitors. There are two GND

CLOCK AND PLL

Signal Name Type

EXTAL Input Input External Clock Input—An external clock source must be connected to EXTAL in

PCAP Input Input PLL Capacitor—PCAP is a n input connecting an off-ch ip c apacitor to the PLL filter.

PINIT/NMI

Input Input PLL Initial/Nonmaskable Interrupt—During a ssert ion of RESET, the valu e of

State

during

Reset

connections.

Table 4 Clock and PLL Signals

Signal Description

order to supply the cloc k to the internal clock generator and PLL.

Connect one capacitor t erm i nal to PCAP and the other termina l t o V If the PLL is not use d, PCAP may be tied to V

PINIT/NMI determining whethe r the PLL is enabled or disabled. A fte r RESET during normal instruction processing, the PINIT/NMI negative-edge-tri ggered nonmaskable interru pt (N MI) re quest internally synchroni ze d to internal system clock.

is written into the PLL Enable (PEN) bit of the PLL control register,

, GND, or left floating.

Schmitt-trigger input is a

CCP

de assertion and

EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership

and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.

MOTOROLA DSP56367 Data Sheet 1-5

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Signal/Connection Descriptions External Address Bus

EXTERNAL ADDRESS BUS

Signal Name Type

A0–A17 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that

EXTERNAL DATA BUS

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Table 5 External Address Bus Signals

State

during

Reset

specify the addre s s for external program and d at a m emory accesses. Otherwise, the signals are tri-stated. To mini mi ze power dissipation, A0–A17 do not change sta te when external memo ry spaces are not being accessed.

Signal Description

Table 6 External Data Bus Signals

Signal Name Type State during Reset Signal Description

D0–D23 Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are

EXTERNAL BUS CONTROL

Signal

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Name

AA0–AA2/

–RAS

RAS0

Type

Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these signals can be

Frees

CAS

Output Tri-stated Column Address Strobe— When the DSP is the bus master, CAS is an active-low output

State

during

Reset

active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory acc esse s. Oth er w ise , D0–D23 are tri-s tated.

Table 7 External Bus Control Sign als

Signal Description

used as chip sele ct s o r additional address lines. When defined as RA S be used as RAS programmable polarity.

used by DRAM to strobe the column addre ss. Otherwi se, if th e bus m aste rship enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.

for DRAM interface. These sign al s are tri -sta ta bl e ou tputs with

, these signals can

1-6 DSP56367 Data Sheet MOTOROLA

Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is

asserted to read external me mory on the data bus (D0-D23). Otherwise, R D

Output Tri-stated Write Enable —When the DSP is the bus master, WR is an active-low output that is

asserted to write external memory on the data bus (D0-D23). Otherwise, WR

is tri-stated.

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Signal/Connection Descriptions

Table 7 External Bus Control Signals (Continued)

External Bus Control

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Signal

Name

TA Input Ig nore d

Type

Output Output

Input Ignored

Input/

Output

State

during

Reset

Input

(deasserted)

Input

Input Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is

Signal Description

Transfer Acknowledge—If the DSP is the bus master and there is no external bus

activity, or the DSP is not the bus master, the TA transfer acknowledge (DT A CK) function that can extend an e xternal bus cycle indefinitely. Any number of wait states (1, 2. . .in finity) may be added to the wait stat e s inserted by the BCR by keeping TA the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA asserted synchronous to the i nternal system clock. The nu mber of wait states is determined by the TA BCR can be used to set the minimum number of wait states in ext ernal bus cycles. In order to use the TA state. A zero wait st ate access cannot be ex tended by TA operation may result. TA setting of the TAS bit in the operati ng mode register (OMR). TA

functionality may not be used whi le performing DRAM type accesses, othe rwi s e

improper operation m ay resul t.

Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus slave. Bus “parking” allows BR master. (See the descript ion of bus “parking” in the BB request hold (BRH) bit in the BCR allows BR though the DSP does not need the bus. BR that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, neve r for t he i nternal bus. During hardware reset, BR

Bus Grant—BG is an active-low input. BG is as s erted by an external bu s arbitration circuit when the DSP56367 becomes the next bus master. When BG DSP56367 must wait until BB deasserted, bus mastership is typically given up at the end of t he current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution.

For proper BG register must be set.

active. Only after BB (and then assert the signal again). The bus master may keep BB activity regardless of whether BR and allows the current bus m ast er to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB

is driven high and then released and held high by an external pull-up resistor).

input or by the bus control register (BCR), whichever is longer. The

functionality, the BCR must be programmed to at le ast one wait

can operate synchronously or asynchronously, depending on the

is deasserted and the arbitration is reset to the bus slave stat e.

operation, the async hronous bus arbitration enabl e bi t (ABE) in the OMR

is deasserted can the pendi ng bus master become the bus mast er

deasserted. In typi ca l operation, TA is deasserted at

is deasserted when the DSP no longer needs the bus. BR may

to be deasserted even though the D SP563 67 is the bus

is deasserted before taking bus mast ership. When BG is

is asserted or deasserted. This is called “bus parking”

input is ignored. Th e TA input is a data

deassertion, otherwise improper

signal description.) The bus

to be asserted under softw are control even

is typically sent to an ext ernal bus arbitrator

is asserted, th e

asserted af ter ceasing b u s

is done by an “active pull-up” method (i.e.,

For proper BB register must be set.

requires an external pull-up resistor.

MOTOROLA DSP56367 Data Sheet 1-7

operation, the async hronous bus arbitration enable bit (ABE) in the OMR

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Signal/Connection Descriptions Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 8 Interrupt and Mode Control

State

Signal Name Type

during

Reset

Signal Description

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MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

Input Input Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA initial chip operating mod e du ring hardware reset and becomes a le ve l-se nsitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched int o the OMR when the RESET stop standby state and the MODA/IRQA stop state. This input is 3.3V tolerant.

Input Input Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low

Input Input Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low

Input Input Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low

Input Input Reset—RESET is an active-lo w , Schmitt-trigger input. Wh en asserted, the chip is placed in

Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB initial chip operating mod e du ring hardware reset and becomes a le ve l-se nsitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latche d into OMR when the RESET This input is 3.3V tole r an t.

Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC initial chip operating mod e du ring hardware reset and becomes a le ve l-se nsitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latche d into OMR when the RESET This input is 3.3V tole r an t.

Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD initial chip operating mod e du ring hardware reset and becomes a le ve l-se nsitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latche d into OMR when the RESET This input is 3.3V tole r an t.

the Reset stat e and the internal phase generator is reset. T h e Sc hmitt-trigger inpu t al lows a slowly rising input (such as a capac itor charging) to reset the chip reliabl y. Wh en the

signal is deasserted, the initial chip operating mode is latched from the MODA,

RESET MODB, MODC, and MODD inputs. The RESET A stable EXTAL signal must be supplied while RESET This input is 3.3V tolerant.

signal is deasserted. If the processor is in the

pin is pulled to GND, the processor will exit the

signal is deasserted.

signal must be asserted during power up.

is being asserted.

selects the

1-8 DSP56367 Data Sheet MOTOROLA

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Signal/Connection Descriptions

Parallel Host Interface (HDI08)

PARALLEL HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.

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cale Semiconductor,

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MOTOROLA DSP56367 Data Sheet 1-9

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Signal/Connection Descriptions Parallel Host Interface (HDI08)

Table 9 Host Interface

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cale Semiconductor,

Frees

Signal Name Type

H0–H7 Input/

HAD0–HAD7 Input/

PB0–PB7 Input, output, or

HA0 Input GPIO

HAS Input Host Address Strobe—When HDI08 is programmed to inte rface a

HAS/

PB8 Input, output, or

HA1 Input GPIO

HA8 Input Host Address 8—When HDI08 is programmed to int erf ace a multiplexed

PB9 Input, output, or

output

disconnected

State during

Reset

GPIO

disconnected

Host Data—When HDI08 is programmed to interface a nonmultiplexed

host bus and the HI function is sele cted, these signals are lines 0–7 of the bidirectional, tri-state data bus.

Host Address/Data—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines

0–7 of the address/data bidirectional, multiplex ed , tr i-state bus.

Port B 0–7—When the HDI08 is c onfi gu red as GPIO, these signals are individually programmable as input, output, or int er n a ll y disconnected.

The default state after reset for the s e si gna ls is GPIO di sconnected.

These inputs are 3.3V tolerant.

Host Address Input 0—When the HDI08 is programm e d to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus.

multiplexed ho s t bus and the HI function is s el ected, this signal is the host address strobe (HAS) Schmitt -trigger input. The pola rit y of the address strobe is programmable, but is co nfi gure d active-low (HAS reset.

Port B 8—When the HDI08 is con figured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

Host Address Input 1—When the HDI08 is programm e d to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus.

host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus.

Port B 9—When the HDI08 is con figured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

Signal Description

) following

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

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Signal/Connection Descriptions

Parallel Host Interface (HDI08)

Table 9 Host Interface (Continued)

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Frees

Signal Name Type

HA2 Input GPIO

HA9 Input Host Address 9—When HDI08 is programmed to int erf ace a multiplexed

PB10 Input, Output, or

HRW Input GPIO

HRD

PB11 Input, Output, or

HDS

HWR

Disconnecte d

Input Host Read Data—When HDI08 is programmed to int e rfa ce a

Disconnecte d

Input GPIO

Input Host Write Data—When HDI08 is programm ed to interface a

State during

Reset

disconnected

Host Address Input 2—When the HDI08 is program m ed to interface a non-multiplexed host bus and the HI function is selected, this signa l is li ne 2 of the host address (HA2) input bus.

host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus.

Port B 10—When th e HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

Host Read/Write—When HDI08 is program med to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Wri te

double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The pol arity of the data strobe is programm a ble, but is configured as active -l ow (HRD reset.

Port B 11—When th e HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

Host Data Strobe—When HDI0 8 is programmed to inter face a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS ) Schm itt-trigger input. The polarity of the data strobe is programmable, but is co nfi gure d as active-low (HDS reset.

double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programm a ble, but is configured as active -l ow (HWR following reset.

(HRW) input.

Signal Description

) following

) after

)

PB12 Input, output, or

MOTOROLA DSP56367 Data Sheet 1-11

disconnected

Port B 12—When th e HDI0 8 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

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Signal/Connection Descriptions Parallel Host Interface (HDI08)

Table 9 Host Interface (Continued)

nc...

cale Semiconductor,

Frees

Signal Name Type

HCS Input GPIO

HA10 Input Host Address 10—When HDI08 is programmed to interface a multiplexed

PB13 Input, output, or

/HOREQ Output GPIO

HOREQ

HTRQ

PB14 Input, output, or

HACK

HRRQ

disconnected

Output Transmit Host Request—When HDI08 is programmed to interface a

disconnected

Input GPIO

Output Receive Host Request—When HDI08 is programmed to int er fac e a

State during

Reset

disconnected

Host Chip Select—When HDI08 is programmed to interface a nonmultiplexed host bus and the H I function is select ed, this signal is the host chip select (HCS) input. The po larity of the chip sel ect is programmable, but is configured active-lo w (HCS

host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus.

Port B 13—When th e HDI0 8 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

Host Request—When HDI08 is programmed t o int er fac e a single host request host bus and the HI function is sele cted, this signal is the host request (HOREQ) outpu t. The pol arity of the host request is programmable, but is configured as active-lo w (HORE Q The host request may be programmed as a driven or open-drain output.

double host request host bus a nd the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ The host request may be programmed as a driven or open-drain output.

Port B 14—When th e HDI0 8 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

Host Acknowledge—When HDI08 is programmed to interface a singl e host request host bus and th e HI function is selected, this sign al is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK after reset.

double host request host bus and the HI function is selected, this signal is the receive host reques t (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ host request may be program m ed a s a dri ven or open-drain output.

Signal Description

) after reset.

) following reset.

) after reset. Th e

)

PB15 Input, output, or

1-12 DSP56367 Data Sheet MOTOROLA

disconnected

Port B 15—When th e HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V toleran t.

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Signal/Connection Descriptions

Serial Host Interface

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.

Table 10 Serial Host Interface Signals

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Signal

Name

SCK Input or

SCL Input or

MISO Input or

SDA Input or

Signal Type

output

open-drain

output

State

during

Reset

Tri-stated SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and

Tri-stated SPI Master-In-Slave-Out—When the SPI is confi gured as a master, MISO is the master

a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is deriv ed fr om the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS devices, data is shifted on on e edge of the SCK signal and is sample d on t he opposite edge where data is stable. Edge polarity is determined by the SP I tra n s fer protocol.

C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a

Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connec ted to V

This signal is tri-state d during hardware, software, and indi vi dual reset. Thus, there is no need for an external pull-up in this state.

This input is 3.3V tolerant.

data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI S lave mode when S S required for SPI operation.

C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when receiving

and an open-drain output when transmitting. SDA shoul d be connected to V pull-up resistor. SDA carries the data for I

during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to -high transition of SDA while SCL is high is a unique situation defined as the stop event.

This signal is tri-state d during hardware, software, and indi vi dual reset. Thus, there is no need for an external pull-up in this state.

Signal Description

) signal is not asse rted. In both the master and slave SPI

through a pull-up resistor.

is deasserted. An external pull-up resistor is not

through a

C transactions. The data in SDA must be stable

This input is 3.3V tolerant.

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Signal/Connection Descriptions Serial Host Interface

Table 10 Serial Host Interface Signals (Continued)

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Frees

Signal

Name

MOSI Input or

HA0 Input

HA2 Input

HREQ

Signal Type

output

Input Tri-stated SPI Slave Select—This signal is an active low Schmitt-trigger input when configured for

Input or

Output

State

during

Reset

Tri-stated SPI Master-Out-Slave-In— When the SPI is configured as a master, MOSI is the master

data output line. The MOSI si gnal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave . Th i s signa l i s a Schmi tt -trigger input when configur ed for the SPI Slave mode.

C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the I2C

mode. When configured for I address. HA0 is ignored when co nfi gured for the I

This signal is tri-state d during hardware, software, and indi vi dual reset. Thus, there is no need for an external pull-up in this state.

This input is 3.3V tolerant.

the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When co nfi gured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS output signal in the high-impedance state.

C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I2C

mode. When configured for the I device address. HA2 is ignored in the I

This signal is tri-state d during hardware, software, and indi vi dua l reset. Thus, there is no need for an external pull-up in this state.

This input is 3.3V tolerant.

Tri-stated Host Request—This signal is an active low Schmi tt -tri gger input when configured for the

master mode but an ac ti ve low output when configured for the slave mode.

When configured for the slave mode, HREQ the next data word tran sf er and deasserted at the first clock pulse of the new data word transfer. When confi gured for the master mode, HREQ external slave device, it will trigge r the start of the data wor d transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to the next trans fer.

This signal is tri-stated dur ing hardware, software, personal reset , or when t he HREQ1–HREQ0 bit s in the HCSR are cleared. The re is no need for external pu ll -up in this state.

is deasserted, the SHI ignores SCK clocks and keeps the MISO

Signal Description

C slave mode, the HA0 signal is used to form the slave device

C Slave mode, the HA2 signal is used t o form the slave

C master mode.

is asserted to indicate tha t the SHI is ready for

is an input. When asserted by the

to proceed

This input is 3.3V tolerant.

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ENHANCED SERIAL AUDIO INTERFACE

Table 11 Enhanced Serial Audio Interface Signals

Signal/Connection Descriptions

Enhanced Serial Audio Interface

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Frees

Signal

Name

HCKR Input or output GPIO disconnected High Frequency Clock for Receiver—When programmed as an input, this

PC2 Input, output, or

HCKT Input or output GPIO disconnected High Frequency Clock for Transmitter—When programmed as an input,

PC5 Input, output, or

FSR Inp ut or output GPIO disconnected Frame Sync for Receiver—Thi s is the receiver frame sync input /output

PC1 Input, output, or

FST Input or output GPIO disconnected Frame Sync for Transmitter—This is the transmitter frame sync input/output

Signal Type State during Reset Signal Description

signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-freque nc y sam p l e c loc k (e .g., for external digital to anal og converters [DACs]) or as an additional system clock.

Port C 2—When the ESAI is configured as GPIO, thi s signa l is i ndividually

disconnected

programmable as input, output, or internally disconnected. The default stat e after reset is GPIO dis connected.

This input is 3.3V tolerant.

this signal provides a high frequency clock source for the ESAI t ransmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequen cy sample clock (e.g., for exte rna l DACs) or as an additional system clock.

Port C 5—When the ESAI is configured as GPIO, thi s signa l is i ndividually programmable as input, output, or internally disconnected.

The default stat e after reset is GPIO dis connected.

This input is 3.3V tolerant.

signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as ei the r the serial flag 1 pin (TEBE=0 ), or as the transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the val ue of the OF1 bit in the SAICR register, a nd t h e da t a in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured a s the input flag IF1, the data value at the pin will be store d in the IF1 bit in the SAISR register, synchronized by the fram e sync in normal mode or the slot in netw ork mode.

Port C 1—When the ESAI is configured as GPIO, thi s signa l is i ndividually programmable as input, output, or internally disconnected.

The default stat e after reset is GPIO dis connected.

This input is 3.3V tolerant.

signal. For synchronous mode, thi s signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitter s o nly. The dir ecti on is dete r mined b y t he t ran smit ter frame sy nc direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

PC4 Input, output, or

disconnected

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Port C 4—When the ESAI is configured as GPIO, thi s signa l is i ndividually programmable as input, output, or internally disconnected.

The default stat e after reset is GPIO dis connected.

This input is 3.3V tolerant.

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Signal/Connection Descriptions Enhanced Serial Audio Interface

Table 11 Enhanced Serial Audio Interface Signals (Continued)

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Frees

Signal

Name

SCKR Input or output GPIO disconnected Receiver Serial Clock—SCKR provides the receiver serial bit clock for the

PC0 Input, output, or

SCKT Input or output GPIO disconnected Transmitter Serial Clock—This signal provides the serial bit rate clock for

PC3 In put , output, or

SDO5 Output GPIO disconnected Serial Data Output 5— W he n programmed as a transmitter, SD O5 is use d to

SDI0 Input Serial Data Input 0—When programme d as a rec ei ve r, SDI0 is used to

PC6 Input, output, or

SDO4 Output GPIO disconnected Serial Data Output 4— W he n programmed as a transmitter, SD O4 is use d to

SDI1 Input Serial Data Input 1—When programme d as a rec ei ve r, SDI1 is used to

PC7 Input, output, or

Signal Type State during Reset Signal Description

ESAI. The SCKR operates as a clock input or output used by al l the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will refle ct the value of the OF0 bit in th e S A IC R r egister, and the da ta in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the inp u t fl ag IF0, the data value at the pi n wil l be store d in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

disconnected

Port C 0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or interna ll y disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V toleran t.

the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

Port C 3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or interna ll y disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V toleran t.

transmit data from the TX5 serial transmit shift register.

receive serial data into the RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal is individually

programmable as input, output, or interna ll y disconnected. The default state after reset is GPIO disconnected.

This input is 3.3V toleran t.

transmit data from the TX4 serial transmit shift register.

receive serial data into the RX1 serial receive shift register. Port C 7—When the ESAI is configured as GPIO, this signal is individually

programmable as input, output, or interna ll y disconnected. The default state after reset is GPIO disconnected.

This input is 3.3V toleran t.

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 11 Enhanced Serial Audio Interface Signals (Continued)

nc...

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Frees

Signal

Name

SDO3/SD

O3_1

SDI2/SDI

2_1

PC8/PE8 Input, outp ut, or

SDO2/SD

O2_1

SDI3/SDI

3_1

PC9/PE9 Input, outp ut, or

SDO1/SD

O1_1

PC10/PE10Input, output, or

SDO0/SD

O0_1

PC11/PE11Input, output, or

Signal Type State during Reset Signal Description

Output GPIO disconnected Serial Data Output 3—When programm ed as a transmitter, SDO3 is used to

Input Se rial Data Input 2—W hen programmed as a receiver, SDI2 is used to

disconnected

Output GPIO disconnected Serial Data Output 2—When programm ed as a transmitter, SDO2 is used to

Input Se rial Data Input 3—W hen programmed as a receiver, SDI3 is used to

disconnected

Output GPIO disconnected Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial

disconnected

Output GPIO disconnected Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial

disconnected

transmit data from the TX3 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3.

receive serial data in to the RX2 serial receive shift re gister. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2.

Port C 8—When the ESAI is configured as GPIO, thi s signa l is i ndividually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 8 signal.

The default stat e after reset is GPIO d isconnected.

This input is 3.3V tolerant.

transmit data from the TX2 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.

receive serial data in to the RX3 serial receive shift re gister. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3.

Port C 9—When the ESAI is configured as GPIO, thi s signa l is i ndividually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal.

The default stat e after reset is GPIO d isconnected.

This input is 3.3V tolerant.

transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1.

Port C 10—When th e ESAI is configured as GPIO, this signal is indi vidually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal.

The default stat e after reset is GPIO d isconnected.

This input is 3.3V tolerant.

transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0.

Port C 11—When th e ESAI is configured as GPIO, this signal is indi vidually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal.

The default stat e after reset is GPIO d isconnected.

This input is 3.3V tolerant.

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Signal/Connection Descriptions Enhanced Serial Audio Interface_1

ENHANCED SERIAL AUDIO INTERFACE_1

Table 12 Enhanced Serial Audio Interface_1 Signals

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Signal

Name

FSR_1 Inpu t or output GPIO disconnected Frame Sync for Receive r_1—This is the receiver frame sync input/output

PE1 Input, output, or

FST_1 Input or output GPIO disconnected Frame Sync for Tr ansmitter_1—This is the transmitte r fr ame sync

PE4 Input, output, or

SCKR_1 Input or output GPIO disconnected Receiver Serial Clock_1—SCKR provides the receiver seri al bit cl ock for

PE0 Input, output, or

Signal Type State during Reset Signal Description

signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by al l the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffe r enable control (TEBE =1, RFSD=1).

When this pin is configured as serial fl ag pi n, its direction is determined by the RFSD bit in the RCCR regi ste r. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR regis ter, and the data in the OF1 bit will show up at the pin synchronized to the fram e sync in normal mode or the slot in ne twork mode. When configur ed a s the inpu t flag IF1, the data value at t h e pin will be stored in th e IF 1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port E 1—When the ESAI is configured as GP IO, thi s signa l i s indi vidually

disconnected

programmable as input, output, or internally disconnected. The default state after reset is GPIO disco nne cted.

This input cannot tolerate 3.3V .

input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and re ceivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transm i tt er frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).

Port E 4—When the ESAI is configured as GP IO, thi s signa l i s indi vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disco nne cted.

This input cannot tolerate 3.3V .

the ESAI. The SC K R operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

When this pin is configured as serial fl ag pi n, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR regis ter, and the data in the OF0 bit will show up at the pin synchronized to the fram e sync in normal mode or the slot in ne twork mode. When configur ed a s the inpu t flag IF0, the data value at t h e pin will be stored in th e IF 0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.

Port E 0—When the ESAI is configured as GP IO, thi s signa l i s indi vidually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disco nne cted.

This input cannot tolerate 3.3V .

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Signal/Connection Descriptions

SPDIF Transmitter Digital Audio Interface

Table 12 Enhanced Serial Audio Interface_1 Signals

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Frees

Signal Name

SCKT_1 Input or ou tput GPIO disconnect ed Transmitter Serial Clock_1—This signal provides the serial bit rate clock

PE3 Input, output, or

SDO5_1 Output GPIO disconnected Serial Data Output 5_1—When programmed as a transmitter, SDO5 is used

SDI0_1 Input Serial Data Input 0_1—When programme d a s a receive r, SDI0 is use d to

PE6 Input, output, or

SDO4_1 Output GPIO disconnected Serial Data Output 4_1—When programmed as a transmitter, SDO4 is used

SDI1_1 Input Serial Data Input 1_1—When programme d a s a receive r, SDI1 is use d to

PE7 Input, output, or

Signal Type State during Reset Signal Description

for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode.

disconnected

Port E 3—When the ESAI is configured as GP IO, this signa l i s indi vi dually programmable as input, output, or internally disconnected.

The default state after reset is GPIO disco nne cted.

This input canno t tolerate 3.3V.

to transmit data from the TX5 seri al transmit shift register.

receive serial data into the RX0 seri al r ec ei v e shift register. Port E 6—When the ESAI is configured as GP IO, this signa l i s indi vi dually

programmable as input, output, or internally disconnected. The default state after reset is GPIO disco nne cted.

This input canno t tolerate 3.3V.

to transmit data from the TX4 seri al transmit shift register.

receive serial data into the RX1 seri al r ec ei v e shift register. Port E 7—When the ESAI is configured as GP IO, this signa l i s indi vi dually

programmable as input, output, or internally disconnected. The default state after reset is GPIO disco nne cted.

This input is 3.3V tolerant.

SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE

Table 13 Digital Audio Interface (DAX) Signals

Signal

Name

ACI Input GPIO Disconnected Audio Clock Input—This is the DAX clock input. When programmed to use

Type State During Reset Signal Description

an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs or 512 × Fs, respectively).

PD0 Input,

MOTOROLA DSP56367 Data Sheet 1-19

output, or

disconnected

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Port D 0—When the DAX is configured as GPIO, th is signal is individually programmable as input, output, or internally di sconnected.

The default state after reset is GPIO disc onnected.

This input is 3.3V tolerant.

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Signal/Connection Descriptions Timer

Table 13 Digital Audio Interface (DAX) Signals (Continued)

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Signal Name

ADO Output GPIO Disconnected Digital Audio Data Output—This signal is an audio and no n-a udio output in

PD1 Input,

TIMER

Signal Name Type

TIO0 Input or Output Inp ut Timer 0 Schmitt-Trigger Input/Output— When timer 0 functions as an ext e rnal

Type State During Reset Signal Description

output, or

disconnected

cale Semiconductor,

JTAG/OnCE INTERFACE

State during

Reset

the form of AES/EBU, CP340 a nd IE C958 data in a biphase mark format.

Port D 1—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internal ly disconnected.

The default state after reset is GPIO disc onnected.

This input is 3.3V tolerant.

Table 14 Timer Signal

Signal Description

event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pul se m odulation mode, TIO0 is used as out put.

The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either de fine it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input.

This input is 3.3V tolerant.

Frees

Table 15 JTAG/OnCE Interface

Signal

Name

TCK Input Input Test Clock—TCK is a test clock input sign al used to synchronize the JTAG test l ogi c. It

1-20 DSP56367 Data Sheet MOTOROLA

Signal

Type

State

during

Reset

Signal Description

has an internal pull-up resistor.

This input is 3.3V toler ant.

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Signal/Connection Descriptions

Table 15 JTAG/OnCE Interface (Continued)

Signal

Name

TDI Input Input Test Data Input—TDI is a test data serial input signa l used for test instructions and data.

TDO Output Tri-stated Test Data Output—TDO is a te st data serial output signal used for test instructions and

TMS Input Input Test Mode Select—TM S is an input signal used to s equence the test cont roller’s state

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Signal

Type

cale Semiconductor,

State

during

Reset

Signal Description

TDI is sampled on the rising edge of TCK and has an intern al pull-up resistor.

This input is 3.3V toler ant.

data. TDO is tri-stat able and is acti ve ly dr ive n in the sh ift -IR and shif t-DR contro ller sta tes. TDO changes on the falling edge of TCK.

machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor.

This input is 3.3V toler ant.

Frees

MOTOROLA DSP56367 Data Sheet 1-21

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Signal/Connection Descriptions

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Freescale Semiconductor, Inc.

cale Semiconductor,

Frees

1-22 DSP56367 Data Sheet MOTOROLA

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SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs.

Note: This document contains information on a new product.

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Finalized specifications may be published after further characterization and device qualifications are completed.

Specifications and information herein are subject to change without notice.

cale Semiconductor,

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MAXIMUM RATINGS

CAUTION

This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 kΩ.

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the

worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum”

MOTOROLA DSP56367 Data Sheet 2-1

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Specifications Maximum Ratings

value for another specification; adding a maximum to a minimum represents a condition that can never exist.

Freescale Semiconductor, Inc.

Table 1 Maximum Ratings

Rating

Supply Voltage V

All “3.3V to lerant” input voltages

Current drain per pin ex cluding V

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Operating temperature range

Storage temperat ure T

Note: 1. GND = 0 V, VCCP, VCCQL = 1.8 V ±5%, TJ = –4 0× C to + 95×C, CL = 50 pF

All other VCC = 3.3 V ± 5%, TJ = –40×C to +95 ×C , CL = 50 pF

2. Absolute maximum ratings are stress ratings only, and functional operation at th e m aximum is not guaranteed. Stress beyond the maximum rating may affect devi ce reliability or cause permanent damage to the device.

3. Temperatures below -0°C are qu alified for consumer appli cations.

and GND I 10 mA

Symbol

CCQL, VCCP

CCQH, VCCA,

CCD, VCCC,

CCH, VCCS,

STG

GND − 0.3 to V

cale Semiconductor,

Value

1, 2

Unit

−0.3 to + 2.0

−0.3 to + 4.0

+ 0.7

−40 to + 95 °C

−55 to +125 °C

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2-2 DSP56367 Data Sheet MOTOROLA

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+ 111 hidden pages

Freescale DSP56367 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

Data Sheet Conventions

FEATURES

DSP56300 MODULAR CHASSIS

ON-CHIP MEMORY CONFIGURATION

OFF-CHIP MEMORY EXPANSION

PERIPHERAL MODULES

144-PIN PLASTIC LQFP PACKAGE

Documentation

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

POWER

GROUND

Clock and PLL

EXTERNAL MEMORY EXPANSION PORT (PORT A)

EXTERNAL ADDRESS BUS

EXTERNAL DATA BUS

EXTERNAL BUS CONTROL

INTERRUPT AND MODE CONTROL

Parallel Host Interface (HDI08)

Serial Host Interface

ENHANCED SERIAL AUDIO INTERFACE

ENHANCED SERIAL AUDIO INTERFACE_1

SPDIF Transmitter Digital Audio Interface

TIMER

JTAG/OnCE INTERFACE

SPECIFICATIONS

INTRODUCTION

MAXIMUM RATINGS