Freescale DSP56362 Technical Data
Technical Data
DSP56362/D
Rev. 3, 02/2004
24-Bit Audio Digital
Signal Processor
Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression
and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The
DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the
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Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance
increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct
memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal
100 MHz clock at 3.3 V.
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EXTAL
CLKOUT
PINIT/NMI
Triple
Timer
RESET
Address
Generation
Unit
Six Channel
DMA Unit
Internal
Data
Bus
Switch
Clock
Generator
PLL
2
DAX
(SPDIF)
Interface
PIO_EB
Program
Interrupt
Controller
1216
Host
ESAI
Peripheral
Expansion Area
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
5
SHI
Program RAM/
Instruction
Cache
× 24
3072
Program ROM
× 24
30K
Bootstrap ROM
× 24
192
PM_EB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Program
Address
Generator
YAB
XAB
PAB
DAB
24
Figure 1 DSP56362 Block Diagram
X Data
RAM
5632
ROM
6144
×
24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
× 24
5632
× 24
6144
XM_EB
Data ALU
Y Data
RAM
× 24
ROM
× 24
YM_EB
DRAM/SRAM
Memory
Expansion
Area
External
Address
Bus
Switch
Bus
Interface
&
I - Cache
Control
External
Data Bus
Switch
Power
Mngmnt.
JTAG
OnCE
18
Address
11
Control
24
Data
6
AA0456G
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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MOTOROLA DSP56362 Advance Information iii
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SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK. . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I
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FOR TECHNICAL ASSISTANCE:
Telephone: 1-800-521-6274
Email: dsphelp@dsp.sps.mot.com
Internet: http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
“asserted” Means that a high true (active high) signal is high or that a low true (active low)
signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Examples:
Signal/Symbol Logic State Signal State Voltage*
PIN
True Asserted VIL/V
OL
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
!! DSP56362 Advance Information MOTOROLA
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OH
OH
OL
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FEATURES
• Multimode, multichannel decoder software functionality
– Dolby Digital and Pro Logic
– MPEG2 5.1
–DTS
– Bass management
OVERVIEW
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• Digital audio post-processing capabilities
– 3D Virtual surround sound
– Lucasfilm THX5.1
– Soundfield processing
– Equalization
• Digital Signal Processing Core
– 100 MIPS with a 100 MHz clock at 3.3 V +/- 5%
– Object code compatible with the DSP56000 core
– Highly parallel instruction set
– Data arithmetic logic unit (ALU)
• Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
• 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
• Conditional ALU instructions
• 24-bit or 16-bit arithmetic support under software control
– Program control unit (PCU)
• Position independent code (PIC) support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
– Direct memory access (DMA)
• Six DMA channels supporting internal and external accesses
• One-, two-, and three- dimensional transfers (including circular buffering)
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Overview
Features
• End-of-block-transfer interrupts
• Triggering from interrupt lines and all peripherals
– Phase-locked loop (PLL)
• Software programmable PLL-based frequency synthesizer for the core clock
• Allows change of low-power divide factor (DF) without loss of lock
• Output clock with skew elimination
– Hardware debugging support
• On-Chip Emulation (OnCE‘) module
• Joint Action Test Group (JTAG) test access port (TAP)
• Address trace mode reflects internal program RAM accesses at the external port
• On-Chip Memories
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– Modified Harvard architecture allows simultaneous access to program and data memories
– 30720 x 24-bit on-chip program ROM
– 6144 x 24-bit on-chip X-data ROM
– 6144 x 24-bit on-chip Y-data ROM
– Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable
Instruction
Cache
Disabled Disabled 3072 × 24-bit 0 5632 × 24-bit 5632 × 24-bit
Enabled Disabled 2048 × 24-bit 1024 × 24-bit 5632 × 24-bit 5632 × 24-bit
Disabled Enabled 5120 × 24-bit 0 5632 × 24-bit 3584 × 24-bit
Enabled Enabled 4096 × 24-bit 1024 × 24-bit 5632 × 24-bit 3584 × 24-bit
– 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)
• Off-Chip Memory Expansion
– Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.
– Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.
– External memory expansion port( twenty-four data pins for high speed external memory
access allowing for a large number of external accesses per sample)
Switch
Mode
Program RAM
Size
1
(disabled in 16-bit compatibility mode)
1
1
.
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
– Chip select logic for glueless interface to SRAMs
– On-chip DRAM controller for glueless interface to DRAMs
• Peripheral and Support Circuits
– Enhanced serial audio interface (ESAI) includes:
• Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.
• Master or slave capability
2
•I
S, Sony, AC97, and other audio protocol implementations
1.These ROMs may be factory programmed with data or programs provided by the application developer.
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– Serial host interface (SHI) features:
• SPI protocol with multi-master capability
2
•I
C protocol with single-master capability
• Ten-word receive FIFO
• Support for 8-, 16-, and 24-bit words.
– Byte-wide parallel host interface (HDI08) with DMA support
– DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,
and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines
– Triple timer module with single external interface or GPIO line
– On-chip peripheral registers are memory mapped in data memory space
• Reduced Power Dissipation
– Very low-power (3.3 V) CMOS design
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– Wait and stop low-power standby modes
– Fully-static logic, operation frequency down to 0 Hz (dc)
Overview
Documentation
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– Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
Package
• 144-pin plastic thin quad flat pack (LQFP) surface-mount package
DOCUMENTATION
Table 1 lists the documents that provide a complete description of the DSP56362 and are required to
design properly with the part. Documentation is available from a local Motorola distributor, a Motorola
semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home
page on the Internet (the source for the latest information).
Table 1 DSP56362 Documentation
Document Name Description Order Number
DSP56300 Family Manual Detailed description of the 56000-family
architecture and the 24-bit core processor and
instruction set
DSP56362 User’s Manual Detailed description of memory, peripherals,
and interfaces
DSP56362 Advance Information Electrical and timing specifications; pin and
package descriptions
DSP56300FM/AD
DSP56362UM/AD
DSP56362/D
There is also a product brief for this chip.
DSP56362 Product Brief Brief description of the chip DSP56362P/D
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NOTES
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SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The input and output signals of the DSP56362 are organized into functional groups, which are listed in
Table 1-1 and illustrated in Figure 1-1.
The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
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Table 1-1 DSP56362 Functional Signal Groupings
Functional Group
Power (V
Ground (GND)
Clock and PLL
Address bus
Data bus
Bus control
Interrupt and mode control
HDI08
SHI
ESAI
Digital audio transmitter (DAX)
Timer
CC
)
Port A
Port B
Port C
Port D
Number of
Signals
20 Table 1-2
19 Table 1-3
4 Table 1-4
18 Table 1-5
1
2
3
4
24 Table 1-6
11 Table 1-7
5 Table 1-8
16 Table 1-9
5 Table 1-10
12 Table 1-11
2 Table 1-12
1 Table 1-13
Detailed
Description
JTAG/OnCE Port
Port A is the external memory interface port, including the external address bus, data bus, and
control signals.
Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
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Signal/Connection Descriptions
Signal Groupings
DSP56362
V
CCP
V
CCQH
V
CCQL
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
GNDP
GNDP1
GND
GND
GND
GND
GND
GND
EXTAL
CLKOUT
PCAP
PINIT/NMI
Q
A
D
C
H
S
Power Inputs:
PLL
3
External I/O
4
Internal Logic
3
Address Bus
4
Data Bus
2
Bus Control
HDI08
2
SHI/ESAI/DAX/Timer
Grounds:
PLL
PLL
4
Internal Logic
4
Address Bus
4
Data Bus
2
Bus Control
HDI08
2
SHI/ESAI/DAX/Timer
Clock and
PLL
Host
Interface
(HDI08)
Port
Serial
Host
Interface
(SHI)
1
Port A
18
24
4
External
Address Bus
External
Data Bus
External
Bus
Control
Transmitter (DAX)
Interrupt/
Mode
Control
A0–A17
D0–D23
AA0–AA3/
–RAS3
RAS0
CAS
RD
WR
TA
BR
BG
BB
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Notes: 1. The HDI08 port supports a nonmultiplexed or a multiplexed bus, single or double data strobe (DS), and single or
double host request (HR) configurations. Since each of these modes is configured independently, any
combination of these modes is possible. These HDI08 signals can also be configured alternately as GPIO
signals (PB0–PB15). Signals with dual designations (e.g., HAS
2. The ESAI signals are multiplexed with the port C GPIO signals (PC0–PC11). The DAX signals are multiplexed
with the Port D GPIO signals (PD0–PD1). The timer 0 signal can be configured alternately as the timer GPIO
signal (TIO0).
Enhanced
Serial
Audio
Interface
(ESAI)
Digital Audio
Timer 0
JTAG/
OnCE Port
2
2
2
NonMultiplexed Bus
8
H0–H7
HA0
HA1
HA2
HCS
HCS/
Single DS
HRW
HDS/HDS
Single HR
/HOREQ
HOREQ
HACK
/HACK
SPI Mode
MOSI
SS
MISO
SCK
HREQ
SCKR
FSR
HCKR
SCKT
FST
HCKT
SDO5/SDI0
SDO4/SDI1
SDO3/SDI2
SDO2/SDI3
SDO1
SDO0
ACI
ADO
TIO0
TCK
TDI
TDO
TMS
TRST
DE
/HAS) have configurable polarity.
Multiplexed
Bus
HAD0–HAD7
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
/HTRQ
HTRQ
HRRQ
I2C Mode
HA0
HA2
SDA
SCL
HREQ
Port C GPIO
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
Port D GPIO
PD0
PD1
Timer GPIO
TIO0
/HRRQ
Port B
GPIO
PB0–PB7
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
AA0601
Figure 1-1 Signals Identified by Functional Group
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POWER
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Signal/Connection Descriptions
Table 1-2 Power Inputs
Power
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V
CCP
V
CCQL
V
CCQH
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
Power
Name
(4)
(3)
(3)
(4)
(2)
(2)
Description
PLL Power—V
regulated and the input should be provided with an extremely low impedance path
to the V
Quiet Core (Low) Power—V
logic. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four V
Quiet External (High) Power—V
input must be tied externally to all other chip power inputs. The user must provide
adequate decoupling capacitors. There are three V
Address Bus Power—V
O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are three V
inputs.
Data Bus Power—V
drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four V
Bus Control Power—V
This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors. There are two V
Host Power—V
be tied externally to all other chip power inputs. The user must provide adequate
external decoupling capacitors. There is one V
SHI, ESAI, DAX, and Timer Power—V
DAX, and Timer I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.
There are two V
power rail. There is one V
CC
is VCC dedicated for PLL use. The voltage should be well-
CCP
input.
CCP
is an isolated power for the core processing
CCQL
CCQ
is a quiet power source for I/O lines. This
CCQH
inputs.
CCQH
is an isolated power for sections of the address bus I/
CCA
is an isolated power for sections of the data bus I/O
CCD
CCD
is an isolated power for the bus control I/O drivers.
CCC
inputs.
CCC
is an isolated power for the HDI08 I/O drivers. This input must
CCH
input.
CCH
is an isolated power for the SHI, ESAI,
CCS
inputs.
CCS
inputs.
CCA
inputs.
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Signal/Connection Descriptions
Ground
GROUND
Table 1-3 Grounds
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Ground
Name
GND
GND
GND
GND
GND
GND
GND
GND
P
P1
(4)
Q
A (4)
(4)
D
(2)
C
H
(2)
S
Description
PLL Ground—GNDP is a ground dedicated for PLL use. The connection should be
provided with an extremely low-impedance path to ground. V
bypassed to GND
package. There is one GND
PLL Ground 1—GNDP1 is a ground dedicated for PLL use. The connection should
be provided with an extremely low-impedance path to ground. There is one GND
connection.
Quiet Ground—GND
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There are four GND
connections.
Address Bus Ground—GNDA is an isolated ground for sections of the address
bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
There are four GND
Data Bus Ground—GND
drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
There are four GND
Bus Control Ground—GND
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors. There are two GND
connections.
Host Ground—GNDH is an isolated ground for the HDI08 I/O drivers. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There is one GND
connection.
SHI, ESAI, DAX, and Timer Ground—GND
ESAI, DAX, and Timer I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND
by a 0.47 µF capacitor located as close as possible to the chip
P
Q
connections.
A
connections.
D
connection.
P
is an isolated ground for the internal processing logic. This
is an isolated ground for sections of the data bus I/O
D
is an isolated ground for the bus control I/O drivers.
C
is an isolated ground for the SHI,
S
connections.
S
should be
CCP
P1
Q
C
H
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CLOCK AND PLL
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Signal/Connection Descriptions
Table 1-4 Clock and PLL Signals
Clock and PLL
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Signal
Name
EXTAL Input Input
CLKOUT Output Chip-driven
PCAP Input Input
PINIT/
NMI
Type
Input Input
State during
Reset
Signal Description
External Clock Input—An external clock source must be
connected to EXTAL in order to supply the clock to the
internal clock generator and PLL.
This input cannot tolerate 5V.
Clock Output—CLKOUT provides an output clock
synchronized to the internal core clock phase.
If the PLL is enabled and both the multiplication and division
factors equal one, then CLKOUT is also synchronized to
EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the
frequency of EXTAL. CLKOUT is not functional at
frequencies of 100 MHz and above.
PLL Capacitor—PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor terminal to
PCAP and the other terminal to V
If the PLL is not used, PCAP may be tied to V
floating.
PLL Initial/Non maskable Interrupt—During assertion of
RESET
(PEN) bit of the PLL control register, determining whether the
PLL is enabled or disabled. After RESET
during normal instruction processing, the PINIT/NMI
trigger input is a negative-edge-triggered non maskable
interrupt (NMI) request internally synchronized to CLKOUT.
PINIT/NMI
, the value of PINIT/NMI is written into the PLL Enable
cannot tolerate 5 V.
CCP
.
, GND, or left
CC
deassertion and
Schmitt-
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tristates the relevant port A signals: A0–A17, D0–D23, AA0/RAS0
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–AA3/RAS3, RD, WR, BB, CAS.
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
External Address Bus
Table 1-5 External Address Bus Signals
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Signal
Name
A0–A17 Output Tri-stated
Type
State during
External Data Bus
Table 1-6 External Data Bus Signals
Signal
Name
D0–D23 Input/Output Tri-stated
Type
State during
External Bus Control
Table 1-7 External Bus Control Signals
Signal
Name
Type
State during
Reset
Reset
Reset
Signal Description
Address Bus—When the DSP is the bus master,
A0–A17 are active-high outputs that specify the
address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To
minimize power dissipation, A0–A17 do not change
state when external memory spaces are not being
accessed.
Signal Description
Data Bus—When the DSP is the bus master,
D0–D23 are active-high, bidirectional input/
outputs that provide the bidirectional data bus for
external program and data memory accesses.
Otherwise, D0–D23 are tri-stated.
Signal Description
Address Attribute or Row Address Strobe—When
AA0–AA3/
RAS0
–
RAS3
1-6 DSP56362 Advance Information MOTOROLA
Output Tri-stated
defined as AA, these signals can be used as chip selects
or additional address lines. When defined as RAS
signals can be used as RAS
signals are can be tri-stated outputs with programmable
polarity.
for DRAM interface. These
, these
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Table 1-7 External Bus Control Signals (Continued)
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
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Signal
Name
CAS Output Tri-stated
RD
WR
TA
Type
Output Tri-stated
Output Tri-stated
Input Ignored Input
State during
Reset
Signal Description
Column Address Strobe—When the DSP is the bus
master, CAS
strobe the column address. Otherwise, if the bus
mastership enable (BME) bit in the DRAM control
register is cleared, the signal is tri-stated.
Read Enable—When the DSP is the bus master, RD
an active-low output that is asserted to read external
memory on the data bus (D0–D23). Otherwise, RD
stated.
Write Enable—When the DSP is the bus master, WR
an active-low output that is asserted to write external
memory on the data bus (D0–D23). Otherwise, the
signals are tri-stated.
Transfer Acknowledge—If the DSP56362 is the bus
master and there is no external bus activity, or the
DSP56362 is not the bus master, the TA
The TA
function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity)
may be added to the wait states inserted by the BCR by
keeping TA
deasserted at the start of a bus cycle, is asserted to
enable completion of the bus cycle, and is deasserted
before the next bus cycle. The current bus cycle
completes one clock period after TA
synchronous to CLKOUT. The number of wait states is
determined by the TA
(BCR), whichever is longer. The BCR can be used to set
the minimum number of wait states in external bus
cycles.
In order to use the TA
programmed to at least one wait state. A zero wait state
access cannot be extended by TA
otherwise improper operation may result. TA
synchronously or asynchronously, depending on the
setting of the TAS bit in the operating mode register
(OMR).
is an active-low output used by DRAM to
is
is tri-
is
input is ignored.
input is a data transfer acknowledge (DTACK)
deasserted. In typical operation, TA is
is asserted
input or by the bus control register
functionality, the BCR must be
deassertion,
can operate
TA
functionality may not be used while performing DRAM
type accesses, otherwise improper operation may result.
MOTOROLA DSP56362 Advance Information 1-7
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Table 1-7 External Bus Control Signals (Continued)
nc...
I
cale Semiconductor,
Frees
Signal
Name
BR Output
BG
Type
Input Ignored Input
State during
Reset
Output
(deasserted)
Signal Description
Bus Request—BR
stated. BR
mastership. BR
needs the bus. BR
independent of whether the DSP56362 is a bus master
or a bus slave. Bus “parking” allows BR
even though the DSP56362 is the bus master. (See the
description of bus “parking” in the BB
The bus request hold (BRH) bit in the BCR allows BR
be asserted under software control even though the DSP
does not need the bus. BR
bus arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR
only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR
deasserted and the arbitration is reset to the bus slave
state.
Bus Grant—BG
an external bus arbitration circuit when the DSP56362
becomes the next bus master. When BG
DSP56362 must wait until BB
bus mastership. When BG
is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that
requires more than one external bus cycle for execution.
The default mode of operation of this signal requires a
setup and hold time referred to CLKOUT. But CLKOUT
operation is not guaranteed from 100MHz and up, so the
asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus
arbitration is enabled by setting the ABE bit in the OMR
register.
is asserted when the DSP requests bus
is an active-low output, never tri-
is deasserted when the DSP no longer
may be asserted or deasserted
to be deasserted
signal description.)
to
is typically sent to an external
is
is
is an active-low input. BG is asserted by
is asserted, the
is deasserted before taking
is deasserted, bus mastership
1-8 DSP56362 Advance Information MOTOROLA
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Table 1-7 External Bus Control Signals (Continued)
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Signal
Name
BB
nc...
I
Type
Input/
Output
cale Semiconductor,
State during
Reset
Input
Signal Description
Bus Busy—BB
BB
indicates that the bus is active. Only after BB is
deasserted can the pending bus master become the bus
master (and then assert the signal again). The bus
master may keep BB
regardless of whether BR
is called “bus parking” and allows the current bus master
to reuse the bus without rearbitration until another device
requires the bus. The deassertion of BB
“active pull-up” method (i.e., BB
released and held high by an external pull-up resistor).
The default mode of operation of this signal requires a
setup and hold time referred to CLKOUT. But CLKOUT
operation is not guaranteed from 100MHz and up, so the
asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus
arbitration is enabled by setting the ABE bit in the OMR
register.
BB
requires an external pull-up resistor.
is a bidirectional active-low input/output.
asserted after ceasing bus activity
is asserted or deasserted. This
is done by an
is driven high and then
Frees
MOTOROLA DSP56362 Advance Information 1-9
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Signal/Connection Descriptions
Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET
is deasserted, these inputs are hardware interrupt request lines.
Table 1-8 Interrupt and Mode Control
nc...
I
cale Semiconductor,
Frees
Signal Name Type
MODA/IRQA
MODB/IRQB
Input Input
Input Input
State during
Reset
Signal Description
Mode Select A/External Interrupt Request A—
MODA/IRQA
internally synchronized to the DSP clock. MODA/IRQA
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into the OMR when the RESET
is deasserted. If IRQA
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQA
the wait state. If the processor is in the stop standby
state and the MODA/IRQA
processor will exit the stop state.
This input is 5 V tolerant.
Mode Select B/External Interrupt Request B—
MODB/IRQB
internally synchronized to the DSP clock. MODB/IRQB
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET
deasserted. If IRQB
CLKOUT, multiple processors can be re-synchronized
using the WAIT instruction and asserting IRQB
the wait state.
is an active-low Schmitt-trigger input,
signal
is asserted synchronous to
to exit
pin is pulled to GND, the
is an active-low Schmitt-trigger input,
signal is
is asserted synchronous to
to exit
This input is 5 V tolerant.
1-10 DSP56362 Advance Information MOTOROLA
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Table 1-8 Interrupt and Mode Control (Continued)
Signal/Connection Descriptions
Interrupt and Mode Control
Signal Name Type
MODC/IRQC Input Input
nc...
I
MODD/IRQD
Input Input
cale Semiconductor,
State during
Reset
Signal Description
Mode Select C/External Interrupt Request C—
MODC/IRQC
internally synchronized to the DSP clock. MODC/IRQC
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET
deasserted. If IRQC
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQC
the wait state.
This input is 5 V tolerant.
Mode Select D/External Interrupt Request D—
MODD/IRQD
internally synchronized to the DSP clock. MODD/IRQD
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET
deasserted. If IRQD
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQD
the wait state.
This input is 5 V tolerant.
is an active-low Schmitt-trigger input,
signal is
is asserted synchronous to
to exit
is an active-low Schmitt-trigger input,
signal is
is asserted synchronous to
to exit
Frees
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Signal/Connection Descriptions
Host Interface (HDI08)
Table 1-8 Interrupt and Mode Control (Continued)
Signal Name Type
RESET
nc...
I
Input Input
State during
Reset
Signal Description
Reset—RESET
When asserted, the chip is placed in the reset state
and the internal phase generator is reset. The Schmitttrigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. If RESET
is deasserted synchronous to CLKOUT, exact start-up
timing is guaranteed, allowing multiple processors to
start synchronously and operate together in “lockstep.” When the RESET
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET
must be asserted during power up. A stable EXTAL
signal must be supplied while RESET
asserted.
This input is 5 V tolerant.
is an active-low, Schmitt-trigger input.
signal is deasserted, the initial
signal
is being
HOST INTERFACE (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The
HDI08 supports a variety of standard buses and can be directly connected to a number of industry
standard microcomputers, microprocessors, DSPs, and DMA hardware.
Host Port Configuration
cale Semiconductor,
Signal functions associated with the HDI08 vary according to the interface operating mode as determined
by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on
page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on
page Section 6-1.) for descriptions of the other HDI08 configuration registers.
Frees
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Signal/Connection Descriptions
Table 1-9 Host Interface
Host Interface (HDI08)
Signal
Name
H0–H7
HAD0–
HAD7
nc...
I
PB0–PB7
HA0
HAS
cale Semiconductor,
/
HAS
Type
Input/
output
Input/
output
Input, output,
or
disconnected
Input
Input
State during
Reset
GPIO
disconnected
GPIO
disconnected
Signal Description
Host Data—When the HDI08 is programmed to
interface a nonmultiplexed host bus and the HI
function is selected, these signals are lines 0–7
of the bidirectional, tri-state data bus.
Host Address—When HDI08 is programmed to
interface a multiplexed host bus and the HI
function is selected, these signals are lines 0–7
of the address/data bidirectional, multiplexed, tristate bus.
Port B 0–7—When the HDI08 is configured as
GPIO, these signals are individually
programmable as input, output, or internally
disconnected.
The default state after reset for these signals is
GPIO disconnected.
This input is 5 V tolerant.
Host Address Input 0—When the HDI08 is
programmed to interface a nonmultiplexed host
bus and the HI function is selected, this signal is
line 0 of the host address input bus.
Host Address Strobe—When HDI08 is
programmed to interface a multiplexed host bus
and the HI function is selected, this signal is the
host address strobe (HAS) Schmitt-trigger input.
The polarity of the address strobe is
programmable, but is configured active-low
(HAS
) following reset.
Frees
Port B 8—When the HDI08 is configured as
GPIO, this signal is individually programmed as
Input, output,
PB8
MOTOROLA DSP56362 Advance Information 1-13
or
disconnected
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Host Interface (HDI08)
Table 1-9 Host Interface (Continued)
nc...
I
cale Semiconductor,
Frees
Signal
Name
HA1
HA8
PB9
HA2
HA9
PB10
Type
Input
Input
Input, output,
or
disconnected
Input
Input
Input, Output,
or
Disconnected
State during
Reset
GPIO
disconnected
GPIO
disconnected
Signal Description
Host Address Input 1—When the HDI08 is
programmed to interface a nonmultiplexed host
bus and the HI function is selected, this signal is
line 1 of the host address (HA1) input bus.
Host Address 8—When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 8 of the
host address (HA8) input bus.
Port B 9—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
Host Address Input 2—When the HDI08 is
programmed to interface a non-multiplexed host
bus and the HI function is selected, this signal is
line 2 of the host address (HA2) input bus.
Host Address 9—When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 9 of the
host address (HA9) input bus.
Port B 10—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
1-14 DSP56362 Advance Information MOTOROLA
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Table 1-9 Host Interface (Continued)
Signal/Connection Descriptions
Host Interface (HDI08)
nc...
I
cale Semiconductor,
Frees
Signal
Name
HRW
HRD
HRD
PB11
HDS
HDS
HWR
HWR
Type
Input
Input
/
Input, Output,
or
Disconnected
Input
/
Input
/
State during
Reset
GPIO
disconnected
GPIO
disconnected
Signal Description
Host Read/Write—When HDI08 is programmed
to interface a single-data-strobe host bus and the
HI function is selected, this signal is the Host
Read/Write
Host Read Data—When HDI08 is programmed
to interface a double-data-strobe host bus and
the HI function is selected, this signal is the host
read data strobe (HRD) Schmitt-trigger input. The
polarity of the data strobe is programmable, but is
configured as active-low (HRD
Port B 11—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
Host Data Strobe—When HDI08 is programmed
to interface a single-data-strobe host bus and the
HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is
configured as active-low (HDS
Host Write Data—When HDI08 is programmed
to interface a double-data-strobe host bus and
the HI function is selected, this signal is the host
write data strobe (HWR) Schmitt-trigger input.
The polarity of the data strobe is programmable,
but is configured as active-low (HWR
reset.
(HRW) input.
) after reset.
) following reset.
) following
Port B 12—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
Input, output,
PB12
MOTOROLA DSP56362 Advance Information 1-15
or
disconnected
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
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Signal/Connection Descriptions
Host Interface (HDI08)
Table 1-9 Host Interface (Continued)
nc...
I
cale Semiconductor,
Frees
Signal
Name
HCS
HA10
PB13
HOREQ
HOREQ
HTRQ
HTRQ
Type
Input
Input
Input, output,
or
disconnected
Output
/
Output
/
State during
Reset
GPIO
disconnected
GPIO
disconnected
Signal Description
Host Chip Select—When HDI08 is programmed
to interface a nonmultiplexed host bus and the HI
function is selected, this signal is the host chip
select (HCS) input. The polarity of the chip select
is programmable, but is configured active-low
(HCS
) after reset.
Host Address 10—When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 10 of the
host address (HA10) input bus.
Port B 13—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
Host Request—When HDI08 is programmed to
interface a single host request host bus and the
HI function is selected, this signal is the host
request (HOREQ) output. The polarity of the host
request is programmable, but is configured as
active-low (HOREQ
request may be programmed as a driven or
open-drain output.
Transmit Host Request—When HDI08 is
programmed to interface a double host request
host bus and the HI function is selected, this
signal is the transmit host request (HTRQ)
output. The polarity of the host request is
programmable, but is configured as active-low
(HTRQ
programmed as a driven or open-drain output.
) following reset. The host request may be
) following reset. The host
Port B 14—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
Input, output,
PB14
1-16 DSP56362 Advance Information MOTOROLA
or
disconnected
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
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Table 1-9 Host Interface (Continued)
Signal/Connection Descriptions
Host Interface (HDI08)
Signal
Name
HACK/
HACK
HRRQ
nc...
I
/
HRRQ
PB15
Type
Input
Output
Input, output,
or
disconnected
cale Semiconductor,
State during
Reset
GPIO
disconnected
Signal Description
Host Acknowledge—When HDI08 is
programmed to interface a single host request
host bus and the HI function is selected, this
signal is the host acknowledge (HACK) Schmitttrigger input. The polarity of the host
acknowledge is programmable, but is configured
as active-low (HACK
Receive Host Request—When HDI08 is
programmed to interface a double host request
host bus and the HI function is selected, this
signal is the receive host request (HRRQ) output.
The polarity of the host request is programmable,
but is configured as active-low (HRRQ
reset. The host request may be programmed as a
driven or open-drain output.
Port B 15—When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.
The default state after reset for this signal is
GPIO disconnected.
This input is 5 V tolerant.
) after reset.
) after
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cale Semiconductor,
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Signal/Connection Descriptions
Serial Host Interface
SERIAL HOST INTERFACE
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 1-10 Serial Host Interface Signals
State
Signal Name Signal Type
SCK
SCL
Input or
output
Input or
output
during
Reset
Tri-stated
Signal Description
SPI Serial Clock—The SCK signal is an output
when the SPI is configured as a master and a
Schmitt-trigger input when the SPI is configured as
a slave. When the SPI is configured as a master,
the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a
slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the
data transfer. The SCK signal is ignored by the SPI
if it is defined as a slave and the slave select (SS
signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where
data is stable. Edge polarity is determined by the
SPI transfer protocol.
2
I
C Serial Clock—SCL carries the clock for I2C bus
transactions in the I
trigger input when configured as a slave and an
open-drain output when configured as a master.
SCL should be connected to V
resistor.
This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.
This input is 5 V tolerant.
2
C mode. SCL is a Schmitt-
through a pull-up
CC
)
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Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type
Input or
nc...
I
MISO
SDA
output
Input or
open-drain
output
cale Semiconductor,
State
during
Reset
Tri-stated
Signal/Connection Descriptions
Serial Host Interface
Signal Description
SPI Master-In-Slave-Out—When the SPI is
configured as a master, MISO is the master data
input line. The MISO signal is used in conjunction
with the MOSI signal for transmitting and receiving
serial data. This signal is a Schmitt-trigger input
when configured for the SPI Master mode, an
output when configured for the SPI Slave mode,
and tri-stated if configured for the SPI Slave mode
when SS
is not required for SPI operation.
2
I
C Data and Acknowledge—In I2C mode, SDA is
a Schmitt-trigger input when receiving and an opendrain output when transmitting. SDA should be
connected to V
carries the data for I
SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when
SCL is low. When the bus is free, SDA is high. The
SDA line is only allowed to change during the time
SCL is high in the case of start and stop events. A
high-to-low transition of the SDA line while SCL is
high is a unique situation, and is defined as the start
event. A low-to-high transition of SDA while SCL is
high is a unique situation defined as the stop event.
This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.
This input is 5 V tolerant.
is deasserted. An external pull-up resistor
through a pull-up resistor. SDA
CC
2
C transactions. The data in
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Signal/Connection Descriptions
Serial Host Interface
Table 1-10 Serial Host Interface Signals (Continued)
State
Signal Name Signal Type
MOSI
nc...
I
HA0
Input or
output
Input
during
Reset
Tri-stated
Signal Description
SPI Master-Out-Slave-In—When the SPI is
configured as a master, MOSI is the master data
output line. The MOSI signal is used in conjunction
with the MISO signal for transmitting and receiving
serial data. MOSI is the slave data input line when
the SPI is configured as a slave. This signal is a
Schmitt-trigger input when configured for the SPI
Slave mode.
2
I
C Slave Address 0—This signal uses a Schmitt-
trigger input when configured for the I
When configured for I
signal is used to form the slave device address.
HA0 is ignored when configured for the I
mode.
2
C slave mode, the HA0
2
C mode.
2
C master
cale Semiconductor,
Frees
SS
HA2
Input
Input
Tri-stated
This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.
This input is 5 V tolerant.
SPI Slave Select—This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode,
this signal is used to enable the SPI slave for
transfer. When configured for the SPI master mode,
this signal should be kept deasserted (pulled high).
If it is asserted while configured as SPI master, a
bus error condition is flagged. If SS
the SHI ignores SCK clocks and keeps the MISO
output signal in the high-impedance state.
2
I
C Slave Address 2—This signal uses a Schmitt-
trigger input when configured for the I
When configured for the I
signal is used to form the slave device address.
HA2 is ignored in the I
This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.
2
C Slave mode, the HA2
2
C master mode.
is deasserted,
2
C mode.
This input is 5 V tolerant.
1-20 DSP56362 Advance Information MOTOROLA
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Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type
State
during
Reset
Signal/Connection Descriptions
Serial Host Interface
Signal Description
Host Request—This signal is an active low
Schmitt-trigger input when configured for the
master mode but an active low output when
configured for the slave mode.
When configured for the slave mode, HREQ
asserted to indicate that the SHI is ready for the
next data word transfer and deasserted at the first
clock pulse of the new data word transfer. When
configured for the master mode, HREQ
nc...
I
HREQ
Input or
Output
Tri-stated
When asserted by the external slave device, it will
trigger the start of the data word transfer by the
master. After finishing the data word transfer, the
master will await the next assertion of HREQ
proceed to the next transfer.
This signal is tri-stated during hardware, software,
personal reset, or when the HREQ1–HREQ0 bits in
the HCSR are cleared. There is no need for
external pull-up in this state.
This input is 5 V tolerant.
cale Semiconductor,
is
is an input.
to
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Signal/Connection Descriptions
Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-11 Enhanced Serial Audio Interface Signals
Signal
Name
HCKR
nc...
I
PC2
HCKT
cale Semiconductor,
PC5
Signal Type
Input or output
Input, output,
or
disconnected
Input or output
Input, output,
or
disconnected
State during
Reset
GPIO
disconnected
GPIO
disconnected
Signal Description
High Frequency Clock for Receiver—When
programmed as an input, this signal provides a high
frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed
as an output, this signal can serve as a highfrequency sample clock (e.g., for external digital to
analog converters [DACs]) or as an additional
system clock.
Port C 2—When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
High Frequency Clock for Transmitter—When
programmed as an input, this signal provides a high
frequency clock source for the ESAI transmitter as
an alternate to the DSP core clock. When
programmed as an output, this signal can serve as a
high frequency sample clock (e.g., for external
DACs) or as an additional system clock.
Port C 5—When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.
The default state after reset is GPIO disconnected.
Frees
This input is 5 V tolerant.
1-22 DSP56362 Advance Information MOTOROLA
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