Freescale DSP56321 Technical Data
Freescale Semiconductor
Technical Data
DSP56321
24-Bit Digital Signal Processor
DSP56321
Rev. 11, 2/2005
3
SCI
Bootstrap
Internal
Switch
Generator
EXTAL
XTAL
RESET
PINIT /NMI
Address
Generation
Six Channel
DMA Unit
ROM
Data
Bus
Clock
Unit
Tr i pl e
Timer
PLL
HI08
PIO_EB
Program
Interrupt
Controller
616
6
ESSI
Peripheral
Expansion Area
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
EFCOP
Program
RAM
32 K × 24 bits
or
31 K × 24 bits
and
Instruction
Cache
1024 × 24 bits
DSP56300
Program
Address
Generator
Memory Expansion Area
X Data
RAM
80 K × 24 bits
YA B
PM_EB
XAB
PA B
DAB
XM_EB
24-Bit
Core
DDB
YDB
XDB
PDB
GDB
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Y Data
RAM
80 K × 24 bits
YM_EB
External
Address
Switch
External
Interface
I - Cache
Control
External
Pow er
Management
JTAG
OnCE™
Bus
Bus
and
Data
Bus
Switch
18
Address
10
Control
24
Data
5
DE
The DSP56321 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolutionbased algorithms.
What’s New?
Rev. 11 includes the following
changes:
• Adds lead-free packaging and
part numbers.
Figure 1. DSP56321 Block Diagram
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and
home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 codecompatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller
(see Figure 1).
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550
MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and
independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall
enhanced performance and signal quality with no impact on channel throughput or total channel support. This
device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
© Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
Table of Contents
Data Sheet Conventions .......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications ............................................................................................................................................. iv
Product Documentation .......................................................................................................................................v
Chapter 1 Signals/Connections
1.1 Power ................................................................................................................................................................1-3
1.2 Ground ..............................................................................................................................................................1-3
1.3 Clock .................................................................................................................................................................1-3
1.4 External Memory Expansion Port (Port A) ......................................................................................................1-4
1.5 Interrupt and Mode Control ..............................................................................................................................1-6
1.6 Host Interface (HI08) ........................................................................................................................................1-7
1.7 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10
1.8 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11
1.9 Serial Communication Interface (SCI) ...........................................................................................................1-12
1.10 Timers .............................................................................................................................................................1-13
1.11 JTAG and OnCE Interface ..............................................................................................................................1-14
Chapter 2 Specifications
2.1 Maximum Ratings.............................................................................................................................................2-1
2.2 Thermal Characteristics ....................................................................................................................................2-2
2.3 DC Electrical Characteristics............................................................................................................................2-2
2.4 AC Electrical Characteristics............................................................................................................................2-3
Chapter 3 Packaging
3.1 Package Description .........................................................................................................................................3-2
3.2 MAP-BGA Package Mechanical Drawing .....................................................................................................3-10
Chapter 4 Design Considerations
4.1 Thermal Design Considerations........................................................................................................................4-1
4.2 Electrical Design Considerations......................................................................................................................4-2
4.3 Power Consumption Considerations.................................................................................................................4-3
4.4 Input (EXTAL) Jitter Requirements .................................................................................................................4-4
Appendix A Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples: Signal/Symbol Logic State Signal State Voltage
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Indicates a signal that is active when pulled low (For example, the RESET pin is active when
low.)
PIN
PIN
PIN
PIN
True Asserted
False Deasserted
True Asserted
False Deasserted
VIL/V
VIH/V
VIH/V
VIL/V
OL
OH
OH
OL
DSP56321 Technical Data, Rev. 11
ii Freescale Semiconductor
Features
Tab l e 1 lists the features of the DSP56321 device.
Table 1. DSP56321 Features
Feature Description
• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering
applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
High-Performance
DSP56300 Core
Enhanced Filter
Coprocessor (EFCOP)
Internal Peripherals
• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 275 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
iii
Table 1 . DSP56321 Features (Continued)
:
Feature Description
•192 × 24-bit bootstrap ROM
•192 K × 24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
Internal Memories
External Memory
Expansion
Power Dissipation
Packaging
Program RAM
Size
32 K × 24-bit 0 80 K × 24-bit 80 K × 24-bit disabled 0 0 0
31 K × 24-bit 1024 × 24-bit 80 K × 24-bit 80 K × 24-bit enabled 0 0 0
40 K × 24-bit 0 76 K × 24-bit 76 K × 24-bit disabled 0 0 1
39 K × 24-bit 1024 × 24-bit 76 K × 24-bit 76 K × 24-bit enabled 0 0 1
48 K × 24-bit 0 72 K × 24-bit 72 K × 24-bit disabled 0 1 0
47 K × 24-bit 1024 × 24-bit 72 K × 24-bit 72 K × 24-bit enabled 0 1 0
64 K × 24-bit 0 64 K × 24-bit 64 K × 24-bit disabled 0 1 1
63 K × 24-bit 1024 × 24-bit 64 K × 24-bit 64 K × 24-bit enabled 0 1 1
72 K × 24-bit 0 60 K × 24-bit 60 K × 24-bit disabled 1 0 0
71 K × 24-bit 1024 × 24-bit 60 K × 24-bit 60 K × 24-bit enabled 1 0 0
80 K × 24-bit 0 56 K × 24-bit 56 K × 24-bit disabled 1 0 1
79 K × 24-bit 1024
96 K × 24-bit 0 48 K × 24-bit 48 K × 24-bit disabled 1 1 0
95 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled 1 1 0
112 K × 24-bit 0 40 K × 24-bit 40 K × 24-bit disabled 1 1 1
111 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled 1 1 1
*Includes 12 K × 24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)
• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent)
• Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Instruction
Cache Size
× 24-bit 56 K × 24-bit 56 K × 24-bit enabled 1 0 1
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
MSW2 MSW1 MSW0
Target Applications
DSP56321 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• Security encryption systems
• Home entertainment systems
• DSP resource boards
• High-speed modem banks
• IP telephony
DSP56321 Technical Data, Rev. 11
iv Freescale Semiconductor
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56321 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2. DSP56321 Documentation
Name Description Order Number
DSP56321
Reference Manual
DSP56300 Family
Manual
Application Notes Documents describing specific applications or optimized device operation
Detailed functional description of the DSP56321 memory configuration,
operation, and register programming
Detailed description of the DSP56300 family processor core and instruction set DSP56300FM
including code examples
DSP56321RM
See the DSP56321 product website
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
v
DSP56321 Technical Data, Rev. 11
vi Freescale Semiconductor
Signals/Connections 1
The DSP56321 input and output signals are organized into functional groups as shown in Tab l e 1- 1 . Figure 1-1
diagrams the DSP56321 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Table 1-1. DSP56321 Functional Signal Groupings
Functional Group
Power (VCC) 20
Ground (GND) 66
Clock 2
Address bus
Data bus 24
Bus control 10
Interrupt and mode control 6
Host interface (HI08) Port B
Enhanced synchronous serial interface (ESSI) Ports C and D
Serial communication interface (SCI) Port E
Timer 3
OnCE/JTAG Port 6
Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals.
5. Eight signal lines are not connected internally. These are designated as no connect (NC) in the package description (see
Chapter 3). There are also two reserved lines.
Port A
1
2
3
4
Number of
Signals
18
16
12
3
Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal
functionality. See the DSP56321 Reference Manual for details on these configuration registers.
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 1-1
Signals/Connections
V
CCQL
V
CCQH
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
GND
EXTAL
XTAL
5
3
3
4
2
2
66
DSP56321
Power Inputs:
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
Grounds:
Ground plane
Clock
Interrupt/
Mode Control
Host
Interface
(HI08) Port
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)
During Reset
MODA
MODB
MODC
MODD
RESET
PINIT
Non-Multiplexed
Bus
8
H[0–7]
HA0
HA1
1
HA2
HCS/
HCS
Single DS
HRW
HDS
/HDS
Single HR
HREQ
/HREQ
HACK
/HACK
3
SC0[0–2]
SCK0
2
SRD0
STD0
After Reset
IRQA
IRQB
IRQC
IRQD
RESET
NMI
Multiplexed
Bus
HAD[0–7]
HAS
/HAS
HA8
HA9
HA10
Double DS
HRD
/HRD
HWR
/HWR
Double HR
HTRQ
/HTRQ
HRRQ
/HRRQ
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Port E GPIO
PE0
PE1
PE2
Timer GPIO
TIO0
TIO1
TIO2
A[0–17]
D[0–23]
AA[0–3]
RD
WR
TA
BR
BG
BB
18
24
4
Port A
External
Address Bus
External
Data Bus
External
Bus
Control
Synchronous Serial
Enhanced
Interface Port 1
(ESSI1)
Serial
Communications
Interface (SCI) Port
Timers
OnCE/
JTAG Port
3
SC1[0–2]
SCK1
2
SRD1
STD1
RXD
2
TXD
SCLK
3
TIO0
TIO1
TIO2
TCK
TDI
TDO
TMS
TRST
DE
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (DS), and single or
double host request (HR) configurations. Since each of these modes is configured independently, any combination of
these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS
/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
Figure 1-1. Signals Identified by Functional Group
DSP56321 Technical Data, Rev. 11
1-2 Freescale Semiconductor
1.1 Power
Table 1-2. Power Inputs
Power Name Description
V
Quiet Core (Low) Power—An isolated power for the core processing and clock logic. This input must be isolated
CCQL
V
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
CCQH
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
V
CCA
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
V
CCD
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
V
CCC
V
CCH
V
CCS
Note: The user must provide adequate external decoupling capacitors for all power connections.
externally from all other chip power inputs.
power inputs
to all other chip power inputs,
other chip power inputs,
chip power inputs,
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs,
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs,
except
, except
V
CCQL
V
CCQL
except
.
.
except
V
CCQL
except
V
CCQL
.
V
.
CCQL
except
.
V
.
CCQL
Power
1.2 Ground
Table 1-3. Grounds
Name Description
GND Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
1.3 Clock
Table 1-4. Clock Signals
Signal Name Type
EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input
XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external
State During
Reset
Signal Description
to an external crystal or an external clock.
crystal. If an external clock is used, leave XTAL unconnected.
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 1-3
Signals/Connections
1.4 External Memory Expansion Port (Port A)
Note: When the DSP56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals: A[0–17], D[0–23], AA[0–3], RD, WR, BB.
1.4.1 External Address Bus
Table 1-5. External Address Bus Signals
State During
Signal Name Type
A[0–17] Output Tri-stated Address Bus—When the DSP is the bus master, A[0–17] are active-high
1.4.2 External Data Bus
Reset, Stop,
or Wait
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
Table 1-6. External Data Bus Signals
Signal Description
Signal Name Type
D[0–23] Input/ Output Ignored Input Last state:
State During
Reset
State During
Stop or Wait
Input
: Ignored
Output
:
Last value
Signal Description
Data Bus—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data
memory accesses. Otherwise, D[0–23] drivers are tristated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tristated.
1.4.3 External Bus Control
Table 1-7. External Bus Control Signals
State During
Signal Name Type
AA[0–3] Output Tri-stated Address Attribute—When defined as AA, these signals can be used as chip
RD
WR
Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that
Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output
Reset, Stop, or
Wait
Signal Description
selects or additional address lines. The default use defines a priority scheme
under which only one AA signal can be asserted at a time. Setting the AA priority
disable (APD) bit (Bit 14) of the Operating Mode Register, the priority
mechanism is disabled and the lines can be used together as four external lines
that can be decoded externally into 16 chip select signals.
is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD
tri-stated.
that is asserted to write external memory on the data bus (D[0–23]). Otherwise,
the signals are tri-stated.
is
DSP56321 Technical Data, Rev. 11
1-4 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 1-7. External Bus Control Signals (Continued)
State During
Signal Name Type
TA Input Ignored Input Transfer Acknowledge—If the DSP56321 is the bus master and there is no
Reset, Stop, or
Wait
Signal Description
external bus activity, or the DSP56321 is not the bus master, the TA
ignored. The TA
extend an external bus cycle indefinitely. Any number of wait states (1,
2. . .infinity) can be added to the wait states inserted by the bus control register
(BCR) by keeping TA
start of a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA
states is determined by the TA
BCR can be used to set the minimum number of wait states in external bus
cycles.
input is a data transfer acknowledge (DTACK) function that can
deasserted. In typical operation, TA is deasserted at the
is asserted synchronous to CLKOUT. The number of wait
input or by the BCR, whichever is longer. The
input is
BR
BG
BB
To use the TA
state. A zero wait state access cannot be extended by TA
otherwise, improper operation may result.
Output Reset: Output
(deasserted)
State during
Stop/Wait
depends on BRH
bit setting:
• BRH = 0: Output
(deasserted)
• BRH = 1:
Maintains last
state (that is, if
asserted, remains
asserted)
Input Ignored Input Bus Grant—Asserted by an external bus arbitration circuit when the DSP56321
Input/ Output Ignored Input Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
Bus Request—Asserted when the DSP requests bus mastership. BR
deasserted when the DSP no longer needs the bus. BR
deasserted independently of whether the DSP56321 is a bus master or a bus
slave. Bus “parking” allows BR
the bus master. (See the description of bus “parking” in the BB
description.) The bus request hold (BRH) bit in the BCR allows BR
asserted under software control even though the DSP does not need the bus.
BR
is typically sent to an external bus arbitrator that controls the priority,
parking, and tenure of each master on the same external bus. BR
only by DSP requests for the external bus, never for the internal bus. During
hardware reset, BR
state.
becomes the next bus master. When BG
until BB
bus mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
To ensure proper operation, the user must set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set,
BG
and BB are synchronized internally. This adds a required delay between the
deassertion of an initial BG
pending bus master become the bus master (and then assert the signal again).
The bus master may keep BB
whether BR
current bus master to reuse the bus without rearbitration until another device
requires the bus. BB
driven high and then released and held high by an external pull-up resistor).
functionality, the BCR must be programmed to at least one wait
deassertion;
is
may be asserted or
to be deasserted even though the DSP56321 is
signal
to be
is affected
is deasserted and the arbitration is reset to the bus slave
is asserted, the DSP56321 must wait
is deasserted before taking bus mastership. When BG is deasserted,
input and the assertion of a subsequent BG input.
asserted after ceasing bus activity regardless of
is asserted or deasserted. Called “bus parking,” this allows the
is deasserted by an “active pull-up” method (that is, BB is
Notes: 1. See BG
2. BB
for additional information.
requires an external pull-up resistor.
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 1-5
Signals/Connections
1.5 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET
is deasserted, these inputs are hardware interrupt request lines.
Table 1-8. Interrupt and Mode Control
Signal Name Type
MODA
IRQA
MODB
IRQB
MODC
IRQC
MODD
Input
Input
Input
Input
Input
Input
Input
State During
Reset
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Signal Description
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request A—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT
standby state and IRQA
state.
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
signal is deasserted.
External Interrupt Request B—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQB
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
External Interrupt Request C—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQC
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET
is asserted, the processor exits the WAIT state.
signal is deasserted.
is asserted, the processor exits the WAIT state.
signal is deasserted.
is asserted, the processor exits the STOP or WAIT
IRQD
RESET
PINIT
NMI
Input
Input Schmitt-trigger
Input
Input
Input
Schmitt-trigger
Input
External Interrupt Request D—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQD
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET
powerup.
PLL Initial—During assertion of RESET, the value of PINIT determines
whether the DPLL is enabled or disabled.
Nonmaskable Interrupt—After RESET
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI
is asserted, the processor exits the WAIT state.
signal is
signal must be asserted after
deassertion and during normal
request.
DSP56321 Technical Data, Rev. 11
1-6 Freescale Semiconductor
Host Interface (HI08)
1.6 Host Interface (HI08)
The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety
of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs,
and DMA hardware.
1.6.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written by another
asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the
Host port). The considerations for proper operation are discussed in Tab le 1- 9.
Table 1-9. Host Port Usage Considerations
Action Description
Asynchronous read of receive byte
registers
Asynchronous write to transmit byte
registers
Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when the Host
When reading the receive byte registers, Receive register High (RXH), Receive register Middle
(RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll
the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data
in the receive byte registers is valid.
The host interface programmer should not write to the transmit byte registers, Transmit register High
(TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register
Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees
that the transmit byte registers transfer valid data to the Host Receive (HRX) register.
Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a
stable vector.
1.6.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits
in the HI08 Port Control Register.
Table 1-10. Host Interface
Signal Name Type
H[0–7]
Input/Output
State During
Ignored Input Host Data—When the HI08 is programmed to interface with a non-multiplexed
Reset
1,2
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional Data bus.
Signal Description
HAD[0–7]
PB[0–7]
Freescale Semiconductor 1-7
Input/Output
Input or Output
Host Address—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional multiplexed Address/Data bus.
Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port
Control Register, these signals are individually programmed as inputs or outputs
through the HI08 Data Direction Register.
DSP56321 Technical Data, Rev. 11
Signals/Connections
Table 1-10. Host Interface (Continued)
Signal Name Type
HA0
HAS
/HAS
PB8
HA1
HA8
PB9
HA2
Input or Output
Input or Output
Input
Input
Input
Input
Input
State During
Ignored Input Host Address Input 0—When the HI08 is programmed to interface with a
Ignored Input Host Address Input 1—When the HI08 is programmed to interface with a
Ignored Input Host Address Input 2—When the HI08 is programmed to interface with a
Reset
1,2
nonmultiplexed host bus and the HI function is selected, this signal is line 0 of
the host address input bus.
Host Address Strobe—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is the host
address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is
programmable but is configured active-low (HAS
Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
nonmultiplexed host bus and the HI function is selected, this signal is line 1 of
the host address (HA1) input bus.
Host Address 8—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 8 of the host address
(HA8) input bus.
Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
nonmultiplexed host bus and the HI function is selected, this signal is line 2 of
the host address (HA2) input bus.
Signal Description
) following reset.
HA9
PB10
HCS
HA10
PB13
HRW
HRD
PB11
/HCS
/HRD
Input
Input or Output
Input
Input
Input or Output
Input
Input
Input or Output
Host Address 9—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 9 of the host address
(HA9) input bus.
Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Ignored Input Host Chip Select—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is the host
chip select (HCS) input. The polarity of the chip select is programmable but is
configured active-low (HCS
Host Address 10—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line 10 of the
host address (HA10) input bus.
Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Ignored Input Host Read/Write—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the Host
Read/Write
Host Read Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the HRD
strobe Schmitt-trigger input. The polarity of the data strobe is programmable but
is configured as active-low (HRD
Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
(HRW) input.
) after reset.
) after reset.
DSP56321 Technical Data, Rev. 11
1-8 Freescale Semiconductor
Table 1-10. Host Interface (Continued)
Host Interface (HI08)
Signal Name Type
HDS/HDS
/HWR
HWR
PB12
HREQ
HTRQ
PB14
HACK
/HREQ
/HTRQ
/HACK
Input or Output
Output
Output
Input or Output
Input
Input
Input
State During
Ignored Input Host Data Strobe—When the HI08 is programmed to interface with a single-
Ignored Input Host Request—When the HI08 is programmed to interface with a single host
Ignored Input Host Acknowledge—When the HI08 is programmed to interface with a single
Reset
1,2
data-strobe host bus and the HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HDS
Host Write Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the host write
data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HWR
Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
request host bus and the HI function is selected, this signal is the host request
(HREQ) output. The polarity of the host request is programmable but is
configured as active-low (HREQ
programmed as a driven or open-drain output.
Transmit Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
transmit host request (HTRQ) output. The polarity of the host request is
programmable but is configured as active-low (HTRQ
request may be programmed as a driven or open-drain output.
Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
host request host bus and the HI function is selected, this signal is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable but is configured as active-low (HACK
reset.
Signal Description
) following reset.
) following reset.
) following reset. The host request may be
) following reset. The host
) after
/HRRQ
HRRQ
PB15
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Output
Input or Output
Receive Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
receive host request (HRRQ) output. The polarity of the host request is
programmable but is configured as active-low (HRRQ
request may be programmed as a driven or open-drain output.
Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
DSP56321 Technical Data, Rev. 11
) after reset. The host
Freescale Semiconductor 1-9
Signals/Connections
1.7 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication
with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
DSP56321 Technical Data, Rev. 11
1-10 Freescale Semiconductor
Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-11. Enhanced Synchronous Serial Interface 0 (Continued)
Signal Name Type
STD0
PC5
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Output
Input or Output
State During
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
Reset
1,2
STD0 is an output when data is transmitted.
Port C 5—The default configuration following reset is GPIO input PC5. When
configured as PC5, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal STD0 through the Port
C Control Register.
Signal Description
1.8 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-12. Enhanced Serial Synchronous Interface 1
Signal Name Type
SC10
PD0
SC11
Input or Output
Input or Output
Input/Output
State During
Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive
Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame
Reset
1,2
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO input PD0. When
configured as PD0, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC10 through the Port
D Control Register.
sync I/O. For synchronous mode, this signal is used either for Transmitter 2
output or for Serial I/O Flag 1.
Signal Description
PD1
SC12
PD2
Input or Output
Input/Output
Input or Output
Port D 1—The default configuration following reset is GPIO input PD1. When
configured as PD1, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC11 through the Port
D Control Register.
Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port D 2—The default configuration following reset is GPIO input PD2. When
configured as PD2, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC12 through the Port
D Control Register.
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 1-11
Signals/Connections
Table 1-12. Enhanced Serial Synchronous Interface 1 (Continued)
Signal Name Type
SCK1
PD3
SRD1
PD4
STD1
PD5
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Input/Output
Input or Output
Input
Input or Output
Output
Input or Output
State During
Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a
Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
Reset
1,2
clock input or output used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port D 3—The default configuration following reset is GPIO input PD3. When
configured as PD3, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SCK1 through the Port
D Control Register.
Receive Shift Register. SRD1 is an input when data is being received.
Port D 4—The default configuration following reset is GPIO input PD4. When
configured as PD4, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SRD1 through the
Port D Control Register.
STD1 is an output when data is being transmitted.
Port D 5—The default configuration following reset is GPIO input PD5. When
configured as PD5, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal STD1 through the Port
D Control Register.
Signal Description
1.9 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
Table 1-13. Serial Communication Interface
Signal Name Type
RXD
PE0
TXD
PE1
Input
Input or Output
Output
Input or Output
State During
Ignored Input Serial Receive Data—Receives byte-oriented serial data and transfers it to the
Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Reset
1,2
SCI Receive Shift Register.
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
Signal Description
DSP56321 Technical Data, Rev. 11
1-12 Freescale Semiconductor
Table 1-13. Serial Communication Interface (Continued)
Timers
Signal Name Type
SCLK
PE2
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
Input/Output
Input or Output
State During
Ignored Input Serial Clock—Provides the input or output clock used by the transmitter and/or
Reset
1,2
the receiver.
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Signal Description
1.10 Timers
The DSP56321 has three identical and independent timers. Each timer can use internal or external clocking and can
either interrupt the DSP56321 after a specified number of events (clocks) or signal an external device after
counting a specific number of internal events.
Table 1-14. Triple Timer Signals
Signal Name Type
State During
1,2
Reset
Signal Description
TIO0 Input or Output Ignored Input Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input. When
Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. TIO0 can be changed to output or
configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).
TIO1 Input or Output Ignored Input Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an
TIO2 Input or Output Ignored Input Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
external event counter or in measurement mode, TIO1 is used as input. When
Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. TIO1 can be changed to output or
configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).
external event counter or in measurement mode, TIO2 is used as input. When
Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. TIO2 can be changed to output or
configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 1-13
Signals/Connections
1.11 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56321 support circuit-board test strategies based on the IEEE®
Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to
interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or
on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming
models, see the chapter on debugging support in the DSP56300 Family Manual.
Table 1-15. JTAG/OnCE Interface
Signal
Name
TCK Input Input Test Clo ck—A test clock input signal to synchronize the JTAG test logic.
TDI Input Input Test Data Input—A test data serial input signal for test instructions and data.
TDO Output Tri-stated Test Data Output—A test data serial output signal for test instructions and
TMS Input Input Test Mode Select—Sequences the test controller’s state machine. TMS is
TRST
DE
Type
Input Input Test Res e t—Initializes the test controller asynchronously. TRST has an
Input/ Output Input Debug Event—As an input, initiates Debug mode from an external command
State During
Reset
Signal Description
TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.
data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
sampled on the rising edge of TCK and has an internal pull-up resistor.
internal pull-up resistor. TRST
(see EB610/D for details).
controller, and, as an open-drain output, acknowledges that the chip has
entered Debug mode. As an input, DE
executing the current instruction, save the instruction pipeline information,
enter Debug mode, and wait for commands to be entered from the debug
serial input line. This signal is asserted as an output for three clock cycles
when the chip enters Debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE
This signal is not a standard part of the JTAG TAP controller. The signal
connects directly to the OnCE module to initiate debug mode directly or to
provide a direct external indication that the chip has entered Debug mode. All
other interface with the OnCE module must occur through the JTAG port.
must be asserted during and after power-up
causes the DSP56300 core to finish
has an internal pull-up resistor.
DSP56321 Technical Data, Rev. 11
1-14 Freescale Semiconductor
Specifications 2
The DSP56321 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and
outputs.
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (for example, either GND or V
CC
).
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of
another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum specification is calculated using the worst
case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never
occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum
represents a condition that can never exist.
Table 2-1. Absolute Maximum Ratings
1
Rating
Supply Voltage
Input/Output Supply Voltage
All input voltages V
Current drain per pin excluding V
Operating temperature range T
Storage temperature T
Notes: 1. GND = 0 V, V
3
3
and GND I 10 mA
CC
= 1.6 V ± 0.1 V, V
CCQL
CCQL
voltage.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the maximum rating may affect device reliability or cause permanent damage to the device.
3. Power-up sequence: During power-up, and throughout the DSP56321 operation, V
equal to V
CCQH
Symbol Value
V
V
CCQH
= 3.3 V ± 0.3 V, TJ = –40°C to +100°C, CL = 50 pF
CCQL
IN
J
STG
GND – 0.3 to V
1, 2
–0.1 to 2.25 V
–0.3 to 4.35 V
+ 0.3 V
CCQH
–40 to +100 °C
–55 to +150 °C
voltage must always be higher or
CCQH
Unit
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 2-1
Specifications
2.2 Thermal Characteristics
Table 2-2. Thermal Characteristics
Thermal Resistance Characteristic Symbol
Junction-to-ambient, natural convection, single-layer board (1s)
Junction-to-ambient, natural convection, four-layer board (2s2p)
Junction-to-ambient, @200 ft/min air flow, single-layer board (1s)
Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)
Junction-to-board
Junction-to-case thermal resistance
4
5
1,2
1,3
1,3
1,3
R
R
R
R
θJMA
θJMA
θJMA
R
R
θJA
θJB
θJC
MAP-BGA
Value
44 °C/W
25 °C/W
35 °C/W
22 °C/W
13 °C/W
7 °C/W
Unit
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
2.3 DC Electrical Characteristics
Table 2-3. DC Electrical Characteristics
7
Characteristics Symbol Min Typ Max Unit
Supply voltage1:
•Core (V
•I/O (V
Input high voltage
• D[0–23], BG
• MOD/IRQ2 RESET, PINIT/NMI and all
JTAG/ESSI/SCI/Timer/HI08 pins
•EXTAL
Input low voltage
• D[0–23], BG
• All JTAG/ESSI/SCI/Timer/HI08 pins
•EXTAL
Input leakage current I
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
Output high voltage
•TTL (I
•CMOS (IOH = –10 µA)
Output low voltage
•TTL (I
•CMOS (IOL = 10 µA)
)
CCQL
, V
, V
, V
CCQH
CCA
CCD
CCC
, V
, BB, TA
9
, BB, TA, MOD/IRQ2, RESET, PINIT
9
8
= –0.4 mA)
OH
= 3.0 mA)
OL
6
6
8
6
6
CCH
, and V
CCS
)
1.5
3.0
V
IH
V
IHP
V
IHX
V
IL
V
ILP
V
ILX
IN
I
TSI
V
OH
2.0
2.0
0.8 × V
CCQH
–0.3
–0.3
–0.3
–10 — 10 µA
–10 — 10 µA
2.4
V
– 0.01
CCQH
V
OL
—
—
1.6
3.3
—
—
—
—
—
—
—
—
—
—
1.7
3.6
V
CCQH
V
CCQH
V
CCQH
0.8
0.8
0.2 × V
—
—
0.4
0.01
+ 0.3
+ 0.3
CCQH
V
V
V
V
V
V
V
V
V
V
V
V
DSP56321 Technical Data, Rev. 11
2-2 Freescale Semiconductor
AC Electrical Characteristics
Table 2-3. DC Electrical Characteristics
Characteristics Symbol Min Typ Max Unit
Internal supply current:
• In Normal mode
— at 200 MHz
— at 220 MHz
— at 240 MHz
— at 275 MHz
• In Wait mode
• In Stop mode
Input capacitance
Notes: 1. Power-up sequence: During power-up, and throughout the DSP56321 operation, V
2. Refers to MODA/IRQA
3. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all
4. To obtain these results, all inputs must be terminated (that is, not allowed to float).
5. To obtain these results, all inputs not disconnected at Stop mode must be terminated (that is, not allowed to float), and the
6. Periodically sampled and not 100 percent tested.
7. V
8. This characteristic does not apply to XTAL.
9. Driving EXTAL to the low V
3
4
5
6
equal to V
inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see
Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark.
This reflects typical DSP applications.
DPLL and on-chip crystal oscillator must be disabled.
CCQH
power consumption, the minimum V
0.9 × V
voltage.
CCQL
= 3.3 V ± 0.3 V, V
and the maximum V
CCQH
, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
CQLC
or the high V
IHX
ILX
IHX
should be no higher than 0.1 × V
value may cause additional power consumption (DC current). To minimize
ILX
should be no lower than
I
I
CCW
I
CCS
C
CCI
—
—
—
—
—
—
IN
— — 10 pF
.
CCQH
7
190
200
210
235
25
15
voltage must always be higher or
CCQH
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
2.4 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V
and a V
and 9 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50 percent point of the respective input signal’s transition. DSP56321 output levels
are measured with the production test machine V
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 16
2.4.1 Internal Clocks
Internal operating frequency
• With DPLL disabled
• With DPLL enabled
Internal clock cycle time
• With DPLL disabled
• With DPLL enabled
Internal clock high period
• With DPLL disabled
• With DPLL enabled
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Notes 7
IH
and VOH reference levels set at 0.4 V and 2.4 V, respectively.
OL
MHz and rated speed with the DPLL enabled.
Table 2-4. Internal Clocks
Expression
Characteristics Symbol
Min Typ Max
f
T
C
T
H
—
—
—
—
—
0.49 × T
Ef/2
(Ef × MF)/(PDF × DF)
2 × ET
ET
C
C
—
ETC × PDF × DF/MF
C
—
—
—
—
—
0.51 × T
C
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 2-3
Specifications
S
Table 2-4. Internal Clocks (Continued)
Expression
Characteristics Symbol
Min Typ Max
Internal clock low period
• With DPLL disabled
• With DPLL enabled
Note: Ef = External frequency; MF = Multiplication Factor = MFI + MFN/MFD; PDF = Predivision Factor;
DF = Division Factor; T
T
= Internal clock low
L
= Internal clock cycle; ETC = External clock cycle; TH = Internal clock high;
C
T
L
—
0.49 × T
ET
C
C
—
—
0.51 × T
C
2.4.2 External Clock Operation
The DSP56321 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is
shown in
Figure 2-1.
XTALEXTAL
R
C
XTAL1
Fundamental Frequency
Crystal Oscillator
No. Characteristics Symbol
1 Frequency of EXTAL
(EXTAL Pin Frequency)
• With DPLL disabled
• With DPLL enabled
2 EXTAL input high
• With DPLL disabled
(46.7%–53.3% duty
4
cycle
)
• With DPLL enabled
(42.5%–57.5% duty
4
cycle
)
3 EXTAL input low
• With DPLL disabled
(46.7%–53.3% duty
4
cycle
• With DPLL enabled
)
(42.5%–57.5% duty
4
cycle
)
1
2
3
4
C
Ef
DEFR = PDF
× PDFR
ET
H
ET
L
uggested Component Values:
f
= 16–32 MHz
OSC
R = 1 MΩ ± 10%
C = 10 pF ± 10%
Calculations are for a 16–32 MHz crystal with the following parameters:
• shunt capacitance (C
• series resistance of 5–15 Ω, and
• drive level of 2 mW.
Note: Make sure that in the PCTL Register:
•XTLD (bit 2) = 0
) of 5.2–7.3 pF,
0
Figure 2-1. Crystal Oscillator Circuits
Table 2-5. External Clock Operation
200 MHz 220 MHz 240 MHz 275 MHz
Min Max Min Max Min Max Min Max
0 MHz
16 MHz
2.34 ns
2.13 ns∞35.9 ns
2.34 ns
2.13 ns∞35.9 ns
200 MHz
200 MHz
0 MHz
16 MHz
2.12 ns
1.93 ns∞35.9 ns
2.12ns
1.93 ns∞35.9 ns
220 MHz
220 MHz
0 MHz
16 MHz
1.95 ns
1.77 ns∞35.9 ns
1.95 ns
1.77 ns∞35.9 ns
240 MHz
240 MHz
0 MHz
16 MHz
1.70 ns
1.55 ns∞35.9 ns
1.70 ns
1.55 ns∞35.9 ns
275 MHz
275 MHz
DSP56321 Technical Data, Rev. 11
2-4 Freescale Semiconductor
AC Electrical Characteristics
Table 2-5. External Clock Operation (Continued)
200 MHz 220 MHz 240 MHz 275 MHz
No. Characteristics Symbol
Min Max Min Max Min Max Min Max
4 EXTAL cycle time
• With DPLL disabled
• With DPLL enabled
7 Instruction cycle time =
I
= ET
CYC
• With DPLL disabled
• With DPLL enabled
Notes: 1. The rise and fall time of this external clock should be 2 ns maximum.
2. Refer to Tab l e 2-6 for a description of PDF and PDFR.
3. Measured at 50 percent of the input transition.
4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
3
C
ET
I
CYC
C
5.0 ns
5.0 ns∞62.5 ns
10 ns
5.0 ns∞1.6 µs
4.55 ns
4.55 ns∞62.5 ns
9.09 ns
4.55 ns∞1.6 µs
4.17 ns
4.17 ns∞62.5 ns
8.33 ns
4.17 ns∞1.6 µs
3.64 ns
3.64 ns∞62.5 ns
7.28 ns
3.64 ns∞1.6 µs
Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit after
boot-up by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321 Reference Manual). The external
square wave source connects to EXTAL and XTAL is not used. Figure 2-2 shows the EXTAL input signal.
IHX
V
+ V
IHX
ILX
).
EXTAL
Midpoint
ET
ILX
H
2
V
ET
L
3
4
ET
C
Note: The midpoint is 0.5 (V
Figure 2-2. External Input Clock Timing
2.4.3 Clock Generator (CLKGEN) and Digital PLL (DPLL) Characteristics
Table 2-6. CLKGEN and DPLL Characteristics
200 MHz 220 MHz 240 MHz 275 MHz
Characteristics Symbol
Min Max Min Max Min Max Min Max
Predivision factor PDF
Predivider output clock frequency range PDFR 16 32 16 32 16 32 16 32 MHz
Total multiplication factor
Multiplication factor integer part MFI
Multiplication factor numerator
Multiplication factor denominator MFD 1 128 1 128 1 128 1 128 —
Double clock frequency range DDFR 160 400 160 440 160 480 160 550 MHz
Phase lock-in time
2
3
4
1
116116116116—
MF515515515515—
1
515515515515—
MFN0127012701270127—
DPLT 6.8
5
150
6
6.8
5
150
6
6.8
5
150
6
6.8
5
150
Unit
6
µs
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor 2-5
Specifications
Characteristics Symbol
Table 2-6. CLKGEN and DPLL Characteristics (Continued)
200 MHz 220 MHz 240 MHz 275 MHz
Unit
Min Max Min Max Min Max Min Max
Notes: 1. Refer to the
2. The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI + MFN/MFD).
3. The numerator (MFN) should be less than the denominator (MFD).
4. DPLL lock procedure duration is specified for the case when an external clock source is supplied to the EXTAL pin.
5. Frequency-only Lock Mode or non-integer MF, after par tial reset.
6. Frequency and Phase Lock Mode, integer MF, after full reset.
DSP56321 User’s Manual
for a detailed description of register reset values.
2.4.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing
200 MHz 220 MHz 240 MHz 275 MHz
No. Characteristics Expression
Min Max Min Max Min Max Min Max
8 Delay from RESET assertion to all
pins at reset value
9 Required RESET
• Power on, external clock
generator, DPLL disabled
• Power on, external clock
generator, DPLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled
• During STOP, XTAL enabled
• During normal operation
10 Delay from asynchronous RESET
deassertion to first external address
output (internal reset deassertion)
• Minimum
•Maximum
13 Mode select setup time 30.0 — 30.0 — 30.0 — 30.0 — ns
14 Mode select hold time 0.0 — 0.0 — 0.0 — 0.0 — ns
15 Minimum edge-triggered interrupt
request assertion width
16 Minimum edge-triggered interrupt
request deassertion width
17 Delay from IRQA
NMI
assertion to external memory
access address out valid
• Caused by first interrupt instruction
fetch
• Caused by first interrupt instruction
execution
18 Delay from IRQA
NMI
assertion to general-purpose
transfer output valid caused by first
interrupt instruction execution
19 Delay from address output valid
caused by first interrupt instruction
execute to interrupt request
deassertion for level sensitive fast
interrupts
1, 6, 7
3
duration
, IRQB, IRQC, IRQD,
, IRQB, IRQC, IRQD,
4
(WS + 3.75) × TC –
——26—26—26—26ns
50 × ET
1000 × ET
75000 × ET
75000 × ET
2.5 × T
2.5 × T
3.25 × T
4.25 × T
7.25 × T
8.9 × T
10.94
C
C
C
C
C
C
+ 2.0 18.25——
C
+ 2.0
C
+ 2.0
C
C
250.0
5.0
0.375
0.375
12.5
17
4.0 — 4.0 — 4.0 — 4.0 — ns
4.0 — 4.0 — 4.0 — 4.0 — ns
23.25
38.25——
44.5 — 40.45 — 37.0 — 32.37 — ns
—
227.5
—
4.55
—
0.341
—
0.341
—
11.38
—
16.77——
180
21.24
34.99——
— Note 7 — Note 7 — Note 7 — Note 7 ns
16
—
—
—
—
—
—
163
5
208.5
4.17
0.313
0.313
10.43
15
15.55——
150
19.72
32.23——
—
182.0
—
3.64
—
0.273
—
0.273
—
9.1
—
9.1
13.82——
17.45
28.36——nsns
—
—
—
—
—
—
140nsns
Unit
ns
µs
ms
ms
ns
ns
DSP56321 Technical Data, Rev. 11
2-6 Freescale Semiconductor
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