Freescale DSP56321 Technical Data

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Freescale Semiconductor

Technical Data

DSP56321

24-Bit Digital Signal Processor

DSP56321

Rev. 11, 2/2005

SCI

Bootstrap

Internal

Switch

Generator

EXTAL

XTAL

RESET

PINIT /NMI

Address

Generation

Six Channel

DMA Unit

ROM

Data

Bus

Clock

Unit

Tr i pl e Timer

PLL

HI08

PIO_EB

Program Interrupt

Controller

616

ESSI

Peripheral

Expansion Area

Program

Decode

Controller

MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD

EFCOP

Program

RAM

32 K × 24 bits

31 K × 24 bits

and

Instruction

Cache

1024 × 24 bits

DSP56300

Program Address

Generator

Memory Expansion Area

X Data

RAM

80 K × 24 bits

YA B

PM_EB

XAB PA B

DAB

XM_EB

24-Bit

Core

DDB YDB XDB PDB GDB

Data ALU

24 × 24 + 56 → 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Y Data

RAM

80 K × 24 bits

YM_EB

External Address

Switch

External

Interface

I - Cache

Control

External

Pow er

Management

JTAG

OnCE™

Bus

and

Data

Bus

Switch

Address

Control

Data

The DSP56321 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. The onboard EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolutionbased algorithms.

What’s New?

Rev. 11 includes the following changes:

• Adds lead-free packaging and part numbers.

Figure 1. DSP56321 Block Diagram

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 codecompatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1).

The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.

Data Sheet Conventions .......................................................................................................................................ii

Features...............................................................................................................................................................iii

Target Applications ............................................................................................................................................. iv

Product Documentation .......................................................................................................................................v

Chapter 1 Signals/Connections

1.1 Power ................................................................................................................................................................1-3

1.2 Ground ..............................................................................................................................................................1-3

1.3 Clock .................................................................................................................................................................1-3

1.4 External Memory Expansion Port (Port A) ......................................................................................................1-4

1.5 Interrupt and Mode Control ..............................................................................................................................1-6

1.6 Host Interface (HI08) ........................................................................................................................................1-7

1.7 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10

1.8 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11

1.9 Serial Communication Interface (SCI) ...........................................................................................................1-12

1.10 Timers .............................................................................................................................................................1-13

1.11 JTAG and OnCE Interface ..............................................................................................................................1-14

Chapter 2 Specifications

2.1 Maximum Ratings.............................................................................................................................................2-1

2.2 Thermal Characteristics ....................................................................................................................................2-2

2.3 DC Electrical Characteristics............................................................................................................................2-2

2.4 AC Electrical Characteristics............................................................................................................................2-3

Chapter 3 Packaging

3.1 Package Description .........................................................................................................................................3-2

3.2 MAP-BGA Package Mechanical Drawing .....................................................................................................3-10

Chapter 4 Design Considerations

4.1 Thermal Design Considerations........................................................................................................................4-1

4.2 Electrical Design Considerations......................................................................................................................4-2

4.3 Power Consumption Considerations.................................................................................................................4-3

4.4 Input (EXTAL) Jitter Requirements .................................................................................................................4-4

Appendix A Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.)

True Asserted

False Deasserted

True Asserted

False Deasserted

VIL/V

VIH/V

VIL/V

DSP56321 Technical Data, Rev. 11

ii Freescale Semiconductor

Features

Tab l e 1 lists the features of the DSP56321 device.

Table 1. DSP56321 Features

Feature Description

• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control

High-Performance

DSP56300 Core

Enhanced Filter

Coprocessor (EFCOP)

Internal Peripherals

• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals

• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination

• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG) test access port (TAP)

• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core

• Operation at the same frequency as the core (up to 275 MHz)

• Support for a variety of filter modes, some of which are optimized for cellular base station applications:

• Real finite impulse response (FIR) with real taps

• Complex FIR with complex taps

• Complex FIR generating pure real or pure imaginary outputs alternately

• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16

• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter

• Direct form 2 (DFII) IIR filter

• Four scaling factors (1, 4, 8, 16) for IIR output

• Adaptive FIR filter with true least mean square (LMS) coefficient updates

• Adaptive FIR filter with delayed LMS coefficient updates

• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

Freescale Semiconductor

DSP56321 Technical Data, Rev. 11

iii

Table 1 . DSP56321 Features (Continued)

Feature Description

•192 × 24-bit bootstrap ROM

•192 K × 24-bit RAM total

• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:

Internal Memories

External Memory

Expansion

Power Dissipation

Packaging

Program RAM

Size 32 K × 24-bit 0 80 K × 24-bit 80 K × 24-bit disabled 0 0 0 31 K × 24-bit 1024 × 24-bit 80 K × 24-bit 80 K × 24-bit enabled 0 0 0 40 K × 24-bit 0 76 K × 24-bit 76 K × 24-bit disabled 0 0 1 39 K × 24-bit 1024 × 24-bit 76 K × 24-bit 76 K × 24-bit enabled 0 0 1 48 K × 24-bit 0 72 K × 24-bit 72 K × 24-bit disabled 0 1 0 47 K × 24-bit 1024 × 24-bit 72 K × 24-bit 72 K × 24-bit enabled 0 1 0 64 K × 24-bit 0 64 K × 24-bit 64 K × 24-bit disabled 0 1 1 63 K × 24-bit 1024 × 24-bit 64 K × 24-bit 64 K × 24-bit enabled 0 1 1 72 K × 24-bit 0 60 K × 24-bit 60 K × 24-bit disabled 1 0 0 71 K × 24-bit 1024 × 24-bit 60 K × 24-bit 60 K × 24-bit enabled 1 0 0 80 K × 24-bit 0 56 K × 24-bit 56 K × 24-bit disabled 1 0 1 79 K × 24-bit 1024 96 K × 24-bit 0 48 K × 24-bit 48 K × 24-bit disabled 1 1 0 95 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled 1 1 0

112 K × 24-bit 0 40 K × 24-bit 40 K × 24-bit disabled 1 1 1 111 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled 1 1 1 *Includes 12 K × 24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)

• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines

• Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines

• External memory expansion port

• Chip select logic for glueless interface to static random access memory (SRAMs)

• Very low-power CMOS design

• Wait and Stop low-power standby modes

• Fully static design specified to operate down to 0 Hz (dc)

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent)

• Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.

Instruction

Cache Size

× 24-bit 56 K × 24-bit 56 K × 24-bit enabled 1 0 1

X Data RAM

Size*

Y Data RAM

Size*

Instruction

Cache

MSW2 MSW1 MSW0

Target Applications

DSP56321 applications require high performance, low power, small packaging, and a large amount of internal memory. The EFCOP can accelerate general filtering applications. Examples include:

• Wireless and wireline infrastructure applications

• Multi-channel wireless local loop systems

• Security encryption systems

• Home entertainment systems

• DSP resource boards

• High-speed modem banks

• IP telephony

DSP56321 Technical Data, Rev. 11

iv Freescale Semiconductor

Product Documentation

The documents listed in Table 2 are required for a complete description of the DSP56321 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document.

Table 2. DSP56321 Documentation

Name Description Order Number

DSP56321 Reference Manual

DSP56300 Family Manual

Application Notes Documents describing specific applications or optimized device operation

Detailed functional description of the DSP56321 memory configuration, operation, and register programming

Detailed description of the DSP56300 family processor core and instruction set DSP56300FM

including code examples

DSP56321RM

See the DSP56321 product website

Freescale Semiconductor

DSP56321 Technical Data, Rev. 11

vi Freescale Semiconductor

Signals/Connections 1

The DSP56321 input and output signals are organized into functional groups as shown in Tab l e 1- 1 . Figure 1-1 diagrams the DSP56321 signals by functional group. The remainder of this chapter describes the signal pins in each functional group.

Table 1-1. DSP56321 Functional Signal Groupings

Functional Group

Power (VCC) 20

Ground (GND) 66

Clock 2

Address bus

Data bus 24

Bus control 10

Interrupt and mode control 6

Host interface (HI08) Port B

Enhanced synchronous serial interface (ESSI) Ports C and D

Serial communication interface (SCI) Port E

Timer 3

OnCE/JTAG Port 6

Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

5. Eight signal lines are not connected internally. These are designated as no connect (NC) in the package description (see Chapter 3). There are also two reserved lines.

Port A

Number of

Signals

Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal

functionality. See the DSP56321 Reference Manual for details on these configuration registers.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 1-1

Signals/Connections

CCQL

CCQH

CCA

CCD

CCC

CCH

CCS

GND

EXTAL

XTAL

5 3 3 4 2

DSP56321

Power Inputs:

Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer

Grounds:

Ground plane

Clock

Interrupt/

Mode Control

Host

Interface

(HI08) Port

Enhanced

Synchronous Serial

Interface Port 0

(ESSI0)

During Reset

MODA MODB MODC MODD RESET PINIT

Non-Multiplexed Bus

H[0–7] HA0 HA1

HA2 HCS/

HCS

Single DS

HRW HDS

/HDS

Single HR

HREQ

/HREQ

HACK

/HACK

SC0[0–2] SCK0

SRD0 STD0

After Reset

IRQA IRQB IRQC IRQD RESET NMI

Multiplexed Bus

HAD[0–7] HAS

/HAS HA8 HA9 HA10

Double DS

HRD

/HRD

HWR

/HWR

Double HR

HTRQ

/HTRQ

HRRQ

/HRRQ

Port C GPIO

PC[0–2] PC3 PC4 PC5

Port B GPIO

PB[0–7] PB8 PB9 PB10 PB13

PB11 PB12

PB14 PB15

Port D GPIO

PD[0–2] PD3 PD4 PD5

Port E GPIO

PE0 PE1 PE2

Timer GPIO

TIO0 TIO1 TIO2

A[0–17]

D[0–23]

AA[0–3]

TA BR BG

Port A

External Address Bus

External Data Bus

External Bus Control

Synchronous Serial

Enhanced

Interface Port 1

(ESSI1)

Serial

Communications

Interface (SCI) Port

Timers

OnCE/

JTAG Port

SC1[0–2] SCK1

SRD1 STD1

RXD

TXD SCLK

TIO0 TIO1 TIO2

TCK TDI TDO TMS TRST DE

Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (DS), and single or

double host request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]). Signals with dual designations (for example, HAS

/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

3. TIO[0–2] can be configured as GPIO signals.

Figure 1-1. Signals Identified by Functional Group

DSP56321 Technical Data, Rev. 11

1-2 Freescale Semiconductor

1.1 Power

Table 1-2. Power Inputs

Power Name Description

Quiet Core (Low) Power—An isolated power for the core processing and clock logic. This input must be isolated

CCQL

Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip

CCQH

Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally

CCA

Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all

CCD

Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other

CCC

CCH

CCS

Note: The user must provide adequate external decoupling capacitors for all power connections.

externally from all other chip power inputs.

power inputs

to all other chip power inputs,

other chip power inputs,

chip power inputs,

Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs,

ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs,

except

, except

CCQL

except

CCQL

except

CCQL

except

CCQL

Power

1.2 Ground

Table 1-3. Grounds

Name Description

GND Ground—Connected to an internal device ground plane.

Note: The user must provide adequate external decoupling capacitors for all GND connections.

1.3 Clock

Table 1-4. Clock Signals

Signal Name Type

EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input

XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external

State During

Reset

Signal Description

to an external crystal or an external clock.

crystal. If an external clock is used, leave XTAL unconnected.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 1-3

Signals/Connections

1.4 External Memory Expansion Port (Port A)

Note: When the DSP56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-

states the relevant Port A signals: A[0–17], D[0–23], AA[0–3], RD, WR, BB.

1.4.1 External Address Bus

Table 1-5. External Address Bus Signals

State During

Signal Name Type

A[0–17] Output Tri-stated Address Bus—When the DSP is the bus master, A[0–17] are active-high

1.4.2 External Data Bus

Reset, Stop,

or Wait

outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when external memory spaces are not being accessed.

Table 1-6. External Data Bus Signals

Signal Description

Signal Name Type

D[0–23] Input/ Output Ignored Input Last state:

State During

Reset

State During

Stop or Wait

Input

: Ignored

Output

Last value

Signal Description

Data Bus—When the DSP is the bus master, D[0–23] are

active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0–23] drivers are tristated. If the last state is output, these lines have weak keepers to maintain the last output state if all drivers are tristated.

1.4.3 External Bus Control

Table 1-7. External Bus Control Signals

State During

Signal Name Type

AA[0–3] Output Tri-stated Address Attribute—When defined as AA, these signals can be used as chip

Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that

Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output

Reset, Stop, or

Wait

Signal Description

selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the Operating Mode Register, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals.

is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD tri-stated.

that is asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals are tri-stated.

DSP56321 Technical Data, Rev. 11

1-4 Freescale Semiconductor

External Memory Expansion Port (Port A)

Table 1-7. External Bus Control Signals (Continued)

State During

Signal Name Type

TA Input Ignored Input Transfer Acknowledge—If the DSP56321 is the bus master and there is no

Reset, Stop, or

Wait

Signal Description

external bus activity, or the DSP56321 is not the bus master, the TA ignored. The TA extend an external bus cycle indefinitely. Any number of wait states (1,

2. . .infinity) can be added to the wait states inserted by the bus control register (BCR) by keeping TA start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA states is determined by the TA BCR can be used to set the minimum number of wait states in external bus cycles.

input is a data transfer acknowledge (DTACK) function that can

deasserted. In typical operation, TA is deasserted at the

is asserted synchronous to CLKOUT. The number of wait

input or by the BCR, whichever is longer. The

input is

To use the TA state. A zero wait state access cannot be extended by TA otherwise, improper operation may result.

Output Reset: Output

(deasserted)

State during Stop/Wait depends on BRH bit setting:

• BRH = 0: Output (deasserted)

• BRH = 1: Maintains last state (that is, if asserted, remains asserted)

Input Ignored Input Bus Grant—Asserted by an external bus arbitration circuit when the DSP56321

Input/ Output Ignored Input Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the

Bus Request—Asserted when the DSP requests bus mastership. BR deasserted when the DSP no longer needs the bus. BR deasserted independently of whether the DSP56321 is a bus master or a bus slave. Bus “parking” allows BR the bus master. (See the description of bus “parking” in the BB description.) The bus request hold (BRH) bit in the BCR allows BR asserted under software control even though the DSP does not need the bus. BR

is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR only by DSP requests for the external bus, never for the internal bus. During hardware reset, BR state.

becomes the next bus master. When BG until BB bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution.

To ensure proper operation, the user must set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG

and BB are synchronized internally. This adds a required delay between the deassertion of an initial BG

pending bus master become the bus master (and then assert the signal again). The bus master may keep BB whether BR current bus master to reuse the bus without rearbitration until another device requires the bus. BB driven high and then released and held high by an external pull-up resistor).

functionality, the BCR must be programmed to at least one wait

deassertion;

may be asserted or

to be deasserted even though the DSP56321 is

signal

to be

is affected

is deasserted and the arbitration is reset to the bus slave

is asserted, the DSP56321 must wait

is deasserted before taking bus mastership. When BG is deasserted,

input and the assertion of a subsequent BG input.

asserted after ceasing bus activity regardless of

is asserted or deasserted. Called “bus parking,” this allows the

is deasserted by an “active pull-up” method (that is, BB is

Notes: 1. See BG

2. BB

for additional information.

requires an external pull-up resistor.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 1-5

Signals/Connections

1.5 Interrupt and Mode Control

The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET

is deasserted, these inputs are hardware interrupt request lines.

Table 1-8. Interrupt and Mode Control

Signal Name Type

MODA

IRQA

MODB

IRQB

MODC

IRQC

MODD

Input

State During

Reset

Schmitt-trigger Input

Signal Description

Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial

chip operating modes, latched into the Operating Mode Register when the RESET

signal is deasserted.

External Interrupt Request A—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the STOP or WAIT standby state and IRQA state.

Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET

signal is deasserted.

External Interrupt Request B—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQB

Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET

External Interrupt Request C—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQC

Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET

is asserted, the processor exits the WAIT state.

signal is deasserted.

is asserted, the processor exits the WAIT state.

signal is deasserted.

is asserted, the processor exits the STOP or WAIT

IRQD

RESET

PINIT

NMI

Input

Input Schmitt-trigger

Input

Schmitt-trigger Input

External Interrupt Request D—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQD

Reset—Places the chip in the Reset state and resets the internal phase generator. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET powerup.

PLL Initial—During assertion of RESET, the value of PINIT determines whether the DPLL is enabled or disabled.

Nonmaskable Interrupt—After RESET instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI

is asserted, the processor exits the WAIT state.

signal is

signal must be asserted after

deassertion and during normal

request.

DSP56321 Technical Data, Rev. 11

1-6 Freescale Semiconductor

Host Interface (HI08)

1.6 Host Interface (HI08)

The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.

1.6.1 Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in Tab le 1- 9.

Table 1-9. Host Port Usage Considerations

Action Description

Asynchronous read of receive byte registers

Asynchronous write to transmit byte registers

Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when the Host

When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid.

The host interface programmer should not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX) register.

Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a stable vector.

1.6.2 Host Port Configuration

HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits in the HI08 Port Control Register.

Table 1-10. Host Interface

Signal Name Type

H[0–7]

Input/Output

State During

Ignored Input Host Data—When the HI08 is programmed to interface with a non-multiplexed

Reset

1,2

host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional Data bus.

Signal Description

HAD[0–7]

PB[0–7]

Freescale Semiconductor 1-7

Input/Output

Input or Output

Host Address—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus.

Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register.

DSP56321 Technical Data, Rev. 11

Signals/Connections

Table 1-10. Host Interface (Continued)

Signal Name Type

HA0

HAS

/HAS

PB8

HA1

HA8

PB9

HA2

Input or Output

Input

State During

Ignored Input Host Address Input 0—When the HI08 is programmed to interface with a

Ignored Input Host Address Input 1—When the HI08 is programmed to interface with a

Ignored Input Host Address Input 2—When the HI08 is programmed to interface with a

Reset

1,2

nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus.

Host Address Strobe—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS

Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus.

Host Address 8—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus.

Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

nonmultiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus.

Signal Description

) following reset.

HA9

PB10

HCS

HA10

PB13

HRW

HRD

PB11

/HCS

/HRD

Input

Input or Output

Input

Input or Output

Input

Input or Output

Host Address 9—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus.

Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

Ignored Input Host Chip Select—When the HI08 is programmed to interface with a

nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable but is configured active-low (HCS

Host Address 10—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus.

Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

Ignored Input Host Read/Write—When the HI08 is programmed to interface with a single-

data-strobe host bus and the HI function is selected, this signal is the Host Read/Write

Host Read Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the HRD strobe Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HRD

Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

(HRW) input.

) after reset.

DSP56321 Technical Data, Rev. 11

1-8 Freescale Semiconductor

Table 1-10. Host Interface (Continued)

Host Interface (HI08)

Signal Name Type

HDS/HDS

/HWR

HWR

PB12

HREQ

HTRQ

PB14

HACK

/HREQ

/HTRQ

/HACK

Input or Output

Output

Input or Output

Input

State During

Ignored Input Host Data Strobe—When the HI08 is programmed to interface with a single-

Ignored Input Host Request—When the HI08 is programmed to interface with a single host

Ignored Input Host Acknowledge—When the HI08 is programmed to interface with a single

Reset

1,2

data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HDS

Host Write Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HWR

Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

request host bus and the HI function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable but is configured as active-low (HREQ programmed as a driven or open-drain output.

Transmit Host Request—When the HI08 is programmed to interface with a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable but is configured as active-low (HTRQ request may be programmed as a driven or open-drain output.

Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable but is configured as active-low (HACK reset.

Signal Description

) following reset.

) following reset. The host request may be

) following reset. The host

) after

/HRRQ

HRRQ

PB15

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.

2. The Wait processing state does not affect the signal state.

Output

Input or Output

Receive Host Request—When the HI08 is programmed to interface with a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable but is configured as active-low (HRRQ request may be programmed as a driven or open-drain output.

Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register.

DSP56321 Technical Data, Rev. 11

) after reset. The host

Freescale Semiconductor 1-9

Signals/Connections

1.7 Enhanced Synchronous Serial Interface 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and

DSP56321 Technical Data, Rev. 11

1-10 Freescale Semiconductor

Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-11. Enhanced Synchronous Serial Interface 0 (Continued)

Signal Name Type

STD0

PC5

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.

2. The Wait processing state does not affect the signal state.

Output

Input or Output

State During

Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.

Reset

1,2

STD0 is an output when data is transmitted.

Port C 5—The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal STD0 through the Port C Control Register.

Signal Description

1.8 Enhanced Synchronous Serial Interface 1 (ESSI1)

Table 1-12. Enhanced Serial Synchronous Interface 1

Signal Name Type

SC10

PD0

SC11

Input or Output

Input/Output

State During

Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive

Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame

Reset

1,2

clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0.

Port D 0—The default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC10 through the Port D Control Register.

sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1.

Signal Description

PD1

SC12

PD2

Input or Output

Input/Output

Input or Output

Port D 1—The default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC11 through the Port D Control Register.

Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver

in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation).

Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 1-11

Signals/Connections

Table 1-12. Enhanced Serial Synchronous Interface 1 (Continued)

Signal Name Type

SCK1

PD3

SRD1

PD4

STD1

PD5

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.

2. The Wait processing state does not affect the signal state.

Input/Output

Input or Output

Input

Input or Output

Output

Input or Output

State During

Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a

Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI

Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.

Reset

1,2

clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes.

Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.

Port D 3—The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SCK1 through the Port D Control Register.

Receive Shift Register. SRD1 is an input when data is being received.

Port D 4—The default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SRD1 through the Port D Control Register.

STD1 is an output when data is being transmitted.

Port D 5—The default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal STD1 through the Port D Control Register.

Signal Description

1.9 Serial Communication Interface (SCI)

The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems.

Table 1-13. Serial Communication Interface

Signal Name Type

RXD

PE0

TXD

PE1

Input

Input or Output

Output

Input or Output

State During

Ignored Input Serial Receive Data—Receives byte-oriented serial data and transfers it to the

Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit Data Register.

Reset

1,2

SCI Receive Shift Register.

Port E 0—The default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal RXD through the Port E Control Register.

Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register.

Signal Description

DSP56321 Technical Data, Rev. 11

1-12 Freescale Semiconductor

Table 1-13. Serial Communication Interface (Continued)

Timers

Signal Name Type

SCLK

PE2

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.

2. The Wait processing state does not affect the signal state.

Input/Output

Input or Output

State During

Ignored Input Serial Clock—Provides the input or output clock used by the transmitter and/or

Reset

1,2

the receiver.

Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal SCLK through the Port E Control Register.

Signal Description

1.10 Timers

The DSP56321 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56321 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events.

Table 1-14. Triple Timer Signals

Signal Name Type

State During

1,2

Reset

Signal Description

TIO0 Input or Output Ignored Input Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an

external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. TIO0 can be changed to output or configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).

TIO1 Input or Output Ignored Input Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an

TIO2 Input or Output Ignored Input Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.

2. The Wait processing state does not affect the signal state.

external event counter or in measurement mode, TIO1 is used as input. When Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output.

The default mode after reset is GPIO input. TIO1 can be changed to output or configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).

external event counter or in measurement mode, TIO2 is used as input. When Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output.

The default mode after reset is GPIO input. TIO2 can be changed to output or configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 1-13

Signals/Connections

1.11 JTAG and OnCE Interface

The DSP56300 family and in particular the DSP56321 support circuit-board test strategies based on the IEEE® Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the

sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming models, see the chapter on debugging support in the DSP56300 Family Manual.

Table 1-15. JTAG/OnCE Interface

Signal

Name

TCK Input Input Test Clo ck—A test clock input signal to synchronize the JTAG test logic.

TDI Input Input Test Data Input—A test data serial input signal for test instructions and data.

TDO Output Tri-stated Test Data Output—A test data serial output signal for test instructions and

TMS Input Input Test Mode Select—Sequences the test controller’s state machine. TMS is

TRST

Type

Input Input Test Res e t—Initializes the test controller asynchronously. TRST has an

Input/ Output Input Debug Event—As an input, initiates Debug mode from an external command

State During

Reset

Signal Description

TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.

data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK.

sampled on the rising edge of TCK and has an internal pull-up resistor.

internal pull-up resistor. TRST (see EB610/D for details).

controller, and, as an open-drain output, acknowledges that the chip has entered Debug mode. As an input, DE executing the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters Debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE

This signal is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered Debug mode. All other interface with the OnCE module must occur through the JTAG port.

must be asserted during and after power-up

causes the DSP56300 core to finish

has an internal pull-up resistor.

DSP56321 Technical Data, Rev. 11

1-14 Freescale Semiconductor

Specifications 2

The DSP56321 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs.

2.1 Maximum Ratings

CAUTION

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V

In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist.

Table 2-1. Absolute Maximum Ratings

Rating

Supply Voltage

Input/Output Supply Voltage

All input voltages V

Current drain per pin excluding V

Operating temperature range T

Storage temperature T

Notes: 1. GND = 0 V, V

and GND I 10 mA

= 1.6 V ± 0.1 V, V

CCQL

voltage.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.

3. Power-up sequence: During power-up, and throughout the DSP56321 operation, V equal to V

CCQH

Symbol Value

CCQH

= 3.3 V ± 0.3 V, TJ = –40°C to +100°C, CL = 50 pF

CCQL

STG

GND – 0.3 to V

1, 2

–0.1 to 2.25 V

–0.3 to 4.35 V

+ 0.3 V

CCQH

–40 to +100 °C

–55 to +150 °C

voltage must always be higher or

CCQH

Unit

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-1

Specifications

2.2 Thermal Characteristics

Table 2-2. Thermal Characteristics

Thermal Resistance Characteristic Symbol

Junction-to-ambient, natural convection, single-layer board (1s)

Junction-to-ambient, natural convection, four-layer board (2s2p)

Junction-to-ambient, @200 ft/min air flow, single-layer board (1s)

Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)

Junction-to-board

Junction-to-case thermal resistance

1,2

1,3

θJMA

θJA

θJB

θJC

MAP-BGA

Value

44 °C/W 25 °C/W 35 °C/W 22 °C/W 13 °C/W

7 °C/W

Unit

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

2.3 DC Electrical Characteristics

Table 2-3. DC Electrical Characteristics

Characteristics Symbol Min Typ Max Unit

Supply voltage1:

•Core (V

•I/O (V

Input high voltage

• D[0–23], BG

• MOD/IRQ2 RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI08 pins

•EXTAL

Input low voltage

• D[0–23], BG

• All JTAG/ESSI/SCI/Timer/HI08 pins

•EXTAL

Input leakage current I

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

Output high voltage

•TTL (I

•CMOS (IOH = –10 µA)

Output low voltage

•TTL (I

•CMOS (IOL = 10 µA)

)

CCQL

, V

CCQH

CCA

CCD

CCC

, V

, BB, TA

, BB, TA, MOD/IRQ2, RESET, PINIT

= –0.4 mA)

= 3.0 mA)

CCH

, and V

CCS

)

1.5

3.0

IHP

IHX

ILP

ILX

TSI

2.0

0.8 × V

CCQH

–0.3 –0.3 –0.3

–10 — 10 µA

2.4

– 0.01

CCQH

— —

1.6

3.3

— —

—

— — —

— —

1.7

3.6

CCQH

0.8

0.2 × V

— —

0.4

0.01

+ 0.3 + 0.3

CCQH

V V

V V V

V V

DSP56321 Technical Data, Rev. 11

2-2 Freescale Semiconductor

AC Electrical Characteristics

Table 2-3. DC Electrical Characteristics

Characteristics Symbol Min Typ Max Unit

Internal supply current:

• In Normal mode — at 200 MHz — at 220 MHz — at 240 MHz — at 275 MHz

• In Wait mode

• In Stop mode

Input capacitance

Notes: 1. Power-up sequence: During power-up, and throughout the DSP56321 operation, V

2. Refers to MODA/IRQA

3. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all

4. To obtain these results, all inputs must be terminated (that is, not allowed to float).

5. To obtain these results, all inputs not disconnected at Stop mode must be terminated (that is, not allowed to float), and the

6. Periodically sampled and not 100 percent tested.

7. V

8. This characteristic does not apply to XTAL.

9. Driving EXTAL to the low V

equal to V

inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP applications.

DPLL and on-chip crystal oscillator must be disabled.

CCQH

power consumption, the minimum V

0.9 × V

voltage.

CCQL

= 3.3 V ± 0.3 V, V

and the maximum V

CCQH

, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF

CQLC

or the high V

IHX

ILX

IHX

should be no higher than 0.1 × V

value may cause additional power consumption (DC current). To minimize

ILX

should be no lower than

CCW

CCS

CCI

— — — — — —

— — 10 pF

CCQH

190 200 210 235

25 15

voltage must always be higher or

CCQH

— — — — — —

mA mA mA mA mA mA

2.4 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a V and 9 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal’s transition. DSP56321 output levels are measured with the production test machine V

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 16

2.4.1 Internal Clocks

Internal operating frequency

• With DPLL disabled

• With DPLL enabled

Internal clock cycle time

• With DPLL disabled

• With DPLL enabled

Internal clock high period

• With DPLL disabled

• With DPLL enabled

minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Notes 7

and VOH reference levels set at 0.4 V and 2.4 V, respectively.

MHz and rated speed with the DPLL enabled.

Table 2-4. Internal Clocks

Expression

Characteristics Symbol

Min Typ Max

— —

—

0.49 × T

Ef/2

(Ef × MF)/(PDF × DF)

2 × ET

—

ETC × PDF × DF/MF

— —

—

0.51 × T

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-3

Specifications

Table 2-4. Internal Clocks (Continued)

Expression

Characteristics Symbol

Min Typ Max

Internal clock low period

• With DPLL disabled

• With DPLL enabled

Note: Ef = External frequency; MF = Multiplication Factor = MFI + MFN/MFD; PDF = Predivision Factor;

DF = Division Factor; T T

= Internal clock low

= Internal clock cycle; ETC = External clock cycle; TH = Internal clock high;

—

0.49 × T

—

0.51 × T

2.4.2 External Clock Operation

The DSP56321 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is shown in

Figure 2-1.

XTALEXTAL

XTAL1

Fundamental Frequency

Crystal Oscillator

No. Characteristics Symbol

1 Frequency of EXTAL

(EXTAL Pin Frequency)

• With DPLL disabled

• With DPLL enabled

2 EXTAL input high

• With DPLL disabled (46.7%–53.3% duty

cycle

)

• With DPLL enabled (42.5%–57.5% duty

cycle

)

3 EXTAL input low

• With DPLL disabled (46.7%–53.3% duty

cycle

• With DPLL enabled

)

(42.5%–57.5% duty

cycle

)

DEFR = PDF

× PDFR

uggested Component Values:

= 16–32 MHz

OSC

R = 1 MΩ ± 10% C = 10 pF ± 10%

Calculations are for a 16–32 MHz crystal with the following parameters:

• shunt capacitance (C

• series resistance of 5–15 Ω, and

• drive level of 2 mW.

Note: Make sure that in the PCTL Register:

•XTLD (bit 2) = 0

) of 5.2–7.3 pF,

Figure 2-1. Crystal Oscillator Circuits

Table 2-5. External Clock Operation

200 MHz 220 MHz 240 MHz 275 MHz

Min Max Min Max Min Max Min Max

0 MHz

16 MHz

2.34 ns

2.13 ns∞35.9 ns

2.34 ns

2.13 ns∞35.9 ns

200 MHz 200 MHz

0 MHz

16 MHz

2.12 ns

1.93 ns∞35.9 ns

2.12ns

1.93 ns∞35.9 ns

220 MHz 220 MHz

0 MHz

16 MHz

1.95 ns

1.77 ns∞35.9 ns

1.95 ns

1.77 ns∞35.9 ns

240 MHz 240 MHz

0 MHz

16 MHz

1.70 ns

1.55 ns∞35.9 ns

1.70 ns

1.55 ns∞35.9 ns

275 MHz 275 MHz

DSP56321 Technical Data, Rev. 11

2-4 Freescale Semiconductor

AC Electrical Characteristics

Table 2-5. External Clock Operation (Continued)

200 MHz 220 MHz 240 MHz 275 MHz

No. Characteristics Symbol

Min Max Min Max Min Max Min Max

4 EXTAL cycle time

• With DPLL disabled

• With DPLL enabled

7 Instruction cycle time =

= ET

CYC

• With DPLL disabled

• With DPLL enabled

Notes: 1. The rise and fall time of this external clock should be 2 ns maximum.

2. Refer to Tab l e 2-6 for a description of PDF and PDFR.

3. Measured at 50 percent of the input transition.

4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met.

CYC

5.0 ns

5.0 ns∞62.5 ns

10 ns

5.0 ns∞1.6 µs

4.55 ns

4.55 ns∞62.5 ns

9.09 ns

4.55 ns∞1.6 µs

4.17 ns

4.17 ns∞62.5 ns

8.33 ns

4.17 ns∞1.6 µs

3.64 ns

3.64 ns∞62.5 ns

7.28 ns

3.64 ns∞1.6 µs

Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit after

boot-up by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321 Reference Manual). The external square wave source connects to EXTAL and XTAL is not used. Figure 2-2 shows the EXTAL input signal.

IHX

+ V

IHX

ILX

EXTAL

Midpoint

ILX

Note: The midpoint is 0.5 (V

Figure 2-2. External Input Clock Timing

2.4.3 Clock Generator (CLKGEN) and Digital PLL (DPLL) Characteristics

Table 2-6. CLKGEN and DPLL Characteristics

200 MHz 220 MHz 240 MHz 275 MHz

Characteristics Symbol

Min Max Min Max Min Max Min Max

Predivision factor PDF

Predivider output clock frequency range PDFR 16 32 16 32 16 32 16 32 MHz

Total multiplication factor

Multiplication factor integer part MFI

Multiplication factor numerator

Multiplication factor denominator MFD 1 128 1 128 1 128 1 128 —

Double clock frequency range DDFR 160 400 160 440 160 480 160 550 MHz

Phase lock-in time

116116116116—

MF515515515515—

515515515515—

MFN0127012701270127—

DPLT 6.8

150

6.8

150

6.8

150

6.8

150

Unit

µs

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-5

Specifications

Characteristics Symbol

Table 2-6. CLKGEN and DPLL Characteristics (Continued)

200 MHz 220 MHz 240 MHz 275 MHz

Unit

Min Max Min Max Min Max Min Max

Notes: 1. Refer to the

2. The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI + MFN/MFD).

3. The numerator (MFN) should be less than the denominator (MFD).

4. DPLL lock procedure duration is specified for the case when an external clock source is supplied to the EXTAL pin.

5. Frequency-only Lock Mode or non-integer MF, after par tial reset.

6. Frequency and Phase Lock Mode, integer MF, after full reset.

DSP56321 User’s Manual

for a detailed description of register reset values.

2.4.4 Reset, Stop, Mode Select, and Interrupt Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

200 MHz 220 MHz 240 MHz 275 MHz

No. Characteristics Expression

Min Max Min Max Min Max Min Max

8 Delay from RESET assertion to all

pins at reset value

9 Required RESET

• Power on, external clock generator, DPLL disabled

• Power on, external clock generator, DPLL enabled

• Power on, internal oscillator

• During STOP, XTAL disabled

• During STOP, XTAL enabled

• During normal operation

10 Delay from asynchronous RESET

deassertion to first external address output (internal reset deassertion)

• Minimum

•Maximum

13 Mode select setup time 30.0 — 30.0 — 30.0 — 30.0 — ns

14 Mode select hold time 0.0 — 0.0 — 0.0 — 0.0 — ns

15 Minimum edge-triggered interrupt

request assertion width

16 Minimum edge-triggered interrupt

request deassertion width

17 Delay from IRQA

NMI

assertion to external memory

access address out valid

• Caused by first interrupt instruction fetch

• Caused by first interrupt instruction execution

18 Delay from IRQA

NMI

assertion to general-purpose transfer output valid caused by first interrupt instruction execution

19 Delay from address output valid

caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts

1, 6, 7

duration

, IRQB, IRQC, IRQD,

(WS + 3.75) × TC –

——26—26—26—26ns

50 × ET

1000 × ET

75000 × ET 75000 × ET

2.5 × T

3.25 × T

4.25 × T

7.25 × T

8.9 × T

10.94

+ 2.0 18.25——

+ 2.0

250.0

5.0

0.375

12.5 17

4.0 — 4.0 — 4.0 — 4.0 — ns

23.25

38.25——

44.5 — 40.45 — 37.0 — 32.37 — ns

—

227.5

—

4.55

—

0.341

—

0.341

—

11.38

—

16.77——

180

21.24

34.99——

— Note 7 — Note 7 — Note 7 — Note 7 ns

—

— — — —

163

208.5

4.17

0.313

10.43 15

15.55——

150

19.72

32.23——

—

182.0

—

3.64

—

0.273

—

0.273

—

9.1

—

9.1

13.82——

17.45

28.36——nsns

—

— — — —

140nsns

Unit

µs

ms ms

ns ns

DSP56321 Technical Data, Rev. 11

2-6 Freescale Semiconductor

AC Electrical Characteristics

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

No. Characteristics Expression

20 Delay from RD assertion to interrupt

request deassertion for level sensitive fast interrupts

21 Delay from WR

request deassertion for level sensitive fast interrupts

1, 6, 7

assertion to interrupt

1, 6, 7

•SRAM WS = 3

•SRAM WS ≥ 4

24 Duration for IRQA assertion to recover

from Stop state

25 Delay from IRQA

assertion to fetch of

first instruction (when exiting Stop)

• DPLL is not active during Stop (PCTL Bit 1 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0)

• DPLL is not active during Stop (PCTL Bit 1 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1)

• DPLL is active during Stop (PCTL Bit 1 = 1; Implies No Stop Delay)

26 Duration of level sensitive IRQA

assertion to ensure interrupt service (when exiting Stop)

2, 3

• DPLL is not active during Stop (PCTL bit 1 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0)

• DPLL is not active during Stop (PCTL bit 1 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1)

• DPLL is active during Stop ((PCTL bit 1 = 0; implies no Stop delay)

27 Interrupt Request Rate

• HI08, ESSI, SCI, Timer

•DMA

•IRQ

, NMI (edge trigger)

•IRQ

, NMI (level trigger)

28 DMA Request Rate

• Data read from HI08, ESSI, SCI

• Data write to HI08, ESSI, SCI

•Timer

•IRQ

, NMI (edge trigger)

29 Delay from IRQA

NMI

assertion to external memory

, IRQB, IRQC, IRQD,

(DMA source) access address out valid

(WS + 3.25) × TC –

10.94

(WS + 3) × TC – 10.94

(WS + 2.5) × T

2, 3

DPLT + (128K × T

DPLT + (23.75 ± 0.5) ×

(10.0 ± 1.75) × T

DPLT + (128 K × T

DPLT + (20.5 ± 0.5) × T

5.5 × T

12T

4.25 × T

– 10.94——

+ 2.0 23.25 — 21.34 — 19.72 — 17.45 — ns

(CONTINUED)

200 MHz 220 MHz 240 MHz 275 MHz

Min Max Min Max Min Max Min Max

— Note 7 — Note 7 — Note 7 — Note 7 ns

Note 7 Note 7——

8.0 — 8.0 — 8.0 — 8.0 — ns

)

662.2 µs

6.9

41.25

805.4

150.1

27.5

— — — —

209.9 ms

188.8

58.8

—

60.0

40.0

60.0

30.0

35.0

10.0

15.0

)

662.2 µs

6.9

37.5

805.4

150.1

— — — —

Note 7 Note 7——

209.9

662.2

188.8

53.3

6.9

34.4

—

805.4

—

150.1

—

22.9

54.6

36.4

54.6

27.3

31.9

9.1

13.7

µs

— — — —

Note 7 Note 7——

209.9

662.2

188.8

49.0

6.9

30.0

—

805.4

—

150.1

—

20.0

50.0

33.4

50.0

25.0

29.2

8.3

12.5

µs

— — — —

Unit

Note 7 Note 7nsns

209.9

188.8

21.84

25.48

10.92

43.0

—

43.7

29.2

43.7

7.28

—

µs

ns ns ns ns

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-7

Specifications

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing

(CONTINUED)

200 MHz 220 MHz 240 MHz 275 MHz

No. Characteristics Expression

Unit

Min Max Min Max Min Max Min Max

Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to

prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.

2. This timing depends on several settings:

• For DPLL disable, using internal oscillator (DPLL Control Register (PCTL) Bit 2 = 0) and oscillator disabled during Stop (PCTL Bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case.

• For DPLL disable, using internal oscillator (PCTL Bit 2 = 0) and oscillator enabled during Stop (PCTL Bit 1 = 1), no stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For DPLL disable, using external clock (PCTL Bit 2 = 1), no stabilization delay is required and recovery time is defined by the PCTL Bit 1 and Operating Mode Register Bit 6 settings.

• For DPLL enable, if PCTL Bit 1 is 0, the DPLL is shut down during Stop. Recovering from Stop requires the DPLL to lock. The DPLL lock procedure duration is defined in Tab l e 2-6 and will be refined after silicon characterization. This procedure is followed by the stop delay counter. Stop recovery ends when the stop delay counter completes its count.

• The DPLT value for DPLL disable is 0.

3. Periodically sampled and not 100 percent tested.

4. For an external clock generator, RESET

active and valid. For an internal oscillator, RESET the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the V device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration.

5. V

CCQH

6. WS = number of wait states (measured in clock cycles, number of T

7. Use the expression to compute a maximum value.

is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

= 3.3 V ± 0.3 V, V

= 1.6 V ± 0.1 V; TJ = –40°C to +100°C, CL = 50 pF.

CCQL

duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is

duration is measured while RESET is asserted and V

is valid. The specified timing reflects

RESET

All Pins

A[0–17]

9 10

Reset Value

First Fetch

Figure 2-3. Reset Timing

DSP56321 Technical Data, Rev. 11

2-8 Freescale Semiconductor

AC Electrical Characteristics

A[0–17]

IRQA, IRQB, IRQC

, IRQD,

NMI

General

Purpose

I/O

First Interrupt Instruction

Execution/Fetch

1917

a) First Interrupt Instruction Execution

IRQA

IRQC

IRQA, IRQB,

IRQC

, IRQD, NMI

IRQA, IRQB,

IRQC

, IRQD, NMI

, IRQB, , IRQD,

NMI

b) General-Purpose I/O

Figure 2-4. External Fast Interrupt Timing

Figure 2-5. External Interrupt Timing (Negative Edge-Triggered)

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-9

Specifications

RESET

MODA, MODB, MODC, MODD, PINIT

IRQA

A[0–17]

IRQA

Figure 2-6. Operating Mode Select Timing

First Instruction Fetch

Figure 2-7. Recovery from Stop State Using IRQA

IRQA IRQC

, IRQB, , IRQD, NMI

A[0–17]

Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service

A[0–17]

IRQA, IRQB, IRQC

, IRQD,

NMI

First Interrupt Instruction Execution

DMA Source Address

Figure 2-9. External Memory Access (DMA Source) Timing

First IRQA Interrupt

Instruction Fetch

DSP56321 Technical Data, Rev. 11

2-10 Freescale Semiconductor

2.4.5 External Memory Expansion Port (Port A)

2.4.5.1 SRAM Timing

Table 2-8. SRAM Timing

AC Electrical Characteristics

No. Characteristics Symbol Expression

100 Address valid and AA

assertion pulse width

101 Address and AA valid to

assertion

102 WR

103 WR

assertion pulse width t

deassertion to

address not valid

104 Address and AA valid to

input data valid

105 RD

assertion to input data

valid

106 RD

deassertion to data

not valid (data hold time)

107 Address valid to WR

deassertion

108 Data valid to WR

deassertion (data setup time)

109 Data hold time from WR

deassertion

110 WR

assertion to data

active

111 WR

deassertion to data

high impedance

112 Previous RD

deassertion

to data active (write)

113 RD

deassertion time — 1.75 × TC − 3.0

114 WR deassertion time

tRC, t

(WS + 2) × TC − 4.0

(WS + 3) × T

0.75 × TC – 3.0

1.25 × T

[3 ≤ WS ≤ 7]

[WS ≥ 8]

[WS = 3]

– 3.0

[WS ≥ 4]

WS × TC − 4.0

[WS = 3]

(WS − 0.5) × T

[WS ≥ 4]

, t

OHZ

(tDW)(WS − 0.25) × TC − 5.4

1.25 × TC − 4.0 [3 ≤ WS ≤ 7]

2.25 × T

[WS ≥ 8]

− 4.0

(WS + 0.75) × TC − 5.8

[WS ≥ 3]

(WS + 0.25) × TC − 6.5

[WS ≥ 3]

(WS + 0.75) × TC − 4.0

[WS ≥ 3]

1.25 × TC − 4.0 [3 ≤ WS ≤ 7]

2.25 × T

[WS ≥ 8]

− 4.0

—0.25 × TC − 4.0

[WS = 3]

–0.25 × T

− 4.0

[WS ≥ 4]

—1.25 × T

—2.25 × TC − 4.0 7.25 — 6.23 — 5.38 — 4.18 — ns

[3 ≤ WS ≤ 7]

2.75 × T

—2.0 × TC − 3.0

[WS ≥ 8]

− 3.0

[3 ≤ WS ≤ 7]

3.0 × T

[WS ≥ 8]

− 3.0

− 4.0

200 MHz 220 MHz 240 MHz 275 MHz

Min Max Min Max Min Max Min Max

21.0

51.0 —

0.75

3.25——

11.0

− 4.0

13.5——

2.25

7.25——

— 12.9 — 11.2 — 9.8 — 7.84 ns

— 9.75 — 8.29 — 7.05 — 5.31 ns

0.0 — 0.0 — 0.0 — 0.0 — ns

14.75 — 13.06 — 11.64 — 9.63 — ns

8.35 — 7.11 — 6.07 — 4.6 — ns

2.25

7.25——

–2.75

–5.25——

6.25 — 5.69 — 5.21 — 4.55 — ns

5.75

10.75——

7.0

12.0——

18.8

46.0 —

0.41

2.69——

9.65

11.93——

1.69

6.24——

1.69

6.23——

–2.86

–5.14——

4.96

9.51——

6.1

10.6——

16.9

41.9 —

0.13

2.21——

8.51

10.6——

1.21

5.38——

1.21

5.38——

–2.96

–5.04——

4.3

—

8.47

—

5.3

9.5——

15.0

36.0 —nsns

–0.27

1.54——nsns

8.72——nsns

0.54

4.18——nsns

0.54

4.18——nsns

–3.1

–4.91——nsns

3.36

4.27

7.91——nsns

6.9

7.0

Unit

——ns

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-11

Specifications

Table 2-8. SRAM Timing (Continued)

No. Characteristics Symbol Expression

200 MHz 220 MHz 240 MHz 275 MHz

Unit

Min Max Min Max Min Max Min Max

115 Address valid to RD

assertion

116 RD

117 RD

118 TA

119 TA

Notes: 1. WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,

assertion pulse width — (WS + 0.25) × TC − 3.0

deassertion to

address not valid

setup before RD or

deassertion

hold after RD or WR

deassertion

2. Timings 100 and 107 are guaranteed by design, not tested.

3. All timings are measured from 0.5 × V

4. The WS number applies to the access in which the deassertion of WR

5. Timing 118 is relative to the deassertion edge of RD

for a category of [3 ≤ WS ≤ 7] timing is specified for 3 wait states.) Three wait states is the minimum value otherwise.

number of wait states.

A[0–17]

AA[0–3]

—0.5 × TC − 2.0 0.5 — 0.3 — 0.1 — –0.18 — ns

13.25 — 11.59 — 10.55 — 8.81 — ns

[WS ≥ 3]

—1.25 × TC − 4.0

[3 ≤ WS ≤ 7]

2.25 × T

—0.25 × TC + 2.0 3.25 — 3.14 — 3.04 — 2.91 — ns

— 0—0—0—0—ns

[WS ≥ 8]

to 0.5 × V

CCQH

− 4.0

2.25

7.25——

CCQH

or WR even if TA remains asserted.

1.69

6.24——

occurs and assumes the next access uses a minimal

1.21

5.38——

0.54

4.18——nsns

D[0–23]

105

Figure 2-10. SRAM Read Access

DSP56321 Technical Data, Rev. 11

2-12 Freescale Semiconductor

A[0–17]

AA[0–3]

114

107

100

AC Electrical Characteristics

102101

103

108

D[0–23]

Data

Out

Figure 2-11. SRAM Write Access

2.4.5.2 Asynchronous Bus Arbitration Timings

Table 2-9. Asynchronous Bus Timings

200 MHz 220 MHz 240 MHz 275 Mhz

No. Characteristics Expression

Min Max Min Max Min Max Min Max

250 BB assertion window from BG input

deassertion.

251 Delay from BB

Notes: 1. Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.

2. To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG

assertion to BG assertion 2 × Tc + 5 15 — 14.1 — 13.3 — 12.27 — ns

devices (on the same bus), as shown in Figure 2-12, where BG1 BG

signal for a second DSP56300 device.

2.5 × Tc + 5 — 17.5 — 16.4 — 15.4 — 14.1 ns

is the BG signal for one DSP56300 device while BG2 is the

109

Uni

inputs to different DSP56300

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-13

Specifications

BG1

BG2

250

251

250+251

Figure 2-12. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a DSP56300 part may assume mastership and assert

BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once

BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If is asserted and Therefore, some non-overlap period between one

BB is deasserted, another DSP56300 component may assume mastership at the same time.

BG input active to another BG input active is required. Timing 251

BG input is asserted before that time, and BG

ensures that overlaps are avoided.

2.4.6 Host Interface Timing

No. Characteristic

317 Read data strobe assertion width

HACK assertion width

318 Read data strobe deassertion width

HACK

deassertion width

319 Read data strobe deassertion width

“Last Data Register” reads consecutive CVR, ICR, or ISR reads HACK deassertion width after “Last Data Register” reads

320 Write data strobe assertion width

321 Write data strobe deassertion width

HACK write deassertion width

• after ICR, CVR and “Last Data Register” writes

• after IVR writes, or after TXH:TXM:TXL writes (with HLEND=

0), or after TXL:TXM:TXH writes (with HLEND =

322 HAS

assertion width 4.95 — 4.5 — 4.13 — 4.0 — ns

8,11

, or between two

Table 2-10. Host Interface Timings

200 MHz 220 MHz 240 MHz 275 MHz

Expression

Min Max Min Max Min Max Min Max

after

+ 4.95 9.95 — 9.05 — 8.3 — 7.77 — ns

4.95 — 4.5 — 4.13 — 4.0 — ns

2.5 × TC + 3.3 15.8 — 14.7 — 13.7 — 12.39 — ns

6.6 — 6.0 — 5.5 — 5.1 — ns

2.5 × T

+ 3.3 15.8

8.25——

1,2,12

14.7

7.5——

13.7

6.88——

Uni

12.39

6.28——nsns

DSP56321 Technical Data, Rev. 11

2-14 Freescale Semiconductor

AC Electrical Characteristics

Table 2-10. Host Interface Timings

No. Characteristic

323 HAS deassertion to data strobe assertion

324 Host data input setup time before write data

strobe deassertion

325 Host data input hold time after write data

strobe deassertion

326 Read data strobe assertion to output data

active from high impedance HACK assertion to output data active from high impedance

327 Read data strobe assertion to output data

valid HACK

assertion to output data valid

328 Read data strobe deassertion to output data

high impedance HACK

deassertion to output data high

impedance

329 Output data hold time after read data strobe

deassertion Output data hold time after HACK

330 HCS assertion to read data strobe

deassertion

331 HCS

assertion to write data strobe

deassertion

332 HCS

333 HCS

assertion to output data valid — 17 — 16 — 15 — 14 ns

hold time after data strobe deassertion

334 Address (HAD[0–7]) setup time before HAS

deassertion (HMUX=1)

335 Address (HAD[0–7]) hold time after HAS

deassertion (HMUX=1)

336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0),

HR/W

setup time before data strobe assertion

•Read

•Write

337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0),

HR/W

hold time after data strobe deassertion

338 Delay from read data strobe deassertion to

host request assertion for “Last Data Register”

5, 7, 8

read

339 Delay from write data strobe deassertion to

host request assertion for “Last Data Register”

6, 7, 8

write

340 Delay from data strobe assertion to host

request deassertion for “Last Data Register” read or write (HROD=0)

341 Delay from data strobe assertion to host

request deassertion for “Last Data Register” read or write (HROD=1, open drain host

4, 7, 8, 9

request)

deassertion

4, 7, 8

1,2,12

(Continued)

200 MHz 220 MHz 240 MHz 275 MHz

Expression

Min Max Min Max Min Max Min Max

0.0 — 0.0 — 0.0 — 0.0 — ns

4.95 — 4.5 — 4.13 — 4.0 — ns

1.65 — 1.5 — 1.38 — 1.23 — ns

— 14.78 — 13.45 — 12.32 — 10.2 ns

— 4.95 — 4.5 — 4.13 4.0 — ns

1.65 — 1.5 — 1.38 — 1.23 — ns

TC + 4.95 9.95 — 9.05 — 8.3 — 7.77 — ns

8—8—8—8—ns

TC + 2.64 7.64 — 7.19 — 6.81 — 6.28 — ns

1.5 × TC +

2.64

0.0 — 0.0 — 0.0 — 0.0 — ns

2.31 — 2.1 — 1.93 — 1.76 — ns

1.65 — 1.5 — 1.38 — 1.23 — ns

2.31——02.1——01.93——01.76——nsns

1.65 — 1.5 — 1.38 — 1.23 — ns

10.14 — 9.47 — 8.9 — 8.1 — ns

— 12.14 — 11.04 — 10.12 — 9.0 ns

—300.0—300.0—300.0—300.0ns

Uni

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-15

Specifications

1,2,12

No. Characteristic

Table 2-10. Host Interface Timings

Expression

200 MHz 220 MHz 240 MHz 275 MHz

Min Max Min Max Min Max Min Max

Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. This timing is applicable only if two consecutive reads from one of these registers are executed.

4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the

Single Data Strobe mode.

5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.

8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is

RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1).

9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.

10. V

11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers

12. After the external host writes a new value to the ICR, the HI08 will be ready for operation after three DSP clock cycles (3 × Tc).

= 3.3 V ± 0.3 V, V

CCQH

without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF

CCQL

317 318

(Continued)

DSP56321 Reference Manual

Uni

HACK

H[0–7]

HREQ

328

326

327

329

Figure 2-13. Host Interrupt Vector Register (IVR) Read Timing Diagram

DSP56321 Technical Data, Rev. 11

2-16 Freescale Semiconductor

HA[2–0]

HCS

HRW

HDS

336

332

330

AC Electrical Characteristics

337336

333

337

317

318

328

319

H[7–0]

HREQ (single host request)

(double host request)

HRRQ

327

326

340

341

329

338

Figure 2-14. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

337336

330

HCS

317

HRD

328

332 319

333

318

327

326

H[7–0]

340

341

HREQ (single host request)

HRRQ (double host request)

329

338

Figure 2-15. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-17

Specifications

HA[2–0]

HCS

HRW

HDS

H[7–0]

336

324

331

337336

333

337

320

321

325

339

HREQ (single host request)

(double host request)

HTRQ

340

341

Figure 2-16. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe

HA[2–0]

337336

331

HCS

320

HWR

324

H[7–0]

333

321

325

339

HREQ (single host request)

HTRQ

(double host request)

340

341

Figure 2-17. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe

DSP56321 Technical Data, Rev. 11

2-18 Freescale Semiconductor

HA[10–8]

AC Electrical Characteristics

336 337

323

335

327

340

341

337

317

318

319

328

329

326

338

HAS

HRW

HDS

HAD[7–0]

HREQ (single host request)

HRRQ

(double host request)

322

336

334

Address Data

Figure 2-18. Read Timing Diagram, Multiplexed Bus, Single Data Strobe

HA[10–8]

336 337

323

335

327

340

341

317

318

319

328

329

326

338

(single host request)

HREQ

HRRQ

(double host request)

322

HAS

HRD

HAD[7–0]

334

Address Data

Figure 2-19. Read Timing Diagram, Multiplexed Bus, Double Data Strobe

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-19

Specifications

HA[10–8]

HAS

HRW

HDS

HAD[7–0]

HREQ (single host request)

HTRQ (double host request)

322

334

336

335

Address

336

323

320

324

Data

340

341

337

321

325

339

Figure 2-20. Write Timing Diagram, Multiplexed Bus, Single Data Strobe

HA[10–8]

(single host request)

HREQ

HTRQ

(double host request)

HAS

HWR

HAD[7–0]

322

334

335

Address

336

323

320

324

Data

340

341

337

321

325

339

Figure 2-21. Write Timing Diagram, Multiplexed Bus, Double Data Strobe

DSP56321 Technical Data, Rev. 11

2-20 Freescale Semiconductor

2.4.7 SCI Timing

AC Electrical Characteristics

Table 2-11. SCI Timings

No. Characteristics

400 Synchronous clock cycle t

Symbol Expression

SCC

401 Clock low period t

402 Clock high period t

403 Output data setup to

clock falling edge

SCC

(internal clock)

404 Output data hold after

clock rising edge (internal clock)

405 Input data setup time

before clock rising edge

SCC

(internal clock)

406 Input data not valid

before clock rising edge

SCC

(internal clock)

407 Clock falling edge to

output data valid (external clock)

408 Output data hold after

clock rising edge (external clock)

409 Input data setup time

before clock rising edge (external clock)

410 Input data hold time after

clock rising edge (external clock)

411 Asynchronous clock cycle t

ACC

412 Clock low period t

413 Clock high period t

414 Output data setup to

clock rising edge (internal clock)

415 Output data hold after

clock rising edge (internal clock)

Notes: 1. V

2. t

3. t

4. In the timing diagrams that follow, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity is

= 3.3 V ± 0.3 V, V

CCQH

= synchronous clock cycle time (for internal clock, t

SCC

= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t

ACC

control register and T

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.

CCQL

programmable in the SCI Control Register (SCR). Refer to the

200 MHz 220 MHz 240 MHz 275 MHz

Min Max Min Max Min Max Min Max

16 × T

/2 − 10.0 30.0 — 26.4 — 23.4 — 19.0 — ns

SCC

/2 − 10.0 30.0 — 26.4 — 23.4 — 19.0 — ns

SCC

/4 + 0.5 × TC −17.0 5.5 — 3.5 — 1.76 — –0.68 — ns

/4 − 1.5 × T

SCC

/4 + 0.5 × TC + 25.0 47.5 — 45.5 — 43.8 — 41.32 — ns

/4 + 0.5 × TC − 5.5 — 17.0 — 15.0 — 13.8 — 10.81 ns

+ 8.0 13.0 — 12.6 — 12.2 — 11.64 — ns

64 × T

/2 − 10.0 150.0 — 135.6 — 123.5 — 106.0 — ns

ACC

/2 − 10.0 150.0 — 135.6 — 123.5 — 106.0 — ns

ACC

/2 − 30.0 130.0 — 115.6 — 103.5 — 86.0 — ns

ACC

/2 − 30.0 130.0 — 115.6 — 103.5 — 86.0 — ns

ACC

80.0 — 72.8 — 66.7 — 58.0 — ns

13 — 11.5 — 10 — 9.04 — ns

— 32.0 — 32.0 — 32.0 — 32.0 ns

0.0 — 0.0 — 0.0 — 0.0 — ns

9.0 — 9.0 — 9.0 — 9.0 — ns

320.0 — 291.2 — 266.9 — 232.0 — ns

is determined by the SCI clock control register and TC).

SCC

DSP56321 Reference Manual

is determined by the SCI clock

ACC

for details.

Uni

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-21

Specifications

SCLK

(Output)

403

401

400

402

404

TXD

RXD

SCLK

(Input)

TXD

RXD

Data Valid

405

406

Data Valid

a) Internal Clock

Data Valid

b) External Clock

Figure 2-22. SCI Synchronous Mode Timing

Figure 2-23. SCI Asynchronous Mode Timing

DSP56321 Technical Data, Rev. 11

2-22 Freescale Semiconductor

AC Electrical Characteristics

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-23

Specifications

Table 2-12. ESSI Timings (Continued)

200 MHz 220 MHz 240 MHz 275 MHz

No. Characteristics

4, 6

Symbol Expression

Min Max Min Max Min Max Min Max

451 TXC rising edge to FST out (word-

length) low

452 TXC rising edge to data out enable from

high impedance

453 TXC rising edge to Transmitter 0 drive

enable assertion

454 TXC rising edge to data out valid ——12.5

455 TXC rising edge to data out high

impedance

456 TXC rising edge to Transmitter 0 drive

enable deassertion

457 FST input (bl, wr) setup time before

TXC falling edge

458 FST input (wl) to data out enable from

high impedance

459 FST input (wl) to Transmitter 0 drive

enable assertion

460 FST input (wl) setup time before TXC

falling edge

461 FST input hold time after TXC falling

edge

462 Flag output valid after TXC rising edge ——12.5

——12.5

8.3——

——12.5

8.3——

——12.5

13.5——

8.3——

——30.0

8.3——

——12.5

8.3——

5.0

10.0——

——15.0

8.0——

——15.0

18.0——

5.0

10.0——

3.8

5.0——

8.3——

12.5

8.3——

12.5

8.3——

12.5

13.5——

12.5

8.3——

30.0

8.3——

12.5

8.3——

5.0

10.0——

15.0

8.0——

15.0

18.0——

5.0

10.0——

3.8

5.0——

12.5

8.3——

12.5

8.3——

12.5

8.3——

12.5

13.5——

12.5

8.3——

30.0

8.3——

12.5

8.3——

5.0

10.0——

15.0

8.0——

15.0

18.0——

5.0

10.0——

3.8

5.0——

12.5

8.3——

5.0

10.0——

5.0

10.0——

3.8

5.0——

12.5

8.3

12.5

8.3

12.5

13.5

12.5

8.3

30.0

8.3

12.5

8.3

15.0

8.0

15.0

18.0

12.5

8.3

Cond-

ition

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

Unit

Notes: 1. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-4) and the

ESSI control register. T

Manual

. T

must be ≥ TC × 4, in accordance with the explanation of CRA[PSR] and the

Block Diagram

ECCI

shown in Figure 7-3 of the

must be ≥ TC × 3, in accordance with the note below Table 7-1 in the

ECCX

DSP56321 Reference Manual

DSP56321 Reference

ESSI Clock Generator Functional

2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit clock of the first word in the frame.

3. Periodically sampled and not 100 percent tested

4. V

= 3.3 V ± 0.3 V, V

CCQH

= 1.6 V ± 0.1 V; TJ = 0°C to +85°C, CL = 50 pF

CCQL

5. TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync

6. i ck = Internal Clock; x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock)

7. In the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first reference. Clock and frame sync polarities are programmable in Control Register B (CRB). Refer to the

DSP56321 Reference Manual

for

details.

DSP56321 Technical Data, Rev. 11

2-24 Freescale Semiconductor

TXC

(Input/

Output)

FST (Bit)

Out

FST (Word)

Out

431

AC Electrical Characteristics

430

432

446 447

450 451

454454

452

Last Bit

456453

See Note

460

First Bit

461

462

Data Out

459

Transmitter 0

Drive

Enable

457

461

FST (Bit) In

458

FST (Word)

Flags Out

Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In

Normal mode, the output flag state is asserted for the entire frame period.

455

Figure 2-24. ESSI Transmitter Timing

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-25

Specifications

Figure 2-25. ESSI Receiver Timing

2.4.9 Timer Timing

Table 2-13. Timer Timings

No. Characteristics Expression

480

TIO Low

481 TIO High 2 × T

486 Synchronous delay time from Timer input

rising edge to the external memory address out valid caused by the first interrupt instruction execution

Notes: 1. V

2. The maximum frequency of pulses generated by a timer will be defined after device characterization is completed.

3. In the timing diagrams below, TIO is drawn using the rising edge as the reference. TIO polarity is programmable in the Timer

= 3.3 V ± 0.3 V, V

CCQH

Control/Status Register (TCSR). Refer to the

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF

CCQL

2 × TC + 2.0 12.0 — 11.1 — 10.3 — 9.27 — ns

+ 2.0 12.0 — 11.1 — 10.3 — 9.27 — ns

10.25 × T

DSP56321 Reference Manual

200 MHz 220 MHz 240 MHz 240 MHz

Unit

Min Max Min Max Min Max Min Max

+ 10.0 61.25—56.64—52.74—47.27—ns

for details.

DSP56321 Technical Data, Rev. 11

2-26 Freescale Semiconductor

TIO

481480

Figure 2-26. TIO Timer Event Input Restrictions

TIO (Input)

Address

First Interrupt Instruction Execution

Figure 2-27. Timer Interrupt Generation

2.4.10 Considerations For GPIO Use

AC Electrical Characteristics

486

The following considerations can be helpful when GPIO is used.

2.4.10.1 GPIO as Output

• The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core clock cycles, if the instruction is a one-cycle instruction and there are no pipeline stalls or any other pipeline delays.

• The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50 pF load limit is met).

2.4.10.2 GPIO as Input

GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled, this lack of synchronization presents no problem, since the read value can be either the previous value or the new value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if:

• Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded in two bits).

• The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00 to 11 may happen through an intermediate state of 01 or 10).

Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two consecutive read operations have identical results.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-27

Specifications

2.4.11 JTAG Timing

Table 2-14. JTAG Timing

All frequencies

No. Characteristics

Min Max

500 TCK frequency of operation (1/(TC × 3); absolute maximum 22 MHz) 0.0 22.0 MHz

501 TCK cycle time in Crystal mode 45.0 — ns

502 TCK clock pulse width measured at 1.6 V 20.0 — ns

503 TCK rise and fall times 0.0 3.0 ns

504 Boundary scan input data setup time 5.0 — ns

505 Boundary scan input data hold time 24.0 — ns

506 TCK low to output data valid 0.0 40.0 ns

507 TCK low to output high impedance 0.0 40.0 ns

508 TMS, TDI data setup time 5.0 — ns

509 TMS, TDI data hold time 25.0 — ns

510 TCK low to TDO data valid 0.0 44.0 ns

511 TCK low to TDO high impedance 0.0 44.0 ns

512 TRST

513 TRST setup time to TCK low 40.0 — ns

Notes: 1. V

assert time 100.0 — ns

= 3.3 V ± 0.3 V, V

CCQH

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.

CCQL

Unit

TCK

(Input)

501

502

M V

502

503503

Figure 2-28. Test Clock Input Timing Diagram

DSP56321 Technical Data, Rev. 11

2-28 Freescale Semiconductor

AC Electrical Characteristics

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Data

Outputs

TCK

(Input)

TDI

TMS

(Input)

Input Data Valid

506

Output Data Valid

507

506

Output Data Valid

Figure 2-29. Boundary Scan (JTAG) Timing Diagram

508

Input Data Valid

510

505504

509

TDO

(Output)

TDO

(Output)

TDO

(Output)

TCK

(Input)

TRST

(Input)

Output Data Valid

511

510

Output Data Valid

Figure 2-30. Test Access Port Timing Diagram

513

512

Figure 2-31. TRST Timing Diagram

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 2-29

Specifications

2.4.12 OnCE Module TimIng

Table 2-15. OnCE Module Timing

All Frequencies

No. Characteristics Expression

Min Max

500 TCK frequency of operation (1/(TC × 3); maximum 22 MHz) Max 22.0 MHz 0.0 22.0 MHz

514 DE

515 Response time when DSP56321 is executing NOP instructions from

516 Debug acknowledge assertion time 3 × T

Note: V

assertion time in order to enter Debug mode 1.5 × TC + 10.0 20.0 — ns

internal memory

= 3.3 V ± 0.3 V, V

CCQH

= 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF

CCQL

514

5.5 × T

+ 30.0 — 67.0 ns

+ 5.0 25.0 — ns

516515

Unit

Figure 2-32. OnCE—Debug Request

DSP56321 Technical Data, Rev. 11

2-30 Freescale Semiconductor

Packaging 3

This section includes diagrams of the DSP56321 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56321 is available in a 196-pin molded array plastic-ball grid array (MAP-BGA) package.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 3-1

Packaging

3.1 Package Description

Top and bottom views of the MAP-BGA packages are shown in Figure 3-1 and Figure 3-2 with their pin-outs.

Top View

1342567810 141312119

SC11

SRD1

SC02

PINIT

STD0

RXD

SCK1 TXD

CCQH

HACK

CCS

SC12

STD1

SC01

CCS

SCLK

CCQL

HRW

HREQ

TDI

TCK

SRD0

SC00SC10

SCK0

HDS

TIO2

IRQB D23

TDOTMS

TRST

IRQA

IRQD

IRQC

GNDGND

GND GND

GND

GND GND

GND

D21 D20 D17

D22

CCQL

GND

GND GND GND GND GND

GND GND

GND

GND GND GND

GND GNDGND

D19

CCD

D18 V

GND

D16 D14

D15

CCD

GND

GNDGNDGND

GND

GNDGNDGNDGND

D13 D10 D8

D12

D11

CCD

GND

A14

CCQL

D2D1

D6 D4

A17 A16

CCQH

A13

CCA

CCD

A15

A12

A11A10

A9A8

HCS

HA1 HA2

TIO1

TIO0

HA0

H5 NC

GND GND

CCH

H4H6 V

RESET

GND

CCQL

CCQH

AA2GNDNC

EXTAL

NCAA3

XTAL

Res’d

CCQL

CCC

GNDGNDGNDGND

GND

BRRes’d

RDWR

AA1

CCA

CCC

A1 A2

AA0

Figure 3-1. DSP56321 MAP-BGA Package, Top View

DSP56321 Technical Data, Rev. 11

A4A3

3-2 Freescale Semiconductor

Package Description

Figure 3-2. DSP56321 MAP-BGA Package, Bottom View

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 3-3

Packaging

Table 3-1. Signal List by Ball Number

Ball

No.

A1 Not Connected (NC) B12 D8 D9 GND

A2 SC11 or PD1 B13 D5 D10 GND

A3 TMS B14 NC D11 GND

A4 TDO C1 SC02 or PC2 D12 D1

A5 MODB/IRQB

A6 D23 C3 TCK D14 V

A7 V

A8 D19 C5 MODC/IRQC

A9 D16 C6 D22 E3 SRD0 or PC4

A10 D14 C7 V

A11 D11 C8 D18 E5 GND

A12 D9 C9 V

A13 D7 C10 D12 E7 GND

CCD

Signal Name

Ball

No.

C2 STD1 or PD5 D13 D2

C4 MODA/IRQA E1 STD0 or PC5

Signal Name

CCQL

CCD

Ball

No.

E2 V

E4 GND

E6 GND

CCD

CCS

Signal Name

A14 NC C11 V

B1 SRD1 or PD4 C12 D6 E9 GND

B2 SC12 or PD2 C13 D3 E10 GND

B3 TDI C14 D4 E11 GND

B4 TRST

B5 MODD/IRQD

B6 D21 D3 DE

B7 D20 D4 GND F1 RXD or PE0

B8 D17 D5 GND F2 SC10 or PD0

B9 D15 D6 GND F3 SC00 or PC0

B10 D13 D7 GND F4 GND

B11 D10 D8 GND F5 GND

D1 PINIT/NMI E12 A17

D2 SC01 or PC1 E13 A16

CCD

E8 GND

E14 D0

DSP56321 Technical Data, Rev. 11

3-4 Freescale Semiconductor

Table 3-1. Signal List by Ball Number (Continued)

Package Description

Ball

No.

F6 GND H3 SCK0 or PC3 J14 A9

F7 GND H4 GND K1 V

F8 GND H5 GND K2 HREQ/HREQ,

F9 GND H6 GND K3 TIO2

F10 GND H7 GND K4 GND

F11 GND H8 GND K5 GND

F12 V

F13 A14 H10 GND K7 GND

F14 A15 H11 GND K8 GND

G1 SCK1 or PD3 H12 V

G2 SCLK or PE2 H13 A10 K10 GND

G3 TXD or PE1 H14 A11 K11 GND

G4 GND J1 HACK

CCQH

Signal Name

Ball

No.

H9 GND K6 GND

HRRQ

Signal Name

CCA

/HACK,

/HRRQ, or PB15

Ball

No.

HTRQ

K9 GND

K12 V

Signal Name

CCS

/HTRQ, or PB14

CCA

G5 GND J2 HRW, HRD/HRD, or PB11 K13 A5

G6 GND J3 HDS

G7 GND J4 GND L1 HCS

G8 GND J5 GND L2 TIO1

G9 GND J6 GND L3 TIO0

G10 GND J7 GND L4 GND

G11 GND J8 GND L5 GND

G12 A13 J9 GND L6 GND

G13 V

G14 A12 J11 GND L8 GND

H1 V

H2 V

CCQL

CCQH

CCQL

J10 GND L7 GND

J12 A8 L9 GND

J13 A7 L10 GND

/HDS, HWR/HWR, or PB12 K14 A6

/HCS, HA10, or PB13

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 3-5

Packaging

Table 3-1. Signal List by Ball Number (Continued)

Ball

No.

L11 GND M13 A1 P1 NC

L12 V

L13 A3 N1 H6, HAD6, or PB6 P3 H3, HAD3, or PB3

L14 A4 N2 H7, HAD7, or PB7 P4 H1, HAD1, or PB1

M1 HA1, HA8, or PB9 N3 H4, HAD4, or PB4 P5 NC

M2 HA2, HA9, or PB10 N4 H2, HAD2, or PB2 P6 GND

M3 HA0, HAS

M4 V

M5 H0, HAD0, or PB0 N7 AA3 P9 V

M6 V

M7 V

M8 EXTAL N10 Reserved P12 AA1

M9 Reserved N11 BR

CCA

CCH

CCQL

CCQH

Signal Name

/HAS, or PB8 N5 RESET P7 AA2

Ball

No.

M14 A2 P2 H5, HAD5, or PB5

N6 GND P8 XTAL

N8 NC P10 TA

N9 V

Signal Name

CCQL

Ball

No.

P11 BB

P13 BG

Signal Name

CCC

M10 NC N12 V

M11 WR

M12 RD

Note: Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal

with dual functionality, such as the MODx/IRQx lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS

/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip.

N13 AA0

N14 A0

CCC

pins that select an operating mode after RESET is deasserted but act as interrupt

P14 NC

DSP56321 Technical Data, Rev. 11

3-6 Freescale Semiconductor

Table 3-2. Signal List by Signal Name

Package Description

Signal Name

A0 N14 BR N11 D9 A12

A1 M13 D0 E14 DE

A10 H13 D1 D12 EXTAL M8

A11H14D10B11GNDD4

A12 G14 D11 A11 GND D5

A13G12D12C10GNDD6

A14 F13 D13 B10 GND D7

A15 F14 D14 A10 GND D8

A16 E13 D15 B9 GND D9

A17 E12 D16 A9 GND D10

A2 M14 D17 B8 GND D11

A3 L13 D18 C8 GND E4

A4 L14 D19 A8 GND E5

A5 K13 D2 D13 GND E6

A6 K14 D20 B7 GND E7

A7 J13 D21 B6 GND E8

Ball

No.

Signal Name

Ball

No.

Signal Name

Ball

No.

A8 J12 D22 C6 GND E9

A9 J14 D23 A6 GND E10

AA0N13D3C13GNDE11

AA1 P12 D4 C14 GND F4

AA2 P7 D5 B13 GND F5

AA3 N7 D6 C12 GND F6

P11D7A13GNDF7

P13D8B12GNDF8

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 3-7

Packaging

Table 3-2. Signal List by Signal Name (Continued)

Signal Name

GND F9 GND K4 HA1 M1

GND F10 GND K5 HA10 L1

GND F11 GND K6 HA2 M2

GND G4 GND K7 HA8 M1

GND G5 GND K8 HA9 M2

GND G6 GND K9 HACK

GND G7 GND K10 HAD0 M5

GND G8 GND K11 HAD1 P4

GND G9 GND L4 HAD2 N4

GND G10 GND L5 HAD3 P3

GND G11 GND L6 HAD4 N3

GND H4 GND L7 HAD5 P2

GND H5 GND L8 HAD6 N1

GND H6 GND L9 HAD7 N2

GND H7 GND L10 HAS

GND H8 GND L11 HCS

Ball

No.

Signal Name

Ball

No.

Signal Name

/HACK J1

/HAS M3

/HCS L1

Ball

No.

GND H9 GND N6 HDS

GND H10 GND P6 HRD

GND H11 H0 M5 HREQ

GND J4 H1 P4 HRRQ

GND J5 H2 N4 HRW J2

GND J6 H3 P3 HTRQ

GND J7 H4 N3 HWR

GND J8 H5 P2 IRQA

GND J9 H6 N2 IRQB

GND J10 H7 N2 IRQC

GND J11 HA0 M3 IRQD

/HDS J3

/HRD J2

/HREQ K2

/HRRQ J1

/HTRQ K2

/HWR J3

DSP56321 Technical Data, Rev. 11

3-8 Freescale Semiconductor

Table 3-2. Signal List by Signal Name (Continued)

Package Description

Signal Name

MODA C4 PB4 N3 Reserved M9

MODB A5 PB5 P2 Reserved N10

MODC C5 PB6 N1 RESET

MODD B5 PB7 N2 RXD F1

NC A1 PB8 M3 SC00 F3

NC A14 PB9 M1 SC01 D2

NC B14 PC0 F3 SC02 C1

NC M10 PC1 D2 SC10 F2

NC N8 PC2 C1 SC11 A2

NC P1 PC3 H3 SC12 B2

NC P5 PC4 E3 SCK0 H3

NC P14 PC5 E1 SCK1 G1

NMI

PB0 M5 PD1 A2 SRD0 E3

PB1 P4 PD2 B2 SRD1 B1

PB10 M2 PD3 G1 STD0 E1

Ball

No.

D1 PD0 F2 SCLK G2

Signal Name

Ball

No.

Signal Name

Ball

No.

PB11 J2 PD4 B1 STD1 C2

PB12 J3 PD5 C2 TA

PB13 L1 PE0 F1 TCK C3

PB14 K2 PE1 G3 TDI B3

PB15 J1 PE2 G2 TDO A4

PB2 N4 PINIT D1 TIO0 L3

PB3 P3 RD

M12 TIO1 L2

P10

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 3-9

Packaging

Table 3-2. Signal List by Signal Name (Continued)

Signal Name

Ball

No.

TIO2 K3 V

TMS A3 V

TRST

B4 V

TXD G3 V

CCA

CCC

H12 V

K12 V

L12 V

N12 V

Signal Name

CCC

CCD

CCH

CCQH

Ball

No.

Signal Name

P9 V

A7 V

C9 V

C11 V

D14 V

M4 V

F12 V

H1 WR M11

M7 XTAL P8

3.2 MAP-BGA Package Mechanical Drawing

CCQL

CCS

Ball

No.

G13

Figure 3-3. DSP56321 Mechanical Information, 196-pin MAP-BGA Package

DSP56321 Technical Data, Rev. 11

3-10 Freescale Semiconductor

Design Considerations 4

This section describes various areas to consider when incorporating the DSP56321 device into a system design.

4.1 Thermal Design Considerations

An estimate of the chip junction temperature, TJ, in ° C can be obtained from this equation:

Equation 1:

TJTAPDR

×()+=

θJA

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

θJA

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a caseto-ambient thermal resistance, as in this equation:

Equation 2:

θJARθJCRθCA

Where:

is device-related and cannot be influenced by the user. The user controls the thermal environment to change

θJC

the case-to-ambient thermal resistance, R

= package junction-to-ambient thermal resistance °C/W

θJA

= package junction-to-case thermal resistance °C/W

θJC

= package case-to-ambient thermal resistance °C/W

θCA

. For example, the user can change the air flow around the device, add

θCA

a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from R

do not satisfactorily answer whether the thermal

θJA

performance is adequate, a system-level model may be appropriate.

A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages.

• To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 4-1

Design Considerations

DSP56321 Technical Data, Rev. 11

4-2 Freescale Semiconductor

Power Consumption Considerations

• Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the

and GND circuits.

• All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (

TRST, TMS, DE).

• The following pins must be asserted during the power-up sequence: signal should be supplied before deassertion of

RESET. If the V

RESET and TRST. A stable EXTAL

reaches the required level before

EXTAL is stable or other “required RESET duration” conditions are met (see Tab l e 2- 7 ), the device circuitry can be in an uninitialized state that may result in significant power consumption and heat-up. Designs should minimize this condition to the shortest possible duration.

• Ensure that during power-up, and throughout the DSP56321 operation, the V

voltage level.

CCQL

is always higher or equal to

CCQH

• If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.

• The Port A data bus (

D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the

last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up resistors (such as an MPC8260), the recommended resistor value is 10 KΩ or less. If more than one DSP must be connected in parallel to the other device, the pull-up resistor value requirement changes as follows:

—2 DSPs = 5 KΩ (mask sets 0K91M and 1K91M)/7 KΩ (mask set 0K93M) or less —3 DSPs = 3 KΩ (mask sets 0K91M and 1K91M)/4 KΩ (mask set 0K93M) or less —4 DSPs = 2 KΩ (mask sets 0K91M and 1K91M)/3 KΩ (mask set 0K93M) or less —5 DSPs = 1.5 KΩ (mask sets 0K91M and 1K91M)/2 KΩ (mask set 0K93M) or less —6 DSPs = 1 KΩ (mask sets 0K91M and 1K91M)/1.5 KΩ (mask set 0K93M) or less

Note: Refer to EB610/D DSP56321/DSP56321T Power-Up Sequencing Guidelines for detailed information

about minimizing power consumption during startup.

4.3 Power Consumption Considerations

Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this formula:

Equation 3:

Where:

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4.

ICVf××=

C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle

Example 4-1. Current Consumption

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor 4-3

Design Considerations

⁄

Equation 4:

I 50 10

The maximum internal current (I case operation conditions—not necessarily a real application case. The typical internal current (I

12–

× 3.3× 33× 106× 5.48 mA==

max) value reflects the typical possible switching of the internal buses on best-

CCI

) value

CCItyp

reflects the average switching of the internal buses on typical operating conditions.

Perform the following steps for applications that require very low current consumption:

1. Set the EBD bit when you are not accessing external memory.

2. Minimize external memory accesses, and use internal memory accesses.

3. Minimize the number of pins that are switching.

4. Minimize the capacitive load on the pins.

5. Connect the unused inputs to pull-up or pull-down resistors.

6. Disable unused peripherals.

7. Disable unused pin activity (for example, CLKOUT, XTAL).

One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current-per-MIPS value.

Equation 5:

MIPS

I MHz⁄ I

–()F2 F1–()⁄==

typF2ItypF1

Where:

typF2

typF1

F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2)

= current at F2

= current at F1

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The

degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.

4.4 Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.

DSP56321 Technical Data, Rev. 11

4-4 Freescale Semiconductor

Power Consumption Benchmark A

The following benchmark program evaluates DSP56321 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.

;************************************************************************** ;************************************************************************** ;* * ;* CHECKS Typical Power Consumption * ;* * ;**************************************************************************

page 200,55,0,0,0 nolist

I_VEC EQU $000000; Interrupt vectors for program debug only START EQU $8000; MAIN (external) program starting address INT_PROG EQU $100 ; INTERNAL program memory starting address INT_XDAT EQU $0; INTERNAL X-data memory starting address INT_YDAT EQU $0; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm" INCLUDE "intequ.asm"

list

org P:START

;

movep #$0243FF,x:M_BCR ; ; BCR: Area 3 = 2 w.s (SRAM) ; Default: 2w.s (SRAM) ;

movep #$00000F,x:M_PCTL ; XTAL disable

; ; Load the program ;

move #INT_PROG,r0

move #PROG_START,r1

do #(PROG_END-PROG_START),PLOAD_LOOP

move p:(r1)+,x0

move x0,p:(r0)+

nop PLOAD_LOOP ; ; Load the X-data ;

move #INT_XDAT,r0

move #XDAT_START,r1

do #(XDAT_END-XDAT_START),XLOAD_LOOP

move p:(r1)+,x0

move x0,x:(r0)+ XLOAD_LOOP

; PLL enable

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-1

Power Consumption Benchmark

; ; Load the Y-data ;

move #INT_YDAT,r0

move #YDAT_START,r1

do #(YDAT_END-YDAT_START),YLOAD_LOOP

move p:(r1)+,x0

move x0,y:(r0)+ YLOAD_LOOP ;

jmp INT_PROG

PROG_START

move #$0,r0

move #$0,r4

move #$3f,m0

move #$3f,m4 ;

clr a

clr b

move #$0,x0

move #$0,x1

move #$0,y0

move #$0,y1

bset #4,omr ; ebd ; sbr dor #60,_end

mac x0,y0,ax:(r0)+,x1 y:(r4)+,y1

mac x1,y1,ax:(r0)+,x0 y:(r4)+,y0

add a,b

mac x0,y0,ax:(r0)+,x1

mac x1,y1,a y:(r4)+,y0

move b1,x:$ff _end

bra sbr

nop

nop PROG_END

nop

XDAT_START ;orgx:0

dc $262EB9

dc $86F2FE

dc $E56A5F

dc $616CAC

dc $8FFD75

dc $9210A

dc $A06D7B

dc $CEA798

dc $8DFBF1

dc $A063D6

dc $6C6657

dc $C2A544

dc $A3662D

dc $A4E762

dc $84F0F3

dc $E6F1B0

DSP56321 Technical Data, Rev. 11

A-2 Freescale Semiconductor

XDAT_END

dc $B3829

dc $8BF7AE

dc $63A94F

dc $EF78DC

dc $242DE5

dc $A3E0BA

dc $EBAB6B

dc $8726C8

dc $CA361

dc $2F6E86

dc $A57347

dc $4BE774

dc $8F349D

dc $A1ED12

dc $4BFCE3

dc $EA26E0

dc $CD7D99

dc $4BA85E

dc $27A43F

dc $A8B10C

dc $D3A55

dc $25EC6A

dc $2A255B

dc $A5F1F8

dc $2426D1

dc $AE6536

dc $CBBC37

dc $6235A4

dc $37F0D

dc $63BEC2

dc $A5E4D3

dc $8CE810

dc $3FF09

dc $60E50E

dc $CFFB2F

dc $40753C

dc $8262C5

dc $CA641A

dc $EB3B4B

dc $2DA928

dc $AB6641

dc $28A7E6

dc $4E2127

dc $482FD4

dc $7257D

dc $E53C72

dc $1A8C3

dc $E27540

YDAT_START ;orgy:0

dc $5B6DA

dc $C3F70B

dc $6A39E8

dc $81E801

dc $C666A6

dc $46F8E7

dc $AAEC94

dc $24233D

dc $802732

dc $2E3C83

dc $A43E00

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-3

Power Consumption Benchmark

dc $C2B639

dc $85A47E

dc $ABFDDF

dc $F3A2C

dc $2D7CF5

dc $E16A8A

dc $ECB8FB

dc $4BED18

dc $43F371

dc $83A556

dc $E1E9D7

dc $ACA2C4

dc $8135AD

dc $2CE0E2

dc $8F2C73

dc $432730

dc $A87FA9

dc $4A292E

dc $A63CCF

dc $6BA65C

dc $E06D65

dc $1AA3A

dc $A1B6EB

dc $48AC48

dc $EF7AE1

dc $6E3006

dc $62F6C7

dc $6064F4

dc $87E41D

dc $CB2692

dc $2C3863

dc $C6BC60

dc $43A519

dc $6139DE

dc $ADF7BF

dc $4B3E8C

dc $6079D5

dc $E0F5EA

dc $8230DB

dc $A3B778

dc $2BFE51

dc $E0A6B6

dc $68FFB7

dc $28F324

dc $8F2E8D

dc $667842

dc $83E053

dc $A1FD90

dc $6B2689

dc $85B68E

dc $622EAF

dc $6162BC

dc $E4A245 YDAT_END

;************************************************************************** ; ; EQUATES for DSP56321 I/O registers and ports ; ;**************************************************************************

page 132,55,0,0,0

opt mex

DSP56321 Technical Data, Rev. 11

A-4 Freescale Semiconductor

ioequ ident 1,0

;-----------------------------------------------------------------------; ; EQUATES for I/O Port Programming ; ;------------------------------------------------------------------------

; Register Addresses

M_HDR EQU $FFFFC9 ; Host port GPIO data Register M_HDDR EQU $FFFFC8 ; Host port GPIO direction Register M_PCRC EQU $FFFFBF ; Port C Control Register M_PRRC EQU $FFFFBE ; Port C Direction Register M_PDRC EQU $FFFFBD ; Port C GPIO Data Register M_PCRD EQU $FFFFAF ; Port D Control register M_PRRD EQU $FFFFAE ; Port D Direction Data Register M_PDRD EQU $FFFFAD ; Port D GPIO Data Register M_PCRE EQU $FFFF9F ; Port E Control register M_PRRE EQU $FFFF9E ; Port E Direction Register M_PDRE EQU $FFFF9D ; Port E Data Register M_OGDB EQU $FFFFFC ; OnCE GDB Register

;-----------------------------------------------------------------------; ; EQUATES for Host Interface ; ;------------------------------------------------------------------------

; Register Addresses

M_HCR EQU $FFFFC2 ; Host Control Register M_HSR EQU $FFFFC3 ; Host Status Register M_HPCR EQU $FFFFC4 ; Host Polarity Control Register M_HBAR EQU $FFFFC5 ; Host Base Address Register M_HRX EQU $FFFFC6 ; Host Receive Register M_HTX EQU $FFFFC7 ; Host Transmit Register

; HCR bits definition M_HRIE EQU $0 ; Host Receive interrupts Enable M_HTIE EQU $1 ; Host Transmit Interrupt Enable M_HCIE EQU $2 ; Host Command Interrupt Enable M_HF2 EQU $3 ; Host Flag 2 M_HF3 EQU $4 ; Host Flag 3

; HSR bits definition M_HRDF EQU $0 ; Host Receive Data Full M_HTDE EQU $1 ; Host Receive Data Empty M_HCP EQU $2 ; Host Command Pending M_HF0 EQU $3 ; Host Flag 0 M_HF1 EQU $4 ; Host Flag 1

; HPCR bits definition M_HGEN EQU $0 ; Host Port GPIO Enable M_HA8EN EQU $1 ; Host Address 8 Enable M_HA9EN EQU $2 ; Host Address 9 Enable M_HCSEN EQU $3 ; Host Chip Select Enable M_HREN EQU $4 ; Host Request Enable M_HAEN EQU $5 ; Host Acknowledge Enable M_HEN EQU $6 ; Host Enable

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-5

Power Consumption Benchmark

M_HOD EQU $8 ; Host Request Open Drain mode M_HDSP EQU $9 ; Host Data Strobe Polarity M_HASP EQU $A ; Host Address Strobe Polarity M_HMUX EQU $B ; Host Multiplexed bus select M_HD_HS EQU $C ; Host Double/Single Strobe select M_HCSP EQU $D ; Host Chip Select Polarity M_HRP EQU $E ; Host Request Polarity M_HAP EQU $F ; Host Acknowledge Polarity

;-----------------------------------------------------------------------; ; EQUATES for Serial Communications Interface (SCI) ; ;------------------------------------------------------------------------

; Register Addresses

M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high) M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low) M_SRXH EQU $FFFF9A ; SCI Receive Data Register (high) M_SRXM EQU $FFFF99 ; SCI Receive Data Register (middle) M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low) M_STXA EQU $FFFF94 ; SCI Transmit Address Register M_SCR EQU $FFFF9C ; SCI Control Register M_SSR EQU $FFFF93 ; SCI Status Register M_SCCR EQU $FFFF9B ; SCI Clock Control Register

; SCI Control Register Bit Flags

M_WDS EQU $7 ; Word Select Mask (WDS0-WDS3) M_WDS0 EQU 0 ; Word Select 0 M_WDS1 EQU 1 ; Word Select 1 M_WDS2 EQU 2 ; Word Select 2 M_SSFTD EQU 3 ; SCI Shift Direction M_SBK EQU 4 ; Send Break M_WAKE EQU 5 ; Wakeup Mode Select M_RWU EQU 6 ; Receiver Wakeup Enable M_WOMS EQU 7 ; Wired-OR Mode Select M_SCRE EQU 8 ; SCI Receiver Enable M_SCTE EQU 9 ; SCI Transmitter Enable M_ILIE EQU 10 ; Idle Line Interrupt Enable M_SCRIE EQU 11 ; SCI Receive Interrupt Enable M_SCTIE EQU 12 ; SCI Transmit Interrupt Enable M_TMIE EQU 13 ; Timer Interrupt Enable M_TIR EQU 14 ; Timer Interrupt Rate M_SCKP EQU 15 ; SCI Clock Polarity M_REIE EQU 16 ; SCI Error Interrupt Enable (REIE)

; SCI Status Register Bit Flags

M_TRNE EQU 0 ; Transmitter Empty M_TDRE EQU 1 ; Transmit Data Register Empty M_RDRF EQU 2 ; Receive Data Register Full M_IDLE EQU 3 ; Idle Line Flag M_OR EQU 4 ; Overrun Error Flag M_PE EQU 5 ; Parity Error M_FE EQU 6 ; Framing Error Flag M_R8 EQU 7 ; Received Bit 8 (R8) Address

; SCI Clock Control Register

DSP56321 Technical Data, Rev. 11

A-6 Freescale Semiconductor

M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11) M_COD EQU 12 ; Clock Out Divider M_SCP EQU 13 ; Clock Prescaler M_RCM EQU 14 ; Receive Clock Mode Source Bit M_TCM EQU 15 ; Transmit Clock Source Bit

;-----------------------------------------------------------------------; ; EQUATES for Synchronous Serial Interface (SSI) ; ;------------------------------------------------------------------------

; ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0 M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1 M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2 M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B

; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0 M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1 M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2 M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B

; SSI Control Register A Bit Flags

M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7) M_PSR EQU 11 ; Prescaler Range M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7) M_ALC EQU 18 ; Alignment Control (ALC) M_WL EQU $380000 ; Word Length Control Mask (WL0-WL7) M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1)

; SSI Control Register B Bit Flags

M_OF EQU $3 ; Serial Output Flag Mask M_OF0 EQU 0 ; Serial Output Flag 0 M_OF1 EQU 1 ; Serial Output Flag 1 M_SCD EQU $1C ; Serial Control Direction Mask M_SCD0 EQU 2 ; Serial Control 0 Direction M_SCD1 EQU 3 ; Serial Control 1 Direction M_SCD2 EQU 4 ; Serial Control 2 Direction M_SCKD EQU 5 ; Clock Source Direction M_SHFD EQU 6 ; Shift Direction M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1) M_FSL0 EQU 7 ; Frame Sync Length 0

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-7

Power Consumption Benchmark

M_FSL1 EQU 8 ; Frame Sync Length 1 M_FSR EQU 9 ; Frame Sync Relative Timing M_FSP EQU 10 ; Frame Sync Polarity M_CKP EQU 11 ; Clock Polarity M_SYN EQU 12 ; Sync/Async Control M_MOD EQU 13 ; SSI Mode Select M_SSTE EQU $1C000 ; SSI Transmit enable Mask M_SSTE2 EQU 14 ; SSI Transmit #2 Enable M_SSTE1 EQU 15 ; SSI Transmit #1 Enable M_SSTE0 EQU 16 ; SSI Transmit #0 Enable M_SSRE EQU 17 ; SSI Receive Enable M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable M_SSRIE EQU 19 ; SSI Receive Interrupt Enable M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable M_SREIE EQU 23 ; SI Receive Error Interrupt Enable

; SSI Status Register Bit Flags

M_IF EQU $3 ; Serial Input Flag Mask M_IF0 EQU 0 ; Serial Input Flag 0 M_IF1 EQU 1 ; Serial Input Flag 1 M_TFS EQU 2 ; Transmit Frame Sync Flag M_RFS EQU 3 ; Receive Frame Sync Flag M_TUE EQU 4 ; Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full

; SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15)

; SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)

; SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15)

; SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31)

;-----------------------------------------------------------------------; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------

; Register Addresses

M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral

; Interrupt Priority Register Core (IPRC)

M_IAL EQU $7 ; IRQA Mode Mask

DSP56321 Technical Data, Rev. 11

A-8 Freescale Semiconductor

M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low) M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL EQU $38 ; IRQB Mode Mask M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low) M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high) M_IBL2 EQU 5 ; IRQB Mode Trigger Mode M_ICL EQU $1C0 ; IRQC Mode Mask M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low) M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high) M_ICL2 EQU 8 ; IRQC Mode Trigger Mode M_IDL EQU $E00 ; IRQD Mode Mask M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level (low) M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level (high) M_IDL2 EQU 11 ; IRQD Mode Trigger Mode M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low) M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high) M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low) M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high) M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low) M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high) M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low) M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high) M_D4L EQU $300000 ; DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) M_D5L EQU $C00000 ; DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low) M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)

; Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3 ; Host Interrupt Priority Level Mask M_HPL0 EQU 0 ; Host Interrupt Priority Level (low) M_HPL1 EQU 1 ; Host Interrupt Priority Level (high) M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low) M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high) M_S1L EQU $30 ; SSI1 Interrupt Priority Level Mask M_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low) M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high) M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low) M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high) M_T0L EQU $300 ; TIMER Interrupt Priority Level Mask M_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low) M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high)

;-----------------------------------------------------------------------; ; EQUATES for TIMER ; ;------------------------------------------------------------------------

; Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F ; Timer 0 Control/Status Register

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-9

Power Consumption Benchmark

M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg M_TCPR0 EQU $FFFF8D ; TIMER0 Compare Register M_TCR0 EQU $FFFF8C ; TIMER0 Count Register

; Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B ; TIMER1 Control/Status Register M_TLR1 EQU $FFFF8A ; TIMER1 Load Reg M_TCPR1 EQU $FFFF89 ; TIMER1 Compare Register M_TCR1 EQU $FFFF88 ; TIMER1 Count Register

; Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87 ; TIMER2 Control/Status Register M_TLR2 EQU $FFFF86 ; TIMER2 Load Reg M_TCPR2 EQU $FFFF85 ; TIMER2 Compare Register M_TCR2 EQU $FFFF84 ; TIMER2 Count Register M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register

; Timer Control/Status Register Bit Flags

M_TE EQU 0 ; Timer Enable M_TOIE EQU 1 ; Timer Overflow Interrupt Enable M_TCIE EQU 2 ; Timer Compare Interrupt Enable M_TC EQU $F0 ; Timer Control Mask (TC0-TC3) M_INV EQU 8 ; Inverter Bit M_TRM EQU 9 ; Timer Restart Mode M_DIR EQU 11 ; Direction Bit M_DI EQU 12 ; Data Input M_DO EQU 13 ; Data Output M_PCE EQU 15 ; Prescaled Clock Enable M_TOF EQU 20 ; Timer Overflow Flag M_TCF EQU 21 ; Timer Compare Flag

; Timer Prescaler Register Bit Flags

M_PS EQU $600000 ; Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22

; Timer Control Bits M_TC0 EQU 4 ; Timer Control 0 M_TC1 EQU 5 ; Timer Control 1 M_TC2 EQU 6 ; Timer Control 2 M_TC3 EQU 7 ; Timer Control 3

;-----------------------------------------------------------------------; ; EQUATES for Direct Memory Access (DMA) ; ;------------------------------------------------------------------------

; Register Addresses Of DMA M_DSTR EQU FFFFF4 ; DMA Status Register M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0 M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1 M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2 M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3

DSP56321 Technical Data, Rev. 11

A-10 Freescale Semiconductor

; Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register M_DCO0 EQU $FFFFED ; DMA0 Counter M_DCR0 EQU $FFFFEC ; DMA0 Control Register

; Register Addresses Of DMA1

M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register M_DCO1 EQU $FFFFE9 ; DMA1 Counter M_DCR1 EQU $FFFFE8 ; DMA1 Control Register

; Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register

; Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register M_DCO3 EQU $FFFFE1 ; DMA3 Counter M_DCR3 EQU $FFFFE0 ; DMA3 Control Register

; Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Register

; Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register M_DCO5 EQU $FFFFD9 ; DMA5 Counter M_DCR5 EQU $FFFFD8 ; DMA5 Control Register

; DMA Control Register

M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 EQU 0 ; DMA Source Memory space 0 M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 EQU 2 ; DMA Destination Memory Space 0 M_DDS1 EQU 3 ; DMA Destination Memory Space 1 M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 EQU 4 ; DMA Address Mode 0 M_DAM1 EQU 5 ; DMA Address Mode 1 M_DAM2 EQU 6 ; DMA Address Mode 2 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode M_DRS EQU $F800 ; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000 ; DMA Channel Priority

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-11

Power Consumption Benchmark

M_DPR0 EQU 17 ; DMA Channel Priority Level (low) M_DPR1 EQU 18 ; DMA Channel Priority Level (high) M_DTM EQU $380000 ; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 EQU 19 ; DMA Transfer Mode 0 M_DTM1 EQU 20 ; DMA Transfer Mode 1 M_DTM2 EQU 21 ; DMA Transfer Mode 2 M_DIE EQU 22 ; DMA Interrupt Enable bit M_DE EQU 23 ; DMA Channel Enable bit

; DMA Status Register

M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5) M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0 M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1 M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2 M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5 M_DACT EQU 8 ; DMA Active State M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2) M_DCH0 EQU 9 ; DMA Active Channel 0 M_DCH1 EQU 10 ; DMA Active Channel 1 M_DCH2 EQU 11 ; DMA Active Channel 2

;-----------------------------------------------------------------------; ; EQUATES for Enhanced Filter Co-Processor (EFCOP) ; ;------------------------------------------------------------------------

M_FDIR EQU $FFFFB0 ; EFCOP Data Input Register M_FDOR EQU $FFFFB1 ; EFCOP Data Output Register M_FKIR EQU $FFFFB2 ; EFCOP K-Constant Register M_FCNT EQU $FFFFB3 ; EFCOP Filter Counter M_FCSR EQU $FFFFB4 ; EFCOP Control Status Register M_FACR EQU $FFFFB5 ; EFCOP ALU Control Register M_FDBA EQU $FFFFB6 ; EFCOP Data Base Address M_FCBA EQU $FFFFB7 ; EFCOP Coefficient Base Address M_FDCH EQU $FFFFB8 ; EFCOP Decimation/Channel Register

;----------------------------------------------------------------------; ; EQUATES for Phase Locked Loop (PLL) ; ;----------------------------------------------------------------------

; Register Addresses Of PLL

M_DMFR EQU $FFFFD0 M_DPSC EQU $FFFFD0 M_PCTL EQU $FFFFD1 ; PLL Control Register

; PLL Control Register

M_MFI EQU $F ; Multiplication Factor Intager Bits Mask (MFI0-MFI3) M_MFN EQU $7F0 ; Multiplication Factor Bits Mask (MFN0-MFN6) M_MFD EQU $3F800 ; Multiplication Factor Bits Mask (MFD0-MFD6) M_PDF EQU $3C0000 ; PreDivider Factor Bits Mask (PD0-PD3) M_CPLM EQU 22 ; M_MFO EQU 23 ; M_CDF EQU $70 ; Division Factor Bits Mask (DF0-DF2)

DSP56321 Technical Data, Rev. 11

A-12 Freescale Semiconductor

M_PCOD EQU 0 ; PLL Clock Output Disable Bit M_PSTP EQU 1 ; STOP Processing State Bit M_XTLD EQU 2 ; XTAL Disable Bit M_PEN EQU 3 ; PLL Enable Bit

;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;------------------------------------------------------------------------

; Register Addresses Of BIU

M_BCR EQU $FFFFFB ; Bus Control Register M_DCR EQU $FFFFFA ; DRAM Control Register M_AAR0 EQU $FFFFF9 ; Address Attribute Register 0 M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2 M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3 M_IDR EQU $FFFFF5 ; ID Register

; Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4) M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 ; Bus State M_BLH EQU 22 ; Bus Lock Hold M_BRH EQU 23 ; Bus Request Hold

; DRAM Control Register

M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7) M_BRP EQU 23 ; Refresh prescaler

; Address Attribute Registers

M_BAT EQU $3 ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) M_BAAP EQU 2 ; Address Attribute Pin Polarity M_BPEN EQU 3 ; Program Space Enable M_BXEN EQU 4 ; X Data Space Enable M_BYEN EQU 5 ; Y Data Space Enable M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BAC EQU $FFF000 ; Address to Compare Bits Mask (BAC0-BAC11)

; control and status bits in SR

M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-13

Power Consumption Benchmark

M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ; Unnormalized M_E EQU 5 ; Extension M_L EQU 6 ; Limit M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ; DO-Loop Flag M_FV EQU 16 ; DO-Forever Flag M_SA EQU 17 ; Sixteen-Bit Arithmetic M_CE EQU 19 ; Instruction Cache Enable M_SM EQU 20 ; Arithmetic Saturation M_RM EQU 21 ; Rounding Mode M_CP0 EQU 22 ; bit 0 of priority bits in SR M_CP1 EQU 23 ; bit 1 of priority bits in SR

; control and status bits in OMR M_CDP EQU $300; mask for CORE-DMA priority bits in OMR M_MA equ0 ; Operating Mode A M_MB equ1 ; Operating Mode B M_MC equ2 ; Operating Mode C M_MD equ3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_MS EQU 7 ; Memory Switch bit in OMR M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ATE EQU 15 ; Address Tracing Enable bit in OMR. M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. M_WRP EQU 19 ; Extended WRaP flag in OMR. M_SEN EQU 20 ; Stack Extension Enable bit in OMR.

;************************************************************************* ; ; EQUATES for DSP56321 interrupts ; ;*************************************************************************

page 132,55,0,0,0

opt mex

intequ ident 1,0

if @DEF(I_VEC)

;leave user definition as is.

else I_VEC EQU $0

endif

DSP56321 Technical Data, Rev. 11

A-14 Freescale Semiconductor

;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt

;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD

;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5

;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow

;-----------------------------------------------------------------------; ESSI Interrupts ;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data w/ exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data w/ exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data w/ exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data w/ exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot

;-----------------------------------------------------------------------; SCI Interrupts ;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor A-15

Power Consumption Benchmark

;-----------------------------------------------------------------------; HOST Interrupts ;-----------------------------------------------------------------------I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ;----------------------------------------------------------------------; EFCOP Filter Interrupts ;-----------------------------------------------------------------------

I_FDIIE EQU I_VEC+$68 ; EFilter input buffer empty I_FDOIE EQU I_VEC+$6A ; EFilter output buffer full

;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space

DSP56321 Technical Data, Rev. 11

A-16 Freescale Semiconductor

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

Part

Supply

Voltage

DSP56321 1.6 V core

3.3 V I/O

Molded Array Process-Ball Grid Array (MAP-BGA)

Package Type

How to Reach Us:

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Count

Core

Frequency

(MHz)

Solder Spheres Order Number

196 200 Lead-free DSP56321VL200

Lead-bearing DSP56321VF200

220 Lead-free DSP56321VL220

Lead-bearing DSP56321VF220

240 Lead-free DSP56321VL240

Lead-bearing DSP56321VF240

275 Lead-free DSP56321VL275

Lead-bearing DSP56321VF275

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Document Order No.: DSP56321 Rev. 11 2/2005

Freescale DSP56321 Technical Data

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

Data Sheet Conventions

Features

Target Applications

Product Documentation

Signals/Connections 1

1.1 Power

1.2 Ground

1.3 Clock

1.4 External Memory Expansion Port (Port A)

1.4.1 External Address Bus

1.4.2 External Data Bus

1.4.3 External Bus Control

1.5 Interrupt and Mode Control

1.6 Host Interface (HI08)

1.6.1 Host Port Usage Considerations

1.6.2 Host Port Configuration

1.7 Enhanced Synchronous Serial Interface 0 (ESSI0)

1.8 Enhanced Synchronous Serial Interface 1 (ESSI1)

1.9 Serial Communication Interface (SCI)

1.10 Timers

1.11 JTAG and OnCE Interface

Specifications 2

2.1 Maximum Ratings

2.2 Thermal Characteristics

2.3 DC Electrical Characteristics

2.4 AC Electrical Characteristics

2.4.1 Internal Clocks

2.4.2 External Clock Operation

2.4.3 Clock Generator (CLKGEN) and Digital PLL (DPLL) Characteristics

2.4.4 Reset, Stop, Mode Select, and Interrupt Timing

2.4.5 External Memory Expansion Port (Port A)

2.4.5.1 SRAM Timing

2.4.5.2 Asynchronous Bus Arbitration Timings

2.4.6 Host Interface Timing

2.4.7 SCI Timing

2.4.9 Timer Timing

2.4.10 Considerations For GPIO Use

2.4.10.1 GPIO as Output

2.4.10.2 GPIO as Input

2.4.11 JTAG Timing

2.4.12 OnCE Module TimIng

Packaging 3

3.1 Package Description

3.2 MAP-BGA Package Mechanical Drawing

Design Considerations 4

4.1 Thermal Design Considerations

4.3 Power Consumption Considerations

4.4 Input (EXTAL) Jitter Requirements

Ordering Information