Freescale 56F8367 User Guide

56F8367

Evaluation Module User Manual

56F8300
16-bit Digital Signal Controllers

MC56F8367EVMUM
Rev. 2
07/2005

freescale.com

Document Revision History

Version History Description of Change

Rev 1.0 Initial Public Release

Rev 2.0 Updated look and feel

TABLE OF CONTENTS

Preface Preface-vii

Chapter 1

Introduction

1.1 56F8367EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 56F8367EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 56F8367EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Chapter 2

Technical Summary

2.1 MC56F8367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.1 EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.2 EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.5.3 CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.6 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.11.1 Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.11.2 Memory Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.12 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Table of Contents, Rev. 2

Freescale Semiconductor i
Preliminary

2.13 CAN Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.13.1 FlexCAN #1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.13.2 FlexCAN #2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.14 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.15.1 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.15.2 Data Bus Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.15.3 External Memory Control Signal Expansion Connector. . . . . . . . . . . . . . . . . . . . . 2-30

2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-30

2.15.5 Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.15.6 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.15.7 Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.15.8 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.15.9 A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-34

2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-35

2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.15.13 FlexCAN #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.15.14 FlexCAN #2 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.15.15 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.15.16 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Appendix A

56F8367EVM Schematics

Appendix B

56F8367EVM Bill of Material

MC56F8367EVM User Manual, Rev. 2

ii Freescale Semiconductor

Preliminary

LIST OF FIGURES

1-1 Block Diagram of the 56F8367EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 MC56F8367 Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1-3 Connecting the 56F8367EVM Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2-1 Schematic Diagram of the External CS0 Memory Interface. . . . . . . . . . . . . . . . . . . 2-5

2-2 Schematic Diagram of the External CS1 / CS4 Memory Interface. . . . . . . . . . . . . . 2-6

2-3 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2-8 Schematic Diagram of the Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2-10 PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2-11 CAN #1 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2-12 CAN #2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2-13 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2-14 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

List of Figures, Rev. 2

Freescale Semiconductor iii
Preliminary

MC56F8367EVM User Manual, Rev. 2

iv Freescale Semiconductor

Preliminary

LIST OF TABLES

1-1 56F8367EVM Default Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 SCI #0 Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-3 EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-4 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-5 EMI Operating Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-6 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-8 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-12

2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-10 Parallel JTAG Interface Voltage Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-14

2-11 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-18

2-12 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2-13 CAN #1 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2-14 CAN #2 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2-15 CAN #2 Pass-Through Jumper Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2-16 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-28

2-17 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-29

2-18 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-30

2-19 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2-20 SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2-21 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2-22 Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2-23 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2-24 A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

2-25 SCI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

List of Tables, Rev. 2

Freescale Semiconductor v
Preliminary

2-26 SCI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2-27 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2-28 CAN #1 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2-29 CAN #2 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2-30 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2-31 PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

MC56F8367EVM User Manual, Rev. 2

vi Freescale Semiconductor

Preliminary

Preface

This reference manual describes in detail the hardware on the 56F8367 Evaluation Module.

Audience

This document is intended for application developers who are creating software for devices using
the Freescale 56F8367 part or a member of the 56F8300 family that is compatible with this part.
Examples would include the 56F8346 and the 56F8357 devices.

Organization

This manual is organized into two chapters and two appendices:

• Chapter 1, Introduction provides an overview of the EVM and its features.

• Chapter 2, Technical Summary describes in detail the 56F8367 hardware.

• Appendix A, "56F8367EVM Schematics"contains the schematics of the
MC56F8367EVM.

• Appendix B, "56F8367EVM Bill of Material" provides a list of the materials used on the

MC56F8367EVM board.

Suggested Reading

More documentation on the 56F8367 and the MC56F8367EVM kit may be found at URL:

www.freescale.com

Preface, Rev. 2

Freescale Semiconductor vii
Preliminary

Notation Conventions

This manual uses the following notational conventions:

Term or Value Symbol Examples Exceptions

Active High Signals
(Logic One)

Active Low Signals
(Logic Zero)

Hexadecimal Values Begin with a “$” sym-

Decimal Values No special symbol

Binary Values Begin with the letter “b”

Numbers Considered positive

Blue Text Linkable on-line ...refer to Chapter 7, License

Bold Reference sources,

No special symbol
attached to the signal
name

Noted with an
overbar in text and in
most figures

bol

attached to the
number

attached to the number

unless specifically
noted as a negative
value

paths, emphasis

A0

CLKO

WE

OE

$0FF0

$80

10
34

b1010

b0011

5

-10

...see: www.freescale.com/

In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE

Voltage is often shown as
positive: +3.3V

MC56F8367EVM User Manual, Rev. 2

viii Freescale Semiconductor

Preliminary

Definitions, Acronyms, and Abbreviations

Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.

A/D Analog-to-Digital; a method of converting Analog signals to Digital values

ADC Analog-to-Digital Converter; a peripheral on the 56F8367 part

CAN Controller Area Network; serial communications peripheral and method

CiA CAN in Automation; an international CAN user’s group that coordinates

standards for CAN communications protocols

D/A Digital-to-Analog; a method of converting Digital values to an Analog form

56F8367

EOnCE

Controller with motor control peripherals

Enhanced On-Chip Emulation; a debug bus and port was created to enable a
designer to create a low-cost hardware interface for a professional-quality
debug environment

EVM

Evaluation Module; a hardware platform which allows a customer to evaluate
the silicon and develop his application

FlexCAN

GPIO

Flexable CAN Interface Module; a peripheral on the 56F8367 part

General Purpose Input and Output port on Freescale’s family of controllers;
does not share pin functionality with any other peripheral on the chip and can
only be set as an input, output or level-sensitive interrupt input

IC

JTAG

LED

Integrated Circuit

Joint Test Action Group; a bus protocol/interface used for test and debug

Light Emitting Diode

LQFP Low-profile Quad Flat Package
MPIO

Multi-Purpose Input and Output port on Freescale’s family of controllers;
shares package pins with other peripherals on the chip and can function as a
GPIO

OnCE

TM

On-Chip Emulation, a debug bus and port created to allow a means for low-cost
hardware to provide a professional-quality debug environment

PCB

PLL

PWM

QuadDec

Freescale Semiconductor ix
Preliminary

Printed Circuit Board

Phase Locked Loop

Pulse Width Modulation

Quadrature Decoder; a peripheral on the 56F8367 part

Preface, Rev. 2

RAM

Random Access Memory

R/C

ROM

SCI

Resistor/Capacitor Network

Read-Only Memory

Serial Communications Interface; a peripheral on Freescale’s family of
controllers

SPI

SRAM

WS

Serial Peripheral Interface; a peripheral on Freescale’s family of controllers

Static Random Access Memory

Wait State

References

The following sources were referenced to produce this manual:

[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor

[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor

[3] 56F8367 Technical Data, MC56F8367, Freescale Semiconductor

[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,

Version 1.0, CAN in Automation

[5] CAN Specification 2.0B, BOSCH or CAN in Automation

MC56F8367EVM User Manual, Rev. 2

x Freescale Semiconductor

Preliminary

Chapter 1 Introduction

The 56F8367EVM is used to demonstrate the abilities of the 56F8367 controller and to provide a
hardware tool allowing the development of applications.

The 56F8367EVM is an evaluation module board that includes a 56F8367 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.

The 56F8367EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56F8367EVM facilitate evaluation of the feature set
and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.

• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
processor is available to the user.

Introduction, Rev. 2

Freescale Semiconductor 1-1
Preliminary

1.1 56F8367EVM Architecture

The 56F8367EVM facilitates the evaluation of various features present in the 56F8367 part. The
56F8367EVM can be used to develop real-time software and hardware products. The
56F8367EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8367EVM is flexible enough to allow a user to fully exploit the 56F8367's
features to optimize the performance of his product, as shown in

Figure 1-1.

DSub

25-Pin

Program Memory

128K x 16-bit

SRAM

Data Memory

128K x 16-bit

SRAM

Memory
Expansion
Connector

Memory

Daughter Card

Connector

Reset Logic

Mode/IRQ

Logic

JTAG

Connector

Parallel

JTAG

Interface

56F8367

Address,
Data &
Control

RESET

MODE/IRQ

JTAG/EOnCE

FlexCAN #1

SCI #0

SPI #0

SCI #1

Timer C

Timer D

PWMA

ADCA

QuadDec #0

PWMB

ADCB

QuadDec #1

FlexCAN #2

CAN #1 Interface

RS-232

Interface

Peripheral
Expansion

Connectors

CAN #2 Interface

Debug LEDs

PWM LEDs

CAN #1 Bus

DaisyChain

CAN #1 Bus

Header

DSub
9-Pin

Peripheral

Daughter Card

Connector

CAN #2 Bus

Header

CAN #2 Bus

DaisyChain

8.00MHz
Crystal

XTAL/
EXTAL

+3.3V & GND

+3.3V A &

AGND

+3.3V

REF

Power Supply

+3.3V, +3.3V A,

+5V & +3.3V

REF

Figure 1-1. Block Diagram of the 56F8367EVM

MC56F8367EVM User Manual, Rev. 2

1-2 Freescale Semiconductor

Preliminary

56F8367EVM Configuration Jumpers

1.2 56F8367EVM Configuration Jumpers

Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the 56F8367EVM board. Table 1-1 describes the default jumper group settings.

3

4

JG14

2

1

JG13

J19

J3

J20

J14

J5

J21

JG13

J22

JG8

JG17

J23

J2

U3

JTAG

U8

S/N

U9

JG3

P3

4

2

JG8

3

1

JG17

JG9

JG12

1

JG15

1

JG16

JG6

JG4

JG5

JG7

3

J18

J16

J13

J15

J14

JG6

JG2

JG1

Y1

J9

MC56F8357EVM

IRQA

J17

J4

JG7

JG5

J24

JG4

U1

S2

U2

JG18

J10

JG19

S1

P1

IRQB

J11

J8

J7

J12

J6

PC0

J1

PC1
PC2
PC3

PD6

3

3

1

4

2

PD7

PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5

JG15

JG9

JG16

JG12

JG10

U4

S3

JG11

P2

LED3

RESET

JG10

JG2

JG11

JG1

1

JG18

3

JG19

1

3

Figure 1-2. MC56F8367 Default Jumper Options

JG3

Introduction, Rev. 2

Freescale Semiconductor 1-3
Preliminary

Table 1-1. 56F8367EVM Default Jumper Options

Jumper

Group

JG1 Use on-board EXTAL crystal input for oscillator 1–2

JG2 Use on-board XTAL crystal input for oscillator 1–2

JG3 Enable on-board Parallel JTAG Host/Target Interface NC

JG4 Enable Internal Boot Mode 1–2

JG5 Enable A0 - A23 for external memory accesses NC

JG6 Enable Crystal Mode 1–2

JG7 Enable SRAM Memory Bank 0 (use CS0) 1–2

JG8 Enable SRAM Memory Bank 1 (use CS1 & CS4) 1–2 & 3–4

JG9 Pass RXD0 & TXD0 to RS-232 level converter 1–2 & 3–4

JG10 Enable RS-232 output NC

JG11 Pass RS-232 RST to CTS 1–2

JG12 Pass Temperature Diode to ANA7 1–2

JG13 CAN #1 termination selected 1–2

JG14 Pass CAN2_TX & CAN2_RX to CAN tranceiver 1–2 & 3–4

JG15 High selected on User Jumper #0 1–2

Comment

Jumpers

Connections

JG16 High selected on User Jumper #1 1–2

JG17 CAN2 termination selected 1–2

JG18 Analog Ground to Digital Ground not reconnected NC

JG19 Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target 1-2

MC56F8367EVM User Manual, Rev. 2

1-4 Freescale Semiconductor

Preliminary

56F8367EVM Connections

1.3 56F8367EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the 56F8367EVM board.

Parallel extension

cable

MC56F8367EVM
PC-compatible
computer

P1

Connect cable

to parallel / printer port

External

+12V

power

P3

with 2.1mm,
receptacle
connector

Figure 1-3. Connecting the 56F8367EVM Cables

Perform the following steps to connect the 56F8367EVM cables:

1. Connect the parallel extension cable to the parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56F8367EVM board. This provides the connection which allows the host computer to
control the board.

3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.

4. Connect the 2.1mm output power plug from the external power supply into P3, shown in

Figure 1-3, on the 56F8367EVM board.

5. Apply power to the external power supply. The green Power-On LED, LED13, will
illuminate when power is correctly applied.

Introduction, Rev. 2

Freescale Semiconductor 1-5
Preliminary

MC56F8367EVM User Manual, Rev. 2

1-6 Freescale Semiconductor

Preliminary

Chapter 2 Technical Summary

The 56F8367EVM is designed as a versatile development card using the 56F8367 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8367
processor, combined with the on-board 128K x 16-bit external Program/Data Static RAM
(SRAM), 128K x 16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
daughter card interface, peripheral expansion connectors and parallel JTAG interface, makes the
56F8367EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8367 processor.

The main features of the 56F8367EVM, with board and schematic reference designators, include:

• MC56F8367VPY60, a 16-bit +3.3V/+2.5V controller operating at 60MHz [U1]

• External Fast Static RAM (FSRAM) memory, configured as:

— 128K x 16-bit of memory [U2] with 0 wait state at 60MHz via CS0

— 128K x 16-bit of memory [U3] with 0 wait state at 60MHz via CS1/CS4

• 8.00MHz crystal oscillator, for base processor frequency generation [Y1]

• Optional external oscillator frequency input connectors [JG1 and JG2]

• Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]

• On-board parallel JTAG host target interface, with a connector for a PC printer port cable
[P1], including a disable jumper [JG3] and a printer port voltage selection jumper [JG19]

• RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]

• RTS and CTS RS-232 control signal access [JG11]

• CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]

• CAN bypass and bus termination [J21 and JG13]

Technical Summary, Rev. 2

Freescale Semiconductor 2-1
Preliminary

• CAN #2 interface, for high speed, 1.0Mbps, FlexCAN communications [U11 and J22]

• CAN #2 bypass and bus termination [J23 and JG17]

• CAN #2 interface signal isolation [JG14]

• Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the controller [J1]

• Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]

• SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]

• SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]

• SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]

• SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]

• PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]

• PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]

• CAN #1 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]

• CAN #2 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J19]

• Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]

• Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]

• Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]

• ADC A expansion connector, to allow the user to attach his own A/D Port A-compatible
peripheral [J9]

• ADC B expansion connector, to allow the user to attach his own A/D Port B-compatible
peripheral [J10]

MC56F8367EVM User Manual, Rev. 2

2-2 Freescale Semiconductor

Preliminary

• Address bus expansion connector, to allow the user to monitor the external address bus
[J4]

• Data bus expansion connector, to allow the user to monitor the external data bus [J5]

• External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]

• On-board power regulation provided from an external +12V DC-supplied power input
[P3]

• Light Emitting Diode (LED) power indicator [LED13]

• Six on-board real-time user debugging LEDs [LED1 - 6]

• Six on-board Port A PWM monitoring LEDs [LED7 - 12]

• Internal/external (EXTBOOT) boot mode selector [JG4]

• Address range (EMI_MODE) boot mode selector [JG5]

• Clock mode (CLKMODE) boot selector [JG6]

• Temperature sense diode to ANA7 selector [JG12]

• Manual reset push button [S1]

• Manual interrupt push button for IRQA [S2]

• Manual interrupt push button for IRQB [S3]

• General-purpose jumper on GPIO PE4 [JG15]

• General-purpose jumper on GPIO PE7 [JG16]

Technical Summary, Rev. 2

Freescale Semiconductor 2-3
Preliminary

2.1 MC56F8367

The 56F8367EVM uses a Freescale MC56F8367VPY60 part, designated as U1 on the board and
in the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8367, including functionality and user information, is provided in these
documents:

• 56F8367 Technical Data Sheet, (MC56F8367): Electrical and timing specifications, pin
descriptions, device-specific peripheral information and package descriptions (this
document)

• 56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices

• DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set

Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:

www.freescale.com

2.2 Program and Data Memory

The 56F8367EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.

MC56F8367EVM User Manual, Rev. 2

2-4 Freescale Semiconductor

Preliminary

Program and Data Memory

2.2.1 SRAM Bank 0

SRAM bank 0, which is controlled by CS0, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic diagram in

Figure 2-1. CS0 can be configured to use this memory bank as 16 bits of Program memory, Data

memory, or both. Additionally, CS0 can be configured to assign this memory’s size and starting
address to any modulo address space.

This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumper at JG7.

MC56F8367 GS72116

A0 - A16

D0 - D15

RD

WR

PS / CS0

Jumper Pin 1-2:
Enable SRAM

Jumper Removed:
Disable SRAM

JG7

+3.3V

1

2

A0 - A16

DQ0 - DQ15

OE

WE

CE

Figure 2-1. Schematic Diagram of the External CS0 Memory Interface

Technical Summary, Rev. 2

Freescale Semiconductor 2-5
Preliminary

2.2.2 SRAM Bank 1

SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in

Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word

(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.

This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumpers at JG8.

MC56F8367 GS72116

A0 - A16

D0 - D15

RD

WR

DS / CS1

PD2 / CS4

Jumper Pin 1-2:
Enable SRAM Low Byte

Jumper Pin 3-4:
Enable SRAM High Byte

JG8

1

3

2

4

A0 - A16

DQ0 - DQ15

OE

WE

LB
HB

CE

Figure 2-2. Schematic Diagram of the External CS1 / CS4 Memory Interface

MC56F8367EVM User Manual, Rev. 2

2-6 Freescale Semiconductor

Preliminary