Freescale 56 F 826 Service Manual
www.DataSheet4U.com
56F826
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F826
Rev. 14
01/2007
freescale.com
56F826 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Program RAM
•2K × 16-bit words (4KB) Data Flash
•4K × 16-bit words (8KB) Data RAM
•2K × 16-bit words (4KB) BootFLASH
• Up to 64K × 16-bit words each of external memory
expansion for Program and Data memory
EXTBOOT
RESET
IRQB
IRQA
6
JTAG/
OnCE
Port
• One Serial Port Interface (SPI)
• One additional SPI or two optional Serial
Communication Interfaces (SCI)
• One Synchronous Serial Interface (SSI)
• One General Purpose Quad Timer
• JTAG/OnCE
™ for debugging
• 100-pin LQFP Package
• 16 dedicated and 30 shared GPIO
• Time-of-Day (TOD) Timer
VDDV
3
Low Voltage Supervisor
V
SS
44
4
DDIOVSSIO
V
DDAVSSA
Analog Reg
TOD
Timer
Interrupt
Controller
Quad Timer
4
6
4
4
16
or
GPIO
SSI
or
GPIO
SCI0 & SCI1
or
SPI0
SPI1
or
GPIO
Dedicated
GPIO
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
Applica-
tion-Specific
Memory &
Peripherals
Program Controller
and
Hardware Looping Unit
PAB
PDB
XDB2
CGDB
XAB1
XAB2
COP
RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
Address
Generation
Unit
INTERRUPT
CONTROLS
IPBus Bridge
CONTROLS
16 16
(IPBB)
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
16-Bit
56800
Core
IPBB
External
Bus
Interface
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
16
16
CLKO
XTAL
EXTAL
A[00:15]
or
GPIO
D[00:15]
PS
Select[0]
Select[1]
DS
WR Enable
RD Enable
56F826 Block Diagram
56F826 Technical Data, Rev. 14
Freescale Semiconductor 3
Part 1 Overview
1.1 56F826 Features
1.1.1 Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE Debug Programming Interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
—31.5K
—512
—2K
—4K
—2K
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
— As much as 64K
× 16-bit words of Program Flash
× 16-bit words of Program RAM
× 16-bit words of Data Flash
× 16-bit words of Data RAM
× 16-bit words of BootFLASH
× 16-bit Data memory
× 16-bit Program memory
1.1.3 Peripheral Circuits for 56F826
• One General Purpose Quad Timer totalling 7 pins
• One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)
• One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces
totalling 4 pins
• Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)
56F826 Technical Data, Rev. 14
4 Freescale Semiconductor
56F826 Description
• Sixteen (16) dedicated General Purpose I/O (GPIO) pins
• Thirty (30) shared General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) Watchdog timer
• Two external interrupt pins
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs
• One Time of Day module
1.1.4 Energy Information
• Dual power supply, 3.3V and 2.5V
• Wait and Multiple Stop modes available
1.2 56F826 Description
The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.
The 56F826 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, POS terminals, feature phones.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F826 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external
dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It
also supports program execution from external memory.
The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of
field-programmable software routines that can be used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page
sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.
56F826 Technical Data, Rev. 14
Freescale Semiconductor 5
This controller also provides a full set of standard programmable peripherals including one Synchronous
Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial
Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as
General Purpose Input/Outputs (GPIOs) if a timer function is not required.
1.3 Award-Winning Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F826 Chip Documentation
Topic Description Order Number
56800E
Family Manual
DSP56F826/F827
User’s Manual
56F826
Technical Data Sheet
56F826
Product Brief
56F826
Errata
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Summary description and block diagram of the 56F826
core, memory, peripherals and interfaces
Details any chip issues that might be present DSP56F826E
56800EFM
DSP56F826-827UM
DSP56F826
DSP56F826PB
56F826 Technical Data, Rev. 14
6 Freescale Semiconductor
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Data Sheet Conventions
Examples: Signal/Symbol Logic State Signal State
PIN True Asserted VIL/V
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Voltage
OL
OH
OH
OL
1
56F826 Technical Data, Rev. 14
Freescale Semiconductor 7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of Pins
Power (V
Ground (V
PLL and Clock 3
Address Bus
Data Bus
Bus Control 4
Quad Timer Module Ports
JTAG/On-Chip Emulation (OnCE) 6
Dedicated General Purpose Input/Output 16
Synchronous Serial Interface (SSI) Port
Serial Peripheral Interface (SPI) Port
Serial Communications Interface (SCI) Ports 4
Interrupt and Program Control 5
1. Alternately, GPIO pins
DD
1
SS
, V
, V
1
DDIO or VDDA
SSIO or VSSA
) (3,4,1)
) (3,4,1)
16
16
1
1
1
4
6
4
56F826 Technical Data, Rev. 14
8 Freescale Semiconductor
Introduction
2.5V Power
3.3V Analog Power
3.3V Power
Ground
Analog Ground
Ground
PLL
and
Clock
External
Address Bus or
GPIO
External Data
Bus
External
Bus Control
V
DD
V
DDA
V
DDIO
V
SS
V
SSA
V
SSIO
EXTAL
XTAL (CLOCKIN)
CLKO
A0-A7 (GPIOE)
A8-A15 (GPIOA)
D0–D15
PS
DS
RD
WR
3
1
4
4*
1
4
1
1
1
8
8
16
1
1
1
1
56F826
GPIOB0–7
8
GPIOD0–7
8
SRD (GPIOC0)
1
SRFS (GPIOC1)
1
SRCK (GPIOC2)
1
STD (GPIOC3)
1
STFS (GPIOC4)
1
STCK (GPIOC5)
1
SCLK (GPIOF4)
1
MOSI (GPIOF5)
1
MISO (GPIOF6)
1
SS
1
TXD0 (SCLK0)
1
RXD0 (MOSI0)
1
TXD1 (MISO0)
1
RXD1 (SS0
1
Dedicated
GPIO
SSI Port
or GPIO
SPI1 Port
or GPIO
(GPIOF7)
SCI0, SCI1
Port or
SPI0 Port
)
TA0 (GPIOF0)
Quad Timer A
or GPIO
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
JTAG/OnCE™
Port
TDI
TDO
TRST
DE
*Includes TCS pin, which is reserved for factory use and is tied to VSS
Figure 2-1 56F826 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parentheses.
1
1
1
1
1
1
1
IRQA
1
1
1
1
1
1
1
IRQB
RESET
EXTBOOT
Interrupt/
Program
Control
1
56F826 Technical Data, Rev. 14
Freescale Semiconductor 9
2.2 Signals and Package Information
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:
1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
V
DD
V
DD
V
DD
V
DDA
Pin No. Type Description
20 V
64 V
94 V
59 V
DD
DD
DD
DDA
Power—These pins provide power to the internal structures of the chip, and are
generally connected to a 2.5V supply.
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
V
V
V
V
V
V
V
V
V
DDIO
DDIO
DDIO
DDIO
V
SS
V
SS
V
SS
SSA
SSIO
SSIO
SSIO
SSIO
5V
30 V
57 V
80 V
19 V
63 V
95 V
60 V
6V
31 V
58 V
81 V
DDIO
DDIO
DDIO
DDIO
SS
SS
SS
SSA
SSIO
SSIO
SSIO
SSIO
TCS 99 Input/Output
(Schmitt)
Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
GND—These pins provide grounding for the internal structures of the chip. All
should be attached to V
SS.
Analog Ground—This pin supplies an analog ground.
GND In/Out—These pins provide grounding for the I/O ring on the chip. All
should be attached to V
SS.
TCS—This pin is reserved for factory use. It must be tied to VSS for normal use.
In block diagrams, this pin is considered an additional V
SS.
EXTAL 61 Input External Crystal Oscillator Input—This input should be connected to a 4MHz
external crystal or ceramic resonator. For more information, please refer to
Section 3.6.
56F826 Technical Data, Rev. 14
10 Freescale Semiconductor
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
XTAL
(CLOCKIN)
CLKO 65 Output Clock Output—This pin outputs a buffered clock signal. By programming the
A0
(GPIOE0)
A1
(GPIOE1)
A2
(GPIOE2)
A3
(GPIOE3)
A4
(GPIOE4)
Pin No. Type Description
62 Output
Input
24 Output
23
22
21
18
Input/Output
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
V
. For more information, please refer to Section 3.6.3.
SS
External Clock Input—This input should be asserted when using an external
clock or ceramic resonator.
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock at
the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
Address Bus—A0–A7 specify the address for external program or data memory
accesses.
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A5
(GPIOE5)
A6
(GPIOE6)
A7
(GPIOE7)
17
16
15
56F826 Technical Data, Rev. 14
Freescale Semiconductor 11
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
A8
(GPIOA0)
A9
(GPIOA1)
A10
(GPIOA2)
A11
(GPIOA3)
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
A15
(GPIOA7)
D0 34 Input/Output Data Bus— D0–D15 specify the data for external program or data memory
D1 35
D2 36
Pin No. Type Description
14 Output
13
12
11
10
9
8
7
Input/Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
accesses. D0–D15 are tri-stated when the external bus is inactive.
D3 37
D4 38
D5 39
D6 40
D7 41
D8 42
D9 43
D10 44
D11 46
D12 47
D13 48
D14 49
D15 50
PS
DS
29 Output Program Memory Select—PS is asserted low for external program memory
28 Output Data Memory Select—DS is asserted low for external data memory access.
access.
56F826 Technical Data, Rev. 14
12 Freescale Semiconductor
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
RD
WR
TA0
(GPIOF0)
TA1
(GPIOF1)
TA2
(GPIOF2)
TA3
(GPIOF3)
TCK 100 Input
TMS 1 Input
Pin No. Type Description
26 Output Read Enable—RD is asserted during external memory read cycles. When RD is
27 Output Write Enable—WR is asserted during external memory write cycles. When WR
91 Input/Output
90
89
88
Input/Output
(Schmitt)
(Schmitt)
asserted low, pins D0–D15 become inputs and an external device is enabled
onto the device data bus. When RD
latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and
pins. RD can be connected directly to the OE pin of a Static RAM or ROM.
DS
is asserted low, pins D0–D15 become outputs and the device puts data on the
bus. When WR
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins.
WR can be connected directly to the WE pin of a Static RAM.
TA0–3—Timer A Channels 0, 1, 2, and 3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually
programmed as input or output.
After reset, the default state is Quad Timer.
Test Clock Input—This input pin provides a gated clock to synchronize the test
logic and shift serial data to the JTAG/OnCE port. The pin is connected internally
to a pull-down resistor.
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
is deasserted high, the external data is latched inside the
is deasserted high, the external data is
Note: Always tie the TMS pin to V
TDI 2 Input
(Schmitt)
TDO 3 Output Test Data Output—This tri-statable output pin provides a serial output data
TRST
DE
4 Input
(Schmitt)
98 Output Debug Event—DE provides a low pulse on recognized debug events.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET
do not assert TRST
Note: For normal operation, connect TRST
in a debugging environment, TRST
56F826 Technical Data, Rev. 14
. TRST must always be asserted at power-up.
is asserted. The only exception occurs in a
through a 2.2K resistor.
DD
directly to VSS. If the design is to be used
may be tied to VSS through a 1K resistor.
, but
Freescale Semiconductor 13
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
GPIOB0 66 Input or
GPIOB1 67
GPIOB2 68
GPIOB3 69
GPIOB4 70
GPIOB5 71
GPIOB6 72
GPIOB7 73
GPIOD0 74 Input or
GPIOD1 75
GPIOD2 76
GPIOD3 77
GPIOD4 78
GPIOD5 79
GPIOD6 82
GPIOD7 83
Pin No. Type Description
Output
Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is GPIO input.
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
SRD
(GPIOC0)
SRFS
(GPIOC1)
51 Input/Output
Input/Output
52 Input/ Output
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used
only by the receiver. It is used to synchronize data transfer and can be an input
or an output.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
56F826 Technical Data, Rev. 14
14 Freescale Semiconductor
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
SRCK
(GPIOC2)
STD
(GPIOC3)
STFS
(GPIOC4)
Pin No. Type Description
53 Input/Output
Input/Output
54 Output
Input/Output
55 Input
Input/Output
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit
rate clock for the Receive section of the SSI. The clock signal can be continuous
or gated and can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the
Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used
by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
STCK
(GPIOC5)
SCLK
(GPIOF4)
MOSI
(GPIOF5)
56 Input/ Output
Input/Output
84 Input/Output
Input/Output
85 Input/Output
Input/Output
After reset, the default state is GPIO input.
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the SSI. The clock signal can be continuous
or gated. It can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data on
the MOSI line a half-cycle before the clock edge that the slave device uses to
latch the data.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
56F826 Technical Data, Rev. 14
Freescale Semiconductor 15
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
MISO
(GPIOF6)
SS
(GPIOF7)
TXD0
(SCLK0)
RXD0
Pin No. Type Description
86 Input/Output
Input/Output
87 Input
Input/Output
97 Output
Input/Output
96 Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS
Transmit Data (TXD0)—transmit data output
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
Receive Data (RXD0)— receive data input
.
(MOSI0)
TXD1
(MISO0)
RXD1
)
(SS0
Input/Output
93 Output
Input/Output
92 Input
(Schmitt)
Input
SPI Master Out/Slave In—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
Transmit Data (TXD1)—transmit data output
SPI Master In/Slave Out—This serial data pin is an input to a master device and
an output from a slave device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
After reset, the default state is SCI output.
Receive Data (RXD1)— receive data input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
56F826 Technical Data, Rev. 14
16 Freescale Semiconductor
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
IRQA
IRQB
RESET 45 Input
EXTBOOT 25 Input
Pin No. Type Description
32 Input
(Schmitt)
33 Input
(Schmitt)
(Schmitt)
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA
the Stop state.
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the device is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET
External Boot—This input is tied to V
memory. Otherwise, it is tied to ground.
is asserted, the processor will exit
and TRST should be asserted
, but do not assert TRST.
to force device to boot from off-chip
DD
56F826 Technical Data, Rev. 14
Freescale Semiconductor 17
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