Freescale 56 F 826 Service Manual

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56F826

Data Sheet

Preliminary Technical Data

56F800 16-bit Digital Signal Controllers

DSP56F826 Rev. 14 01/2007

freescale.com

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56F826 General Description

• Up to 40 MIPS at 80MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• Hardware DO and REP loops

• MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes

• 31.5K × 16-bit words (64KB) Program Flash

• 512 × 16-bit words (1KB) Program RAM

•2K × 16-bit words (4KB) Data Flash

•4K × 16-bit words (8KB) Data RAM

•2K × 16-bit words (4KB) BootFLASH

• Up to 64K × 16-bit words each of external memory expansion for Program and Data memory

EXTBOOT

RESET

IRQB

IRQA

JTAG/ OnCE

Port

• One Serial Port Interface (SPI)

• One additional SPI or two optional Serial Communication Interfaces (SCI)

• One Synchronous Serial Interface (SSI)

• One General Purpose Quad Timer

• JTAG/OnCE

™ for debugging

• 100-pin LQFP Package

• 16 dedicated and 30 shared GPIO

• Time-of-Day (TOD) Timer

VDDV

Low Voltage Supervisor

DDIOVSSIO

DDAVSSA

Analog Reg

TOD

Timer

Interrupt

Controller

Quad Timer

GPIO

SSI

GPIO

SCI0 & SCI1

SPI0

SPI1

GPIO

Dedicated

GPIO

Program Memory 32252 x 16 Flash

512 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

2048 x 16 Flash

4096 x 16 SRAM

COP/

Watchdog

Applica-

tion-Specific

Memory &

Peripherals

Program Controller

and

Hardware Looping Unit

PAB

PDB

XDB2

CGDB

XAB1

XAB2

COP

RESET

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

Address

Generation

Unit

INTERRUPT CONTROLS

IPBus Bridge

CONTROLS

16 16

(IPBB)

Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers

Two 36-bit Accumulators

16-Bit 56800

Core

IPBB

External

Bus

Interface

Unit

Bit

Manipulation

Unit

PLL

Clock Gen

External

Address Bus

Switch

External

Data Bus

Switch

Bus

Control

CLKO

XTAL

EXTAL

A[00:15] or GPIO

D[00:15]

Select[0]

Select[1]

DS WR Enable RD Enable

56F826 Block Diagram

56F826 Technical Data, Rev. 14

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Part 1 Overview

1.1 56F826 Features

1.1.1 Processing Core

• Efficient 16-bit 56800 family controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Two 36-bit accumulators, including extension bits

• 16-bit bidirectional barrel shifter

• Parallel instruction set with unique processor addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE Debug Programming Interface

1.1.2 Memory

• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

• On-chip memory including a low-cost, high-volume Flash solution

—31.5K

—512

—2K

—4K

—2K

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

— As much as 64K

× 16-bit words of Program Flash

× 16-bit words of Program RAM

× 16-bit words of Data Flash

× 16-bit words of Data RAM

× 16-bit words of BootFLASH

× 16-bit Data memory

× 16-bit Program memory

1.1.3 Peripheral Circuits for 56F826

• One General Purpose Quad Timer totalling 7 pins

• One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)

• One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling 4 pins

• Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)

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56F826 Description

• Sixteen (16) dedicated General Purpose I/O (GPIO) pins

• Thirty (30) shared General Purpose I/O (GPIO) pins

• Computer-Operating Properly (COP) Watchdog timer

• Two external interrupt pins

• External reset pin for hardware reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

• Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs

• One Time of Day module

1.1.4 Energy Information

• Dual power supply, 3.3V and 2.5V

• Wait and Multiple Stop modes available

1.2 56F826 Description

The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost, configuration flexibility, and compact program code, the 56F826 is well-suited for many applications. The 56F826 includes many peripherals that are especially useful for applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic alarms, POS terminals, feature phones.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.

The 56F826 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It also supports program execution from external memory.

The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.

56F826 Technical Data, Rev. 14

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This controller also provides a full set of standard programmable peripherals including one Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as General Purpose Input/Outputs (GPIOs) if a timer function is not required.

1.3 Award-Winning Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system.

• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56F826 Chip Documentation

Topic Description Order Number

56800E Family Manual

DSP56F826/F827 User’s Manual

56F826 Technical Data Sheet

56F826 Product Brief

56F826 Errata

Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set

Detailed description of memory, peripherals, and interfaces of the 56F826 and 56F827

Electrical and timing specifications, pin descriptions, and package descriptions (this document)

Summary description and block diagram of the 56F826 core, memory, peripherals and interfaces

Details any chip issues that might be present DSP56F826E

56800EFM

DSP56F826-827UM

DSP56F826

DSP56F826PB

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1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Data Sheet Conventions

Examples: Signal/Symbol Logic State Signal State

PIN True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Voltage

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Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group Number of Pins

Power (V

Ground (V

PLL and Clock 3

Address Bus

Data Bus

Bus Control 4

Quad Timer Module Ports

JTAG/On-Chip Emulation (OnCE) 6

Dedicated General Purpose Input/Output 16

Synchronous Serial Interface (SSI) Port

Serial Peripheral Interface (SPI) Port

Serial Communications Interface (SCI) Ports 4

Interrupt and Program Control 5

1. Alternately, GPIO pins

, V

DDIO or VDDA

SSIO or VSSA

) (3,4,1)

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Introduction

2.5V Power

3.3V Analog Power

3.3V Power

Ground

Analog Ground

Ground

PLL

and

Clock

External

Address Bus or

GPIO

External Data

Bus

External

Bus Control

DDA

DDIO

SSA

SSIO

EXTAL

XTAL (CLOCKIN)

CLKO

A0-A7 (GPIOE)

A8-A15 (GPIOA)

D0–D15

56F826

GPIOB0–7

GPIOD0–7

SRD (GPIOC0)

SRFS (GPIOC1)

SRCK (GPIOC2)

STD (GPIOC3)

STFS (GPIOC4)

STCK (GPIOC5)

SCLK (GPIOF4)

MOSI (GPIOF5)

MISO (GPIOF6)

TXD0 (SCLK0)

RXD0 (MOSI0)

TXD1 (MISO0)

RXD1 (SS0

Dedicated GPIO

SSI Port or GPIO

SPI1 Port or GPIO

(GPIOF7)

SCI0, SCI1 Port or SPI0 Port

)

TA0 (GPIOF0)

Quad Timer A

or GPIO

TA1 (GPIOF1)

TA2 (GPIOF2)

TA3 (GPIOF3)

TCK

TMS

JTAG/OnCE™

Port

TDI

TDO

TRST

*Includes TCS pin, which is reserved for factory use and is tied to VSS

Figure 2-1 56F826 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parentheses.

IRQA

IRQB

RESET

EXTBOOT

Interrupt/ Program Control

56F826 Technical Data, Rev. 14

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2.2 Signals and Package Information

All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions:

1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.

2. TCK has a weak pull-down circuit always active.

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

DDA

Pin No. Type Description

20 V

64 V

94 V

59 V

DDA

Power—These pins provide power to the internal structures of the chip, and are generally connected to a 2.5V supply.

Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low-noise 3.3V supply.

DDIO

SSA

SSIO

30 V

57 V

80 V

19 V

63 V

95 V

60 V

31 V

58 V

81 V

DDIO

SSA

SSIO

TCS 99 Input/Output

(Schmitt)

Power In/Out—These pins provide power to the I/O structures of the chip, and are generally connected to a 3.3V supply.

GND—These pins provide grounding for the internal structures of the chip. All should be attached to V

SS.

Analog Ground—This pin supplies an analog ground.

GND In/Out—These pins provide grounding for the I/O ring on the chip. All

should be attached to V

SS.

TCS—This pin is reserved for factory use. It must be tied to VSS for normal use. In block diagrams, this pin is considered an additional V

SS.

EXTAL 61 Input External Crystal Oscillator Input—This input should be connected to a 4MHz

external crystal or ceramic resonator. For more information, please refer to

Section 3.6.

56F826 Technical Data, Rev. 14

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Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

XTAL

(CLOCKIN)

CLKO 65 Output Clock Output—This pin outputs a buffered clock signal. By programming the

(GPIOE0)

(GPIOE1)

(GPIOE2)

(GPIOE3)

(GPIOE4)

Pin No. Type Description

62 Output

Input

24 Output

Input/Output

Crystal Oscillator Output—This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. If an external clock source over 4MHz is used, XTAL must be used as the input and EXTAL connected to

. For more information, please refer to Section 3.6.3.

External Clock Input—This input should be asserted when using an external clock or ceramic resonator.

CLKO Select Register (CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the device master clock at the output of the PLL. The clock frequency on this pin can be disabled by programming the CLKO Select Register (CLKOSR).

Address Bus—A0–A7 specify the address for external program or data memory accesses.

Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins.

After reset, the default state is Address Bus.

(GPIOE5)

(GPIOE6)

(GPIOE7)

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Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

(GPIOA0)

(GPIOA1)

A10

(GPIOA2)

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

A14

(GPIOA6)

A15

(GPIOA7)

D0 34 Input/Output Data Bus— D0–D15 specify the data for external program or data memory

D1 35

D2 36

Pin No. Type Description

14 Output

Input/Output

Address Bus—A8–A15 specify the address for external program or data memory accesses.

Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins.

After reset, the default state is Address Bus.

accesses. D0–D15 are tri-stated when the external bus is inactive.

D3 37

D4 38

D5 39

D6 40

D7 41

D8 42

D9 43

D10 44

D11 46

D12 47

D13 48

D14 49

D15 50

29 Output Program Memory Select—PS is asserted low for external program memory

28 Output Data Memory Select—DS is asserted low for external data memory access.

access.

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Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

TA0

(GPIOF0)

TA1

(GPIOF1)

TA2

(GPIOF2)

TA3

(GPIOF3)

TCK 100 Input

TMS 1 Input

Pin No. Type Description

26 Output Read Enable—RD is asserted during external memory read cycles. When RD is

27 Output Write Enable—WR is asserted during external memory write cycles. When WR

91 Input/Output

Input/Output

(Schmitt)

asserted low, pins D0–D15 become inputs and an external device is enabled onto the device data bus. When RD latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and

pins. RD can be connected directly to the OE pin of a Static RAM or ROM.

is asserted low, pins D0–D15 become outputs and the device puts data on the bus. When WR external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM.

TA0–3—Timer A Channels 0, 1, 2, and 3

Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually

programmed as input or output.

After reset, the default state is Quad Timer.

Test Clock Input—This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.

Test Mode Select Input—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

is deasserted high, the external data is latched inside the

is deasserted high, the external data is

Note: Always tie the TMS pin to V

TDI 2 Input

(Schmitt)

TDO 3 Output Test Data Output—This tri-statable output pin provides a serial output data

TRST

4 Input

(Schmitt)

98 Output Debug Event—DE provides a low pulse on recognized debug events.

Test Data Input—This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK.

Test Reset—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET debugging environment when a hardware device reset is required and it is necessary not to reset the JTAG/OnCE module. In this case, assert RESET do not assert TRST

Note: For normal operation, connect TRST

in a debugging environment, TRST

56F826 Technical Data, Rev. 14

. TRST must always be asserted at power-up.

is asserted. The only exception occurs in a

through a 2.2K resistor.

directly to VSS. If the design is to be used

may be tied to VSS through a 1K resistor.

, but

Freescale Semiconductor 13

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Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

GPIOB0 66 Input or

GPIOB1 67

GPIOB2 68

GPIOB3 69

GPIOB4 70

GPIOB5 71

GPIOB6 72

GPIOB7 73

GPIOD0 74 Input or

GPIOD1 75

GPIOD2 76

GPIOD3 77

GPIOD4 78

GPIOD5 79

GPIOD6 82

GPIOD7 83

Pin No. Type Description

Output

Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be individually programmed as input or output pins.

After reset, the default state is GPIO input.

Port D GPIO—These eight dedicated GPIO pins can be individually programmed as an input or output pins.

After reset, the default state is GPIO input.

SRD

(GPIOC0)

SRFS

(GPIOC1)

51 Input/Output

Input/Output

52 Input/ Output

Input/Output

SSI Receive Data (SRD)—This input pin receives serial data and transfers the data to the SSI Receive Shift Receiver.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used only by the receiver. It is used to synchronize data transfer and can be an input or an output.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

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Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

SRCK

(GPIOC2)

STD

(GPIOC3)

STFS

(GPIOC4)

Pin No. Type Description

53 Input/Output

Input/Output

54 Output

Input/Output

55 Input

Input/Output

SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit rate clock for the Receive section of the SSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SSI Transmit Data (STD)—This output pin transmits serial data from the SSI Transmitter Shift Register.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used by both the transmitter and receiver in synchronous mode. It is used to synchronize data transfer and can be an input or output pin.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

STCK

(GPIOC5)

SCLK

(GPIOF4)

MOSI

(GPIOF5)

56 Input/ Output

Input/Output

84 Input/Output

Input/Output

85 Input/Output

Input/Output

After reset, the default state is GPIO input.

SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit rate clock for the transmit section of the SSI. The clock signal can be continuous or gated. It can be used by both the transmitter and receiver in synchronous mode.

Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output.

After reset, the default state is SCLK.

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data.

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output.

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Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

MISO

(GPIOF6)

(GPIOF7)

TXD0

(SCLK0)

RXD0

Pin No. Type Description

86 Input/Output

Input/Output

87 Input

Input/Output

97 Output

Input/Output

96 Input

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output.

After reset, the default state is MISO.

SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave.

Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output.

After reset, the default state is SS

Transmit Data (TXD0)—transmit data output

SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved

listeners. In slave mode, this pin serves as the data clock input.

After reset, the default state is SCI output.

Receive Data (RXD0)— receive data input

(MOSI0)

TXD1

(MISO0)

RXD1

)

(SS0

Input/Output

93 Output

Input/Output

92 Input

(Schmitt)

Input

SPI Master Out/Slave In—This serial data pin is an output from a master device, and an input to a slave device. The master device places data on the MOSI line one half-cycle before the clock edge the slave device uses to latch the data.

After reset, the default state is SCI input.

Transmit Data (TXD1)—transmit data output

SPI Master In/Slave Out—This serial data pin is an input to a master device and

an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.

After reset, the default state is SCI output.

Receive Data (RXD1)— receive data input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.

In slave mode, this pin is used to select the slave.

After reset, the default state is SCI input.

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Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

IRQA

IRQB

RESET 45 Input

EXTBOOT 25 Input

Pin No. Type Description

32 Input

(Schmitt)

33 Input

(Schmitt)

External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for wired-OR operation.

If the processor is in the Stop state and IRQA the Stop state.

External Interrupt Request B—The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for wired-OR operation.

Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the external boot pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks.

To ensure complete hardware reset, RESET together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET

External Boot—This input is tied to V memory. Otherwise, it is tied to ground.

is asserted, the processor will exit

and TRST should be asserted

, but do not assert TRST.

to force device to boot from off-chip

56F826 Technical Data, Rev. 14

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Part 3 Specifications

3.1 General Characteristics

The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device.

The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.

CAUTION

This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

56F826 Technical Data, Rev. 14

18 Freescale Semiconductor

Page 19

General Characteristics

Table 3-1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage, core

Supply voltage, IO

Supply voltage, Analog

DDIO

Digital input voltages

Analog input voltages - XTAL, EXTAL

Voltage difference V

Current drain per pin excluding V V

, V

DDIO

SSIO

to V

DD_IO

SS _IO

, V

DDA

SSA

, V

SS, VDDA

, V

SSA,

ΔV

Junction temperature T

Storage temperature range T

1. VDD must not exceed V

2. V

DDIO

and V

DDA

DDIO

must not differ by more that 0.5V

Table 3-2 Recommended Operating Conditions

Characteristic Symbol Min Typ Max Unit

DDA

INA

VSS – 0.3 V

– 0.3

SSIO

– 0.3

SSA

– 0.3

SSIO

– 0.3

SSA

V V

SSIO

SSA

SSIO

DDA

+ 3.0

+ 4.0

+ 5.5

+ 0.3

- 0.3 0.3 V

I— 10

STG

—150°C

–55 150 °C

Supply voltage, core V

Supply Voltage, IO and analog V

Voltage difference V

to V

DD_IO

SS _IO

, V

DDA

SSA

DDIO,VDDA

ΔV

Ambient operating temperature T

2.25 2.5 2.75 V

3.0 3.3 3.6 V

-0.1 - 0.1 V

–40 – 85 °C

56F826 Technical Data, Rev. 14

Freescale Semiconductor 19

Page 20

Characteristic

Table 3-3 Thermal Characteristics

Comments

Symbol

100-pin LQFP

Value

Unit Notes

Junction to ambient Natural convection

Junction to ambient (@1m/sec) R

Junction to ambient Natural convection

Junction to ambient (@1m/sec) Four layer board (2s2p) R

Junction to case R

Junction to center of case Ψ

I/O pin power dissipation P

Power dissipation P

Junction to center of case P

Four layer board (2s2p) R

(2s2p)

θJA

θJMA

θJC

I/O

DMAX

P D = (IDD x VDD + P

48.3 °C/W 2

43.9 °C/W 2

40.7 °C/W 1.2

38.6 °C/W 1,2

13.5 °C/W 3

1.0 °C/W 4, 5

User Determined W

I/O

(TJ - TA) /RθJA

Notes:

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on

a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold

plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink.

4. Thermal Characterization Parameter, Psi-JT (ΨJT), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. Ψ temperature in steady state customer environments.

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

6. See Section 5.1 for more details on thermal design considerations.

7. TJ = Junction Temperature TA = Ambient Temperature

) was simulated to be equivalent to the JEDEC

θJA

), was simulated to be equivalent to the measured values

θJC

is a useful value to use to estimate junction

56F826 Technical Data, Rev. 14

20 Freescale Semiconductor

Page 21

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions: V

SSIO=VSS

= V

SSA

= 0V, V

DDA =VDDIO

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic Symbol Min Typ Max Unit

DC Electrical Characteristics

Input high voltage (XTAL/EXTAL) V

Input low voltage (XTAL/EXTAL) V

Input high voltage (Schmitt trigger inputs)

Input low voltage (Schmitt trigger inputs)

Input high voltage (all other digital inputs) V

Input low voltage (all other digital inputs) V

Input current high (pull-up/pull-down resistors disabled,

IHC

ILC

IHS

ILS

2.25 — 3.6 V

0—0.5V

2.2 — 5.5 V

-0.3 — 0.8 V

2.0 — 5.5 V

-0.3 — 0.8 V

-1 — 1 μA

VIN=VDD)

Input current low (pull-up/pull-down resistors disabled,

-1 — 1 μA

VIN=VSS)

Input current high (with pull-up resistor, V

Input current low (with pull-up resistor, V

IN=VSS

Input current high (with pull-down resistor, VIN=VDD)I

Input current low (with pull-down resistor, V

Nominal pull-up or pull-down resistor value R

IN=VDD

IN=VSS

IHPU

ILPU

IHPD

ILPD

, R

-1 — 1 μA

-210 — -50 μA

20 — 180 μA

-1 — 1 μA

30 KΩ

Output tri-state current low I

Output tri-state current high I

Input current high (analog inputs, V

Input current low (analog inputs, V

IN=VDDA

IN=VSSA

)

Output High Voltage (at IOH) V

Output Low Voltage (at IOL) V

Output source current I

Output sink current I

PWM pin output source current

PWM pin output sink current

OZL

OZH

OHP

OLP

IHA

ILA

-10 — 10 μA

-15 — 15 μA

VDD – 0.7 — — V

——0.4V

4——mA

10 — — mA

16 — — mA

56F826 Technical Data, Rev. 14

Freescale Semiconductor 21

Page 22

Operating Conditions: V

Table 3-4 DC Electrical Characteristics (Continued)

= V

SSIO=VSS

SSA

= 0V, V

DDA =VDDIO

Characteristic Symbol Min Typ Max Unit

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Input capacitance C

Output capacitance C

supply current

Run

Wait

OUT

DDT

—8—pF

—12—pF

—4775mA

—2136mA

Stop —28mA

Low Voltage Interrupt, V

Power on Reset

power supply

DDIO

power supply

1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. I

DDT

= IDD + I

(Total supply current for VDD + V

DDA

)

6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled.

7. Wait IDD measured using external square wave clock source (f less than 50pF on all outputs. C measured with PLL enabled.

8. This low-voltage interrupt monitors the V of the device is guaranteed under transient conditions when V the V

interrupt is generated).

EIO

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;

power supply. If V

DDIO

9. This low-voltage interrupt monitors theVDD power supply. If V the device is guaranteed under transient conditions when V V

interrupt is generated).

EIC

osc

DDIO

DDIO >VEIO

DDIO

DD >VEIC

(between the minimum specified V

10. Power–on reset occurs whenever the VDD power supply drops below V active for as long as V

is below V

no matter how long the ramp-up rate is.

POR

EIO

EIC

POR

2.4 2.7 3.0 V

2.0 2.2 2.4 V

—1.72.0V

= 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads;

drops below V

(between the minimum specified V

drops below V

. While power is ramping up, this signal remains

POR

, an interrupt is generated. Functionality

EIO

, an interrupt is generated. Functionality of

EIC

and the point when

DDIO

and the point when the

56F826 Technical Data, Rev. 14

22 Freescale Semiconductor

Page 23

100

IDD (mA)

IDD Digital

IDD Analog

Supply Voltage Sequencing and Separation Cautions

IDD Total

Freq. (MHz)

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)

3.3 Supply Voltage Sequencing and Separation Cautions

Figure 3-2 shows two situations to avoid in sequencing the VDD and V

3.3V

2.5V

Supplies Stable

DDIO, VDDA

supplies.

DDIO,VDDA

DC Power Supply Voltage

Notes: 1. VDD rising before V

2. V

DDIO

, V

rising much faster than V

DDA

DDIO

, V

DDA

Time

Figure 3-2 Supply Voltage Sequencing and Separation Cautions

56F826 Technical Data, Rev. 14

Freescale Semiconductor 23

Page 24

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the V supply (2.5V) from the voltage generated by the 3.3V V rising faster than V

DDIO

supply, see Figure 3-3. This keeps VDD from

DDIO

VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 3-3. The series diodes forward bias when the difference between V approximately 1.4, causing V

to rise as V

ramps up. When the V

DDIO

regulator begins proper

DDIO

and V

reaches

operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: V

DDIO

> V

> (V

DDIO

- 1.4V)

In practice, V

is typically connected directly to V

DDA

with some filtering.

DDIO

3.3V

Supply

Regulator

2.5V

Regulator

Figure 3-3 Example Circuit to Control Supply Sequencing

3.4 AC Electrical Characteristics

Timing waveforms in Section 3.4 are tested using the VIL and V table. The levels of VIH and VIL for an input signal are shown in Figure 3-4.

Pulse Width

Low High

Input Signal

Midpoint1

Fall Time

levels specified in the DC Characteristics

Rise Time

DDIO,VDDA

90%

50%

10%

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 3-4 Input Signal Measurement References

Figure 3-5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state

• Tri-stated, when a bus or signal is placed in a high impedance state

• Data Valid state, when a signal level has reached V

• Data Invalid state, when a signal level is in transition between VOL and V

56F826 Technical Data, Rev. 14

24 Freescale Semiconductor

or V

Page 25

Flash Memory Characteristics

Data1 Valid

Data1

Data2 Valid

Data2 Data3

Data Invalid State

Data Active Data Active

Figure 3-5 Signal States

3.5 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table

Mode

Standby L L L L L L L L

Read HHHH L L L L

Word Program H H L L H L L H

Page Erase H L L L L H L H

Mass Erase H L L L L H H H

1. X address enable, all rows are disabled when XE = 0

2. Y address enable, YMUX is disabled when YE = 0

3. Sense amplifier enable

4. Output enable, tri-state Flash data out bus when OE = 0

5. Defines program cycle

6. Defines erase cycle

7. Defines mass erase cycle, erase whole block

8. Defines non-volatile store cycle

Tri-stated

PROG

Data

ERASE

Data3 Valid

MAS1

NVSTR

Table 3-6 IFREN Truth Table

Mode IFREN = 1 IFREN = 0

Read Read information block Read main memory block

Word program Program information block Program main memory block

Page erase Erase information block Erase main memory block

Mass erase Erase both block Erase main memory block

56F826 Technical Data, Rev. 14

Freescale Semiconductor 25

Page 26

Table 3-7 Flash Timing Parameters

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit Figure

Program time

Erase time

Mass erase time

Endurance1

Data Retention

PROG/ERASE to NVSTR set up time

NVSTR hold time

NVSTR hold time (mass erase)

NVSTR to program set up time

Recovery time

The following parameters should only be used in the Manual Word Programming Mode

= V

Tprog*

Terase*

Tme*

CYC

RET

Tnvs*

Tnvh*

Tnvh1*

Tpgs*

Trcv*

= 0 V, VDD = V

SSA

20 – – us Figure 3-6

20 – – ms Figure 3-7

100 – – ms Figure 3-8

10,000 20,000 – cycles

10 30 – years

–5–usFigure 3-6,

–100–usFigure 3-8

–10–usFigure 3-6

–1–usFigure 3-6,

= 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

DDA

Figure 3-7,

Figure 3-8

Figure 3-7

Figure 3-7,

Figure 3-8

Cumulative program

HV period

Program hold time

Address/data set up time

Address/data hold time

1. One cycle is equal to an erase program and read.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase.

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

Thv

Tpgh

Tads

Tadh

56F826 Technical Data, Rev. 14

–3–ms Figure 3-6

––– Figure 3-6

26 Freescale Semiconductor

Page 27

IFREN

XADR

Flash Memory Characteristics

YADR

DIN

PROG

NVSTR

IFREN

Tnvs

Tadh

Tads

Tprog

Tpgs

Thv

Figure 3-6 Flash Program Cycle

Tpgh

Tnvh

Trcv

XADR

YE=SE=OE=MAS1=0

ERASE

NVSTR

Tnvs

Terase

Tnvh

Trcv

Figure 3-7 Flash Erase Cycle

56F826 Technical Data, Rev. 14

Freescale Semiconductor 27

Page 28

IFREN

XADR

MAS1

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tme

Tnvh1

Trcv

Figure 3-8 Flash Mass Erase Cycle

3.6 External Clock Operation

The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins.

3.6.1 Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-9. A recommended crystal oscillator circuit is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no external load capacitors should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF

56F826 Technical Data, Rev. 14

28 Freescale Semiconductor

Page 29

External Clock Operation

as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation:

CL =

CL1 * CL2

CL1 + CL2

+ Cs =

12 * 12

+ 3 = 6 + 3 = 9pF

12 + 12

This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit.

EXTAL XTAL

Recommended External Crystal Parameters: Rz = 1 to 3MΩ

= 4Mhz (optimized for 4MHz)

Figure 3-9 Connecting to a Crystal Oscillator Circuit

3.6.2 Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in

Figure 3-10. Refer to supplier’s recommendations when selecting a ceramic resonator and associated

components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-10, no external load capacitors should be used.

EXTAL XTAL

Recommended Ceramic Resonator Parameters: Rz = 1 to 3 MΩ

= 4Mhz (optimized for 4MHz)

Figure 3-10 Connecting a Ceramic Resonator

Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground).

56F826 Technical Data, Rev. 14

Freescale Semiconductor 29

Page 30

3.6.3 External Clock Source

The recommended method of connecting an external clock is given in Figure 3-11. The external clock source is connected to XTAL and the EXTAL pin is held V

56F826

XTAL

External

EXTAL

DDA

Clock

Figure 3-11 Connecting an External Clock Signal

Table 3-8 External Clock Operation Timing Requirements

DDA

/2.

Operating Conditions: V

SSIO=VSS

= V

SSA

= 0V, V

DDA =VDDIO

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic Symbol Min Typ Max Unit

osc

Frequency of operation (external clock driver)

Clock Pulse Width

1. See Figure 3-11 for details on using the recommended connection of an external clock driver.

2. When using Time of Day (TOD), maximum external frequency is 6MHz.

3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

4. Parameters listed are guaranteed by design.

External

Clock

3, 4

50%

10%

90%

6.25 — — ns

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 3-12 External Clock Timing

90%

50%

10%

MHz

56F826 Technical Data, Rev. 14

30 Freescale Semiconductor

Page 31

3.6.4 Phase Locked Loop Timing

Table 3-9 PLL Timing

Operating Conditions: V

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

DDIO

Characteristic Symbol Min Typ Max Unit

External Bus Asynchronous Timing

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz

External reference crystal frequency for the PLL

PLL output frequency

PLL stabilization time

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f User Manual. ZCLK = f

3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

-40o to +85oC

osc

/2 40 — 110 MHz

out

plls

246MHz

—110ms

/2, please refer to the OCCS chapter in the

out

3.7 External Bus Asynchronous Timing

Table 3-10 External Bus Asynchronous Timing

Operating Conditions: V

Address Valid to WR Asserted t

Width Asserted

WR Wait states = 0 Wait states > 0

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

Characteristic Symbol

AWR

Min

6.5 — ns

7.5

(T*WS) + 7.5

1, 2

Max

— —

Unit

ns ns

Asserted to D0–D15 Out Valid t

Data Out Hold Time from WR

Data Out Set Up Time to WR

Deasserted t

Deasserted Wait states = 0 Wait states > 0

Deasserted to Address Not Valid t

Address Valid to RD

Deasserted Wait states = 0 Wait states > 0

WRD

DOH

DOS

RDA

ARDD

—T + 4.2ns

4.8 — ns

2.2

(T*WS) + 6.4

— —

ns ns

0—ns

—

18.7

(T*WS) + 18.7

ns ns

56F826 Technical Data, Rev. 14

Freescale Semiconductor 31

Page 32

Table 3-10 External Bus Asynchronous Timing

1, 2

(Continued)

Operating Conditions: V

SSIO

= VSS = V

SSA

= 0V, V

Characteristic Symbol

Input Data Hold to RD

Assertion Width

Deasserted t

Wait states = 0 Wait states > 0

Address Valid to Input Data Valid Wait states = 0 Wait states > 0

Address Valid to RD

Asserted to Input Data Valid

Asserted t

Wait states = 0 Wait states > 0

Deasserted to RD Asserted t

Deasserted to WR Asserted t

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

DRD

ARDA

RDD

WRRD

RDRD

WRWR

Min

0—ns

(T*WS) + 19

— —

(T*WS) + 1

-4.4 — ns

— —

(T*WS) + 2.4

6.8 — ns

0—ns

14.1 — ns

Max

— —

2.4

Unit

ns ns

Deasserted to WR Asserted t

1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

RDWR

12.8 — ns

56F826 Technical Data, Rev. 14

32 Freescale Semiconductor

Page 33

A0–A15,

, DS

(See Note)

AWR

WRWR

ARDA

WRRD

ARDD

External Bus Asynchronous Timing

RDA

RDRD

RDWR

D0–D15

WRD

DOS

DOH

RDD

DRD

Data InData Out

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Figure 3-13 External Bus Asynchronous Timing

56F826 Technical Data, Rev. 14

Freescale Semiconductor 33

Page 34

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: V

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

1, 5

Characteristic Symbol Min Max Unit See Figure

RESET

Assertion to Address, Data and Control

RAZ

—21nsFigure 3-14

Signals High Impedance

Minimum RESET

Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1

RESET

Deassertion to First External Address Output t

Edge-sensitive Interrupt Request Width t

IRQA

, IRQB Assertion to External Data Memory

RDA

IRW

IDM

275,000T

128T

— —

ns ns

33T 34T ns Figure 3-14

1.5T — ns Figure 3-15

15T — ns Figure 3-16

Figure 3-14

Access Out Valid, caused by first instruction execution in the interrupt service routine

IRQA

, IRQB Assertion to General Purpose Output

16T — ns Figure 3-16 Valid, caused by first instruction execution in the interrupt service routine

IRQA

Low to First Valid Interrupt Vector Address Out

recovery from Wait State

Width Assertion to Recover from Stop State

IRQA

Delay from IRQA

Assertion to Fetch of first instruction

IRI

13T — ns Figure 3-17

2T — ns Figure 3-18

Figure 3-18

(exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1

Duration for Level Sensitive IRQA the Fetch of First IRQA

Interrupt Instruction (exiting

Assertion to Cause

— —

IRQ

275,000T

12T

ns ns

Figure 3-19

Stop) OMR Bit 6 = 0 OMR Bit 6 = 1

Delay from Level Sensitive IRQA

Assertion to First

— —

275,000T

12T

ns ns

Figure 3-19

Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

— —

275,000T

12T

ns ns

56F826 Technical Data, Rev. 14

34 Freescale Semiconductor

Page 35

RESET

RAZ

Reset, Stop, Wait, Mode Select, and Interrupt Timing

RDA

A0–A15,

D0–D15

, DS,

, WR

IRQA, IRQB

A0–A15,

, DS,

, WR

IRQA,

IRQB

First Fetch

Figure 3-14 Asynchronous Reset Timing

IRW

Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive)

First Interrupt Instruction Execution

IDM

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA

IRQB

b) General Purpose I/O

Figure 3-16 External Level-Sensitive Interrupt Timing

56F826 Technical Data, Rev. 14

Freescale Semiconductor 35

Page 36

IRQA,

IRQB

IRI

A0–A15,

, DS,

, WR

First Interrupt Vector Instruction Fetch

Figure 3-17 Interrupt from Wait State Timing

IRQA

A0–A15,

, DS,

, WR

First Instruction Fetch

Not IRQA Interrupt Vector

Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing

IRQ

IRQA

A0–A15 PS

, DS,

, WR

Figure 3-19 Recovery from Stop State Using IRQA

56F826 Technical Data, Rev. 14

First IRQA Interrupt

Instruction Fetch

Interrupt Service

36 Freescale Semiconductor

Page 37

3.9 Serial Peripheral Interface (SPI) Timing

Serial Peripheral Interface (SPI) Timing

Operating Conditions: V

SSIO=VSS

= V

SSA

Table 3-12 SPI Timing

= 0V, V

DDA =VDDIO

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic Symbol Min Max Unit See Figure

Cycle time Master Slave

Enable lead time Master Slave

Enable lag time Master Slave

Clock (SCLK) high time Master Slave

Clock (SCLK) low time Master Slave

Data set-up time required for inputs Master Slave

Data hold time required for inputs Master Slave

Access time (time to data active from high-impedance state) Slave

Disable time (hold time to high-impedance state) Slave

ELD

ELG

50 25

—

100

— —

ns ns

ns 24 12

24.1 12

0 2

— —

ns ns

4.8 15 ns

3.7 15.2 ns

Figures

3-20, 3-21,

3-22, 3-23

Figure 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figure 3-23

Data Valid for outputs Master Slave (after enable edge)

Data invalid Master Slave

Rise time Master Slave

Fall time Master Slave

1. Parameters are guaranteed by design.

— —

4.5

20.4

0 0

— —

11.5

10.0

9.7

9.0

ns ns

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

Figures

3-20, 3-21,

3-22, 3-23

56F826 Technical Data, Rev. 14

Freescale Semiconductor 37

Page 38

(Input)

SCLK (CPOL = 0)

(Output)

SS is held High on master

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

(Input)

SCLK (CPOL = 0)

(Output)

MSB in Bits 14–1 LSB in

Master MSB out Bits 14–1 Master LSB out

Figure 3-20 SPI Master Timing (CPHA = 0)

SS is held High on master

(ref)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in Bits 14–1 LSB in

(ref)

Master MSB out Bits 14– 1 Master LSB out

Figure 3-21 SPI Master Timing (CPHA = 1)

56F826 Technical Data, Rev. 14

38 Freescale Semiconductor

Page 39

(Input)

SCLK (CPOL = 0)

(Input)

ELD

Serial Peripheral Interface (SPI) Timing

ELG

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

SCLK (CPOL = 0)

(Input)

Slave MSB out Bits 14–1

MSB in Bits 14–1 LSB in

Figure 3-22 SPI Slave Timing (CPHA = 0)

ELD

Slave LSB out

ELG

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out Bits 14–1

Slave LSB out

MSB in Bits 14–1 LSB in

Figure 3-23 SPI Slave Timing (CPHA = 1)

56F826 Technical Data, Rev. 14

Freescale Semiconductor 39

Page 40

3.10 Synchronous Serial Interface (SSI) Timing

Table 3-13 SSI Master Mode1 Switching Characteristics

Operating Conditions: V

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

Parameter Symbol Min Typ Max Units

STCK frequency fs

STCK period

STCK high time t

STCK low time t

SCKW

SCKH

SCKL

100 — — ns

Output clock rise/fall time (STCK, SRCK) —

Delay from STCK high to STFS (bl) high - Master

Delay from STCK high to STFS (wl) high - Master

Delay from SRCK high to SRFS (bl) high - Master

Delay from SRCK high to SRFS (wl) high - Master

Delay from STCK high to STFS (bl) low - Master

Delay from STCK high to STFS (wl) low - Master

Delay from SRCK high to SRFS (bl) low - Master

Delay from SRCK high to SRFS (wl) low - Master

TFSBHM

TFSWHM

RFSBHM

RFSWHM

TFSBLM

TFSWLM

RFSBLM

RFSWLM

0.1 — 0.5 ns

0.6 — 1.3 ns

-1.0 — -0.1 ns

-0.1 — 0 ns

——ns

—ns

MHz

STCK high to STXD enable from high impedance - Master t

STCK high to STXD valid - Master t

STCK high to STXD not valid - Master t

STCK high to STXD high impedance - Master t

SRXD Setup time before SRCK low - Master t

SRXD Hold time after SRCK low - Master t

TXEM

TXVM

TXNVM

TXHIM

20 — 22 ns

24 — 26 ns

0.1 — 0.2 ns

24 — 25.5 ns

4—— ns

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master t

SRXD Hold time after STCK low - Master t

1. Master mode is internally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

TSM

THM

4——

56F826 Technical Data, Rev. 14

40 Freescale Semiconductor

Page 41

Synchronous Serial Interface (SSI) Timing

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures.

4. 50% duty cycle

5. bl = bit length; wl = word length

SCKW

SCKH

SCKL

STCK output

STFS (bl) output

STFS (wl) output

STXD

SRCK output

SRFS (bl) output

SRFS (wl) output

SRXD

TXVM

TFSBHM

TFSWHM

TXEM

RFSBHM

RFSWHM

TFSBLM

TXNVM

First Bit Last Bit

RFBLM

TSM

THM

TFSWLM

TXHIM

RFSWLM

Figure 3-24 Master Mode Timing Diagram

56F826 Technical Data, Rev. 14

Freescale Semiconductor 41

Page 42

Table 3-14 SSI Slave Mode1 Switching Characteristics

Operating Conditions: V

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

Parameter Symbol Min Typ Max Units

STCK frequency fs —

STCK period

STCK high time t

STCK low time t

SCKW

SCKH

SCKL

100 — — ns

—— ns

MHz

Output clock rise/fall time — TBD —ns

Delay from STCK high to STFS (bl) high - Slave

Delay from STCK high to STFS (wl) high - Slave

Delay from SRCK high to SRFS (bl) high - Slave

Delay from SRCK high to SRFS (wl) high - Slave

Delay from STCK high to STFS (bl) low - Slave

Delay from STCK high to STFS (wl) low - Slave

Delay from SRCK high to SRFS (bl) low - Slave

Delay from SRCK high to SRFS (wl) low - Slave

TFSBHS

TFSWHS

RFSBHS

RFSWHS

TFSBLS

TFSWLS

RFSBLS

RFSWLS

0.1 — 46 ns

-1 — — ns

-46 — — ns

STCK high to STXD enable from high impedance - Slave t

STCK high to STXD valid - Slave t

STFS high to STXD enable from high impedance (first bit) -

Slave

STFS high to STXD valid (first bit) - Slave t

STCK high to STXD not valid - Slave t

STCK high to STXD high impedance - Slave t

SRXD Setup time before SRCK low - Slave t

SRXD Hold time after SRCK low - Slave t

56F826 Technical Data, Rev. 14

TXES

TXVS

FTXES

FTXVS

TXNVS

TXHIS

—— ns

1—25 ns

5.5 — 25 ns

6—27 ns

11 — 13 ns

11 — 28.5 ns

4—— ns

42 Freescale Semiconductor

Page 43

Table 3-14 SSI Slave Mode1 Switching Characteristics

Operating Conditions: V

Synchronous Serial Interface (SSI) Timing

SSIO

= VSS = V

SSA

= 0V, V

DDA

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

Parameter Symbol Min Typ Max Units

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave t

SRXD Hold time after STCK low - Slave t

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

4. 50% duty cycle

5. bl = bit length; wl = word length

TSS

THS

4——

56F826 Technical Data, Rev. 14

Freescale Semiconductor 43

Page 44

SCKW

STCK input

STFS (bl) input

STFS (wl) input

STXD

SRCK input

SRFS (bl) input

SRFS (wl) input

SCKH

FTXES

TXES

TFSBHS

TFSWHS

TXVS

RFSBHS

RFSWHS

SCKL

TFSBLS

FTXVS

TXNVS

First Bit Last Bit

RFBLS

TFSWLS

TXHIS

RFSWLS

SRXD

Figure 3-25 Slave Mode Clock Timing

3.11 Quad Timer Timing

Table 3-15 Timer Timing

Operating Conditions: V

Timer input period P

Timer input high/low period P

Timer output period P

Timer output high/low period P

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

SSIO

= VSS = V

SSA

= 0V, V

Characteristic Symbol Min Max Unit

DDA

TSS

THS

1, 2

= V

= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

DDIO

INHL

OUT

OUTHL

4T+6 — ns

2T+3 — ns

2T — ns

1T — ns

56F826 Technical Data, Rev. 14

44 Freescale Semiconductor

Page 45

Serial Communication Interface (SCI) Timing

Timer Inputs

INHL

Timer Outputs

OUT

OUTHL

Figure 3-26 Quad Timer Timing

3.12 Serial Communication Interface (SCI) Timing

Table 3-16 SCI Timing

Operating Conditions: V

SSIO=VSS

Characteristic Symbol Min Max Unit

Baud Rate

RXD

TXD

1. f

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

Pulse Width

is the frequency of operation of the system clock in MHz.

MAX

RXD

SCI receive

data pin

(Input)

= V

SSA

= 0V, V

DDA =VDDIO

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

BR — (f

RXD

TXD

RXD

0.965/BR 1.04/BR ns

Figure 3-27 RXD Pulse Width

*2.5)/(80) Mbps

MAX

56F826 Technical Data, Rev. 14

Freescale Semiconductor 45

Page 46

TXD

SCI receive

data pin

(Input)

3.13 JTAG Timing

TXD

Figure 3-28 TXD Pulse Width

1, 3

Operating Conditions: V

SSIO=VSS

= V

Table 3-17 JTAG Timing

SSA

= 0V, V

DDA =VDDIO

=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic Symbol Min Max Unit

TCK frequency of operation

TCK cycle time t

TCK clock pulse width t

TMS, TDI data set-up time t

TMS, TDI data hold time t

TCK low to TDO data valid t

TCK low to TDO tri-state t

TRST

assertion time t

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

TRST

DC 10 MHz

100 — ns

50 — ns

0.4 — ns

1.2 — ns

— 26.6 ns

— 23.5 ns

50 — ns

4T — ns

TCK

(Input)

VM = V

+ (VIH – VIL)/2

Figure 3-29 Test Clock Input Timing Diagram

56F826 Technical Data, Rev. 14

46 Freescale Semiconductor

Page 47

TCK

(Input)

JTAG Timing

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output

TDO

(Output)

TRST

(Input)

Input Data Valid

Output Data Valid

)

Output Data Valid

Figure 3-30 Test Access Port Timing Diagram

TRST

Figure 3-31 TRST Timing Diagram

Figure 3-32 OnCE—Debug Event

56F826 Technical Data, Rev. 14

Freescale Semiconductor 47

Page 48

Part 4 Packaging

4.1 Package and Pin-Out Information 56F826

This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.

TMS

TDI

TDO TRST VDDIO

VSSIO

A15 A14 A13

A12 A11

A10

A9 A8 A7 A6 A5 A4

VDD

A3 A2 A1 A0

EXTBOOT

TCK

TCSDETXD0

PIN 1

PIN 26

RXD0

VSSVDD

TXD1

RXD1

ORIENTATION

MARK

TA0

TA1

TA2

TA3SSMISO

MOSI

SCLK

SSIO

GPIOD7

GPIOD6

VDDIO

GPIOD5

GPIOD4

GPIOD3

GPIOD2

GPIOD1

PIN 76

PIN 51

GPIOD0 GPIOB7 GPIOB6 GPIOB5

GPIOB4 GPIOB3 GPIOB2

GPIOB1 GPIOB0

CLKO

V VSS XTAL EXTAL V

SSA

VDDA VSSIO

VDDIO STCK STFS STD SRCK SRFS SRD

D0D1D2D3D4D5D6D7D8

IRQA

IRQB

VSSIO

VDDIO

D10

D11

RESET

D12

D13

D14

D15

Figure 4-1 Top View, 56F826 100-pin LQFP Package

56F826 Technical Data, Rev. 14

48 Freescale Semiconductor

Page 49

Package and Pin-Out Information 56F826

Table 4-1 56F826 Pin Identification by Pin Number

Pin No.

1TMS26 RD

2TDI27 WR

3 TDO 28 DS

4TRST

7 A15 32 IRQA 57 V

8 A14 33 IRQB

9 A13 34 D0 59 V

10A1235D160 V

Signal

Name

DDIO

SSIO

Pin No. Signal Name Pin No. Signal Name Pin No.

51 SRD 76 GPIOD2

52 SRFS 77 GPIOD3

53 SRCK 78 GPIOD4

29 PS 54 STD 79 GPIOD5

30 V

31 V

DDIO

SSIO

55 STFS 80 V

56 STCK 81 V

DDIO

58 V

SSIO

DDA

SSA

82 GPIOD6

83 GPIOD7

84 SCLK

85 MOSI

Signal

Name

DDIO

SSIO

11 A11 36 D2 61 EXTAL 86 MISO

12A1037D362 XTAL87SS

13 A9 38 D4 63 V

14 A8 39 D5 64 V

88 TA3

89 TA2

15 A7 40 D6 65 CLKO 90 TA1

16 A6 41 D7 66 GPIOB0 91 TA0

17 A5 42 D8 67 GPIOB1 92 RXD1

18 A4 43 D9 68 GPIOB2 93 TXD1

19 V

20 V

44 D10 69GPIOB394V

45 RESET 70 GPIOB4 95 V

21 A3 46 D11 71 GPIOB5 96 RXD0

22 A2 47 D12 72 GPIOB6 97 TXD0

23 A1 48 D13 73 GPIOB7 98 DE

24 A0 49 D14 74 GPIOD0 99 TCS

25 EXTBOOT 50 D15 75 GPIOD1 100 TCK

56F826 Technical Data, Rev. 14

Freescale Semiconductor 49

Page 50

-AB-

T- U

0.15(0.006) Z

-T-

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

T-U

0.15(0.006) Z

-Z-

T- U

0.15(0.006) Z

-U-

0.15(0.006) Z

T- U

-AC-

96X

(24X PER SIDE)

0.100(0.004)

SEATING PLANE

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-.

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED

0.350 (0.014). DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.070 (0.003).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.003).

9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.

DIM MIN M AX MIN MAX

A 13.950 14.050 0.549 0.553

B 13.950 14.050 0.549 0.553 C 1.400 1.600 0.055 0.063 D 0.170 0.270 0.007 0.011

E 1.350 1.450 0.053 0.057

F 0.170 0.230 0.007 0.009 G 0.500 BSC 0.020 BSC H 0.050 0.150 0.002 0.006

J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12 REF 12 REF

°°

N 0.090 0.160 0.004 0.006 Q 1 5 1 5

°°°°

R 0.150 0.250 0.006 0.010

S 15.950 16.050 0.628 0.632 V 15.950 16.050 0.628 0.632 W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF

INCHESMILLIMETERS

T- U

0.25 (0.010)

GAUGE PLANE

0.20(0.008) Z

SECTION AE-AE

DETAIL AD

CASE 842F-01

Figure 4-2 100-pin LQPF Mechanical Information

Please see www.freescale.com for the most current case outline.

56F826 Technical Data, Rev. 14

50 Freescale Semiconductor

Page 51

Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1:

TJTAPDR

×()+=

θJA

Where:

TA = ambient temperature °C R

= package junction-to-ambient thermal resistance °C/W

θJA

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

Equation 2:

θJARθJCRθCA

Where:

= package junction-to-ambient thermal resistance °C/W

θJA

= package junction-to-case thermal resistance °C/W

θJC

= package case-to-ambient thermal resistance °C/W

θCA

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

θJA

the thermal performance is adequate, a system-level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages:

• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface.

• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction-to-board thermal resistance.

56F826 Technical Data, Rev. 14

Freescale Semiconductor 51

Page 52

• Use the value obtained by the equation (TJ – TT)/PD, where TT is the temperature of the package case determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each V controller, and from the board ground to each V

SS,VSSIO,

and V

DD, VDDIO,

(GND) pin.

SSA

• The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V

DD/VSS

pairs, including V

DDA/VSSA

and V

DDIO/VSSIO.

Ceramic and tantalum capacitors tend to provide

better performance tolerances.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V V

and V

DDA

• Bypass the V

SS, VSSIO,

and VSS layers of the PCB with approximately 100μF, preferably with a high-grade

and V

(GND) pins are less than 0.5 inch per capacitor lead.

SSA

capacitor such as a tantalum capacitor.

and V

pin on the

DDA

DD, VDDIO,

and

56F826 Technical Data, Rev. 14

52 Freescale Semiconductor

Page 53

Electrical Design Considerations

• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V

• Take special care to minimize noise levels on the VREF, V

• When using Wired-OR mode on the SPI or the IRQx

• Designs that utilize the TRST debugging systems) should allow a means to assert TRST to assert TRST that do not require debugging functionality, such as consumer products, TRST

and VSS circuits.

independently of RESET. TRST must be asserted at power up for proper operation. Designs

DDA

and V

SSA

pins.

pins, the user must provide an external pull-up device.

pin for JTAG port or OnCE module functionality (such as development or

whenever RESET is asserted, as well as a means

should be tied low.

• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming.

56F826 Technical Data, Rev. 14

Freescale Semiconductor 53

Page 54

Part 6 Ordering Information

Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 6-1 56F826 Ordering Information

Part

56F826 3.0–3.6 V

Supply

Voltage

Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80

2.25-2.75 V

Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80E *

2.25-2.75 V

*This package is RoHS compliant.

Package Type

Count

Ambient

Frequency

(MHz)

Order Number

56F826 Technical Data, Rev. 14

54 Freescale Semiconductor

Page 55

Electrical Design Considerations

56F826 Technical Data, Rev. 14

Freescale Semiconductor 55

Page 56

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

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DSP56F826 Rev. 14 01/2007

Freescale 56 F 826 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Part 1 Overview

1.1 56F826 Features

1.1.1 Processing Core

1.1.2 Memory

1.1.3 Peripheral Circuits for 56F826

1.1.4 Energy Information

1.2 56F826 Description

1.3 Award-Winning Development Environment

1.4 Product Documentation

1.5 Data Sheet Conventions

Part 2 Signal/Connection Descriptions

2.1 Introduction

2.2 Signals and Package Information

Part 3 Specifications

3.1 General Characteristics

3.2 DC Electrical Characteristics

3.3 Supply Voltage Sequencing and Separation Cautions

3.4 AC Electrical Characteristics

3.5 Flash Memory Characteristics

3.6 External Clock Operation

3.6.1 Crystal Oscillator

3.6.2 Ceramic Resonator

3.6.3 External Clock Source

3.6.4 Phase Locked Loop Timing

3.7 External Bus Asynchronous Timing

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

3.9 Serial Peripheral Interface (SPI) Timing

3.10 Synchronous Serial Interface (SSI) Timing

3.11 Quad Timer Timing

3.12 Serial Communication Interface (SCI) Timing

3.13 JTAG Timing

Part 4 Packaging

4.1 Package and Pin-Out Information 56F826

Part 5 Design Considerations

5.1 Thermal Design Considerations

5.2 Electrical Design Considerations

Part 6 Ordering Information