•Two 36-bit accumulators, including extension bits
•16-bit bidirectional barrel shifter
•Parallel instruction set with unique processor addressing modes
•Hardware DO and REP loops
•Three internal address buses and one external address bus
•Four internal data buses and one external data bus
•Instruction set supports both DSP and controller functions
•Controller-style addressing modes and instructions for compact code
•Efficient C Compiler and local variable support
•Software subroutine and interrupt stack with depth limited only by memory
•JTAG/OnCE Debug Programming Interface
1.1.2Memory
•Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
•On-chip memory including a low-cost, high-volume Flash solution
—31.5K
—512
—2K
—4K
—2K
•Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
— As much as 64K
× 16-bit words of Program Flash
× 16-bit words of Program RAM
× 16-bit words of Data Flash
× 16-bit words of Data RAM
× 16-bit words of BootFLASH
× 16-bit Data memory
× 16-bit Program memory
1.1.3Peripheral Circuits for 56F826
•One General Purpose Quad Timer totalling 7 pins
•One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)
•One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces
totalling 4 pins
•Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)
56F826 Technical Data, Rev. 14
4 Freescale Semiconductor
Page 5
56F826 Description
•Sixteen (16) dedicated General Purpose I/O (GPIO) pins
•Thirty (30) shared General Purpose I/O (GPIO) pins
•Computer-Operating Properly (COP) Watchdog timer
•Two external interrupt pins
•External reset pin for hardware reset
•JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
•Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
•Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs
•One Time of Day module
1.1.4Energy Information
•Dual power supply, 3.3V and 2.5V
•Wait and Multiple Stop modes available
1.2 56F826 Description
The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.
The 56F826 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, POS terminals, feature phones.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F826 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external
dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It
also supports program execution from external memory.
The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of
field-programmable software routines that can be used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page
sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.
56F826 Technical Data, Rev. 14
Freescale Semiconductor5
Page 6
This controller also provides a full set of standard programmable peripherals including one Synchronous
Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial
Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as
General Purpose Input/Outputs (GPIOs) if a timer function is not required.
1.3 Award-Winning Development Environment
•Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
•The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F826 Chip Documentation
TopicDescriptionOrder Number
56800E
Family Manual
DSP56F826/F827
User’s Manual
56F826
Technical Data Sheet
56F826
Product Brief
56F826
Errata
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Summary description and block diagram of the 56F826
core, memory, peripherals and interfaces
Details any chip issues that might be presentDSP56F826E
56800EFM
DSP56F826-827UM
DSP56F826
DSP56F826PB
56F826 Technical Data, Rev. 14
6 Freescale Semiconductor
Page 7
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBARThis is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”A high true (active high) signal is low or a low true (active low) signal is high.
Data Sheet Conventions
Examples:Signal/SymbolLogic StateSignal State
PINTrueAssertedVIL/V
PINFalseDeassertedVIH/V
PINTrueAssertedVIH/V
PINFalseDeassertedVIL/V
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Voltage
OL
OH
OH
OL
1
56F826 Technical Data, Rev. 14
Freescale Semiconductor7
Page 8
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional GroupNumber of Pins
Power (V
Ground (V
PLL and Clock3
Address Bus
Data Bus
Bus Control4
Quad Timer Module Ports
JTAG/On-Chip Emulation (OnCE)6
Dedicated General Purpose Input/Output16
Synchronous Serial Interface (SSI) Port
Serial Peripheral Interface (SPI) Port
Serial Communications Interface (SCI) Ports4
Interrupt and Program Control5
1. Alternately, GPIO pins
DD
1
SS
, V
, V
1
DDIO or VDDA
SSIO or VSSA
)(3,4,1)
)(3,4,1)
16
16
1
1
1
4
6
4
56F826 Technical Data, Rev. 14
8 Freescale Semiconductor
Page 9
Introduction
2.5V Power
3.3V Analog Power
3.3V Power
Ground
Analog Ground
Ground
PLL
and
Clock
External
Address Bus or
GPIO
External Data
Bus
External
Bus Control
V
DD
V
DDA
V
DDIO
V
SS
V
SSA
V
SSIO
EXTAL
XTAL (CLOCKIN)
CLKO
A0-A7 (GPIOE)
A8-A15 (GPIOA)
D0–D15
PS
DS
RD
WR
3
1
4
4*
1
4
1
1
1
8
8
16
1
1
1
1
56F826
GPIOB0–7
8
GPIOD0–7
8
SRD (GPIOC0)
1
SRFS (GPIOC1)
1
SRCK (GPIOC2)
1
STD (GPIOC3)
1
STFS (GPIOC4)
1
STCK (GPIOC5)
1
SCLK (GPIOF4)
1
MOSI (GPIOF5)
1
MISO (GPIOF6)
1
SS
1
TXD0 (SCLK0)
1
RXD0 (MOSI0)
1
TXD1 (MISO0)
1
RXD1 (SS0
1
Dedicated
GPIO
SSI Port
or GPIO
SPI1 Port
or GPIO
(GPIOF7)
SCI0, SCI1
Port or
SPI0 Port
)
TA0 (GPIOF0)
Quad Timer A
or GPIO
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
JTAG/OnCE™
Port
TDI
TDO
TRST
DE
*Includes TCS pin, which is reserved for factory use and is tied toVSS
Figure 2-1 56F826 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parentheses.
1
1
1
1
1
1
1
IRQA
1
1
1
1
1
1
1
IRQB
RESET
EXTBOOT
Interrupt/
Program
Control
1
56F826 Technical Data, Rev. 14
Freescale Semiconductor9
Page 10
2.2 Signals and Package Information
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:
1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
V
DD
V
DD
V
DD
V
DDA
Pin No.TypeDescription
20V
64V
94V
59V
DD
DD
DD
DDA
Power—These pins provide power to the internal structures of the chip, and are
generally connected to a 2.5V supply.
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
V
V
V
V
V
V
V
V
V
DDIO
DDIO
DDIO
DDIO
V
SS
V
SS
V
SS
SSA
SSIO
SSIO
SSIO
SSIO
5V
30V
57V
80V
19V
63V
95V
60V
6V
31V
58V
81V
DDIO
DDIO
DDIO
DDIO
SS
SS
SS
SSA
SSIO
SSIO
SSIO
SSIO
TCS99Input/Output
(Schmitt)
Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
GND—These pins provide grounding for the internal structures of the chip. All
should be attached to V
SS.
Analog Ground—This pin supplies an analog ground.
GND In/Out—These pins provide grounding for the I/O ring on the chip. All
should be attached to V
SS.
TCS—This pin is reserved for factory use. It must be tied to VSS for normal use.
In block diagrams, this pin is considered an additional V
SS.
EXTAL61InputExternal Crystal Oscillator Input—This input should be connected to a 4MHz
external crystal or ceramic resonator. For more information, please refer to
Section 3.6.
56F826 Technical Data, Rev. 14
10 Freescale Semiconductor
Page 11
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
XTAL
(CLOCKIN)
CLKO65OutputClock Output—This pin outputs a buffered clock signal. By programming the
A0
(GPIOE0)
A1
(GPIOE1)
A2
(GPIOE2)
A3
(GPIOE3)
A4
(GPIOE4)
Pin No.TypeDescription
62Output
Input
24Output
23
22
21
18
Input/Output
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
V
. For more information, please refer to Section 3.6.3.
SS
External Clock Input—This input should be asserted when using an external
clock or ceramic resonator.
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock at
the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
Address Bus—A0–A7 specify the address for external program or data memory
accesses.
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A5
(GPIOE5)
A6
(GPIOE6)
A7
(GPIOE7)
17
16
15
56F826 Technical Data, Rev. 14
Freescale Semiconductor11
Page 12
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
A8
(GPIOA0)
A9
(GPIOA1)
A10
(GPIOA2)
A11
(GPIOA3)
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
A15
(GPIOA7)
D034Input/OutputData Bus— D0–D15 specify the data for external program or data memory
D135
D236
Pin No.TypeDescription
14Output
13
12
11
10
9
8
7
Input/Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
accesses. D0–D15 are tri-stated when the external bus is inactive.
D337
D438
D539
D640
D741
D842
D943
D1044
D1146
D1247
D1348
D1449
D1550
PS
DS
29OutputProgram Memory Select—PS is asserted low for external program memory
28OutputData Memory Select—DS is asserted low for external data memory access.
access.
56F826 Technical Data, Rev. 14
12 Freescale Semiconductor
Page 13
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
RD
WR
TA0
(GPIOF0)
TA1
(GPIOF1)
TA2
(GPIOF2)
TA3
(GPIOF3)
TCK100Input
TMS1Input
Pin No.TypeDescription
26OutputRead Enable—RD is asserted during external memory read cycles. When RD is
27OutputWrite Enable—WR is asserted during external memory write cycles. When WR
91Input/Output
90
89
88
Input/Output
(Schmitt)
(Schmitt)
asserted low, pins D0–D15 become inputs and an external device is enabled
onto the device data bus. When RD
latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and
pins. RD can be connected directly to the OE pin of a Static RAM or ROM.
DS
is asserted low, pins D0–D15 become outputs and the device puts data on the
bus. When WR
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins.
WR can be connected directly to the WE pin of a Static RAM.
TA0–3—Timer A Channels 0, 1, 2, and 3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually
programmed as input or output.
After reset, the default state is Quad Timer.
Test Clock Input—This input pin provides a gated clock to synchronize the test
logic and shift serial data to the JTAG/OnCE port. The pin is connected internally
to a pull-down resistor.
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
is deasserted high, the external data is latched inside the
is deasserted high, the external data is
Note:Always tie the TMS pin to V
TDI2Input
(Schmitt)
TDO3OutputTest Data Output—This tri-statable output pin provides a serial output data
TRST
DE
4Input
(Schmitt)
98OutputDebug Event—DE provides a low pulse on recognized debug events.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET
do not assert TRST
Note:For normal operation, connect TRST
in a debugging environment, TRST
56F826 Technical Data, Rev. 14
. TRST must always be asserted at power-up.
is asserted. The only exception occurs in a
through a 2.2K resistor.
DD
directly to VSS. If the design is to be used
may be tied to VSS through a 1K resistor.
, but
Freescale Semiconductor13
Page 14
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
GPIOB066Input or
GPIOB167
GPIOB268
GPIOB369
GPIOB470
GPIOB571
GPIOB672
GPIOB773
GPIOD074Input or
GPIOD175
GPIOD276
GPIOD377
GPIOD478
GPIOD579
GPIOD682
GPIOD783
Pin No.TypeDescription
Output
Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is GPIO input.
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
SRD
(GPIOC0)
SRFS
(GPIOC1)
51Input/Output
Input/Output
52Input/ Output
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used
only by the receiver. It is used to synchronize data transfer and can be an input
or an output.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
56F826 Technical Data, Rev. 14
14 Freescale Semiconductor
Page 15
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
SRCK
(GPIOC2)
STD
(GPIOC3)
STFS
(GPIOC4)
Pin No.TypeDescription
53Input/Output
Input/Output
54Output
Input/Output
55Input
Input/Output
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit
rate clock for the Receive section of the SSI. The clock signal can be continuous
or gated and can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the
Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used
by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
STCK
(GPIOC5)
SCLK
(GPIOF4)
MOSI
(GPIOF5)
56Input/ Output
Input/Output
84Input/Output
Input/Output
85Input/Output
Input/Output
After reset, the default state is GPIO input.
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the SSI. The clock signal can be continuous
or gated. It can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data on
the MOSI line a half-cycle before the clock edge that the slave device uses to
latch the data.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
56F826 Technical Data, Rev. 14
Freescale Semiconductor15
Page 16
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
MISO
(GPIOF6)
SS
(GPIOF7)
TXD0
(SCLK0)
RXD0
Pin No.TypeDescription
86Input/Output
Input/Output
87Input
Input/Output
97Output
Input/Output
96Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS
Transmit Data (TXD0)—transmit data output
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
Receive Data (RXD0)— receive data input
.
(MOSI0)
TXD1
(MISO0)
RXD1
)
(SS0
Input/Output
93Output
Input/Output
92Input
(Schmitt)
Input
SPI Master Out/Slave In—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
Transmit Data (TXD1)—transmit data output
SPI Master In/Slave Out—This serial data pin is an input to a master device and
an output from a slave device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
After reset, the default state is SCI output.
Receive Data (RXD1)— receive data input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
56F826 Technical Data, Rev. 14
16 Freescale Semiconductor
Page 17
Signals and Package Information
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
IRQA
IRQB
RESET45Input
EXTBOOT25Input
Pin No.TypeDescription
32Input
(Schmitt)
33Input
(Schmitt)
(Schmitt)
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA
the Stop state.
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the device is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET
External Boot—This input is tied to V
memory. Otherwise, it is tied to ground.
is asserted, the processor will exit
and TRST should be asserted
, but do not assert TRST.
to force device to boot from off-chip
DD
56F826 Technical Data, Rev. 14
Freescale Semiconductor17
Page 18
Part 3 Specifications
3.1 General Characteristics
The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
56F826 Technical Data, Rev. 14
18 Freescale Semiconductor
Page 19
General Characteristics
Table 3-1 Absolute Maximum Ratings
CharacteristicSymbolMinMaxUnit
Supply voltage, core
Supply voltage, IO
Supply voltage, Analog
V
V
V
DDIO
Digital input voltages
Analog input voltages - XTAL, EXTAL
Voltage difference V
Voltage difference V
Current drain per pin excluding V
V
, V
DDIO
SSIO
DD
SS
to V
to V
DD_IO
SS _IO
, V
, V
DD
DDA
SSA
, V
SS, VDDA
, V
SSA,
V
ΔV
ΔV
Junction temperatureT
Storage temperature rangeT
1. VDD must not exceed V
2. V
DDIO
and V
DDA
DDIO
must not differ by more that 0.5V
Table 3-2 Recommended Operating Conditions
CharacteristicSymbolMinTypMaxUnit
DD
DDA
V
IN
INA
1
2
2
DD
SS
VSS – 0.3V
V
– 0.3
SSIO
– 0.3
V
SSA
V
– 0.3
SSIO
– 0.3
V
SSA
V
V
V
V
SS
SSIO
SSA
SSIO
DDA
+ 3.0
+ 4.0
+ 4.0
+ 5.5
+ 0.3
- 0.30.3V
- 0.30.3V
I— 10
J
STG
—150°C
–55150°C
V
V
V
mA
Supply voltage, core V
Supply Voltage, IO and analogV
Voltage difference V
Voltage difference V
DD
SS
to V
to V
DD_IO
SS _IO
, V
, V
DDA
SSA
DDIO,VDDA
ΔV
ΔV
Ambient operating temperatureT
DD
DD
SS
A
2.252.52.75V
3.03.33.6V
-0.1-0.1V
-0.1-0.1V
–40–85°C
56F826 Technical Data, Rev. 14
Freescale Semiconductor19
Page 20
Characteristic
Table 3-3 Thermal Characteristics
Comments
Symbol
100-pin LQFP
6
Value
UnitNotes
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)R
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)Four layer board (2s2p)R
Junction to caseR
Junction to center of caseΨ
I/O pin power dissipationP
Power dissipationP
Junction to center of caseP
Four layer board (2s2p)R
R
(2s2p)
θJA
θJMA
θJMA
θJMA
θJC
JT
I/O
D
DMAX
P D = (IDD x VDD + P
48.3°C/W2
43.9°C/W2
40.7°C/W1.2
38.6°C/W1,2
13.5°C/W3
1.0°C/W4, 5
User DeterminedW
)W
I/O
(TJ - TA) /RθJA
Notes:
1.Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2.Junction to ambient thermal resistance, Theta-JA (R
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the
number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with
the non-single layer boards is Theta-JMA.
3.Junction to case thermal resistance, Theta-JC (R
using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4.Thermal Characterization Parameter, Psi-JT (ΨJT), is the “resistance” from junction to reference point
thermocouple on top center of case as defined in JESD51-2. Ψ
temperature in steady state customer environments.
5.Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6.See Section 5.1 for more details on thermal design considerations.
7.TJ = Junction Temperature
TA = Ambient Temperature
) was simulated to be equivalent to the JEDEC
θJA
), was simulated to be equivalent to the measured values
θJC
is a useful value to use to estimate junction
JT
W7
56F826 Technical Data, Rev. 14
20 Freescale Semiconductor
Page 21
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: V
SSIO=VSS
= V
SSA
= 0V, V
DDA =VDDIO
=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
CharacteristicSymbolMinTypMaxUnit
DC Electrical Characteristics
Input high voltage (XTAL/EXTAL)V
Input low voltage (XTAL/EXTAL)V
Input high voltage (Schmitt trigger inputs)
Input low voltage (Schmitt trigger inputs)
1
1
V
Input high voltage (all other digital inputs)V
Input low voltage (all other digital inputs)V
Input current high (pull-up/pull-down resistors disabled,
V
IHC
ILC
IHS
ILS
I
IH
IH
IL
2.25—3.6V
0—0.5V
2.2—5.5V
-0.3—0.8V
2.0—5.5V
-0.3—0.8V
-1—1μA
VIN=VDD)
Input current low (pull-up/pull-down resistors disabled,
I
IL
-1—1μA
VIN=VSS)
Input current high (with pull-up resistor, V
Input current low (with pull-up resistor, V
IN=VSS
Input current high (with pull-down resistor, VIN=VDD)I
Input current low (with pull-down resistor, V
Nominal pull-up or pull-down resistor valueR
)I
IN=VDD
)I
)I
IN=VSS
IHPU
ILPU
IHPD
ILPD
PU
, R
PD
-1—1μA
-210—-50μA
20—180μA
-1—1μA
30KΩ
Output tri-state current lowI
Output tri-state current highI
2
Input current high (analog inputs, V
Input current low (analog inputs, V
IN=VDDA
IN=VSSA
)
2
)
Output High Voltage (at IOH)V
Output Low Voltage (at IOL)V
Output source currentI
Output sink currentI
PWM pin output source current
PWM pin output sink current
3
4
OZL
OZH
I
I
I
OHP
I
OLP
IHA
ILA
OH
OL
OH
OL
-10—10μA
-10—10μA
-15—15μA
-15—15μA
VDD – 0.7——V
——0.4V
4——mA
4——mA
10——mA
16——mA
56F826 Technical Data, Rev. 14
Freescale Semiconductor21
Page 22
Operating Conditions: V
Table 3-4 DC Electrical Characteristics (Continued)
= V
SSIO=VSS
SSA
= 0V, V
DDA =VDDIO
CharacteristicSymbolMinTypMaxUnit
=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. I
DDT
= IDD + I
(Total supply current for VDD + V
DDA
DDA
)
6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
inputs; measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (f
less than 50pF on all outputs. C
measured with PLL enabled.
8. This low-voltage interrupt monitors the V
of the device is guaranteed under transient conditions when V
the V
interrupt is generated).
EIO
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;
L
power supply. If V
DDIO
9. This low-voltage interrupt monitors theVDD power supply. If V
the device is guaranteed under transient conditions when V
V
interrupt is generated).
EIC
osc
DDIO
DDIO >VEIO
DDIO
DD >VEIC
(between the minimum specified V
10. Power–on reset occurs whenever the VDD power supply drops below V
active for as long as V
is below V
DD
no matter how long the ramp-up rate is.
POR
V
V
V
EIO
EIC
POR
2.42.73.0V
2.02.22.4V
—1.72.0V
= 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads;
drops below V
(between the minimum specified V
drops below V
. While power is ramping up, this signal remains
POR
, an interrupt is generated. Functionality
EIO
, an interrupt is generated. Functionality of
EIC
and the point when
DDIO
and the point when the
DD
56F826 Technical Data, Rev. 14
22 Freescale Semiconductor
Page 23
100
75
50
25
IDD (mA)
IDD Digital
IDD Analog
Supply Voltage Sequencing and Separation Cautions
IDD Total
0
20
40
60
Freq. (MHz)
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)
3.3 Supply Voltage Sequencing and Separation Cautions
Figure 3-2 shows two situations to avoid in sequencing the VDD and V
3.3V
2
2.5V
1
Supplies Stable
DDIO, VDDA
supplies.
V
DDIO,VDDA
80
V
DD
DC Power Supply Voltage
0
Notes: 1. VDD rising before V
2. V
DDIO
, V
rising much faster than V
DDA
DDIO
, V
DDA
DD
Time
Figure 3-2 Supply Voltage Sequencing and Separation Cautions
56F826 Technical Data, Rev. 14
Freescale Semiconductor23
Page 24
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
supply (2.5V) from the voltage generated by the 3.3V V
rising faster than V
DDIO
.
supply, see Figure 3-3. This keeps VDD from
DDIO
DD
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between V
approximately 1.4, causing V
to rise as V
DD
ramps up. When the V
DDIO
DD
regulator begins proper
DDIO
and V
DD
reaches
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V
DDIO
> V
DD
> (V
DDIO
- 1.4V)
In practice, V
is typically connected directly to V
DDA
with some filtering.
DDIO
3.3V
Supply
Regulator
2.5V
Regulator
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the VIL and V
table. The levels of VIH and VIL for an input signal are shown in Figure 3-4.
Pulse Width
LowHigh
V
IL
Input Signal
Midpoint1
Fall Time
V
IH
levels specified in the DC Characteristics
IH
Rise Time
V
DDIO,VDDA
V
DD
90%
50%
10%
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
•Active state, when a bus or signal is driven, and enters a low impedance state
•Tri-stated, when a bus or signal is placed in a high impedance state
•Data Valid state, when a signal level has reached V
•Data Invalid state, when a signal level is in transition between VOL and V
56F826 Technical Data, Rev. 14
24 Freescale Semiconductor
OL
or V
OH
OH
Page 25
Flash Memory Characteristics
Data1 Valid
Data1
Data2 Valid
Data2Data3
Data Invalid State
Data ActiveData Active
Figure 3-5 Signal States
3.5 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode
StandbyLLLLLLLL
ReadHHHHLLLL
Word ProgramHHLLHLLH
Page EraseHLLLLHLH
Mass EraseHLL LLHHH
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
XE
1
YE
2
SE
3
OE
4
Tri-stated
PROG
Data
5
ERASE
Data3 Valid
6
MAS1
7
NVSTR
8
Table 3-6 IFREN Truth Table
ModeIFREN = 1IFREN = 0
ReadRead information blockRead main memory block
Word programProgram information blockProgram main memory block
Page eraseErase information blockErase main memory block
Mass eraseErase both blockErase main memory block
56F826 Technical Data, Rev. 14
Freescale Semiconductor25
Page 26
Table 3-7 Flash Timing Parameters
Operating Conditions: V
CharacteristicSymbolMin TypMax UnitFigure
Program time
Erase time
Mass erase time
Endurance1
Data Retention
PROG/ERASE to NVSTR set
up time
NVSTR hold time
NVSTR hold time (mass erase)
NVSTR to program set up time
Recovery time
1
The following parameters should only be used in the Manual Word Programming Mode
= V
SS
Tprog*
Terase*
Tme*
E
CYC
D
RET
Tnvs*
Tnvh*
Tnvh1*
Tpgs*
Trcv*
= 0 V, VDD = V
SSA
20––usFigure 3-6
20––msFigure 3-7
100––msFigure 3-8
10,00020,000–cycles
1030–years
–5–usFigure 3-6,
–5–usFigure 3-6,
–100–usFigure 3-8
–10–usFigure 3-6
–1–usFigure 3-6,
= 3.0–3.6V, TA = –40° to +85°C, CL ≤50pF
DDA
Figure 3-7,
Figure 3-8
Figure 3-7
Figure 3-7,
Figure 3-8
Cumulative program
HV period
Program hold time
Address/data set up time
Address/data hold time
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
2
3
3
3
Thv
Tpgh
Tads
Tadh
56F826 Technical Data, Rev. 14
–3–ms Figure 3-6
–––Figure 3-6
–––Figure 3-6
–––Figure 3-6
26 Freescale Semiconductor
Page 27
IFREN
XADR
Flash Memory Characteristics
XE
YADR
YE
DIN
PROG
NVSTR
IFREN
Tnvs
Tadh
Tads
Tprog
Tpgs
Thv
Figure 3-6 Flash Program Cycle
Tpgh
Tnvh
Trcv
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Terase
Tnvh
Trcv
Figure 3-7 Flash Erase Cycle
56F826 Technical Data, Rev. 14
Freescale Semiconductor27
Page 28
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tme
Tnvh1
Trcv
Figure 3-8 Flash Mass Erase Cycle
3.6 External Clock Operation
The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.6.1Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-9. A recommended crystal oscillator circuit
is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL
and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
56F826 Technical Data, Rev. 14
28 Freescale Semiconductor
Page 29
External Clock Operation
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
CL =
CL1 * CL2
CL1 + CL2
+ Cs =
12 * 12
+ 3 = 6 + 3 = 9pF
12 + 12
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
EXTAL XTAL
R
z
f
c
Recommended External Crystal
Parameters:
Rz = 1 to 3MΩ
= 4Mhz (optimized for 4MHz)
f
c
Figure 3-9 Connecting to a Crystal Oscillator Circuit
3.6.2Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in
Figure 3-10. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-10, no external load capacitors should be used.
EXTAL XTAL
R
z
f
c
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
= 4Mhz (optimized for 4MHz)
f
c
Figure 3-10 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
56F826 Technical Data, Rev. 14
Freescale Semiconductor29
Page 30
3.6.3External Clock Source
The recommended method of connecting an external clock is given in Figure 3-11. The external clock
source is connected to XTAL and the EXTAL pin is held V
=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
CharacteristicSymbolMinTypMaxUnit
1
f
t
PW
t
osc
PW
Frequency of operation (external clock driver)
Clock Pulse Width
1. See Figure 3-11 for details on using the recommended connection of an external clock driver.
2. When using Time of Day (TOD), maximum external frequency is 6MHz.
3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
4. Parameters listed are guaranteed by design.
External
Clock
3, 4
50%
10%
90%
t
PW
04
6.25——ns
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-12 External Clock Timing
80
2
90%
50%
10%
MHz
V
IH
V
IL
56F826 Technical Data, Rev. 14
30 Freescale Semiconductor
Page 31
3.6.4Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: V
SSIO
= VSS = V
SSA
= 0V, V
DDA
= V
DDIO
CharacteristicSymbolMinTypMaxUnit
External Bus Asynchronous Timing
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
External reference crystal frequency for the PLL
2
PLL output frequency
PLL stabilization time
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 4MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
User Manual. ZCLK = f
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
3
-40o to +85oC
op
1
f
osc
f
/240—110MHz
out
t
plls
246MHz
—110ms
/2, please refer to the OCCS chapter in the
out
3.7 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing
Operating Conditions: V
Address Valid to WR Assertedt
Width Asserted
WR
Wait states = 0
Wait states > 0
SSIO
= VSS = V
SSA
= 0V, V
DDA
= V
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
CharacteristicSymbol
AWR
t
WR
Min
6.5 —ns
7.5
(T*WS) + 7.5
1, 2
Max
—
—
Unit
ns
ns
Asserted to D0–D15 Out Validt
WR
Data Out Hold Time from WR
Data Out Set Up Time to WR
Deassertedt
Deasserted
Wait states = 0
Wait states > 0
Deasserted to Address Not Validt
RD
Address Valid to RD
Deasserted
Wait states = 0
Wait states > 0
WRD
DOH
t
DOS
RDA
t
ARDD
—T + 4.2ns
4.8—ns
2.2
(T*WS) + 6.4
—
—
ns
ns
0—ns
—
18.7
(T*WS) + 18.7
ns
ns
56F826 Technical Data, Rev. 14
Freescale Semiconductor31
Page 32
Table 3-10 External Bus Asynchronous Timing
1, 2
(Continued)
Operating Conditions: V
SSIO
= VSS = V
SSA
= 0V, V
CharacteristicSymbol
Input Data Hold to RD
Assertion Width
RD
Deassertedt
Wait states = 0
Wait states > 0
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
Address Valid to RD
Asserted to Input Data Valid
RD
Assertedt
Wait states = 0
Wait states > 0
Deasserted to RD Assertedt
WR
Deasserted to RD Asserted t
RD
WR
Deasserted to WR Asserted t
DDA
= V
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
DRD
t
RD
t
AD
ARDA
t
RDD
WRRD
RDRD
WRWR
Min
0—ns
19
(T*WS) + 19
—
—
(T*WS) + 1
-4.4—ns
—
—
(T*WS) + 2.4
6.8—ns
0—ns
14.1—ns
Max
—
—
1
2.4
Unit
ns
ns
ns
ns
ns
ns
Deasserted to WR Assertedt
RD
1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
RDWR
12.8—ns
56F826 Technical Data, Rev. 14
32 Freescale Semiconductor
Page 33
A0–A15,
PS
, DS
(See Note)
RD
t
AWR
t
WRWR
t
WR
t
ARDA
t
WRRD
t
ARDD
t
RD
External Bus Asynchronous Timing
t
RDA
t
RDRD
t
RDWR
WR
D0–D15
t
WRD
t
DOS
t
DOH
t
AD
t
RDD
t
DRD
Data InData Out
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 3-13 External Bus Asynchronous Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor33
Page 34
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: V
SSIO
= VSS = V
SSA
= 0V, V
DDA
= V
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
1, 5
CharacteristicSymbolMinMaxUnitSee Figure
RESET
Assertion to Address, Data and Control
t
RAZ
—21nsFigure 3-14
Signals High Impedance
Minimum RESET
Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
RESET
Deassertion to First External Address Outputt
Edge-sensitive Interrupt Request Width t
IRQA
, IRQB Assertion to External Data Memory
t
RA
RDA
IRW
t
IDM
275,000T
128T
—
—
ns
ns
33T34TnsFigure 3-14
1.5T—nsFigure 3-15
15T—nsFigure 3-16
Figure 3-14
Access Out Valid, caused by first instruction execution
in the interrupt service routine
IRQA
, IRQB Assertion to General Purpose Output
t
IG
16T—nsFigure 3-16
Valid, caused by first instruction execution in the
interrupt service routine
IRQA
Low to First Valid Interrupt Vector Address Out
recovery from Wait State
Width Assertion to Recover from Stop State
IRQA
Delay from IRQA
3
Assertion to Fetch of first instruction
4
t
IRI
t
IW
t
IF
13T—nsFigure 3-17
2T—nsFigure 3-18
Figure 3-18
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Duration for Level Sensitive IRQA
the Fetch of First IRQA
Interrupt Instruction (exiting
Assertion to Cause
t
—
—
IRQ
275,000T
12T
ns
ns
Figure 3-19
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Delay from Level Sensitive IRQA
Assertion to First
—
—
t
II
275,000T
12T
ns
ns
Figure 3-19
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
—
—
275,000T
12T
ns
ns
56F826 Technical Data, Rev. 14
34 Freescale Semiconductor
Page 35
RESET
t
RAZ
Reset, Stop, Wait, Mode Select, and Interrupt Timing
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
ParameterSymbolMinTypMaxUnits
STCK frequencyfs
STCK period
3
STCK high timet
STCK low timet
t
SCKW
SCKH
SCKL
100——ns
50
50
Output clock rise/fall time (STCK, SRCK)—
Delay from STCK high to STFS (bl) high - Master
Delay from STCK high to STFS (wl) high - Master
Delay from SRCK high to SRFS (bl) high - Master
Delay from SRCK high to SRFS (wl) high - Master
Delay from STCK high to STFS (bl) low - Master
Delay from STCK high to STFS (wl) low - Master
Delay from SRCK high to SRFS (bl) low - Master
Delay from SRCK high to SRFS (wl) low - Master
5
5
5
5
5
5
5
5
t
TFSBHM
t
TFSWHM
t
RFSBHM
t
RFSWHM
t
TFSBLM
t
TFSWLM
t
RFSBLM
t
RFSWLM
0.1—0.5ns
0.1—0.5ns
0.6—1.3ns
0.6—1.3ns
-1.0—-0.1ns
-1.0—-0.1ns
-0.1—0ns
-0.1—0ns
2
10
4
——ns
4
——ns
4
—ns
MHz
STCK high to STXD enable from high impedance - Mastert
STCK high to STXD valid - Mastert
STCK high to STXD not valid - Mastert
STCK high to STXD high impedance - Mastert
SRXD Setup time before SRCK low - Mastert
SRXD Hold time after SRCK low - Mastert
TXEM
TXVM
TXNVM
TXHIM
SM
HM
20—22ns
24—26ns
0.1—0.2ns
24—25.5ns
4—— ns
4—— ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Mastert
SRXD Hold time after STCK low - Mastert
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
TSM
THM
4——
4——
56F826 Technical Data, Rev. 14
40 Freescale Semiconductor
Page 41
Synchronous Serial Interface (SSI) Timing
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
ParameterSymbolMinTypMaxUnits
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slavet
SRXD Hold time after STCK low - Slavet
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
TSS
THS
4——
4——
56F826 Technical Data, Rev. 14
Freescale Semiconductor43
Page 44
t
SCKW
STCK input
STFS (bl) input
STFS (wl) input
STXD
SRCK input
SRFS (bl) input
SRFS (wl) input
t
SCKH
t
FTXES
t
TXES
t
TFSBHS
t
TFSWHS
t
TXVS
t
RFSBHS
t
RFSWHS
t
SCKL
t
TFSBLS
t
FTXVS
t
TXNVS
First BitLast Bit
t
RFBLS
t
TFSWLS
t
TXHIS
t
RFSWLS
t
SS
SRXD
Figure 3-25 Slave Mode Clock Timing
3.11 Quad Timer Timing
Table 3-15 Timer Timing
Operating Conditions: V
Timer input periodP
Timer input high/low periodP
Timer output periodP
Timer output high/low periodP
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
SSIO
= VSS = V
SSA
= 0V, V
CharacteristicSymbolMinMaxUnit
DDA
t
t
HS
TSS
t
THS
1, 2
= V
= 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
DDIO
IN
INHL
OUT
OUTHL
4T+6—ns
2T+3—ns
2T—ns
1T—ns
56F826 Technical Data, Rev. 14
44 Freescale Semiconductor
Page 45
Serial Communication Interface (SCI) Timing
Timer Inputs
P
IN
P
INHL
P
INHL
Timer Outputs
P
OUT
P
OUTHL
P
OUTHL
Figure 3-26 Quad Timer Timing
3.12 Serial Communication Interface (SCI) Timing
Table 3-16 SCI Timing
Operating Conditions: V
SSIO=VSS
CharacteristicSymbolMinMaxUnit
Baud Rate
RXD
TXD
1. f
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
1
2
Pulse Width
3
Pulse Width
is the frequency of operation of the system clock in MHz.
MAX
RXD
SCI receive
data pin
(Input)
= V
SSA
= 0V, V
DDA =VDDIO
=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
BR—(f
RXD
TXD
PW
PW
RXD
0.965/BR1.04/BRns
0.965/BR1.04/BRns
PW
Figure 3-27 RXD Pulse Width
4
*2.5)/(80)Mbps
MAX
56F826 Technical Data, Rev. 14
Freescale Semiconductor45
Page 46
TXD
SCI receive
data pin
(Input)
3.13 JTAG Timing
TXD
PW
Figure 3-28 TXD Pulse Width
1, 3
Operating Conditions: V
SSIO=VSS
= V
Table 3-17 JTAG Timing
SSA
= 0V, V
DDA =VDDIO
=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
CharacteristicSymbolMinMaxUnit
TCK frequency of operation
2
TCK cycle time t
TCK clock pulse widtht
TMS, TDI data set-up timet
TMS, TDI data hold timet
TCK low to TDO data validt
TCK low to TDO tri-statet
TRST
assertion timet
DE
assertion timet
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
f
OP
CY
PW
DS
DH
DV
TS
TRST
DE
DC10MHz
100—ns
50—ns
0.4—ns
1.2—ns
—26.6ns
—23.5ns
50—ns
4T—ns
t
CY
t
PW
V
M
TCK
(Input)
VM = V
+ (VIH – VIL)/2
IL
t
PW
V
IH
V
M
V
IL
Figure 3-29 Test Clock Input Timing Diagram
56F826 Technical Data, Rev. 14
46 Freescale Semiconductor
Page 47
TCK
(Input)
JTAG Timing
t
DS
t
DH
TDI
TMS
(Input)
TDO
(Output)
TDO
(Output
TDO
(Output)
TRST
(Input)
Input Data Valid
t
DV
Output Data Valid
t
TS
)
t
DV
Output Data Valid
Figure 3-30 Test Access Port Timing Diagram
t
TRST
DE
Figure 3-31 TRST Timing Diagram
t
DE
Figure 3-32 OnCE—Debug Event
56F826 Technical Data, Rev. 14
Freescale Semiconductor47
Page 48
Part 4 Packaging
4.1 Package and Pin-Out Information 56F826
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.
TMS
TDI
TDO
TRST
VDDIO
VSSIO
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
V
SS
VDD
A3
A2
A1
A0
EXTBOOT
TCK
TCSDETXD0
PIN 1
PIN 26
RXD0
VSSVDD
TXD1
RXD1
ORIENTATION
MARK
TA0
TA1
TA2
TA3SSMISO
MOSI
SCLK
SSIO
GPIOD7
GPIOD6
V
VDDIO
GPIOD5
GPIOD4
GPIOD3
GPIOD2
GPIOD1
PIN 76
PIN 51
GPIOD0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
CLKO
DD
V
VSS
XTAL
EXTAL
V
SSA
VDDA
VSSIO
VDDIO
STCK
STFS
STD
SRCK
SRFS
SRD
RD
WR
DS
PS
D0D1D2D3D4D5D6D7D8
IRQA
IRQB
VSSIO
VDDIO
D9
D10
D11
RESET
D12
D13
D14
D15
Figure 4-1 Top View, 56F826 100-pin LQFP Package
56F826 Technical Data, Rev. 14
48 Freescale Semiconductor
Page 49
Package and Pin-Out Information 56F826
Table 4-1 56F826 Pin Identification by Pin Number
Pin No.
1TMS26 RD
2TDI27 WR
3TDO28DS
4TRST
5V
6V
7A1532IRQA57V
8A1433IRQB
9A1334D059V
10A1235D160 V
Signal
Name
DDIO
SSIO
Pin No.Signal NamePin No.Signal NamePin No.
51SRD76GPIOD2
52SRFS77GPIOD3
53SRCK78GPIOD4
29PS54STD79GPIOD5
30V
31V
DDIO
SSIO
55STFS80V
56STCK81V
DDIO
58V
SSIO
DDA
SSA
82GPIOD6
83GPIOD7
84SCLK
85MOSI
Signal
Name
DDIO
SSIO
11A1136D261EXTAL86MISO
12A1037D362 XTAL87SS
13A938D463V
14A839D564V
SS
DD
88TA3
89TA2
15A740D665CLKO90TA1
16A641D766GPIOB091TA0
17A542D867GPIOB192RXD1
18A443D968GPIOB293TXD1
19V
20V
SS
DD
44 D10 69GPIOB394V
45RESET70GPIOB495V
DD
SS
21A346D1171GPIOB596RXD0
22A247D1272GPIOB697TXD0
23A148D1373GPIOB798DE
24A049D1474GPIOD099TCS
25EXTBOOT50D1575GPIOD1100TCK
56F826 Technical Data, Rev. 14
Freescale Semiconductor49
Page 50
V
-AB-
S
T- U
S
S
0.15(0.006)Z
S
AC
-T-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
T-U
S
AC
S
0.15(0.006)Z
-Z-
S
T- U
S
AC
B
S
0.15(0.006)Z
-U-
9
0.15(0.006)Z
AE
A
T- U
S
S
S
AB
AD
-AC-
G
96X
(24X PER SIDE)
AE
°
M
0.100(0.004)
R
AC
SEATING
PLANE
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM MIN M AX MIN MAX
A 13.950 14.050 0.549 0.553
B 13.950 14.050 0.549 0.553
C 1.400 1.600 0.055 0.063
D 0.170 0.270 0.007 0.011
E 1.350 1.450 0.053 0.057
F 0.170 0.230 0.007 0.009
G0.500 BSC0.020 BSC
H 0.050 0.150 0.002 0.006
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system-level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R
do not satisfactorily answer whether
θJA
the thermal performance is adequate, a system-level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
•Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction-to-board thermal resistance.
56F826 Technical Data, Rev. 14
Freescale Semiconductor51
Page 52
•Use the value obtained by the equation (TJ – TT)/PD, where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation:
•Provide a low-impedance path from the board power supply to each V
controller, and from the board ground to each V
SS,VSSIO,
and V
DD, VDDIO,
(GND) pin.
SSA
•The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the
V
DD/VSS
pairs, including V
DDA/VSSA
and V
DDIO/VSSIO.
Ceramic and tantalum capacitors tend to provide
better performance tolerances.
•Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
V
and V
DDA
•Bypass the V
SS, VSSIO,
and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
DD
and V
(GND) pins are less than 0.5 inch per capacitor lead.
SSA
capacitor such as a tantalum capacitor.
and V
pin on the
DDA
DD, VDDIO,
and
56F826 Technical Data, Rev. 14
52 Freescale Semiconductor
Page 53
Electrical Design Considerations
•Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
•Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
•Take special care to minimize noise levels on the VREF, V
•When using Wired-OR mode on the SPI or the IRQx
•Designs that utilize the TRST
debugging systems) should allow a means to assert TRST
to assert TRST
that do not require debugging functionality, such as consumer products, TRST
and VSS circuits.
DD
independently of RESET. TRST must be asserted at power up for proper operation. Designs
DDA
and V
SSA
pins.
pins, the user must provide an external pull-up device.
pin for JTAG port or OnCE module functionality (such as development or
whenever RESET is asserted, as well as a means
should be tied low.
•Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
56F826 Technical Data, Rev. 14
Freescale Semiconductor53
Page 54
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
RoHS-compliant and/or Pb-free versions of Freescale products have the
functionality and electrical characteristics of their non-RoH S-compliant
and/or non-Pb-free counterparts. For further information, see
http://www.freescale.com or contact your Freescale sales representative.
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,
Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.