Freescale 56F801 DATA SHEET
56F801
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F801
Rev. 15
10/2005
freescale.com
56F801 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
6
PWM Outputs
Fault Input
A/D1
4
A/D2
4
3
2
4
ADC
VREF
Quad Timer C
Quad Timer D
or GPIO
SCI0
or
GPIO
SPI
or
GPIO
*includes TCS pin which is reserved for factory use and is tied to VSS
PWMA
Interrupt
Controller
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
COP/
Watchdog
Applica-
tion-Specific
Memory &
Peripherals
RESET
IRQA
Program Controller
and
Hardware Looping Unit
•
•
•
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
PAB
PDB
XDB2
CGDB
XAB1
XAB2
6
JTAG/
OnCE
Port
Address
Generation
Unit
•
•
INTERRUPT
CONTROLS
IPBus Bridge
•8K × 16-bit words (16KB) Program Flash
•1K × 16-bit words (2KB) Program RAM
•2K × 16-bit words (4KB) Data Flash
•1K × 16-bit words (2KB) Data RAM
•2K × 16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCE
TM
port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
VCAPC VDDVSSV
24 5*
Digital Reg
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Low Voltage
Supervisor
16-Bit
56800
Core
DDAVSSA
Analog Reg
Manipulation
Clock Gen
or Optional
Internal
Relaxation Osc.
Bit
Unit
PLL
•
•
•
IPBB
CONTROLS
16 16
(IPBB)
GPIOB3/XTAL
GPIOB2/EXTAL
56F801 Block Diagram
56F801 Technical Data, Rev. 15
Freescale Semiconductor 3
Part 1 Overview
1.1 56F801 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
—8K × 16 bit words of Program Flash
—1K × 16-bit words of Program RAM
—2K × 16-bit words of Data Flash
—1K × 16-bit words of Data RAM
—2K × 16-bit words of Boot Flash
• Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG, SPI)
1.1.3 Peripheral Circuits for 56F801
• Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime
insertion; supports both center- and edge-aligned modes
• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two
4-multiplexed inputs; ADC and PWM modules can be synchronized
• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
56F801 Technical Data, Rev. 15
4 Freescale Semiconductor
56F801 Description
• Eleven multiplexed General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) watchdog timer
• One dedicated external interrupt pin
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for
lower system cost and two additional GPIO lines
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F801 Description
The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine
management, noise suppression, remote utility metering, and industrial control for power, lighting, and
automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F801 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external
dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
56F801 Technical Data, Rev. 15
Freescale Semiconductor 5
A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
insertion, and separate top and bottom output polarity control. The up-counter value is programmable to
support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width
control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:
ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM
(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection
and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard
opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The
PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable
from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital
Converters.
The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard
programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial
Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility
in the choice of either on-chip or externally supplied frequency reference for chip timing operations.
Application code is used to select which source is to be used.
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56F801 Technical Data, Rev. 15
6 Freescale Semiconductor
Product Documentation
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F801. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F801 Chip Documentation
Topic Description Order Number
56800E
Family Manual
DSP56F801/803/805/807
User’s Manual
56F801
Technical Data Sheet
56F801
Errata
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F805, and 56F807
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
Details any chip issues that might be present 56F801E
56800EFM
DSP56F801-7UM
DSP56F801
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State
Voltage
1
PIN True Asserted VIL/V
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F801 Technical Data, Rev. 15
Freescale Semiconductor 7
OL
OH
OH
OL
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power (VDD or V
Ground (VSS or V
Supply Capacitors 2 Table 2-4
PLL and Clock 2 Table 2-5
Interrupt and Program Control 2 Table 2-6
Pulse Width Modulator (PWM) Port 7 Table 2-7
Serial Peripheral Interface (SPI) Port
Serial Communications Interface (SCI) Port
Analog-to-Digital Converter (ADC) Port 9 Table 2-10
Quad Timer Module Port 3 Table 2-11
JTAG/On-Chip Emulation (OnCE) 6 Table 2-12
1. Alternately, GPIO pins
) 5 Table 2-2
DDA
) 6 Table 2-3
SSA
1
1
Number of
Pins
4 Table 2-8
2 Table 2-9
Detailed
Description
56F801 Technical Data, Rev. 15
8 Freescale Semiconductor
Power Port
Ground Port
Power Port
Ground Port
Introduction
V
DD
V
SS
V
DDA
V
SSA
4
5*
1
1
Other
Supply
Port
PLL and Clock
or GPIO
VCAPC
EXTAL (GPIOB2)
XTAL (GPIOB3)
2
1
1
6
1
PWMA0-5
FAULTA0
56F801
1
SCLK (GPIOB4)
1
1
1
1
1
8
1
MOSI (GPIOB5)
MISO (GPIOB6)
SS
(GPIOB7)
TXD0 (GPIOB0)
RXD0 (GPIOB1)
ANA0-7
VREF
SPI Port
or GPIO
SCI0 Port
or GPIO
ADCA Port
Quad
Timer D
or GPIO
Interrupt/
Program
Control
JTAG/OnCE™
Port
TCK
TMS
TDI
TDO
TRST
DE
3
TD0-2 (GPIOA0-2)
1
1
1
1
1
1
1
IRQA
RESET
1
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 2-1 56F801 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
1
56F801 Technical Data, Rev. 15
Freescale Semiconductor 9
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins Signal Name Signal Description
4 V
1 V
DD
DDA
Power—These pins provide power to the internal structures of the chip, and should all be
attached to V
Analog Power—This pin is a dedicated power pin for the analog portion of the chip and
should be connected to a low noise 3.3V supply.
DD.
Table 2-3 Grounds
No. of Pins Signal Name Signal Description
4 VSS GND—These pins provide grounding for the internal structures of the chip, and should all
be attached to V
1 V
1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal use.
SSA
Analog Ground—This pin supplies an analog ground.
In block diagrams, this pin is considered an additional V
SS.
SS.
Table 2-4 Supply Capacitors and VPP
No. of
Pins
2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 µFor greater bypass capacitor in order
Signal
Name
Signal
Type
State
During Reset
Signal Description
to bypass the core logic voltage regulator (required for proper chip
operation). For more information, refer to
Section 5.2.
2.3 Clock and Phase Locked Loop Signals
Table 2-5 PLL and Clock
No. of
Pins
1 EXTAL
10 Freescale Semiconductor
Signal
Name
GPIOB2
Signal
Type
Input
Input/
Output
State
During Reset
Input
Input
Signal Description
External Crystal Oscillator Input—This input should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to
Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the EXTAL pin is not needed.
56F801 Technical Data, Rev. 15
Section 3.5.
Table 2-5 PLL and Clock (Continued)
Interrupt and Program Control Signals
No. of
Pins
1 XTAL
Signal
Name
GPIOB3
Signal
Type
Output
Input/
Output
State
During Reset
Chip-
driven
Input
Signal Description
Crystal Oscillator Output—This output should be connected to an 8MHz
external crystal or ceramic resonator. For more information, please refer to
Section 3.5.
This pin can also be connected to an external clock source. For more
information, please refer to
Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the XTAL pin is not needed.
Section 3.5.3.
2.4 Interrupt and Program Control Signals
Table 2-6 Interrupt and Program Control Signals
No. of
Pins
1 IRQA Input
1 RESET Input
Signal
Name
Signal
Type
(Schmitt)
(Schmitt)
State
During Reset
Input External Interrupt Request A—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered.
Input Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
Signal Description
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
2.5 Pulse Width Modulator (PWM) Signals
Table 2-7 Pulse Width Modulator (PWMA) Signals
No. of
Pins
6 PWMA0-5 Output Tri-stated PWMA0-5— These are six PWMA output pins.
1 FAULTA0 Input
Freescale Semiconductor 11
Signal
Name
Signal
Type
(Schmitt)
State During
Reset
Input FAULTA0— This fault input pin is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
56F801 Technical Data, Rev. 15
Signal Description
2.6 Serial Peripheral Interface (SPI) Signals
Table 2-8 Serial Peripheral Interface (SPI) Signals
No. of
Pins
1 MISO
1 MOSI
1 SCLK
Signal
Name
GPIOB6
GPIOB5
GPIOB4
Signal
Type
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
State During
Reset
Input
Input
Input
Input
Input
Input
Signal Description
SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.
After reset, the default state is MISO.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.
After reset, the default state is MOSI.
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.
1 SS
GPIOB7
Input
Input/Output
After reset, the default state is SCLK.
Input
Input
56F801 Technical Data, Rev. 15
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.
After reset, the default state is SS.
12 Freescale Semiconductor
Serial Communications Interface (SCI) Signals
2.7 Serial Communications Interface (SCI) Signals
Table 2-9 Serial Communications Interface (SCI0) Signals
No. of
Pins
1 TXD0
1 RXD0
Signal
Name
GPIOB0
GPIOB1
Signal
Type
Output
Input/Output
Input
Input/Output
State During
Reset
Input
Input
Input
Input
Signal Description
Transmit Data (TXD0)—SCI0 transmit data output
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.
After reset, the default state is SCI output.
Receive Data (RXD0)—SCI0 receive data input
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.
After reset, the default state is SCI input.
2.8 Analog-to-Digital Converter (ADC) Signals
Table 2-10 Analog to Digital Converter Signals
No. of
Pins
4 ANA0-3 Input Input ANA0-3—Analog inputs to ADC, channel 1
4 ANA4-7 Input Input ANA4-7—Analog inputs to ADC, channel 2
Signal
Name
Signal
Type
State During
Reset
Signal Description
1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to
-0.3V for optimal performance.
V
DDA
2.9 Quad Timer Module Signals
Table 2-11 Quad Timer Module Signals
No. of
Pins
3 TD0-2
Signal
Name
GPIOA0-2
Signal Type
Input/Output
Input/Output
State During
Reset
Input
Input
Signal Description
TD0-2—Timer D Channel 0-2
Port A GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.
After reset, the default state is the quad timer input.
56F801 Technical Data, Rev. 15
Freescale Semiconductor 13
2.10 JTAG/OnCE
Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
1 TCK Input
1 TMS Input
1 TDI Input
1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data
1 TRST Input
1 DE Output Output Debug Event—DE provides a low pulse on recognized debug events.
Signal
Name
Signal
Type
(Schmitt)
(Schmitt)
(Schmitt)
(Schmitt)
State During
Reset
Input, pulled
low internally
Input, pulled
high internally
Input, pulled
high internally
Input, pulled
high internally
Signal Description
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
Test Mode Select Input—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset,
be asserted whenever
debugging environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
but do not assert
RESET is asserted. The only exception occurs in a
TRST.
TRST should
RESET,
Part 3 Specifications
3.1 General Characteristics
The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
56F801 Technical Data, Rev. 15
14 Freescale Semiconductor
General Characteristics
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage V
All other input voltages, excluding Analog inputs V
Voltage difference V
Voltage difference V
DD
SS
to V
to V
DDA
SSA
∆V
∆V
Analog inputs ANA0-7 and VREF V
Analog inputs EXTAL, XTAL V
DD
IN
DD
SS
IN
IN
VSS – 0.3 VSS + 4.0 V
VSS – 0.3 VSS + 5.5V V
- 0.3 0.3 V
- 0.3 0.3 V
V
V
SSA
SSA
– 0.3 V
– 0.3 V
+ 0.3 V
DDA
+ 3.0 V
SSA
Current drain per pin excluding VDD, VSS, & PWM ouputs I — 10 mA
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
Supply voltage, digital V
Supply Voltage, analog V
Voltage difference V
Voltage difference V
ADC reference voltage
DD
SS
to V
to V
1
DDA
SSA
∆V
∆V
VREF 2.7 – 3.3V V
Ambient operating temperature T
1. VREF must be 0.3 below V
DDA
.
DD
DDA
DD
SS
A
3.0 3.3 3.6 V
3.0 3.3 3.6 V
-0.1 - 0.1 V
-0.1 - 0.1 V
–40 – 85 °C
56F801 Technical Data, Rev. 15
Freescale Semiconductor 15
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