Freescale 56855 Service Manual

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56855

Data Sheet

Technical Data

56800E
16-bit Digital Signal Controllers

DSP56855
Rev. 6
01/2007

freescale.com

56855 General Description

• 120 MIPS at 120MHz

• 24K x 16-bit Program SRAM

• 24K x 16-bit Data SRAM

• 1K x 16-bit Boot ROM

• Access up to 2M words of program memory or 8M
words of data memory

• Chip Select Logic for glueless interface to ROM and
SRAM

• Six (6) independent channels of DMA

• Enhanced Synchronous Serial Interface (ESSI)

Program Controller

and

Hardware Looping Unit

PAB
PDB

CDBR

CDBW

Memory

Program Memory

24,576 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

24,576 x 16 SRAM

XDB2

XAB1

XAB2

PAB

PDB

CDBR

CDBW

6

JTAG/

Enhanced

OnCE

Address

Generation Unit

• Two (2) Serial Communication Interfaces (SCI)

• General Purpose 16-bit Quad Timer with 1 external pin

• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging

• Computer Operating Properly (COP)/Watchdog Timer

• Time-of-Day (TOD)

• 100 LQFP package

•Up to 18 GPIO

V

V

DDIO

10

V

V

DD

4

DSP56800E Core

Data ALU

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

System

Bus

Control

SSIO

10

16-Bit

V

SS

DDAVSSA

4

Bit

Manipulation

Unit

DMA

6 channel

Core CLK

IPBus Bridge (IPBB)

DMA Requests

IPAB

A0-20 [20:0]

D0-D15 [15:0]

RD Enable

WR Enable

CS0-CS3[3:0] or

GPIOA0-GPIOA3[3: 0]

Decoding
Peripherals

External Address

Bus Switch

External Data

Bus Switch

Bus Control

External Bus

Interface Unit

2 SCI

or

GPIOE

IPWDB

ESSI0

or

GPIOC

6

4

Quad
Timer

or

GPIOG

IPRDB

Interrupt

Controller

IRQA

IRQB

COP/

Watch -

dog

IPBus CLK

COP/TOD CLK

Time

of

Day

POR

System

Integration

Module

Clock

Generator

OSC PLL

3

CLKO

MODEA-C or
(GPIOH0-H2)

RSTO

RESET

EXTAL

XTAL

56855 Block Diagram

56855 Technical Data, Rev. 6

Freescale Semiconductor 3

Part 1 Overview

1.1 56855 Features

1.1.1 Core

• Efficient 16-bit engine with dual Harvard architecture

• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four (4) 36-bit accumulators including extension bits

• 16-bit bidirectional shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three (3) internal address buses and one (1) external address bus

• Four (4) internal data buses and one (1) external data bus

• Instruction set supports both DSP and controller functions

• Four (4) hardware interrupt levels

• Five (5) software interrupt levels

• Controller-style addressing modes and instructions for compact code

• Efficient C Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory

•On-Chip Memory

—24K × 16-bit Program SRAM

—24K × 16-bit Data SRAM

—1K × 16-bit Boot ROM

• Off-Chip Memory Expansion (EMI)

— Access up to 2M words of program memory or 8M words of data memory

— Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3 Peripheral Circuits for 56855

• General Purpose 16-bit Quad Timer with 1 external pin*

• Two (2) Serial Communication Interfaces (SCI)*

• Enhanced Synchronous Serial Interface (ESSI) module*

• Computer Operating Properly (COP)/Watchdog Timer

• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

56855 Technical Data, Rev. 6

4 Freescale Semiconductor

56855 Description

• Six (6) independent channels of DMA

• Time-of-Day (TOD)

•Up to 18 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

• Wait and Stop modes available

1.2 56855 Description

The 56855 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals, creating an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56855 is well-suited for many applications. The
56855 includes many peripherals that are especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; sonic alarms.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid
development of optimized control applications.

The 56855 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56855 also provides two external
dedicated interrupt lines, and up to 18 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.

The 56855 controller includes 24K words of Program RAM, 24K words of Data RAM and 1K of Boot
ROM. It also supports program execution from external memory.

This controller also provides a full set of standard programmable peripherals that include one Enhanced
Synchronous Serial Interface (ESSI), two Serial Communications Interfaces (SCI), and one Quad Timer.
The ESSI, SCIs, four chip selects and Quad Timer external output can be used as General Purpose
Input/Outputs when its primary function is not required.

56855 Technical Data, Rev. 6

Freescale Semiconductor 5

1.3 State of the Art Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.

• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56855. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56855 Chip Documentation

Topic Description Order Number

56800E
Reference Manual

DSP56855
User’s Manual

56855
Technical Data Sheet

DSP56855
Errata

Detailed description of the 56800E architecture, and
16-bit core processor and the instruction set

Detailed description of memory, peripherals, and
interfaces of the 56855

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

Details any chip issues that might be present DSP56855E

56800ERM

DSP5685xUM

56855

56855 Technical Data, Rev. 6

6 Freescale Semiconductor

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Data Sheet Conventions

Examples: Signal/Symbol Logic State Signal State

PIN True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Voltage

OL

OH

OH

OL

1

56855 Technical Data, Rev. 6

Freescale Semiconductor 7

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56855 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals
present.

Table 2-1 56855 Functional Group Pin Allocations

Functional Group Number of Pins

Power (V

Ground (V

DD, VDDIO, or VDDA

SS, VSSIO,

or V

SSA

)

)

PLL and Clock 3

External Bus Signals 39

External Chip Select* 4

Interrupt and Program Control

Enhanced Synchronous Serial Interface (ESSI0) Port* 6

Serial Communications Interface (SCI0) Ports* 2

Serial Communications Interface (SCI1) Ports* 2

Quad Timer Module Port* 1

JTAG/Enhanced On-Chip Emulation (EOnCE) 6

*Alternately, GPIO pins

1. V

= V

DD

DD CORE, VSS

2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.

= V

SS CORE, VDDIO

= V

DD IO, VSSIO

= V

SS IO, VDDA

= V

DD ANA, VSSA

= V

SS ANA

(4, 10, 1)

(4, 10, 1)

2

7

1

1

56855 Technical Data, Rev. 6

8 Freescale Semiconductor

Introduction

Logic

Power

I/O

Power

Analog

Power

External

Bus

Chip

Select

V

DD

V

SS

4

4

1

1

1

V

V

DDIO

SSIO

10

10

1

1

V

1

V

DDA

SSA

1

1

1

1

1

1

A0 - A20

D0 - D15

RD

WR

CS0 - CS3 (GPIOA0 - A3)

21

16

1

1

4

56855

1

RXDO (GPIOE0)

TXDO (GPIOE1)

RXD1 (GPIOE2)

TXD1 (GPIOE3)

STD0 (GPIOC0)

SRD0 (GPIOC1)

SCK0 (GPIOC2)

SC00 (GPIOC3)

SC01 (GPIOC4)

SC02 (GPIOC5)

SCI 0

SCI 2

ESSI 0

XTAL

EXTAL

CLKO

TCK

TDI

TDO

TMS

TRST

DE

PLL/Clock

JTAG /

Enhanced
OnCE

2

Timer

Module

Interrupt/

Program

Control

1

TIO0 (GPIOG0)

IRQA

IRQB

MODA, MODB, MODC

(GPIOH0 - H2)

RESET

RSTO

1

1

1

3

1

1

1

1

1

1

1

1

1

1

Figure 2-1 56855 Signals Identified by Functional Group

1. Specifically for PLL, OSC, and POR.

2. Alternate pin functions are shown in parentheses.

56855 Technical Data, Rev. 6

Freescale Semiconductor 9

Part 3 Signals and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control.

2. MODE A, MODE B and MODE C pins have no pull-up.

3. TCK has a weak pull-down circuit always active.

4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset.

2. Output(Z) means an output in a High-Z condition.

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP

Pin No. Signal Name Type Description

9V

35 V

65 V

84 V

10 V

36 V

66 V

85 V

DD

DD

DD

DD

SS

SS

SS

SS

V

DD

V

SS

Power (VDD)—These pins provide power to the internal structures of the
chip, and should all be attached to V

Ground (VSS)—These pins provide grounding for the internal structures of
the chip and should all be attached to V

DD.

SS.

56855 Technical Data, Rev. 6

10 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

1V

14 V

29 V

43 V

49 V

58 V

72 V

76 V

86 V

96 V

2V

15 V

30 V

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

SSIO

SSIO

SSIO

V

V

DDIO

SSIO

Power (V

the chip, and should all be attached to V

Ground (V

)—These pins provide power for all I/O and ESD structures of

DDIO

(3.3V).

DDIO

)—These pins provide grounding for all I/O and ESD

SSIO

structures of the chip and should all be attached to V

SS.

44 V

50 V

60 V

73 V

78 V

87 V

97 V

2V

18 V

19 V

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

DDA

SSA

V

V

DDA

SSA

Analog Power (V

Analog Ground (V

)—These pins supply an analog power source.

DDA

)—This pin supplies an analog ground.

SSA

56855 Technical Data, Rev. 6

Freescale Semiconductor 11

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

5 A0 Output(Z) Address Bus (A0-A20)—These signals specify a word address for external

6A1

7A2

8A3

22 A4

23 A5

24 A6

25 A7

31 A8

32 A9

33 A10

34 A11

program or data memory access.

45 A12

46 A13

47 A14

48 A15

53 A16

54 A17

55 A18

56 A19

57 A20

56855 Technical Data, Rev. 6

12 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

59 D0 Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for external

67 D1

68 D2

69 D3

70 D4

71 D5

79 D6

80 D7

81 D8

82 D9

program or data memory accesses.

83 D10

94 D11

95 D12

98 D13

99 D14

3RD

4WR

61 CS0

GPIOA0

62 CS1

GPIOA1

Output Read Enable (RD)— is asserted during external memory read cycles.

This signal is pulled high during reset.

Output Write Enable (WR) — is asserted during external memory write cycles.

This signal is pulled high during reset.

Output

Input/Output

Output

Input/Output

External Chip Select (CS0

Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

External Chip Select (CS1

Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

)—This pin is used as a dedicated GPIO.

)—This pin is used as a dedicated GPIO.

63 CS2

GPIOA2

Freescale Semiconductor 13

Output

Input/Output

External Chip Select (CS2

Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

56855 Technical Data, Rev. 6

)—This pin is used as a dedicated GPIO.

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

64 CS3

GPIOA3

77 TIO0

GPIOG0

16 IRQA

17 IRQB

11 MODA

GPIOH0

12 MODB

Output

Input/Output

Input/Output

Input/Output

Input External Interrupt Request A and B—The IRQA and IRQB inputs are

Input

Input/Output

Input

External Chip Select (CS3

Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

Timer Input/Output (TIO0)—This pin can be independently configured to
be either timer input source or output flag.

Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

asynchronized external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or negative-edge­triggered. If level-sensitive triggering is selected, an external pull-up resistor
is required for Wired-OR operation.

Mode Select (MODA)—During the bootstrap process MODA selects one of
the eight bootstrap modes.

Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

Mode Select (MODB)—During the bootstrap process MODB selects one of
the eight bootstrap modes.

)—This pin is used as a dedicated GPIO.

GPIOH1

13 MODC

GPIOH2

28 RESET

27 RSTO

Input/Output

Input

Input/Output

Input Reset (RESET)—This input is a direct hardware reset on the processor.

Output Reset Output (RSTO)—This output is asserted on any reset condition

Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

Mode Select (MODC)—During the bootstrap process MODC selects one of
the eight bootstrap modes.

Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

When RESET
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET
MODA, MODB, and MODC pins.

To ensure complete hardware reset, RESET
together. The only exception occurs in a debugging environment when a
hardware reset is required and it is necessary not to reset the
JTAG/Enhanced OnCE module. In this case, assert RESET
assert TRST

(external reset, low voltage, software or COP).

is asserted low, the device is initialized and placed in the

pin is deasserted, the initial chip operating mode is latched from the

and TRST should be asserted

, but do not

.

56855 Technical Data, Rev. 6

14 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

51 RXD0

GPIOE0

52 TXD0

GPIOE1

74 RXD1

GPIOE2

75 TXD1

GPIOE3

88 STD0

Input

Input/Output

Output(Z)

Input/Output

Input

Input/Output

Output(Z)

Input/Output

Output

Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial

data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI 0
transmit data register.

Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial
data and transfers it to the SCI 1 receive shift register.

Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI 1
transmit data register.

Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

ESSI Transmit Data (STD0)—This output pin transmits serial data from the
ESSI Transmitter Shift Register.

GPIOC0

89 SRD0

GPIOC1

90 SCK0

GPIOC2

Input/Output

Input

Input/Output

Input/Output

Input/Output

Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Receive Data (SRD0)—This input pin receives serial data and
transfers the data to the ESSI Receive Shift Register.

Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the ESSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver in
synchronous mode.

Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

56855 Technical Data, Rev. 6

Freescale Semiconductor 15

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

91 SC00

GPIOC3

92 SC01

GPIOC4

93 SC02

GPIOC5

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

Input or Output

ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin will be used for the receive clock I/O. For
synchronous mode, this pin is used either for transmitter1 output or for
serial I/O flag 0.

Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.

Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in synchronous
mode and for the transmitter only in asynchronous mode. When configured
as an output, this pin is the internally generated frame sync signal. When
configured as an input, this pin receives an external frame sync signal for
the transmitter (and the receiver in synchronous operation).

Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

20 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal

crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.

21 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be

connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2

26 CLKO Output Clock Output (CLKO)—This pin outputs a buffered clock signal. When

enabled, this signal is the system clock divided by four.

42 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to

synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.

40 TDI Input Test Data Input (TDI)—This input pin provides a serial input data stream to

the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.

39 TDO Output (Z) Test Data Output (TDO)—This tri-statable output pin provides a serial

output data stream from the JTAG/Enhanced OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling edge of
TCK.

56855 Technical Data, Rev. 6

16 Freescale Semiconductor