Freescale 56855 Service Manual

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56855

Data Sheet

Technical Data

56800E
16-bit Digital Signal Controllers

DSP56855
Rev. 6
01/2007

freescale.com

56855 General Description

• 120 MIPS at 120MHz

• 24K x 16-bit Program SRAM

• 24K x 16-bit Data SRAM

• 1K x 16-bit Boot ROM

• Access up to 2M words of program memory or 8M
words of data memory

• Chip Select Logic for glueless interface to ROM and
SRAM

• Six (6) independent channels of DMA

• Enhanced Synchronous Serial Interface (ESSI)

Program Controller

and

Hardware Looping Unit

PAB
PDB

CDBR

CDBW

Memory

Program Memory

24,576 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

24,576 x 16 SRAM

XDB2

XAB1

XAB2

PAB

PDB

CDBR

CDBW

6

JTAG/

Enhanced

OnCE

Address

Generation Unit

• Two (2) Serial Communication Interfaces (SCI)

• General Purpose 16-bit Quad Timer with 1 external pin

• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging

• Computer Operating Properly (COP)/Watchdog Timer

• Time-of-Day (TOD)

• 100 LQFP package

•Up to 18 GPIO

V

V

DDIO

10

V

V

DD

4

DSP56800E Core

Data ALU

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

System

Bus

Control

SSIO

10

16-Bit

V

SS

DDAVSSA

4

Bit

Manipulation

Unit

DMA

6 channel

Core CLK

IPBus Bridge (IPBB)

DMA Requests

IPAB

A0-20 [20:0]

D0-D15 [15:0]

RD Enable

WR Enable

CS0-CS3[3:0] or

GPIOA0-GPIOA3[3: 0]

Decoding
Peripherals

External Address

Bus Switch

External Data

Bus Switch

Bus Control

External Bus

Interface Unit

2 SCI

or

GPIOE

IPWDB

ESSI0

or

GPIOC

6

4

Quad
Timer

or

GPIOG

IPRDB

Interrupt

Controller

IRQA

IRQB

COP/

Watch -

dog

IPBus CLK

COP/TOD CLK

Time

of

Day

POR

System

Integration

Module

Clock

Generator

OSC PLL

3

CLKO

MODEA-C or
(GPIOH0-H2)

RSTO

RESET

EXTAL

XTAL

56855 Block Diagram

56855 Technical Data, Rev. 6

Freescale Semiconductor 3

Part 1 Overview

1.1 56855 Features

1.1.1 Core

• Efficient 16-bit engine with dual Harvard architecture

• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four (4) 36-bit accumulators including extension bits

• 16-bit bidirectional shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three (3) internal address buses and one (1) external address bus

• Four (4) internal data buses and one (1) external data bus

• Instruction set supports both DSP and controller functions

• Four (4) hardware interrupt levels

• Five (5) software interrupt levels

• Controller-style addressing modes and instructions for compact code

• Efficient C Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory

• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory

•On-Chip Memory

—24K × 16-bit Program SRAM

—24K × 16-bit Data SRAM

—1K × 16-bit Boot ROM

• Off-Chip Memory Expansion (EMI)

— Access up to 2M words of program memory or 8M words of data memory

— Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3 Peripheral Circuits for 56855

• General Purpose 16-bit Quad Timer with 1 external pin*

• Two (2) Serial Communication Interfaces (SCI)*

• Enhanced Synchronous Serial Interface (ESSI) module*

• Computer Operating Properly (COP)/Watchdog Timer

• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

56855 Technical Data, Rev. 6

4 Freescale Semiconductor

56855 Description

• Six (6) independent channels of DMA

• Time-of-Day (TOD)

•Up to 18 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

• Wait and Stop modes available

1.2 56855 Description

The 56855 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals, creating an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56855 is well-suited for many applications. The
56855 includes many peripherals that are especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; sonic alarms.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid
development of optimized control applications.

The 56855 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56855 also provides two external
dedicated interrupt lines, and up to 18 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.

The 56855 controller includes 24K words of Program RAM, 24K words of Data RAM and 1K of Boot
ROM. It also supports program execution from external memory.

This controller also provides a full set of standard programmable peripherals that include one Enhanced
Synchronous Serial Interface (ESSI), two Serial Communications Interfaces (SCI), and one Quad Timer.
The ESSI, SCIs, four chip selects and Quad Timer external output can be used as General Purpose
Input/Outputs when its primary function is not required.

56855 Technical Data, Rev. 6

Freescale Semiconductor 5

1.3 State of the Art Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.

• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56855. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56855 Chip Documentation

Topic Description Order Number

56800E
Reference Manual

DSP56855
User’s Manual

56855
Technical Data Sheet

DSP56855
Errata

Detailed description of the 56800E architecture, and
16-bit core processor and the instruction set

Detailed description of memory, peripherals, and
interfaces of the 56855

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

Details any chip issues that might be present DSP56855E

56800ERM

DSP5685xUM

56855

56855 Technical Data, Rev. 6

6 Freescale Semiconductor

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is

active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Data Sheet Conventions

Examples: Signal/Symbol Logic State Signal State

PIN True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Voltage

OL

OH

OH

OL

1

56855 Technical Data, Rev. 6

Freescale Semiconductor 7

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56855 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals
present.

Table 2-1 56855 Functional Group Pin Allocations

Functional Group Number of Pins

Power (V

Ground (V

DD, VDDIO, or VDDA

SS, VSSIO,

or V

SSA

)

)

PLL and Clock 3

External Bus Signals 39

External Chip Select* 4

Interrupt and Program Control

Enhanced Synchronous Serial Interface (ESSI0) Port* 6

Serial Communications Interface (SCI0) Ports* 2

Serial Communications Interface (SCI1) Ports* 2

Quad Timer Module Port* 1

JTAG/Enhanced On-Chip Emulation (EOnCE) 6

*Alternately, GPIO pins

1. V

= V

DD

DD CORE, VSS

2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.

= V

SS CORE, VDDIO

= V

DD IO, VSSIO

= V

SS IO, VDDA

= V

DD ANA, VSSA

= V

SS ANA

(4, 10, 1)

(4, 10, 1)

2

7

1

1

56855 Technical Data, Rev. 6

8 Freescale Semiconductor

Introduction

Logic

Power

I/O

Power

Analog

Power

External

Bus

Chip

Select

V

DD

V

SS

4

4

1

1

1

V

V

DDIO

SSIO

10

10

1

1

V

1

V

DDA

SSA

1

1

1

1

1

1

A0 - A20

D0 - D15

RD

WR

CS0 - CS3 (GPIOA0 - A3)

21

16

1

1

4

56855

1

RXDO (GPIOE0)

TXDO (GPIOE1)

RXD1 (GPIOE2)

TXD1 (GPIOE3)

STD0 (GPIOC0)

SRD0 (GPIOC1)

SCK0 (GPIOC2)

SC00 (GPIOC3)

SC01 (GPIOC4)

SC02 (GPIOC5)

SCI 0

SCI 2

ESSI 0

XTAL

EXTAL

CLKO

TCK

TDI

TDO

TMS

TRST

DE

PLL/Clock

JTAG /

Enhanced
OnCE

2

Timer

Module

Interrupt/

Program

Control

1

TIO0 (GPIOG0)

IRQA

IRQB

MODA, MODB, MODC

(GPIOH0 - H2)

RESET

RSTO

1

1

1

3

1

1

1

1

1

1

1

1

1

1

Figure 2-1 56855 Signals Identified by Functional Group

1. Specifically for PLL, OSC, and POR.

2. Alternate pin functions are shown in parentheses.

56855 Technical Data, Rev. 6

Freescale Semiconductor 9

Part 3 Signals and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control.

2. MODE A, MODE B and MODE C pins have no pull-up.

3. TCK has a weak pull-down circuit always active.

4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset.

2. Output(Z) means an output in a High-Z condition.

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP

Pin No. Signal Name Type Description

9V

35 V

65 V

84 V

10 V

36 V

66 V

85 V

DD

DD

DD

DD

SS

SS

SS

SS

V

DD

V

SS

Power (VDD)—These pins provide power to the internal structures of the
chip, and should all be attached to V

Ground (VSS)—These pins provide grounding for the internal structures of
the chip and should all be attached to V

DD.

SS.

56855 Technical Data, Rev. 6

10 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

1V

14 V

29 V

43 V

49 V

58 V

72 V

76 V

86 V

96 V

2V

15 V

30 V

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

DDIO

SSIO

SSIO

SSIO

V

V

DDIO

SSIO

Power (V

the chip, and should all be attached to V

Ground (V

)—These pins provide power for all I/O and ESD structures of

DDIO

(3.3V).

DDIO

)—These pins provide grounding for all I/O and ESD

SSIO

structures of the chip and should all be attached to V

SS.

44 V

50 V

60 V

73 V

78 V

87 V

97 V

2V

18 V

19 V

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

SSIO

DDA

SSA

V

V

DDA

SSA

Analog Power (V

Analog Ground (V

)—These pins supply an analog power source.

DDA

)—This pin supplies an analog ground.

SSA

56855 Technical Data, Rev. 6

Freescale Semiconductor 11

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

5 A0 Output(Z) Address Bus (A0-A20)—These signals specify a word address for external

6A1

7A2

8A3

22 A4

23 A5

24 A6

25 A7

31 A8

32 A9

33 A10

34 A11

program or data memory access.

45 A12

46 A13

47 A14

48 A15

53 A16

54 A17

55 A18

56 A19

57 A20

56855 Technical Data, Rev. 6

12 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

59 D0 Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for external

67 D1

68 D2

69 D3

70 D4

71 D5

79 D6

80 D7

81 D8

82 D9

program or data memory accesses.

83 D10

94 D11

95 D12

98 D13

99 D14

3RD

4WR

61 CS0

GPIOA0

62 CS1

GPIOA1

Output Read Enable (RD)— is asserted during external memory read cycles.

This signal is pulled high during reset.

Output Write Enable (WR) — is asserted during external memory write cycles.

This signal is pulled high during reset.

Output

Input/Output

Output

Input/Output

External Chip Select (CS0

Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

External Chip Select (CS1

Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

)—This pin is used as a dedicated GPIO.

)—This pin is used as a dedicated GPIO.

63 CS2

GPIOA2

Freescale Semiconductor 13

Output

Input/Output

External Chip Select (CS2

Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

56855 Technical Data, Rev. 6

)—This pin is used as a dedicated GPIO.

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

64 CS3

GPIOA3

77 TIO0

GPIOG0

16 IRQA

17 IRQB

11 MODA

GPIOH0

12 MODB

Output

Input/Output

Input/Output

Input/Output

Input External Interrupt Request A and B—The IRQA and IRQB inputs are

Input

Input/Output

Input

External Chip Select (CS3

Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not

configured for host port usage.

Timer Input/Output (TIO0)—This pin can be independently configured to
be either timer input source or output flag.

Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

asynchronized external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or negative-edge­triggered. If level-sensitive triggering is selected, an external pull-up resistor
is required for Wired-OR operation.

Mode Select (MODA)—During the bootstrap process MODA selects one of
the eight bootstrap modes.

Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

Mode Select (MODB)—During the bootstrap process MODB selects one of
the eight bootstrap modes.

)—This pin is used as a dedicated GPIO.

GPIOH1

13 MODC

GPIOH2

28 RESET

27 RSTO

Input/Output

Input

Input/Output

Input Reset (RESET)—This input is a direct hardware reset on the processor.

Output Reset Output (RSTO)—This output is asserted on any reset condition

Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

Mode Select (MODC)—During the bootstrap process MODC selects one of
the eight bootstrap modes.

Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.

When RESET
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET
MODA, MODB, and MODC pins.

To ensure complete hardware reset, RESET
together. The only exception occurs in a debugging environment when a
hardware reset is required and it is necessary not to reset the
JTAG/Enhanced OnCE module. In this case, assert RESET
assert TRST

(external reset, low voltage, software or COP).

is asserted low, the device is initialized and placed in the

pin is deasserted, the initial chip operating mode is latched from the

and TRST should be asserted

, but do not

.

56855 Technical Data, Rev. 6

14 Freescale Semiconductor

Introduction

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

51 RXD0

GPIOE0

52 TXD0

GPIOE1

74 RXD1

GPIOE2

75 TXD1

GPIOE3

88 STD0

Input

Input/Output

Output(Z)

Input/Output

Input

Input/Output

Output(Z)

Input/Output

Output

Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial

data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI 0
transmit data register.

Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial
data and transfers it to the SCI 1 receive shift register.

Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI 1
transmit data register.

Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.

ESSI Transmit Data (STD0)—This output pin transmits serial data from the
ESSI Transmitter Shift Register.

GPIOC0

89 SRD0

GPIOC1

90 SCK0

GPIOC2

Input/Output

Input

Input/Output

Input/Output

Input/Output

Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Receive Data (SRD0)—This input pin receives serial data and
transfers the data to the ESSI Receive Shift Register.

Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the ESSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver in
synchronous mode.

Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

56855 Technical Data, Rev. 6

Freescale Semiconductor 15

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

91 SC00

GPIOC3

92 SC01

GPIOC4

93 SC02

GPIOC5

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

Input or Output

ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin will be used for the receive clock I/O. For
synchronous mode, this pin is used either for transmitter1 output or for
serial I/O flag 0.

Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.

Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in synchronous
mode and for the transmitter only in asynchronous mode. When configured
as an output, this pin is the internally generated frame sync signal. When
configured as an input, this pin receives an external frame sync signal for
the transmitter (and the receiver in synchronous operation).

Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.

20 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal

crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.

21 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be

connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2

26 CLKO Output Clock Output (CLKO)—This pin outputs a buffered clock signal. When

enabled, this signal is the system clock divided by four.

42 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to

synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.

40 TDI Input Test Data Input (TDI)—This input pin provides a serial input data stream to

the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.

39 TDO Output (Z) Test Data Output (TDO)—This tri-statable output pin provides a serial

output data stream from the JTAG/Enhanced OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling edge of
TCK.

56855 Technical Data, Rev. 6

16 Freescale Semiconductor

General Characteristics

Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)

Pin No. Signal Name Type Description

41 TMS Input Test Mode Select Input (TMS)—This input pin is used to sequence the

JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.

38 TRST

37 DE

Input Test Reset (TRST)—As an input, a low signal on this pin provides a reset

Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low signal.

Part 4 Specifications

Note: Always tie the TMS pin to V

signal to the JTAG TAP controller. To ensure complete hardware reset,

should be asserted whenever RESET is asserted. The only

TRST
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it is
not necessary to assert TRST
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module on
the device.

Note: For normal operation, connect TRST

used in a debugging environment, TRST

As an input, it is a means of entering debug mode of operation from an
external command controller. As an output, it is a means of acknowledging
that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.

through a 2.2K resistor.

DD

when asserting RESET. Outside of a

directly to VSS. If the design is to be

may be tied to VSS through a 1K resistor.

4.1 General Characteristics

The 56855 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of

3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56855 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized

56855 Technical Data, Rev. 6

Freescale Semiconductor 17

specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

Table 4-1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage, core

Supply voltage, IO
Supply voltage, analog

Digital input voltages
Analog input voltages (XTAL, EXTAL)

Current drain per pin excluding V

, GND I — 8 mA

DD

Junction temperature T

Storage temperature range T

1. VDD must not exceed V

2. V

DDIO

and V

DDA

DDIO

must not differ by more that 0.5V

V

V

V

DD

DDIO

DDIO

V

IN

V

INA

J

STG

Table 4-2 Recommended Operating Conditions

Characteristic Symbol Min Max Unit

Supply voltage for Logic Power V

1

2

2

VSS – 0.3 V

V

– 0.3

SSIO

– 0.3

V

SSA

V

– 0.3

SSIO

– 0.3

V

SSA

+ 2.0 V

SS

V

+ 4.0

SSIO

+ 4.0

V

DDA

V

+ 5.5

SSIO

+ 0.3

V

DDA

V

V

-40 120 °C

-55 150 °C

DD

1.62 1.98 V

Supply voltage for I/O Power V

Supply voltage for Analog Power V

DDIO

DDA

3.0 3.6 V

3.0 3.6 V

56855 Technical Data, Rev. 6

18 Freescale Semiconductor

General Characteristics

Table 4-2 Recommended Operating Conditions

Characteristic Symbol Min Max Unit

Ambient operating temperature T

PLL clock frequency

Operating Frequency

1

2

Frequency of peripheral bus f

Frequency of external clock f

Frequency of oscillator f

Frequency of clock via XTAL f

Frequency of clock via EXTAL f

1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.

2. Master clock is derived from on of the following four sources:

f

= f

clk

f

clk

f

clk

f

clk

when the source clock is the direct clock to EXTAL

xtal

= f

when PLL is selected

pll

= f

when the source clock is the crystal oscillator and PLL is not selected

osc

= f

when the source clock is the direct clock to EXTAL and PLL is not selected

extal

A

f

pll

f

op

ipb

clk

osc

xtal

extal

-40 85 °C

—240MHz

—120MHz

—60MHz

—240MHz

24MHz

—240MHz

24MHz

Table 4-3 Thermal Characteristics

Characteristic

Symbol Value Unit

Thermal resistance junction-to-ambient
(estimated)

I/O pin power dissipation P

Power dissipation P

Maximum allowed P

1. See Section 6.1 for more detail.

2. TJ = Junction Temperature
TA = Ambient Temperature

D

P

DMAX

1

100-pin LQFP

θ

JA

I/O

D

PD = (IDD × VDD) + P

41.2 °C/W

User Determined W

I/O

(TJ – TA) / Rθ

JA

2

°C

W

56855 Technical Data, Rev. 6

Freescale Semiconductor 19

4.2 DC Electrical Characteristics

Table 4-4 DC Electrical Characteristics

Operating Conditions: VSS = V

Characteristic Symbol Min Typ Max Unit

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

Input high voltage (XTAL/EXTAL) V

Input low voltage (XTAL/EXTAL) V

Input high voltage V

Input low voltage V

Input current low (pullups disabled) I

Input current high (pullups disabled) I

Output tri-state current low I

Output tri-state current high I

Output High Voltage V

Output Low Voltage V

Output High Current I

Output Low Current I

Input capacitance C

Output capacitance C

supply current (Core logic, memories, peripherals)

V

DD

V

DDIO

V

DDA

Low Voltage Interrupt

1

Run

Deep Stop

Light Stop

2

3

supply current (I/O circuity)

5

Run

Deep Stop

2

supply current (analog circuity)

Deep Stop

2

6

Low Voltage Interrupt Recovery Hysteresis V

Power on Reset

Note:

no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.

Run (operating) IDD measured using external square wave clock source (f

7

IHC

ILC

IH

IL

IL

IH

OZL

OZH

OH

OL

OH

OL

IN

OUT

4

I

DD

I

DDIO

I

DDA

V

EI

EIH

POR — 1.5 2.0 V

V

– 0.8 V

DDA

DDA

V

DDA

+ 0.3 V

-0.3 — 0.5 V

2.0 — 5.5 V

-0.3 — 0.8 V

-1 — 1 μA

-1 — 1 μA

-10 — 10 μA

-10 — 10 μA

V

– 0.7 — — V

DDIO

——0.4V

8—16mA

8—16mA

—8—pF

—12—pF

—
—
—

70

0.05
5

110

10
14

—40050

1.5

—60120μA

— 2.5 2.85 V

—50—mV

= 4MHz) into XTAL. All inputs 0.2V from rail;

osc

mA
mA
mA

mA
mA

1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.

2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.

3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.

4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.

56855 Technical Data, Rev. 6

20 Freescale Semiconductor

Supply Voltage Sequencing and Separation Cautions

5. Running core and performing external memory access. Clock at 120 MHz.

6. When V

7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically
100 mV less than V

drops below VEI max value, an interrupt is generated.

DD

during ramp up until 2.5V is reached, at which time it self-regulates.

DD

150

EMI Mode

5

MAC Mode

1

120

90

60

IDD (mA)

30

0

Figure 4-1 Maximum Run I

20 40

DDTOTAL

60

80

100

vs. Frequency (see Notes 1. and 5. in Table 4-4)

4.3 Supply Voltage Sequencing and Separation Cautions

120

Figure 4-2 shows two situations to avoid in sequencing the VDD and V

56855 Technical Data, Rev. 6

Freescale Semiconductor 21

DDIO, VDDA

supplies.

3.3V

V

DDIO,VDDA

2

1.8V
1

Supplies Stable

V

DD

DC Power Supply Voltage

0

Notes: 1. VDD rising before V

2. V

DDIO

, V

rising much faster than V

DDA

DDIO

, V

DDA

DD

Time

Figure 4-2 Supply Voltage Sequencing and Separation Cautions

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
supply (1.8V) from the voltage generated by the 3.3V V
rising faster than V

DDIO

.

supply, see Figure 4-3. This keeps VDD from

DDIO

DD

VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between V
approximately 2.1, causing V

to rise as V

DD

ramps up. When the V

DDIO

DD

regulator begins proper

DDIO

and V

DD

reaches

operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V

DDIO

> V

DD

> (V

DDIO

- 2.1V)

In practice, V

22 Freescale Semiconductor

is typically connected directly to V

DDA

56855 Technical Data, Rev. 6

with some filtering.

DDIO

AC Electrical Characteristics

V

DDIO,VDDA

V

DD

Supply

3.3V

Regulator

1.8V

Regulator

Figure 4-3 Example Circuit to Control Supply Sequencing

4.4 AC Electrical Characteristics

Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8 V and a V
for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of
VIH and VIL for an input signal are shown.

Low High

V

IL

Rise Time

Input Signal

Midpoint1

Fall Time

V

IH

minimum of 2.0 V

IH

90%

50%

10%

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 4-4 Input Signal Measurement References

Figure 4-5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.

• Tri-stated, when a bus or signal is placed in a high impedance state.

• Data Valid state, when a signal level has reached V

OL

or V

OH.

• Data Invalid state, when a signal level is in transition between VOL and V

Data1 Valid

Data1

Data Invalid State

Data Active Data Active

Data2 Valid

Data2 Data3

Data

Tri-stated

Figure 4-5 Signal State

OH.

Data3 Valid

56855 Technical Data, Rev. 6

Freescale Semiconductor 23

4.5 External Clock Operation

The 56855 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.

4.5.1 Crystal Oscillator

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 4-5. In Figure 4-6 a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.

Crystal Frequency = 2–4 MHz (optimized for 4MHz)

EXTAL XTAL

R

z

Sample External Crystal Parameters:
Rz = 10MΩ
TOD_SEL bit in CGM must be set to 0

Figure 4-6 Crystal Oscillator

4.5.2 High Speed External Clock Source (> 4MHz)

The recommended method of connecting an external clock is given in Figure 4-7. The external clock
source is connected to XTAL and the EXTAL pin is held at ground, V
bit in CGM must be set to 0.

56855

XTAL

External

Clock

(up to 240MHz)

EXTAL

GND,

or V

V

DDA

DDA

,

/2

DDA

, or V

/2. The TOD_SEL

DDA

Figure 4-7 Connecting a High Speed External Clock Signal using XTAL

56855 Technical Data, Rev. 6

24 Freescale Semiconductor

External Clock Operation

4.5.3 Low Speed External Clock Source (2-4MHz)

The recommended method of connecting an external clock is given in Figure 4-8. The external clock
source is connected to XTAL and the EXTAL pin is held at V
set to 0.

56855

XTAL

EXTAL

/2. The TOD_SEL bit in CGM must be

DDA

External

Clock

V

DDA

/2

(2-4MHz)

Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL

Table 4-5 External Clock Operation Timing Requirements

Operating Conditions: VSS = V

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)

Clock Pulse Width

External clock input rise time

External clock input fall time

1. See Figure 4-7 for details on using the recommended connection of an external clock driver.

2. External clock input rise time is measured from 10% to 90%.

3. External clock input fall time is measured from 90% to 10%.

4. Parameters listed are guaranteed by design.

4

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

2, 4

3, 4

= V

DDIO

1

f

t

t

osc

PW

rise

t

fall

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

0 — 240 MHz

6.25 — — ns

——TBDns

——TBDns

4

V

IH

External

Clock

90%

50%

10%

t

PW

t

PW

t

fall

t

rise

90%

50%

10%

V

IL

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 4-9 External Clock Timing

56855 Technical Data, Rev. 6

Freescale Semiconductor 25

Operating Conditions: VSS = V

Characteristic Symbol Min Typ Max Unit

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

Table 4-6 PLL Timing

= V

DDIO

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

External reference crystal frequency for the PLL

PLL output frequency f

PLL stabilization time

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.

2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

2

1

f

t

osc

clk

plls

244MHz

40 — 240 MHz

—110ms

4.6 External Memory Interface Timing

The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10
shows sample timing and parameters that are detailed in Table 4-7.

The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:

t = D + P * (M + W)

should be used to determine the actual time of each parameter. The terms in the above equation are defined as:

t parameter delay time

D fixed portion of the delay, due to on-chip path delays.

P the period of the system clock, which determines the execution rate of the part (i.e. when the device is

operating at 120 MHz, P = 8.33 ns).

M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible

clock duty cycle derating.

W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-7 for

the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.

Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be
used to make the appropriate selection.

56855 Technical Data, Rev. 6

26 Freescale Semiconductor

A0-Axx,CS

External Memory Interface Timing

RD

WR

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Operating Conditions: VSS = V

t

RD

t

t

AD

ARDD

t

RDD

t

t

WRWR

AWR

t

DWR

t

DOS

t

WR

t

WAC

t

DOH

t

WRRD

t

ARDA

Data Out Data In

Figure 4-10 External Memory Interface Timing

Table 4-7 External Memory Interface Timing

= V

SSIO

= 0 V, VDD = 1.62-1.98 V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns

DDA

t

DRD

t

RDA

t

RDRD

t

RDWR

Characteristic Symbol

Address Valid to WR Asserted

Width Asserted to WR

WR
Deasserted

Data Out Valid to WR

Valid Data Out Hold Time after WR
Deasserted

Valid Data Out Set Up Time to WR
Deasserted

Valid Address after WR
Deasserted

RD Deasserted to Address Invalid

Asserted

t

AWR

t

WR

Wait States

Configuration

DM

WWS=0 -0.79 0.50

WWS>0 -1.98 0.69

WWS=0 -0.86 0.19

WWS>0 -0.01 0.00

Wait States

Controls

WWSS

WWS

Unit

ns

ns

WWS=0 -1.52 0.00

t

DWR

WWS=0 - 5.69 0.25

WWS>0 -2.10 0.19

WWSS

ns

WWS>0 -4.66 0.50

t

DOH

t

DOS

t

WAC

t

RDA

-1.47 0.25 WWSH

-2.36 0.19

-4.67 0.50

WWS,WWSS

-1.60 0.25 WWSH

- 0.44 0.00 RWSH

ns

ns

ns

56855 Technical Data, Rev. 6

Freescale Semiconductor 27

Operating Conditions: VSS = V

Table 4-7 External Memory Interface Timing (Continued)

= V

SSIO

= 0 V, VDD = 1.62-1.98 V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns

DDA

Characteristic Symbol

t

Address Valid to RD Deasserted

Valid Input Data Hold after RD
Deasserted

RD Assertion Width

Address Valid to Input Data Valid

Address Valid to RD

RD

Asserted to Input Data Valid

Deasserted to RD Asserted

WR

Deasserted to RD Asserted

RD

Deasserted to WR Asserted

WR

Deasserted to WR Asserted

RD

1. N/A since device captures data before it deasserts RD

2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.

Asserted

ARDD

t

DRD

t

RD

t

AD

t

ARDA

t

RDD

t

WRRD

t

RDRD

t

WRWR

t

RDWR

Wait States

Configuration

DM

-2.07 1.00 RWSS,RWS

0.00

-1.34 1.00 RWS

-10.27 1.00

-13.5 1.19

- 0.94 0.00 RWSS ns

-9.53 1.00

-12.64 1.19

-0.75 0.25

2

-0.16

WWS=0 -0.44 0.75

WWS>0 -0.11 1.00

0.14 0.50

-0.57 0.69

N/A

0.00

1

Wait States

Controls

Unit

—

RWSS,RWS

RWSS,RWS

WWSH,RWSS

RWSS,RWSH

WWSS, WWSH ns

MDAR, BMDAR,

RWSH, WWSS

ns

ns

ns

ns

ns

ns

ns

ns

4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: VSS = V

Characteristic Symbol Min Max Unit See Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

Minimum RESET

Deassertion to First External Address Output t

RESET

Edge-sensitive Interrupt Request Width t

Assertion Duration3

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

56855 Technical Data, Rev. 6

t

RAZ

t

RA

RDA

IRW

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

—11ns4-11

30 — ns 4-11

— 120T ns 4-11

1T + 3 — ns 4-12

1, 2

28 Freescale Semiconductor

Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: VSS = V

Characteristic Symbol Min Max Unit See Figure

, IRQB Assertion to External Data Memory

IRQA
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

Delay from IRQA Assertion (exiting Stop) to External

Data Memory

Delay from IRQA
Data Memory

Fast

Normal

5

Assertion (exiting Wait) to External

6

7

4

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

= V

DDIO

t

IDM

t

IDM -FAST

t

IG

t

IG -FAST

t

IRI

t

IRI -FAST

t

IW

t

IF

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

18T — ns 4-13

14T —

18T — ns 4-13

14T —

22T — ns 4-14

18T —

1.5T — ns

18T

22ET

1, 2 (Continued)

—
—

4-15

4-15

ns
ns

RSTO

pulse width

8

normal operation
internal reset mode

1. In the formulas, T = clock cycle. For fop = 120MHz operation and f

2. Parameters listed are guaranteed by design.

3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
t

, t

or t

xtal

extal

4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.

5. The interrupt instruction fetch is visible on the pins only in Mode 3.

6. Fast stop mode:

Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is re­quested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one
less cycle and t

7. Normal stop mode:

As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and t

8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.

.

osc

will continue same value it had before stop mode was entered.

clk

t

RSTO

128ET

8ET

= 60MHz, T = 8.33ns.

ipb

assumes the period of the source clock,

clk

will resume at the input clock source rate.

clk

—
—

—
—

4-16

56855 Technical Data, Rev. 6

Freescale Semiconductor 29

RESET

t

RAZ

t

RA

t

RDA

A0–A20,

D0–D15

CS,

RD, WR

IRQA

IRQB

A0–A20,

CS

RD, WR

IRQA,

IRQB

First Fetch

First Fetch

Figure 4-11 Asynchronous Reset Timing

t

IRW

Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive)

,

t

IDM

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA

,

t

IG

IRQB

b) General Purpose I/O

Figure 4-13 External Level-Sensitive Interrupt Timing

56855 Technical Data, Rev. 6

30 Freescale Semiconductor

IRQA,

IRQB

Host Interface Port

t

IRI

A0–A20,

CS,

RD

, WR

First Interrupt Vector
Instruction Fetch

Figure 4-14 Interrupt from Wait State Timing

t

IW

IRQA

t

IF

A0–A20,

CS

RD

, WR

,

First Instruction Fetch

Not IRQA Interrupt Vector

Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing

RESET

t

RSTO

Figure 4-16 Reset Output Timing

4.8 Host Interface Port

Table 4-8 Host Interface Port Timing1

Operating Conditions: VSS = V

Characteristic Symbol Min Max Unit See Figure

Access time

Disable time

Time to disassert

Lead time

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

= V

DDIO

TACKDV

TACKDZ

TACKREQH

TREQACKL

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

—13ns4-17

3—ns4-17

3.5 9 ns

0—ns

56855 Technical Data, Rev. 6

4-17
4-20

4-17
4-20

Freescale Semiconductor 31

Table 4-8 Host Interface Port Timing1 (Continued)

Operating Conditions: VSS = V

Characteristic Symbol Min Max Unit See Figure

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

Access time

Disable time

Disable time

Setup time

Hold time

Setup time

Hold time

Pulse width

TRADV

TRADX

TRADZ

TDACKS

TACKDH

TADSS

TDSAH

TWDS

Time to re-assert

1. After second write in 16-bit mode

TACKREQL

2. After first write in 16-bit mode
or after write in 8-bit mode

1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.

—13

5—

3—

ns 4-18

ns 4-18

ns 4-18

3—ns4-20

1—ns4-20

3—ns

1—ns

5—ns

4T + 5

5

5T + 9

13

ns
ns

4-19

4-19

4-19

4-21
4-23

4-21
4-22

4-21
4-22

4-17
4-20

HACK

HD

HREQ

TACKDZ

TACKREQL

TREQACKL

TACKDV

TACKREQH

Figure 4-17 Controller-to-Host DMA Read Mode

56855 Technical Data, Rev. 6

32 Freescale Semiconductor

HA

HCS

HDS

HRW

HD

Host Interface Port

TRADX

TRADV

TRADZ

Figure 4-18 Single Strobe Read Mode

HA

HCS

HWR

HRD

HD

TRADX

TRADZ

TRADV

Figure 4-19 Dual Strobe Read Mode

56855 Technical Data, Rev. 6

Freescale Semiconductor 33

HACK

HD

HREQ

HA

HCS

HDS

HRW

TACKDH

TACKREQL

TREQACKL

TDACKS

TACKREQH

Figure 4-20 Host-to-Controller DMA Write Mode

TDSAH

TWDS

TDSAH

TADSS

TADSS

TDSAH

HD

HA

HCS

HWR

HRD

HD

Figure 4-21 Single Strobe Write Mode

TWDS

TADSS

TADSS

TDSAH

Figure 4-22 Dual Strobe Write Mode

56855 Technical Data, Rev. 6

34 Freescale Semiconductor

4.9 Quad Timer Timing

Quad Timer Timing

1, 2

Operating Conditions: VSS = V

SSIO

Table 4-9 Quad Timer Timing

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

Characteristic Symbol Min Max Unit

Timer input period P

Timer input high/low period P

Timer output period P

Timer output high/low period P

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.

2. Parameters listed are guaranteed by design.

IN

INHL

OUT

OUTHL

2T + 3 — ns

1T + 3 — ns

2T - 3 — ns

1T - 3 — ns

Timer Inputs

P

IN

P

INHL

P

INHL

Timer Outputs

P

OUT

Figure 4-23 Timer Timing

P

OUTHL

P

OUTHL

56855 Technical Data, Rev. 6

Freescale Semiconductor 35

4.10 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-10 ESSI Master Mode1 Switching Characteristics

Operating Conditions: VSS = V

= V

SSIO

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

Parameter Symbol Min Typ Max Units

SCK frequency fs — —

SCK period

3

SCK high time t

SCK low time t

t

SCKW

SCKH

SCKL

66.7 — — ns

4

33.4

33.4

—— ns

4

—— ns

15

2

MHz

Output clock rise/fall time — — 4 — ns

Delay from SCK high to SC2 (bl) high - Master

Delay from SCK high to SC2 (wl) high - Master

Delay from SC0 high to SC1 (bl) high - Master

Delay from SC0 high to SC1 (wl) high - Master

Delay from SCK high to SC2 (bl) low - Master

Delay from SCK high to SC2 (wl) low - Master

Delay from SC0 high to SC1 (bl) low - Master

Delay from SC0 high to SC1 (wl) low - Master

5

5

5

5

5

5

5

5

SCK high to STD enable from high impedance - Master t

t

TFSBHM

t

TFSWHM

t

RFSBHM

t

RFSWHM

t

TFSBLM

t

TFSWLM

t

RFSBLM

t

RFSWLM

TXEM

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-1.0 — 1.0 ns

-0.1 — 2 ns

SCK high to STD valid - Master t

SCK high to STD not valid - Master t

SCK high to STD high impedance - Master t

SRD Setup time before SC0 low - Master t

SRD Hold time after SC0 low - Master t

TXVM

TXNVM

TXHIM

SM

HM

-0.1 — 2 ns

-0.1 — — ns

-4 — 0 ns

4——ns

4——ns

Synchronous Operation (in addition to standard internal clock parameters)

SRD Setup time before SCK low - Master t

SRD Hold time after SCK low - Master t

1. Master mode is internally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.

TSM

THM

4——ns

4——ns

56855 Technical Data, Rev. 6

36 Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI) Timing

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables
and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

t

SCKW

t

SCKH

t

SCKL

SCK output

SC2 (bl) output

SC2 (wl) output

STD

SC0 output

SC1 (bl) output

SC1 (wl) output

SRD

t

TXVM

t

TFSBHM

t

TFSWHM

t

TXEM

t

RFSBHM

t

RFSWHM

t

SM

t

TFSBLM

t

TXNVM

First Bit Last Bit

t

RFBLM

t

t

TSM

HM

t

THM

t

TFSWLM

t

TXHIM

t

RFSWLM

Figure 4-24 Master Mode Timing Diagram

56855 Technical Data, Rev. 6

Freescale Semiconductor 37

Table 4-11 ESSI Slave Mode1 Switching Characteristics

Operating Conditions: VSS = V

= V

SSIO

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

Parameter Symbol Min Typ Max Units

SCK frequency fs — —

SCK period

3

SCK high time t

SCK low time t

t

SCKW

SCKH

SCKL

66.7 — — ns

4

33.4

33.4

—— ns

4

—— ns

15

2

MHz

Output clock rise/fall time — — 4 — ns

Delay from SCK high to SC2 (bl) high - Slave

Delay from SCK high to SC2 (wl) high - Slave

Delay from SC0 high to SC1 (bl) high - Slave

Delay from SC0 high to SC1 (wl) high - Slave

Delay from SCK high to SC2 (bl) low - Slave

Delay from SCK high to SC2 (wl) low - Slave

Delay from SC0 high to SC1 (bl) low - Slave

Delay from SC0 high to SC1 (wl) low - Slave

5

5

5

5

5

5

5

5

SCK high to STD enable from high impedance - Slave t

t

TFSBHS

t

TFSWHS

t

RFSBHS

t

RFSWHS

t

TFSBLS

t

TFSWLS

t

RFSBLS

t

RFSWLS

TXES

-1 — 29 ns

-1 — 29 ns

-1 — 29 ns

-1 — 29 ns

-29 — 29 ns

-29 — 29 ns

-29 — 29 ns

-29 — 29 ns

——15 ns

SCK high to STD valid - Slave t

SC2 high to STD enable from high impedance (first bit) - Slave t

SC2 high to STD valid (first bit) - Slave t

SCK high to STD not valid - Slave t

SCK high to STD high impedance - Slave t

SRD Setup time before SC0 low - Slave t

SRD Hold time after SC0 low - Slave t

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave t

SRD Hold time after SCK low - Slave t

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.

56855 Technical Data, Rev. 6

TXVS

FTXES

FTXVS

TXNVS

TXHIS

SS

HS

TSS

THS

4—15ns

4—15ns

4—15ns

4—15ns

4—15ns

4——ns

4——ns

4——ns

4——ns

38 Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI) Timing

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables
and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

t

SCKW

SCK input

SC2 (bl) input

SC2 (wl) input

STD

SC0 input

SC1 (bl) input

SC1 (wl) input

t

SCKH

t

FTXES

t

t

TXES

t

t

TFSBHS

t

TFSWHS

TXVS

t

RFSBHS

RFSWHS

t

SCKL

t

TFSBLS

t

FTXVS

t

TXNVS

First Bit Last Bit

t

RFBLS

t

TFSWLS

t

TXHIS

t

RFSWLS

t

t

SS

t

HS

TSS

t

THS

SRD

Figure 4-25 Slave Mode Clock Timing

56855 Technical Data, Rev. 6

Freescale Semiconductor 39

4.11 Serial Communication Interface (SCI) Timing

Table 4-12 SCI Timing

Operating Conditions: VSS = V

Characteristic Symbol Min Max Unit

Baud Rate

RXD

TXD

1. f

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

1

2

Pulse Width

3

Pulse Width

is the frequency of operation of the system clock in MHz.

MAX

RXD

SCI receive

data pin

(Input)

SSIO

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

= V

DDIO

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

DDA

BR — (f

RXD

TXD

PW

PW

RXD

PW

0.965/BR 1.04/BR ns

0.965/BR 1.04/BR ns

Figure 4-26 RXD Pulse Width

4

)/(32) Mbps

MAX

TXD

SCI receive

data pin

(Input)

TXD

PW

Figure 4-27 TXD Pulse Width

56855 Technical Data, Rev. 6

40 Freescale Semiconductor

4.12 JTAG Timing

JTAG Timing

1, 3

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Operating Conditions: VSS = V

SSIO

Table 4-13 JTAG Timing

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

DDA

Characteristic Symbol Min Max Unit

TCK frequency of operation

2

TCK cycle time t

TCK clock pulse width t

TMS, TDI data setup time t

TMS, TDI data hold time t

TCK low to TDO data valid t

TCK low to TDO tri-state t

TRST assertion time t

DE

assertion time t

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation,
T = 8.33ns.

2. TCK frequency of operation must be less than 1/4 the processor rate.

3. Parameters listed are guaranteed by design.

f

OP

CY

PW

DS

DH

DV

TS

TRST

DE

DC 30 MHz

33.3 — ns

16.6 — ns

3—ns

3—ns

—12ns

—10ns

35 — ns

4T — ns

t

CY

TCK

(Input)

VM = V

+ (VIH – VIL)/2

IL

t

PW

V

IH

V

M

V

IL

t

PW

V

M

Figure 4-28 Test Clock Input Timing Diagram

56855 Technical Data, Rev. 6

Freescale Semiconductor 41

TCK

(Input)

t

DS

t

DH

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output

TRST

(Input)

DE

Input Data Valid

t

DV

Output Data Valid

t

TS

)

Figure 4-29 Test Access Port Timing Diagram

t

TRST

Figure 4-30 TRST Timing Diagram

t

DE

Figure 4-31 Enhanced OnCE—Debug Event

56855 Technical Data, Rev. 6

42 Freescale Semiconductor

4.13 GPIO Timing

GPIO Timing

1, 2

= 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Operating Conditions: VSS = V

SSIO

Table 4-14 GPIO Timing

= V

= 0 V, VDD = 1.62-1.98V, V

SSA

DDIO

= V

DDA

Characteristic Symbol Min Max Unit

GPIO input period P

GPIO input high/low period P

GPIO output period P

GPIO output high/low period P

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns

IN

INHL

OUT

OUTHL

2. Parameters listed are guaranteed by design.

GPIO Inputs

P

IN

P

INHL

2T + 3 — ns

1T + 3 — ns

2T - 3 — ns

1T - 3 — ns

P

INHL

GPIO Outputs

P

OUT

Figure 4-32 GPIO Timing

P

OUTHL

P

OUTHL

56855 Technical Data, Rev. 6

Freescale Semiconductor 43

Part 5 Packaging

5.1 Package and Pin-Out Information 56855

This section contains package and pin-out information for the 100-pin LQFP configuration of the 56855.

V

DDIO

V

SSIO

RD

WR

A0
A1

A2
A3

V

DD

V

SS

MODA
MODB
MODC

V

DDIO

V

SSIO

IRQA
IRQB

V

DDA

V

SSA

XTAL

EXTAL

A4
A5
A6
A7

D15

D14

D13

V

MARK

PIN 1

PIN 26

SSIOVDDIO

D12

D11

ORIENTATION

SC02

SC01

SC00

SCK0

SRD0

STD0

SSIOVDDIOVSSVDD

V

D10D9D8D7D6

PIN 76

PIN 51

SSIO

V

TIO0

DDIO

V

TXD1
RXD1
V

SSIO

V

DDIO

D5
D4

D3
D2
D1

V

SS

V

DD

CS3
CS2
CS1
CS0
V

SSIO

D0
V

DDIO

A20
A19
A18
A17
A16
TXDO
RXD0

CLKO

RSTO

DDIO

V

V

RESET

SSIO

A8

A9

A10

DD

DE

V

A11

V

TDO

TRST

TDI

TMS

TCK

SSIO

DDIO

V

V

SSIO

DDIO

A15

V

V

A14

A12

A13

SS

Figure 5-1 Top View, 56855 100-pin LQFP Package

56855 Technical Data, Rev. 6

44 Freescale Semiconductor

Package and Pin-Out Information 56855

Table 5-1 56855 Pin Identification By Pin Number

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1V

2V

DDIO

SSIO

3RD28 RESET 53 A16 78 V

4WR29 V

5A030 V

6A1

7A2

8A3

9VDD34 A11 59 D0 84 V

10 V

SS

11 MODA 36 V

12 MODB 37 DE 62 CS1 87 V

26 CLKO 51 RXD0 76 V

DDIO

27 RSTO 52 TXD0 77 TIO0

SSIO

DDIO

SSIO

54 A17 79 D6

55 A18 80 D7

31 A8 56 A19 81 D8

32 A9 57 A20 82 D9

33 A10 58 V

35 V

DD

SS

60 V

61 CS0 86 V

DDIO

SSIO

83 D10

DD

85 V

SS

DDIO

SSIO

13 MODC 38 TRST 63 CS2 88 STD0

14 V

DDIO

39 TDO 64 CS3 89 SRD0

15 V

SSIO

16 IRQA

17 IRQB

18 V

19 V

DDA

SSA

20 XTAL

21 EXTAL

40 TDI 65 V

41 TMS 66 V

42 TCK 67 D1 92 SC01

43 V

44 V

DDIO

SSIO

68 D2 93 SC02

69 D3 94 D11

45 A12 70 D4 95 D12

46 A13 71 D5 96 V

22 A4 47 A14 72 V

23 A5 48 A15 73 V

24 A6

25 A7

49 V

50 V

DDIO

SSIO

74 RXD1 99 D14

75 TXD1 100 D15

56855 Technical Data, Rev. 6

DD

SS

DDIO

SSIO

90 SCK0

91 SC00

DDIO

97 V

SSIO

98 D13

Freescale Semiconductor 45

V

-AB-

S

T-U

S

S

0.15 (0.006) Z

S

AC

-T-

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

S

T- U

S

AC

S

0.15 (0.006) Z

-Z-

S

T- U

S

AC

B

S

0.15 (0.006) Z

-U-

9

0.15 (0.006) Z

AE

A

T- U

S

S

S

AB

AD

-AC-

G

96X

(24X PER SIDE)

AE

°

M

R

0.100 (0.004)

AC

SEATING
PLANE

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.

4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.

5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.

6. DIMENSIONS A AN D B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.

7. DIMENSION D DOES N OT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED

0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).

8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).

9. EXACT SHAPE OF EACH COR NER MAY VARY
FROM DEPICTION.

DIM MIN MAX MIN MAX

A 13.950 14.050 0.549 0.553
B 13.950 14.050 0.549 0.553
C 1.400 1.600 0.055 0.063
D 0.170 0.270 0.007 0.011
E 1.350 1.450 0.053 0.057

F 0.170 0.230 0.007 0.009
G 0.500 BSC 0.020 BSC
H 0.050 0.150 0.002 0.006

J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M 12 REF 12 REF

°°

N 0.090 0.160 0.004 0.006
Q 1 5 1 5

°°°°

R 0.150 0.250 0.006 0.010
S 15.950 16.050 0.628 0.632
V 15.950 16.050 0.628 0.632
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF

INCHESMILLIMETERS

E

C

H

W

0.25 (0.010)

GAUGE PLANE

K

°

Q

0.20 (0.008) Z

X

D

F

M

T-U

AC

SECTION AE-AE

J

N

S

S

DETAIL AD

Figure 5-2 100-pin LQPF Mechanical Information

Please see www.freescale.com for the most current case outline.

56855 Technical Data, Rev. 6

46 Freescale Semiconductor

Thermal Design Considerations

Part 6 Design Considerations

6.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1: TJ = TA + (PD x R

θJA

)

Where:

TA = ambient temperature °C
R

= package junction-to-ambient thermal resistance °C/W

θJA

P

= power dissipation in package

D

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2: R

θJA

= R

θJC

+ R

θCA

Where:

R

= package junction-to-ambient thermal resistance °C/W

θJA

R

= package junction-to-case thermal resistance °C/W

θJC

R

= package case-to-ambient thermal resistance °C/W

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

θJA

the thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.

• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.

• Use the value obtained by the equation (T
determined by a thermocouple.

56855 Technical Data, Rev. 6

Freescale Semiconductor 47

– TT)/PD where TT is the temperature of the package case

J

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,
the new thermal metric, Thermal Characterization Parameter, or Ψ

, has been defined to be (TJ – TT)/PD.

JT

This value gives a better estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.

6.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each V
board ground to each V

(GND) pin.

SS

pin on the controller, and from the

DD

• The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the ten V

DD/VSS

pairs, including V

DDA/VSSA.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and V

DD

SS

pins are less than 0.5 inch per capacitor lead.

• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V

• Bypass the V

and GND layers of the PCB with approximately 100 μF, preferably with a high-grade

DD

and GND.

DD

capacitor such as a tantalum capacitor.

• Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

56855 Technical Data, Rev. 6

(GND)

48 Freescale Semiconductor

Electrical Design Considerations

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V

and GND circuits.

DD

• All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

• Take special care to minimize noise levels on the V

• When using Wired-OR mode on the SPI or the IRQx

• Designs that utilize the TRST

pin for JTAG port or Enhance OnCE module functionality (such as

and V

DDA

pins, the user must provide an external pull-up device.

development or debugging systems) should allow a means to assert TRST
well as a means to assert TRST

independently of RESET. Designs that do not require debugging

SSA

pins.

whenever RESET is asserted, as

functionality, such as consumer products, should tie these pins together.

• The internal POR (Power on Reset) will reset the part at power on with reset
requires that TRST

be asserted at power on.

asserted or pulled high but

56855 Technical Data, Rev. 6

Freescale Semiconductor 49

Part 7 Ordering Information

Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 7-1 56855 Ordering Information

Part

DSP56855 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 DSP56855BU120

DSP56855 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 DSP56855BUE *

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

*This package is RoHS compliant.

56855 Technical Data, Rev. 6

50 Freescale Semiconductor

Electrical Design Considerations

56855 Technical Data, Rev. 6

Freescale Semiconductor 51

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[e-mail]

USA/Europe or Locations Not Listed:

Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
[phone] or [phone]
[e-mail]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
[e-mail]

Japan:

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DSP56855
Rev. 6
01/2007