Freescale 33989 Technical Data

Freescale Semiconductor

Technical Data

System Basis Chip with

Document Number: MC33989

Rev. 13.0, 3/2007

High-Speed CAN Transceiver

The 33989 is a monolithic integrated circuit combining many
functions used by microcontrollers (MCU) found in automotive
Engine Control Units (ECUs). The device incorporates
functions such as: two voltage regulators, four high voltage
(wake up) inputs, a 1Mbaud capable CAN physical interface,
an SPI interface to the MCU and VSUP monitoring and fault
detection circuitry. The 33989 also provides reset control in
conjunction with VSUP monitoring and the watchdog timer
features. Also, an Interrupt can be generated, for the MCU,
based on CAN bus activity as well as mode changes.

Features

•V

•V

• V2: Tracking Function of V

• Low Stand-By Current Consumption in Stop and Sleep Modes

• High-Speed 1 MBaud CAN Physical Interface

• Four External High Voltage Wake-up Inputs Associated with HS1

• 150 mA Output Current Capability for HS1 V

•V

• 40 V Maximum Transient Voltage

• Pb Free designated by suffix code EG

: Low Drop Voltage Regulator, Current Limitation,

DD1

Overtemperature Detection, Monitoring, and Reset Function

: Total Current Capability 200 mA

DD1

External Bipolar Ballast Transistor for High Flexibility in Choice of

Peripheral Voltage and Current Supply

V

Switch

BAT

Drive of External Switches Pull-Up Resistors or Relays

Failure Detection

SUP

Regulator. Control Circuitry for

DD1

Switch Allowing

BAT

33989

Device

MC33989DW/R2
MCZ33989EG/R2

V

PWR

33989

SYSTEM BASIS CHIP

WITH HIGH-SPEED CAN

DW SUFFIX

EG SUFFIX (PB-FREE)

98ASB42345B
28-PIN SOICW

ORDERING INFORMATION

Temperature

Range (T

- 40°C to 125°C 28 SOICW

)

A

Package

5.0 V

MCU

SCLK
MOSI
MISO

CS

SPI

VDD1

GND

RST
INT

CS
SCLK
MOSI
MISO

VSUP

V2CTRL

V2

HS1

L0
L1
L2
L3

WD

TX
RX

Figure 1. MC33989 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

CANH

CANL

V2

Local Module Supply

Wake-Up Inputs

Safe Circuits

Twisted

CAN Bus

Pair

INTERNAL BLOCK DIAGRAM

VSUP

INTERNAL BLOCK DIAGRAM

VSUP Monitor Dual

Voltage Regulator

VDD1 Monitor

VDD1

HS1

L0

L1

TX

RX

CAN H

CAN L

HS1 Control

Oscillator

Interrupt

Watchdog

Programmable

Reset

Wake-Up Inputs

Mode Control

SPI

High Speed

Interface

1.0 MB/s CAN
Physical

Interface

Figure 2. 33989 Simplified Internal Block Diagram

INT

WD

RST

CS

SCLK

MOSI

MISO

GND

33989

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

PIN CONNECTIONS

RX

TX

VDD1

RST

INT
GND
GND
GND
GND

V2

V2CTRL

VSUP

HS1

L0

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28

WD

27

CS

26

MOSI

25

MISO

24

SCLK

23

GND

22

GND

21

GND

20

GND

19

CANL

18

CANH

17

L3

16

L2

15

L1

Figure 3. 33989 Pin Connections

Table 1. 33989 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.

Pin Number Pin Name Pin Function Formal Name Definition

1 RX Output Receive Data
2 TX Input Transmit Data
3 VDD1 Power

Output

Voltage Digital Drain

One

4 RST Output Reset

5 INT Output Interrupt

6–9

GND Ground Ground

20–23

10 V2 Input Voltage Source Two

11 V2CTRL Power

Voltage Control

Output
12 VSUP Power Voltage Supply
13 HS1 Output High Side One

14–17 L0:L3 Input Level 0: 3

22 CANH Output CAN High
23 CANL Output CAN Low
24 SCLK Input System Clock
25 MISO Output Master In/Slave Out

26 MOSI Input Master Out/Slave In
27 CS Input Chip Select
28 WD Output Watch Dog

CAN bus receive data output pin.
CAN bus transmit data input pin.

5.0 V regulator output pin. Supply pin for the MCU.

This is the device reset output pin whose main function is to reset the
MCU. This pin has an internal pullup current source to VDD.

This output is asserted LOW when an enabled interrupt condition occurs.
The output is a push-pull structure.

These device ground pins are internally connected to the package lead
frame to provide a 33989-to-PCB thermal path.

Sense input for the V2 regulator using an external series pass transistor.
V2 is also the internal supply for the CAN transceiver.

Output drive source for the V2 regulator connected to the external series
pass transistor.

Supply input pin for the 33989.
Output of the internal high-side switch. The output current is internally

limited to 150

mA.
Inputs from external switches or from logic circuitry.
CAN high output pin.
CAN low output pin.
Clock input pin for the Serial Peripheral Interface (SPI).
SPI data sent to the MCU by the 33989. When CS is HIGH, the pin is in

the high-impedance state.
SPI data received by the 33989.
The CS input pin is used with the SPI bus to select the 33989.
The WD output pin is asserted LOW if the software watchdog is not

correctly triggered.

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage at VSUP

Continuous (Steady-State)
Transient Voltage (Load Dump)

Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WD, and INT)
Output Current VDD1
HS1

Voltage
Output Current

ESD Voltage, Human Body Model

(1)

HS1, L0, L1, L2, L3
All Other Pins

ESD Voltage Machine Model

All Pins Except CANH and CANL

L0, L1, L2, L3

DC Input Voltage
DC Input Current

Transient Input Voltage with External Component

(2)

CANL and CANH Continuous Voltage
CANL and CANH Continuous Current
CANH and CANL Transient Voltage (Load Dump)
CANH and CANL Transient Voltage

(5)

(4)

Logic Inputs (TX and RX)
ESD Voltage (HBM 100 pF, 1.5 k) CANL, CANH
ESD Voltage Machine Model

CANH and CANL

Notes

1. ESD1 testing is performed in accordance with the Human Body Model (C
= 0 Ω), and the Charge Device Model (CDM), Robotic (C

R

ZAP

ZAP

= 4.0pF).

2. According to ISO 7637 specification. See Table 6, page 24.

3. Load Dump test according to ISO 7637 part 1.

4. Transient test according to ISO 7637 part 1, pulses 1, 2, 3a, and 3b according to schematic in Table 17, page 35.

V
V

V

SUP
SUP

LOG

-0.3 to 27

-0.3 to 40

-0.3 to V

+ 0.3 V

DD1

I Internally Limited A

V

V

I

ESDH

-0.3 to V

SUP

+ 0.3

Internally Limited

- 4.0 to 4.0

-2.0 to 2.0

V

ESDM

±200

V

WUDC

-0.3 to 40

-2.0 to 2.0

-100 to 100

V

CANH/L

I

CANH/L

V

TRH/L

V

TRH/L

-27 to 40 V
200 mA

40 V

-40 to 40 V

V -0.5 to 6.0 V

V

ESDCH

V

ESDCM

-4.0 to 4.0 KV

-200 to 200

= 100 pF, 1.5 k), the Machine Model (MM) (C

ZAP

= 200 pF,

ZAP

V

V
A

kV

V

V

mA

V

V

33989

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

THERMAL RATINGS

Operating Junction Temperature
Storage Temperature
Ambient Temperature
Thermal Resistance Junction to GND Pins

(5)

Peak Package Reflow Temperature During Reflow

(6), (7)

R
T

T

J

T

S

T

A
J/P

Θ

PPRT

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

-40 to 150 °C

-55 to 165 °C

-40 to 125 °C
20 °C/W

Note 7.

°C

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ V

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

POWER INPUT (VSUP)

Nominal DC Supply Voltage Range
Extended DC Voltage Range 1

Reduced Functionality
Extended DC Voltage Range 2
Input Voltage During Load Dump

Load Dump Situation
Input Voltage During Jump Start

Jump Start Situation
Supply Current in Standby Mode

I

at V

= 40 mA CAN recessive or Sleep-Disable State

OUT

DD1

Supply Current in Normal Mode

I

at V

= 40 mA CAN recessive or Sleep-Disable State

OUT

DD1

Supply Current in Sleep Mode

V

and V2 OFF, V

DD1

Sleep-Disable State
Supply Current in Sleep Mode

V

and V2 OFF, V

DD1

Sleep-Disable State
Supply Current in Sleep Mode

V

and V2 OFF, V

DD1

Sleep-Disable State
Supply Current in Stop Mode I

V

ON, V

DD1

SUP

Sleep-Disable State
Supply Current in Stop Mode I

V

ON, V

DD1

SUP

Sleep-Disable State
Supply Current in Stop Mode I

V

ON, V

DD1

SUP

Sleep-Disable State
BATFAIL Flag Internal Threshold

Notes

8. V

> 4.0 V, Reset high, Logic pin high level reduced, device is functional.

DD1

9. Device is fully functional. All functions are operating. All modes available and operating. Watchdog, HS1 turn ON turn OFF, CAN cell
operating, L0:L3 inputs operating, SPI read/write operation. Overtemperature may occur.

10. Current measured at V

11. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value.

12. Oscillator running means Forced Wake-up or Cyclic Sense of Software Watchdog is Stop mode are not activated.

(8)

(9)

(10) (11)

(10)

(10) (11)

< 12 V, Oscillator Running

SUP

(10) (11)

< 12 V, Oscillator Not Running

SUP

(10) (11)

> 12 V, Oscillator Running

SUP

V

OUT

< 12 V, Oscillator Running

OUT VDD1

< 2.0 mA

DD1

< 2.0 mA

(12)

< 12 V, Oscillator Not Running

OUT VDD1

> 12 V, Oscillator Running

SUP

< 2.0 mA

(12)

pin.

CAN in

(11)

(12)

(10) (11)

CAN in

≤ 18 V, - 40°C ≤ T

SUP

(12)

CAN in

(12)

(12)

CAN in

(10) (11)

CAN in

≤ 125°C, GND = 0 V unless otherwise noted. Typical

= 25°C under nominal conditions unless otherwise noted.

A

A

V

SUP

V

SUPEX1

5.5 — 18 V

4.5 — 5.5

V

SUPEX2

V

SUPLD

18 — 27 V

— — 40

V

SUPJS

— — 27

I

SUP(STDBY)

— 42 45

I

SUP(NORM)

— 42.5 45

I

SUP(SLEEP1)

— 72 105

I

SUP(SLEEP2)

CAN in

I

SUP(SLEEP3)

— 57 90

— 100 150

I

SUP(STOP1)

— 135 210

I

SUP(STOP2)

— 130 210

I

SUP(STOP3)

— 160 230

VBF 1.5 3.0 4.0 V

V

V

V

mA

mA

µA

µA

µA

µA

µA

µA

33989

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

BATFAIL Flag Hysteresis
Battery Fall Early Warning Threshold

In Normal and Standby Mode

Battery Fall Early Warning Hysteresis

In Normal and Standby Mode

POWER OUTPUT (VDD1)

VDD1 Output Voltage

I

from 2.0 to 200 mA T

DD1

VDD1 Output Voltage

I

from 2.0 to 200 mA, 4.5 V < V

DD1

Dropout Voltage

I

= 200 mA

DD1

Dropout Voltage, Limited Output Current

I

= 50 mA, 4.5 V < V

DD1

I

Output Current

DD1

Internally Limited

Junction Thermal Shutdown

Normal or Standby Modes

Junction Over Temperature Pre-Warning

V

Temperature Threshold Difference
Reset Threshold 1

Selectable by SPI. Default Value After Reset.

Reset Threshold 2

Selectable by SPI

V

DD1

Reset Delay Time

Measured at 50% of Reset Signal

Line Regulation (C at V

9.0 V V

Line Regulation (C at V

5.5 < V

Load Regulation (C at V

1.0 mA < I

Thermal Stability

V

Notes

13. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value.

14. I

15. Guaranteed by design; however, it is not production tested.

Bit Set

DDTEMP

Range for Reset Active

< 18, IDD = 10 mA

SUP

< 27 V, IDD = 10 mA

SUP

< 200 mA

IDD

= 13.5 V, 1 = -100 mA Not Tested

SUP

is the total regulator output current. VDD specification with external capacitor. Stability requirement: C > 47 µF ESR < 1.3 Ω

DD1

(tantalum capacitor). In reset, normal request, normal and standby modes. Measure with C = 47 µF Tantalum.

(13)

(13)

(14)

-40 to 125°C, 5.5 V < V

AMB

SUP

= 47 µF Tantal)

DD1

= 47 µF Tantal)

DD1

= 47 µF Tantal)

DD1

SUP

< 5.5 V

(15)

SUP

< 27 V

VBF

(HYS)

BF

EW

BF

EWH

V

DD1OUT

V

DD1OUT2

V

DD1DRP

V

DD1DRP2

I

DD1

T

SD

T

PW

T

- T

SD

PW

RST

TH1

RST

TH2

V

DDR

t

D

LR1

LR2 —

LD

THERM

S

— 1.0 — V

5.3 5.8 6.3

0.1 0.2 0.3

4.9 5.0 5.1

4.0 — —

— 0.2 0.5

— 0.1 0.25

200 285 350

160 — 200

125 — 160

20 — 40 °C

4.5 4.6 4.7

4.1 4.2 4.3

1.0 — — V
—

4.0

30

—

5.0 25

10 25

— 25 75

— 30 50

V

V

V

V

V

V

mA

°C

°C

V

V

µs

mV

mV

mV

mV

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SUP

(16)

(19)

< 27 V

(17)

(18)

V

DDSTOP

V

DDSTOP2

I

DD1SWU

I

DD1DGLT

RST

STOP1

RST

STOP2

LR

LD

V

DDst-cap

V2

I2

12

CTRL

V2L

V

OL

V

OH

I

HZ

S

S

TH

4.75 5.00 5.25

4.75 5.00 5.25
10 17 25 mA
40 55 75 µs

4.5 4.6 4.7 V

4.1 4.2 4.3 V

— 5.0 25

— 15 75
— — 200 µF

0.99 1.0 1.01

200 — —

0.0 — 10

3.75 4.0 4.25 V

0.0 — 1.0

V

DD1-0.9

— V

DD1

-2.0 — 2.0

” parameter.

DDst-cap

and prevent the device to stay in

DDSWU

POWER OUTPUT (VDD1) IN STOP MODE

VDD1 Output Voltage

I

< = 2.0 mA

DD1

VDD1 Output Voltage

I

< = 10 mA

DD1

I

Stop Output Current to Wake-up SBC

DD1

I

Over Current to Wake-up Deglitcher Time

DD1

Reset Threshold
Reset Threshold
Line Regulation (C at V

5.5 V < V

< 27 V, IDD = 2.0 mA

SUP

Load Regulation (C at V

= 47 µF Tantal)

DD1

= 47 µF Tantal)

DD1

1 mA < IDD < 10 mA

Max Decoupling Capacitor at VDD1 Pin, in Stop Mode

TRACKING VOLTAGE REGULATOR (V2)

V2 Output Voltage (C at V2 = 10 µF Tantal)

I2 from 2.0 to 200 mA, 5.5 V < V

I2 Output Current (for information only)

Depending Upon External Ballast Transistor

V2 Control Drive Current Capability

Worst Case at TJ = 125°C

V2LOW Flag Threshold

LOGIC OUTPUT PIN (MISO)

(20)

Low Level Output Voltage

I

= 1.5 mA

OUT

High Level Output Voltage

I

= 250 µA

OUT

Tri-Stated MISO Leakage Current

0 V < V

MISO

< V

DD

Notes

16. If stop mode is used, the capacitor connected at VDD pin should not exceed the maximum specified by the “V
If capacitor value is exceeded, upon entering stop mode, VDD output current may exceed the I

stop mode.

17. Guaranteed by design; however, it is not production tested.

18. Guaranteed by design.

19. V2 specification with external capacitor

- Stability requirement: C > 42 µF and ESR < 1.3 Ω (Tantalum capacitor), external resistor between base and emitter required

- Measurement conditions: Ballast transistor MJD32C, C = 10 µF Tantalum, 2.2 k resistor between base and emitter of ballast transistor

20. Push/Pull structure with tri-state condition CS high.

V

V

V

mV

mV

DD1

mA

mA

V

V

µA

33989

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

LOGIC INPUT PINS (MOSI, SCLK, CS)

High Level Input Voltage
Low Level Input Voltage
High Level Input Current on CS
Low Level Input Current on CS
MOSI and SCLK Input Current

RESET PIN (RST)

(21)

High Level Output Current

0 < V

OUT

< 0.7 V

DD

Low Level Output Voltage (I0 = 1.5 mA)

5.5 V < V

SUP

< 27 V

Low Level Output Voltage (I0 = 0 µA

1.0 V < V

SUP

< 5.5 V

Reset Pull Down Current

V > 0.9 V

Reset Duration After V

WATCHDOG OUTPUT PIN (WD)

DD1

High

(22)

Low Level Output Voltage (I0 = 1.5 mA)

1.0 V < V

SUP

< 27 V

High Level Output Voltage (I0 = 250 µA)

INTERRUPT PIN (INT)

(22)

Low Level Output Voltage (I0 = 1.5 mA)
High Level Output Voltage (I0 = 250 µA)

HIGH SIDE OUTPUT PIN (HS1)

R

at TJ = 25°C, and I

DSON

V

> 9.0 V

SUP

R

at TA = 125°C, and I

DSON

V

> 9.0 V

SUP

R

at TA = 125°C, and I

DSON

5.5 < V

SUP

< 9.0 V

OUT

OUT

OUT

- 150 mA

- 150 mA

- 120 mA

Output Current Limitation
HS1 Overtemperature Shutdown
HS1 Leakage Current
Output Clamp Voltage at I

OUT

= -10 mA

No Inductive Load Drive Capability

Notes

21. Push/Pull structure with tri-state condition CS high.

22. Output pin only. Supply from VDD1. Structure switch to ground with pull-up current source.

V

V

I

RST

V

V

V
V

RON

RON

RON

L
O

L

V

IH

V

IL

L

IH

L

IL

L

N

I

OH

OL

OL

PDW

DUR

OL

OH

OL

OH

125-2

LIM

VT

LEAK

V

CL

25

125

0.7 V

DD1

-0.3 — 0.3 V

— V

+ 0.3 V

DD1

DD1

-100 — -20 µA

-100 — -20 µA

-10 — 10 µA

-300 -250 -150

0.0 — 0.9

0.0 — 0.9

2.3 — 5.0

3.0 3.4 4.0 ms

0.0 — 0.9

V

-0.9 — V

DD1

DD1

0.0 — 0.9 V

V

-0.9 — V

DD1

DD1

— 2.0 2.5

— — 4.5

— 3.5 5.5

160 — 500 mA
155 — 190 °C

— — 10 µA

-1.5 — -0.3

V

µA

V

V

mA

V

V

V

Ω

Ω

Ω

V

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

LOGIC INPUTS (L0:L3)

Negative Switching Threshold

5.5 V < V

6.0 V < V
18 V < V

SUP
SUP

SUP

< 6.0 V
< 18 V

< 27 V

Positive Switching Threshold

5.5 V < V

6.0 V < V
18 V < V

SUP
SUP

SUP

< 6.0 V
< 18 V

< 27 V

Hysteresis

5.5 V < V

SUP

< 27 V

Input Current

-0.2 V < V

IN

< 40 V

CAN SUPPLY (V2)

Supply Current Cell

Recessive State

Supply Current Cell

Dominant State without Bus Load

Supply Current Cell, CAN in Sleep State Wake-up Enable

V2 Regulator OFF

Supply Current Cell, CAN in Sleep State Wake-up Disable

V2 Regulator OFF

(23)

Notes

23. Push/Pull structure.

V

THN

V

THP

V

HYS

L

IN

I

RES

I

DOM

I

SLEEP

I

DIS

2.0

2.5

2.7

2.7

3.0

3.5

2.5

3.0

3.2

3.3

4.0

4.2

3.0

3.6

3.7

3.8

4.6

4.7

0.6 — 1.3

-10 — 10

— 1.5 3.0

— 2.0 6.0

— 55 70

— — 1.0

V

V

V

µA

mA

mA

µA

µA

33989

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

CANH AND CANL

Bus Pins Common Mode Voltage
Differential Input Voltage (Common Mode Between -3.0 and 7.0 V)

Recessive State at RXD

Dominant State at RXD
Differential Input Hysteresis (RXD)
Input Resistance
Differential Input Resistance
Unpowered Node Input Current
CANH Output Voltage

TXD Dominant State

TXD Recessive State
CANL Output Voltage

TXD Dominant State

TXD Recessive State
Differential Output Voltage

TXD Dominant State

TXD Recessive State

CANH AND CANL

Output Current Capability (Dominant State)

CANH

CANL
Overtemperature Shutdown
CANL Over Current Detection

Error Reported in CANR
CANH Over Current Detection

Error Reported in CANR

TX AND RX

TX Input High Voltage
TX Input Low Voltage
TX High Level Input Current, VTX = V

DD

TX Low Level Input Current, VTX = 0 V
RX Output Voltage High, IRX = 250 µA
RX Output Voltage Low, IRX = 1.0 mA

V

CM

V

CANH-VCANL

V

HYS

R

IN

R

IND

I

CANUP

V

CANHD

V

CANHR

V

CANLD

V

CANLR

V

DIFFD

V

DIFFR

I

CANH

I

CANL

T

SHUT

I

CANL/OC

I

CANH/OC

V

IH

V

ILP

L

IH

L

IL

V

OH

V

OL

-27 — 40 V

—

900

—
—

500

—

100 — — mV

5.0 — 100 KΩ
10 — 100 KΩ
— — 1.5 mA

2.75
—

0.5

2.0

1.5
—

—

—
—

—
—

—
—

4.5

3.0

2.25
—

3.0

100

— -35

35

160 180°C — °C

60 — 200

-200 — -60

0.7 V

DD

-0.4 — 0.3 V

— VDD + 0.4 V

DD

-10 — 10 µA

-100 -50 -20 µA

VDD-1 — — V

— — 0.5 V

mV

V

V

V

mV

mA

mA

mA

V

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 7.0 V ≤ V

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)

SPI Operation Frequency
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 220 pF)
MISO Fall Time (CL = 220 pF)
Time from Falling or Rising Edges of CS to:

MISO Low Impedance
MISO High Impedance

Time from Rising Edge of SCLK to MISO Data Valid

0.2 V1 = <MISO> = 0.8 V1, CL = 200 pF

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

= 25°C under nominal conditions unless otherwise noted.

A

A

F

REQ

t

PCLK

t

WSCLKH

t

WSCLKH

t

LEAD

t

LAG

t

SISU

t

SIH

t

RSO

t

FSO

t

SOEN

t

SODIS

t

VALID

0.25 — 4.0 MHz
250 — N/A ns
125 — N/A ns
125 — N/A ns
100 — N/A ns
100 — N/A ns

40 — N/A ns
40 — N/A ns
— 25 50 ns
— 25 50 ns

—
—

—
—

50
50

— — 50

ns

ns

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WD, INT)

Delay Between CS Low to High Transition (End of SPI Stop Command) and
Stop Mode Activation Detected by V2 OFF

(24)

Interrupt Low Level Duration

SBC in Stop Mode

Internal Oscillator Frequency

All Modes Except Sleep and Stop

(24)

Internal Low Power Oscillator Frequency

Sleep and Stop Modes

(24)

Watchdog Period 1

Normal and Standby Modes

Watchdog Period 2

Normal and Standby Modes

Watchdog Period 3

Normal and Standby Modes

Watchdog Period 4

Normal and Standby Modes

Watchdog Period Accuracy

Normal and Standby Modes

Notes

24. Guaranteed by design; however it is not production tested.

t

CS

t

O

SCF1

O

SCF2

WD

WD

WD

WD

f

1ACC

STOP

INT

1

2

3

4

µs

18 — 34

µs

7.0 10 13
kHz

— 100 —

kHz

— 100 —

ms

8.58 9.75 10.92
ms

39.6 45 50.4
ms

88 100 112

ms

308 350 392

%

-12 — 12

33989

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Normal Request Mode Timeout

Normal Request Modes

Watchdog Period 1 - Stop

Stop Mode

Watchdog Period 2 - Stop

Stop Mode

Watchdog Period 3 - Stop

Stop Mode

Watchdog Period 4 - Stop

Stop Mode

Stop Mode Watchdog Period Accuracy

Stop Mode

Cyclic Sense/FWU Timing 1

Sleep and Stop Modes

Cyclic Sense/FWU Timing 2

Sleep and Stop Modes

Cyclic Sense/FWU Timing 3

Sleep and Stop Modes

Cyclic Sense/FWU Timing 4

Sleep and Stop Modes

Cyclic Sense/FWU Timing 5

Sleep and Stop Modes

Cyclic Sense/FWU Timing 6

Sleep and Stop Modes

Cyclic Sense/FWU Timing 7

Sleep and Stop Modes

Cyclic Sense/FWU Timing 8

Sleep and Stop Modes

Cyclic Sense ON Time

Sleep and Stop Modes Threshold and Condition to be Added

Cyclic Sense/FWU Timing Accuracy

Sleep and Stop Modes
Delay Between SPI Command and HS1 Turn ON
Delay Between SPI Command and HS1 Turn OFF
Delay Between SPI and V2 Turn ON

(25)

(25)

(25)

Standby Mode
Delay Between SPI and V2 Turn OFF

(25)

Normal Mode

Notes

25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2.

NR

TOUT

WD

1STOP

WD

2STOP

WD

3STOP

WD

4STOP

f

2ACC

CS

FWU1

CS

FWU2

CS

FWU3

CS

FWU4

CS

FWU5

CS

FWU6

CS

FWU7

CS

FWU8

t

ON

t

ACC

t

SHSON

t

SHSOFF

tS

V2ON

tS

V2OFF

308 350 392

6.82 9.75 12.7

31.5 45 58.5

70 100 130

245 350 455

-30 — 30

3.22 4.6 5.98

6.47 9.25 12

12.9 18.5 24

25.9 37 48.1

51.8 74 96.2

66.8 95.5 124

134 191 248

271 388 504

200 350 500

-30 — 30
— — 22 µs
— — 22 µs

9.0 — 22

9.0 — 22

ms

ms

ms

ms

ms

%

ms

ms

ms

ms

ms

ms

ms

ms

µs

%

µs

µs

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 13

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Delay Between Normal Request and Normal Mode After WD Trigger Command

Normal Request Mode

Delay Between SPI and CAN Normal Mode

SBC Normal Mode

(26)

Delay Between SPI and CAN Normal Mode

SBC Normal Mode

(26)

Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode
(V

on and Reset High)

DD1

SBC in Stop Mode

Delay Between CS Wake-up (CS Low to High) and First Accepted API
Command

SBC in Stop Mode

Delay Between INT Pulse and First SPI Command Accepted

In Stop Mode After Wake-up

INPUT TERMINNALS (L0, L1, L2, AND L3)

Wake-up Filter Time

CAN MODULE-SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL)

Dominant State Timeout
Propagation Loop Delay TX to RX, Recessive to Dominant

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

Propagation Delay TX to CAN

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

Propagation Delay CAN to RX, Recessive to Dominant
Propagation Loop Delay TX to RX, Dominant to Recessive

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

Propagation Delay TX to CAN

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

Propagation Delay CAN to RX, Dominant to Recessive

Notes

26. Guaranteed by design; however, it is not production tested.

tS

tS

tS

tW

tW

tS

1STSPI

t

t

DOUT

t

t

t
t

t

t

NR2N

CANN

CANS

CS

SPI

WUF

LRD

TRD

RRD

LDR

TDR

RDR

15 35 70

— — 10

— — 10

15 40 90

90 — N/A

20 —

N/A

8.0 20 38 µs

200 360 520 µs

70
80

100
110

20
40
60

100

140
155
180
220

65

80
120
160

210
225
255
310

110
150
200
300

30 80 140 ns

70

90
100
130

60

65

75

90

120
135
160
200

110
120
150
190

170
180
220
260

130
150
200
300

20 40 60

µs

µs

µs

µs

µs

µs

ns

ns

ns

ns

33989

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V ≤ V

≤ 18 V, - 40°C ≤ T

SUP

≤ 125°C, GND = 0 V unless otherwise noted. Typical

A

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Non Differential Slew Rate (CANL or CANH)

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

t
t
t
t

SL3
SL2
SL1
SL0

4.0

3.0

2.0

1.0

19

13.5

8.0

5.0

40
20
15
10

V/µs

CANH
CANL

WU Receiver

Standby

Pulse Width

Filter

Figure 4. Wake-Up Block Diagram

The block diagram in Figure 4 illustrates how the wake-up
signal is generated. First the CAN signal is detected by a low
consumption receiver (WU receiver). Then the signal passes
through a pulse width filter which discards the undesired
pulses. The pulse must have a width bigger than 0.5 µs and
smaller than 500 µs to be accepted. When a pulse is
discarded the pulse counter is reset and no wake signal is
generated, otherwise when a pulse is accepted the pulse
counter is incremental and after three pulses the wake signal
is asserted.

1nF

LX

10 k

GND

Note: Waveform in accordance to

ISO 7637 part1, test pulses 1, 2, 3a and 3b.

Transient Pulse

Generator

(Note)

GND

Figure 5. Transient Test Pulse for L0:L3 Inputs

Pulse OK

Narrow
Pulse

Counter

RST

+

Timeout

Generator

Latch
RST

Timeout

WU

OUT

Each one of the pulses must be spaced by no more than
500 µs. In that case the pulse counter is reset and no wake
signal is generated. This is accomplished by the wake
timeout generator. The wake-up cycle is completed (and the
wake flag reset) when the CAN interface is brought to CAN
Normal mode.

The wake-up capability of the CAN can be disabled, refer
to SPI interface and register section, CAN register.

1nF

CANH

CANL

GND

1nF

Note: Waveform in accordance to

ISO 7637 part1, test pulses 1, 2, 3a and 3b.

Transient Pulse

Generator

Figure 6. Transient Test Pulses for CANH/CANL

(Note)

GND

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

T

TX

LRD

2.0 V

0.8 V

RX

0.8 V

T

LDR

2.0 V

TX

V

V

0.8 V

DIFF

0.9 V

DIFF

T

TRD

0.9 V

T

RRD

V

DIFF

= V

CANH

2.0 V

- V

0.5 V

CANL

T

TDR

0.5 V

T

RDR

RX

0.8 V

Figure 7. Transceiver AC Characteristics

2.0 V

33989

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

TIMING DIAGRAMS

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 8. SPI Timing Characteristics

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 17

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33989 is an integrated circuit dedicated to automotive

applications. Its functions include:

• One full protected voltage regulator with 200 mA total
output current capability available at V

external pin

DD1

FUNCTIONAL PIN DESCRIPTION

RECEIVE AND TRANSMIT DATA (RXD AND TXD)

The RX and TX pins (receive data and transmit data pins,

respectively) are connected to a microcontroller’s CAN
protocol handler. TXD is an input and controls the CANH and
CANL line state (dominant when TXD is LOW, recessive
when TXD is HIGH). RXD is an output and reports the bus
state (RXD LOW when CAN bus is dominant, HIGH when
CAN bus is recessive).

VOLTAGE DIGITAL DRAIN ONE (VDD1)

The VDD1 pin is the output pin of the 5.0 V internal

regulator. It can deliver up to 200 mA. This output is protected
against overcurrent and overtemperature. It includes an
overtemperature pre-warning flag, which is set when the
internal regulator temperature exceeds 130°C typical. When
the temperature exceeds the overtemperature shutdown
(170°C typical), the regulator is turned off.

VDD1 includes an undervoltage reset circuitry, which sets

the RST pin LOW when V
threshold.

is below the undervoltage reset

DD1

RESET (RST)

The Reset pin RST is an output that is set LOW when the

device is in reset mode. The
device is not in reset mode.
current source. When RST is LOW, the sink current capability
is limited, allowing
debug or software download purposes.

RST to be shorted to 5.0 V for software

RST pin is set HIGH when the

RST includes an internal pullup

INTERRUPT (INT)

The Interrupt pin INT is an output that is set LOW when an

interrupt occurs.
(INTR). When an interrupt occurs,
interrupt source is cleared.

INT output also reports a wake-up event by a 10 µs typical

pulse when the device is in Stop mode.

INT is enabled using the Interrupt Register

INT stays LOW until the

VOLTAGE SOURCE TWO (V2)

The V2 pin is the input sense for the V2 regulator. It is

connected to the external series pass transistor. V2 is also
the 5.0 V supply of the internal CAN interface. It is possible to

• Driver for an external path transistor for the V2 regulator
function

• Reset, programmable watchdog function, interrupt, and
four operational modes

• Programmable wake-up input and Cyclic Sense wake-up

• CAN high-speed physical interface

connect V2 to an external 5.0
output when no external series pass transistor is used. In this
case, the V2CTRL pin must be left open.

V regulator or to the VDD1

VOLTAGE SOURCE 2 CONTROL (V2CTRL)

The V2CTRL pin is the output drive pin for the V2 regulator

connected to the external series pass transistor.

VOLTAGE SUPPLY (VSUP)

The VSUP pin is the battery supply input of the device.

HIGH-SIDE ONE (HS1)

The HS1 pin is the internal high-side driver output. It is

internally protected against overcurrent and
overtemperature.

LEVEL 0-3 INPUTS (L0:L3)

The L0:L3 pins can be connected to contact switches or

the output of other ICs for external inputs. The input states
can be read by SPI. These inputs can be used as wake-up
events for the SBC when operating in the Sleep or Stop
mode.

CAN HIGH AND CAN LOW OUTPUTS
(CANH AND CANL)

The CAN High and CAN Low pins are the interfaces to the

CAN bus lines. They are controlled by TX input level, and the
state of CANH and CANL is reported through RX output. A

Ω termination resistor is connected between CANH and

60
CANL pins.

SYSTEM CLOCK (SCLK)

SCLK is the System Clock input pin of the serial peripheral

interface.

MASTER IN SLAVE OUT (MISO)

MISO is the Master In Slave Out pin of the serial peripheral

interface. Data is sent from the SBC to the microcontroller
through the MISO pin.

33989

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

MASTER OUT SLAVE IN (MOSI)

MOSI is the Master Out Slave In pin of the serial peripheral
interface. Control data from a microcontroller is received
through this pin.

CHIP SELECT (CS)

CS is the Chip Select pin of the serial peripheral interface.

When this pin is LOW, the SPI port of the device is selected.

WATCHDOG (WD)

The Watchdog output pin is asserted LOW to flag that the

software watchdog has not been properly triggered.

33989

Analog Integrated Circuit Device Data
Freescale Semiconductor 19

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

DEVICE SUPPLY

The device is supplied from the battery line through the
VSUP pin. An external diode is required to protect against
negative transients and reverse battery. It can operate from

4.5 V and under the jump start condition at 27

Vdc. This pin
sustains standard automotive voltage conditions such as
load dump at 40 V. When V

falls below 3.0 V typical the

SUP

33989 detects it and stores the information into the SPI
register in a bit called BATFAIL. This detection is available in
all operation modes.

The device incorporates a battery early warning function,

providing a maskable interrupt when the V

voltage is

SUP

below 6.0 V typical. A hysteresis is included. Operation is
only in Normal and Standby modes. V

low is reported in

SUP

the Input/Output Register (IOR).

VDD1 VOLTAGE REGULATOR

The VDD1 Regulator is a 5.0 V output voltage with output
current capability up to 200 mA. It includes a voltage
monitoring circuitry associated with a reset function. The
VDD1 regulator is fully protected against overcurrent and
short-circuit. It has over- temperature detection warning flags
(bit V

in MCR and interrupt registers), and

DDTEMP

overtemperature shutdown with hysteresis.

V2 REGULATOR

V2 Regulator circuitry is designed to drive an external path
transistor increasing output current flexibility. Two pins are
used to achieve the flexibility. Those pins are V2 and V2
control. The output voltage is 5.0 V and is realized by a
tracking function of the VDD1 regulator. The recommended
ballast transistor is MJD32C. Other transistors can be used;

however, depending upon the PNP gain an external resistor­capacitor network might be connected. The V2 is the supply
input for the CAN cell. The state of V2 is reported in the IOR
(bit V2LOW set to 1 if V2 is below 4.5 V typical).

HS1 VBAT SWITCH OUTPUT

The HS1 output is a 2.0 Ω typical switch from the VSUP
pin. It allows the supply of external switches and their
associated pull-up or pull down circuitry, in conjunction with
the wake-up input pins, for example. Output current is limited
to 200 mA and HS1 is protected against short-circuit and has
an overtemperature shutdown (bit HS1OT in IOR and bit
HS1OT-V2LOW in

INT register). The HS1 output is controlled
from the internal register and the SPI. Because of an internal
timer, it can be activated at regular intervals in Sleep and
Stop modes. It can also be permanently turned on in Normal
or Standby modes to drive loads or supply peripheral
components. No internal clamping protection circuit is
implemented, thus a dedicated external protection circuit is
required in case of inductive load drive.

BATTERY FALL EARLY WARNING

Refer to the discussion under the heading: Device Supply.

INTERNAL CLOCK

The device has an internal clock used to generate all
timings (Reset, Watchdog, Cyclic Wake-up, Filtering Time,
etc.). Two oscillators are implemented. A high accuracy

percent) used in Normal Request, Normal and Standby

(±12
modes, and a low accuracy (±30 percent) used in Sleep and
Stop modes.

OPERATIONAL MODES

FUNCTIONAL MODES

The device has four primary operation modes:

1. Standby mode

2. Normal mode

3. Stop mode

4. Sleep mode
All modes are controlled by the SPI. An additional

temporary mode called Normal Request mode is
automatically accessed by the device after reset or wake-up
from Stop mode. A Reset (

RST) mode is also implemented.
Special modes and configuration are possible for debug and
program MCU flash memory.

STANDBY MODE

Only regulator 1 is ON. Regulator 2 is turned OFF by
disabling the V2 control pin. Only the wake-up capability of
the CAN interface is available. Other functions available are

33989

20 Freescale Semiconductor

wake-up input reading through SPI and HS1 activation. The
Watchdog is running.

NORMAL MODE

In this mode both regulators are ON. This corresponds to
the normal application operation. All functions are available in
this mode (Watchdog, wake-up input reading through SPI,
HS1 activation, CAN communication). The software
Watchdog is running and must be periodically cleared
through SPI.

STOP MODE

Regulator 2 is turned OFF by disabling the V2 control pin.
The regulator 1 is activated in a special low power mode,
allowing to deliver few mA. The objective is to maintain the
MCU of the application supplied while it is turned into power
saving condition (i.e Stop or Wait modes). In Stop mode the
device supply current from V

Analog Integrated Circuit Device Data

is very low.

BAT