Freescale 33976 Technical Data

Freescale Semiconductor

Advance Information

Dual Gauge Driver with

Document Number: MC33976

Rev 4.0, 1/2007

Configurable Response Time

The 33976 is a single-packaged, Serial Peripheral Interface (SPI)
controlled, dual step motor gauge driver integrated circuit (IC). This
monolithic IC consists of four dual output H-Bridge coil drivers and the
associated control logic. Each pair of H-Bridge dri ve rs is used to
automatically control the speed, direction, and magnitude of current
through the two coils of a two-phase instrumentation step motor,
similar to an MMT-licensed AFIC

The 33976 is ideal for use in automotive instrumentation systems
requiring distributed and flexible step motor gauge driving. The
device also eases the transition to step motors from air core motors
by emulating the air core pointer movement with little additional
processor bandwidth utilization.

Features

•MMT-Licensed Two-Phase Step Motor Compatible

•Switec MS-X15.xxx Step Motor Compatible

•Minimal Processor Overhead Required

•Fully Integrated Pointer Movement and Position State Machine
with Channel-Independent Configurable Pointer Movement

•4096 Possible Steady State Pointer Positions

•340° Maximum Pointer Sweep

•Maximum Acceleration of 4500°/s2

•Maximum Pointer Velocity of 400°/s

•Analog Microstepping (12 Steps/Degree of Pointer Movement)

•Pointer Calibration and Return to Zero (RTZ)

•SPI-Controlled 16-Bit Word

•Calibratable Internal Clock

•Low Sleep Mode Current

•Pb-Free Packaging Designated by Suffix Code EG

6405 or Switec MS-X15.xxx motor.

33976

CONFIGURABLE DUAL GAUGE DRIVER

DW SUFFIX

EG SUFFIX (PB-FREE)

98ASB42344B
24-PIN SOICW

ORDERING INFORMATION

Device

MC33976DW/R2

MCZ33976EG/R2

Temperature

Range (T

- 40°C to 125°C 24 SOICW

)

A

Package

V

PWR

33976

V

5.0 V

Regulator

DD

MCU

Figure 1. 33976 Simplified Application Diagram

* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

VPWD

VDD

RTZ
RST
CS
SCLK
SI
SO

SIN0+

SIN0-

Motor 0

COS0+

COS0-

SIN1+

SIN1-

Motor 1

COS1+

COS1-

GND

INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VPWR

VDD

CS

SCLK

SO

RST

INTERNAL

REGULATOR

COS0

SPI

SI

LOGIC

STATE

MACHINE

UNDER

-

AND

OVERVOLTAGE

DETECT

ILIM

OVERTEMPERATURE

DETECT

SIGMA-DELTA

ADC

SIN0

COS1

H-BRIDGE

AND

CONTROL

SIN1

MULTIPLEXER

COS0+
COS0-

SIN0+
SIN0-

COS1+
COS1-

SIN1+
SIN1-

VDD

OSCILLATOR

AGND

GND (8)

RTZ

Figure 2. 33976 Simplified Internal Block Diagram

33976

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

PIN CONNECTIONS

COS0+

COS0-

SIN0+

SIN0-

GND
GND
GND
GND

SCLK

Figure 3. 33976 Pin Connections

Table 1. 33976 Pin Definitions

Pin

Number

1
2
3
4

5 – 8,

17–

20

9 CS Input Chip Select

10 SCLK Input Serial Clock

11 SO Output Serial Output

12 SI Input Serial Input

13 RTZ Output Multiplexed Output

14 VDD Input Voltage
15 RST Input Reset
16 VPWR Input Battery Voltage

21
22
23
24

Pin

Name

(MS Motor Pin #)

Pin

Function

Output H-Bridge Outputs 0

COS0+ (MS #4)
COS0

− (MS #3)
SIN0+(MS #1)
SIN0

− (MS #2)

GND Ground Ground

(MS Motor Pin #)

Output H-Bridge Outputs 1

SIN1− (MS #2)
SIN1+

(MS #1)

COS1

− (MS #3)

COS1+

(MS #4)

Formal Name Definition

CS

SO

1
2
3
4
5
6
7
8
9
10
11
12

SI

24

COS1+

23

COS1-

22

SIN1+

21

SIN1-

20

GND

19

GND

18

GND

17

GND

16

PWR

V

15

RST

14

VDD

13

RTZ

Each pin is the output pin of a half bridge, designed to source or sink
current.

These pins serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.

This pin is connected to a chip select output of a LSI IC.
This pin is connected to the SCLK pin of the master device and acts

as a bit clock for the SPI port.
This pin is connected to the SPI Serial Data Input pin of the master

device or to the SI pin of the next device in a daisy chain.
This pin is connected to the SPI Serial Data Output pin of the master

device from which it receives output command data.
This is a multiplexed output pin for the non-driven coil, during a Return

to Zero (RTZ) event.
This SPI and logic power supply input will work with 5.0 V supplies.
This input has an internal active pull-up.
Power supply.
Each of these pins is the output pin of a half bridge, designed to

source or sink current.

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating Symbol Value Unit

Power Supply Voltage

Steady State

Input Pin Voltage

SIN +/- COS +/- Continuous Per Output Current

(1)

(2)

Storage Temperature

Operating Junction Temperature

Thermal Resistance

Junction to Ambient
Junction to Lead

ESD Voltage

(3)

Human Body Model
Machine Model

Peak Package Reflow Temperature During Reflow

(4), (5)

V

PWR(SUS)

V

IN

I

OUTMAX

T

STG

T

R

θJA

R

θJL

V

ESD1

V

ESD2

T

PPRT

V

-0.3 to 41

-0.3 to 7.0 V

40 mA

-55 to 150 °C

J

-40 to 150 °C

°C/W
60
20

V

±2000

±200

Note 5

°C

Notes

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.

2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature will
require maximum output current computation using package thermal resistances.

3. ESD1 testing is performed in accordance with the Human Body Model (C
accordance with the Machine Model (C

= 200 pF, R

ZAP

ZAP

= 0 Ω).

= 100 pF, R

ZAP

= 1500 Ω), ESD2 testing is performed in

ZAP

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

33976

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, - 40°C ≤ T

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER INPUT

≤ 150°C, GND = 0 V unless otherwise noted.

J

Supply Voltage Range

Fully Operational
Limited Operational

V

Supply Current

PWR

(6), (7)

Gauge 1 and 2 Outputs ON, No Output Loads

V

Supply Current (All Outputs Disabled)

PWR

Reset = Logic [0], VDD = 5.0 V
Reset = Logic [0], VDD = 0 V

Overvoltage Detection Level

Undervoltage Detection Level

(8)

(9)

Logic Supply Voltage Range (5.0 V Nominal Supply)

Under VDD Logic Reset

VDD Supply Current

Sleep: Reset Logic [0]
Outputs Enabled

POWER OUTPUTS

Microstep Output (Measured Across Coil Outputs)
SIN0,1, ± (COS0,1, ±) (refer to Table 1)
R

= 200 Ω, PE6 = 0

OUT

Steps 6, 18 (0, 12)
Steps 5, 7, 17, 19 (1, 11, 13, 23)
Steps 4, 8, 16, 20 (2, 10, 14, 22)
Steps 3, 9, 15, 21 (3, 9, 15, 21)
Steps 2, 10, 14, 22 (4, 8,16, 20)
Steps 1, 11, 13, 23 (5, 7, 17, 19)
Steps 0, 12 (6, 18)

V

PWR

I

PWR(ON)

I

PWSLP1

I

PWRSLP2

V

PWROV

V

PWRUV

V

DD

V

DDUV

I

DD(OFF)

I

DD(ON)

V

ST6

V

ST5

V

ST4

V

ST3

V

ST2

V

ST1

V

ST0

6.5

4.0

–
–

26
26

– 4.0 6.0

–
–

42
15

60
25

26 32 38 V

5.0 5.6 6.2 V

4.5 5.0 5.5 V

– – 4.5 V

–
–

4.82

0.94 V

ST6

0.84 V

ST6

0.68 V

ST6

0.47 V

ST6

0.23 VST6

-0.1

40

1.0

5.3

0.97 V

0.87 V

0.71 V

0.50 V

0.26 V

65

1.8

6.0

ST6
ST6
ST6
ST6
ST6

0

1.0 V

0.96 V

0.8 V

0.57 V

0.31 V

0.1

ST6

ST6

ST6

ST6
ST6

V

mA

µA

µA

mA

V

Notes

6. Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reductio n in drive voltage may result in a
loss of position control.

7. The logic will reset at some level below the specified Limited Operational minimum.

8. Outputs will disable and must be re-enabled via the PECCR command.

9. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, - 40°C ≤ T

≤ 150°C, GND = 0 V unless otherwise noted.

J

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUTS (CONTINUED)

Full Step Active Output (Measured Across Coil Outputs)
SIN0, 1, ± (COS0, 1, ±) (see Figure 9, page 26)

Steps 1, 3 (0, 2)

Microstep, Full Step Output
(Measured from Coil Low Side to Ground)

SIN0, 1, ± (COS0, 1, ±), I

Output Flyback Clamp

(11)

OUT

= 30 mA

Output Current Limit (Output = Vst6)

Overtemperature Shutdown

Overtemperature Hysteresis

(10)

(11)

CONTROL I/O

Input Logic High Voltage

Input Logic Low Voltage

Input Logic Voltage Hysteresis

(12)

(12)

(10)

Input Logic Pull Down Current (SI, SCLK)

Input Logic Pull-Up Current (CS, RST)

SO High-State Output Voltage (IOH = 1.0 mA)

SO Low-State Output Voltage (IOL = -1.6 mA)

SO Tri-State Leakage Current (CS ≥ 3.5 V)

Input Capacitance

SO Tri-State Capacitance

(13)

(13)

V

FS

V

LS

V

FB

I

LIM

OT

OT

HYST

V

V

V

IN(HYST)

I

DWN

I

UP

V

SOH

V

SOL

I

SOLK

C

C

SO

V

4.9 5.3 6.0

V

0 0.1 0.3

– V

+ 0.5 V

ST6

+ 1.0 V

ST6

40 100 170 mA

SD

155 – 180 °C

8.0 – 16 °C

IH

IL

2.0 – – V

– – 0.8 V

– 100 – mV

3.0 – 20 µA

5.0 – 20 µA

0.8 V

DD

– – V

– 0.2 0.4 V

-5.0 0 5.0 µA

IN

– 4.0 12 pF

– – 20 pF

ANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT)

ADC Gain

(10), (14)

G

ADC

100 188 270 Counts/

V/ms

Notes

10. This parameter is guaranteed by design, but it is not production tested.

11. Not 100 percent tested.

12. VDD = 5.0 V.

13. Capacitance not measured. This parameter is guaranteed by design, but it is not production tested.

14. Reference RTZ Accumulator (Typical) on page 23

33976

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, - 40°C ≤ T

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Units

POWER OUTPUT AND CLOCK TIMINGS

≤ 150°C, GND = 0 V unless otherwise noted.

J

SIN0,1, ± (COS0,1, ±) Output Turn ON Delay Time
(Time from Rising CS Enabling

Outputs to Steady State Coil Voltages and Currents)

SIN0,1, ± (COS0,1, ±) Output Turn OFF Delay Time (Time from Rising CS
Disables Outputs to Steady State Coil Voltages and Currents)

(15)

(15)

Uncalibrated Oscillator Cycle Time

Calibrated Oscillator Cycle Time

Calibration Pulse = 8.0 µs, PECCR D4 = Logic [0]
Calibration Pulse = 8.0 µs, PECCR D4 = Logic [1]

Maximum Pointer Speed

Maximum Pointer Acceleration

(16)

(16)

t

DLY (ON)

t

DLY (OFF)

t

CLU

t

CLC

V

MAX

A

MAX

1.0

– –

– – 1.0

0.65 1.0 1.7 µs

1.0

0.9

1.1

1.0

1.2

1.1

– – 400 °/s

– – 4500 °/s

Notes

15. Maximum specified time for the 33976 is the minimum guaranteed time needed from the microcontroller.

16. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0

MHz. These are not 100 percent tested.

ms

ms

µs

2

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, - 40°C ≤ T

≤ 150°C, GND = 0 V unless otherwise noted.

J

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Units

SPI INTERFACE TIMING

(17)

Recommended Frequency of SPI Operation

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)

SI to Falling Edge of SCLK (Required Setup Time)

Required High State Duration of SCLK (Required Setup Time

Required Low State Duration of SCLK (Required Setup Time

Falling Edge of SCLK to SI (Required Hold Time)

(18)

(18)

(18)

(18)

SO Rise Time

CL = 200 pF

SO Fall Time

CL = 200 pF

SI, CS, SCLK, Incoming Signal Rise Time

SI, CS, SCLK, Incoming Signal Fall Time

(19)

(19)

Falling Edge of RST to Rising Edge of RST (Required Setup Time)

Rising Edge of CS to Falling Edge of CS (Required Setup Time)

(18), (20)

Rising Edge of RST to Falling Edge of CS (Required Setup Time)

Time from Falling Edge of CS to SO Low Impedance

Time from Rising Edge of CS to SO High Impedance

Time from Rising Edge of SCLK to SO Data Valid

0.2 V

≤ SO ≥ 0.8 VDD, CL = 200 pF

DD

(21)

(22)

(23)

(18)

(18)

(18)

(18)

t

t

t

SI

f

t

LEAD

t

LAG

t

S

SCLK

W

SCLK

W

(

HOLD)

t

R

SPI

ISU

H

L

SO

– 1.0 2.0 MHz

– 50 167 ns

– 50 167 ns

– 25 83 ns

– – 167 ns

– – 167 ns

– 25 83 ns

ns

– 25 50

t

SO

F

ns

– 25 50

t

SI

R

t

SI

F

t

RST

W

t

CS

t

EN

t

SO(EN)

t

SO(DIS)

t

VALID

– – 50 ns

– – 50 ns

– – 3.0 µs

– – 5.0 µs

– – 5.0 µs

– – 145 ns

– 1.3 4.0 µs

ns

– 90 150

Notes

17. The 33976 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device
shall be fully functional for slower clock speeds. Reference

Figure 4 and 5.

18. The maximum setup time specified for the 33976 is the minimum time needed from the microcontroller to guarantee correct operation.

19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

20. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.

21. Time required for output status data to be terminated at SO. 1.0 kΩ load on SO

22. Time required for output status data to be available for use at SO. 1.0 kΩ load on SO.

23. Time required to obtain valid data out from SO following the rise of SCLK.

33976

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

RST

CS

SCLK

SI

t

WRST

0.7 V

0.2 V

DD

0.2 V

DD

t

EN

0.7 V

t

LEAD

DD

DD

0.7 V

0.2 V

DD

TIMING DIAGRAMS

t

WSCLKH

t

LEAD

DD

t

WSCLKL

t

SI(HOLD)

t

RSI

ELECTRICAL CHARACTERISTICS

0.7 V

DD

t

LAG

t

FSI

TIMING DIAGRAMS

t

CS

Don’t CareValidValid Don’t CareDon’t Care

V

IN

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

SCLK

SO

Low-to-High

SO

High-to-Low

Figure 4. Input Timing Switching Characteristics

0.7 V

0.2 V

DD

t

FSI

1.0 V

DD

3.5 V

0.2 V

0.7 V

t

SO(EN)

DD

t

DD

t

SO(DIS)

t

RSI

VALID

50%

t

t

rSO

fSO

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

Figure 5. Valid Data Delay Time and Valid Time Waveforms

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

This 33976 is a single-packaged, Serial Peripheral
Interface (SPI) controlled, dual step motor gauge driver
integrated circuit (IC). This monolithic IC consists of four dual
output H-Bridge coil drivers and the associated control logic.
Each pair of H-Bridge drivers is used to automatically control
the speed, direction, and magnitude of current through the
two coils of a two-phase instrumentation step motor, similar

FUNCTIONAL PIN DESCRIPTION

H-BRIDGE OUTPUTS 0 (COS0+, COS0-, SIN0+,
SIN0-)

Each pin is the output pin of a half bridge, designed to
source or sink current. The H-Bridge pins linearly drive the
sine and cosine coils of two separate step motors to provide
four-quadrant operation.

GROUND (GND)

These pins serve as the ground for the source of the low­side output transistors as well as the logic portion of the
device. They also help dissipate heat from the device.

CHIP SELECT (CS)

The CS pin enables communication with the master
device. When this pin is in a logic [0] state, the 33976 is
capable of transferring information to, and receiving
information from, the master. The 33976 latches data in from
the Input Shift registers to the addressed registers on the
rising edge of

CS is logic [0]. When CS is logic high, signals at the

when
SCLK and SI pins are ignored and the SO pin is tri-stated
(high impedance).
state to a logic
internal pull-up (l
section of the Static Electrical Characteristics table entitled

CONTROL I/O, which is found on page 6.

CS. The output driver on the SO pin is enabled

CS will only be transitioned from a logic [1]

[0] state when SCLK is a logic [0]. CS has an

) connected to the pin, as specified in the

UP

to an MMT-licensed AFIC
motor.

The 33976 is ideal for use in automotive instrumentation
systems requiring distributed and flexible step motor gauge
driving. The device also eases the transition to step motors
from air core motors by emulating the air core pointer
movement with little additional processor bandwidth
utilization.

and SO is tri-stated (high impedance). Refer to the data
transfer timing diagrams in Figure 6 and Figure 7 on page 12.

6405 or a Switec MS-X15.xxx

SERIAL OUTPUT (SO)

The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted
out. Those bits are followed by the message bits clocked in
FIFO, when the device is in a daisy chain connection or being
sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
high impedance state until the
state.

CS pin is put into a logic low

SERIAL INPUT (SI)

The SI pin is the input of the SPI. Serial input information
is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, beginning with the most
significant bit (MSB). Messages that are not multiples of 16
bits (e.g., daisy chained device messages) are ignored. After
transmitting a 16-bit word, the
(logic [1]) before transmitting a new word. SI information is
ignored when

CS is in a logic high state.

CS pin must be de-asserted

MULTIPLEXED OUTPUT (RTZ)

This is a multiplexed output pin for the non-driven coil,
during a Return to Zero (RTZ) event.

SERIAL CLOCK (SCLK)

SCLK clocks the Internal Shift registers of the 33976
device. The SI pin accepts data into the Input Shift register on
the falling edge of the SCLK signal, while the Serial Output
pin (SO) shifts data information out of the SO Line Driver on
the rising edge of the SCLK signal. It is important that the
SCLK pin be in a logic [0] state whenever the
transition. SCLK has an internal pull down (l
specified in the section of the Static Electrical Characteristics
table entitled

CS is logic [1], signals at the SCLK and SI pins are ignored

33976

10 Freescale Semiconductor

CONTROL I/O, which is found on page 6. When

CS makes any

), as

DWN

VOLTAGE (VDD)

This SPI and logic power supply input will work with 5.0 V

supplies.

RESET (RST)

If the master decides to reset the device or place it into a

sleep state, the RST pin is driven to a logic

RST pin will force all internal logic to the known default

the
state. This input has an internal active pull-up.

Analog Integrated Circuit Device Data

[0]. A logic [0] on

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

BATTERY VOLTAGE (V

Power supply.

PWR

)

H-BRIDGE OUTPUTS 1 (SIN1-, SIN1+, COS1-,
COS1+)

Each of these pins is the output pin of a half bridge,
designed to source or sink current. The H-Bridge pins linearly
drive the sine and cosine coils of two separate step motors to
provide four-quadrant operation.

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

SPI PROTOCOL DESCRIPTION

The SPI interface has a full-duplex, three-wire
synchronous, 16-bit serial synchronous interface data
transfer and four I/O lines associated with it: Chip Select (
Serial Clock (SCLK), Serial Input (SI), and Serial Output

TIMING DESCRIPTION

This section provides a description of the 33976 SPI
behavior. To follow the explanations below, refer to Table 5
and to the timing diagrams shown in Figure 6 and Figure 7.

Table 5. Data Transfer Timing

Pin Description

CS),

(SO). The SI/SO pins of the 33976 follow a first in/first out
(D15/D0) protocol with both input and output words
transferring the most significant bit first. All inputs are
compatible with 5.0 V CMOS logic levels.

CS (1-to-0)
CS (0-to-1)

SO

SI

SO pin is enabled.
33976 configuration and desired output states are transferred and executed according to the data

in the Shift registers.
Will change state on the rising edge of the SCLK pin signal.
Will accept data on the falling edge of the SCLK pin signal.

CS

SCLK

SI

SO

Note SO is tri-stated when CS is logic [1].

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1

Output shift register is loaded here.

Figure 6. Single 16-Bit Word SPI Communication

CS

SCLK

D0

OD0

D0

SI

SO

1. SO is tri-stated when

Notes

2. D15, D14, D13, ..., and D0 refer to the first 16 bits of data into the 33976.

3. D15*, D14*, D13*, ..., and D0* refer to the most recent entry of program data into the 33976.

4. OD15, OD14, OD13, ..., and OD0 refer to the first 16 bits of fault and status data out of the 33976.

D15 D14 D13 D12 D11 D2 D1 D0 D15*D14*D13*D4 D3 D2*D1

OD15 OD14 OD13 OD12 OD11 OD2 OD1 OD0 D15 D14 D13 OD4 OD3 D2 D1

CS is logic [1].

*

*

D0

Figure 7. Multiple 16-Bit Word SPI Communication

33976

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DATA INPUT

The Input Shift register captures data at the falling edge of
the SCLK clock. The SCLK clock pulses exactly 16

times only
inside the transmission windows (CS in a logic [0] state). By
the time the CS signal goes to logic [1] again, the contents of
the Input Shift register are transferred to the appropriate
internal register addressed in bits 15:13. The minimum time

CS should be kept high depends on the internal clock speed,

specified in the SPI INTERFACE TIMING

(17)

section of the

Static Electrical Characteristics, found on page 6. It must be
long enough so the internal clock is able to capture the data

LOGIC COMMANDS AND REGISTERS

COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS

The 33976 device is capable of interfacing directly with a
microcontroller via the 16-bit SPI protocol specified below.
The device is controlled by the microprocessor and reports
back status information via the SPI. This section provides a
detailed description of all registers accessible via serial
interface. The various registers control the behavior of this
device.

A message is transmitted by the master beginning with the
MSB (D15) and ending with the LSB (D0). Multiple messages
can be transmitted in succession to accommodate those
applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of

bits. Data is transferred through daisy-chained devices, as

16
illustrated in Figure 7, page 12. If an attempt is made to latch
in a message smaller than 16 bits wide, it is ignored.

Table 6 lists the seven registers the 33976 uses to

configure the device, control the state of the four H-bridge
outputs, and determine the type of status information that is
clocked back to the master. The registers are addressed via
D15:D13 of the incoming SPI word.

Table 6. Module Memory Map

Address

[15:13]

000 Power, Enable, Calibration,

and Configuration Register
001 Maximum Velocity Register VELR Page 15
010 Gauge 0 Position Register POS0R Page 16
011 Gauge 1 Position Register POS1R Page 16
100 Return to 0 Register RTZR Page 16
101 Return to 0

110 Ramp Selection Register RMPSELR Page 19
111 Reserved for Test – –

Register Name See Page

Configuration

Register

PECCR Page 13

RTZCR Page 17

from the Input Shift register and transfer it to the internal
registers.

DATA OUTPUT

At the first rising edge of the SCLK clock, with CS at
logic [0], the contents of the selected Status Word register
are transferred to the Output Shift register. The first 16

bits
clocked out are the status bits. If data continues to clock in
before the

CS transitions to a logic [1], the device begins to

shift out the data previously clocked in FIFO after the CS first
transitioned to logic [0].

MODULE MEMORY MAP

Various registers of the 33976 SPI module are addressed
by the three MSBs of the 16-bit word received serially.
Functions to be controlled include:

• Individual gauge drive enabling

• Power-up/down

• Internal clock calibration

• Gauge pointer position and velocity

• Gauge pointer zeroing

• Air core motor movement emulation

• Status information

Status reporting includes:

• Individual gauge overtemperature condition

• Battery overvoltage

• Battery undervoltage

• Pointer zeroing status

• Internal clock status

• Confirmation of coil output changes that should result in
pointer movement

• Real time pointer position information

• Real time pointer velocity step information

• Pointer movement direction

• Command pointer position status

• RTZ accumulator value

REGISTER DESCRIPTIONS

The following section describes the registers, their

addresses, and their impact on device operation.

Address 000 — Power, Enable, Calibration, and
Configuration Register (PECCR)

The Power, Enable, Calibration, and Configuration
Register is illustrated in
33976 using this register allows the master to

independently enable or disable the output drivers of the

(1)
two-gauge controllers, (2)
(3)

disable the air core emulation, (4) select the direction of
the pointer movement during pointer positioning and zeroing,

configure the device for the desired status information to

(5)

Table 7, page 14. A write to the

calibrate the internal clock,

33976

Analog Integrated Circuit Device Data
Freescale Semiconductor 13