Freescale 33972 A Service Manual
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Freescale Semiconductor
Advance Information
Multiple Switch Detection
Interface with Suppressed
Wake-Up
Document Number: MC33972
Rev. 9.0, 4/2007
33972
33972A
The 33972 Multiple Switch Detection Interface with Suppressed
Wake-Up is designed to detect the closing and opening of up to 22
switch contacts. The switch status, either open or closed, is transferred
to the microprocessor unit (MCU) through a serial peripheral interface
(SPI). The device also features a 22-to-1 analog multiplexer for reading
inputs as analog. The analog input signal is buffered and provided on
the AMUX output pin for the MCU to read.
The 33972 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pullup or pulldown current as it monitors switch change
of state. The Sleep mode provides low quiescent current, which makes
the 33972 ideal for automotive and industrial products requiring low
sleep state currents.
Features
• Designed to Operate 5.5 V ≤ V
• Switch Input Voltage Range -14 V to V
PWR
≤ 26 V
PWR
, 40 V Max
• Interfaces Directly to MPU using 3.3 V / 5.0 V SPI Protocol
• Selectable Wake-Up on Change of State
• Selectable Wetting Current (16 mA or 2.0 mA)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• Typical Standby Current - V
100 µA and VDD = 20 µA
PWR =
• Active Interrupt (INT) on Change-of-Switch State
• Pb-Free Packaging Designated by Suffix Code EW
V
BAT
V
V
BAT
BAT
SP0
SP1
SP7
SG0
SG1
SG12
33972
VPWR
VDD
WAKE
SCLK
CS
SO
INT
AMUX
V
DD
SI
DETECTION INTERFACE
EW SUFFIX (Pb-FREE)
ORDERING INFORMATION
Device
MC33972DWB/R2
MCZ33972AEW/R2
V
Power Supply
LVI
Enable
Watchdog
Reset
MULTIPLE SWITCH
DWB SUFFIX
98ARH99137A
32-PIN SOICW
Temperature
Range (T
-40°C to 125°C 32 SOICWMC33972EW/R2
DD
MCU
MOSI
SCLK
CS
MISO
INT
AN0
)
A
Package
SG13
GND
Figure 1. 33972 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Device Switch Input Voltage Range
33972
33972A
-14 to 38 V
-14 to 40 V
DC
DC
Reference
Location
6
6
33972
Analog Integrated Circuit Device Data
2 Freescale Semiconductor
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
V
16.0
mA
16.0
mA
V
16.0
mA
16.0
mA
V
16.0
mA
V
16.0
mA
PWR
PWR
PWR
PWR
V
V
V
V
PWR
PWR
PWR
PWR
2.0
mA
2.0
mA
2.0
mA
2.0
mA
2.0
mA
2.0
mA
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
PWR
4.0 V
Ref
Comparator
4.0 V
Ref
Comparator
4.0 V
Ref
Comparator
4.0 V
Ref
Comparator
+
–
+
–
+
–
+
–
SP0
To
SPI
SP7
To
SPI
SG0
To
SPI
SG13
To
SPI
5.0 V
V
V
, VDD, 5.0 V
PWR
POR
Bandgap
Sleep PWR
Oscillator
and
Clock Control
Temperature
Monitor and
Control
5.0 V
WAKE Control
SPI Interface
and Control
INT Control
MUX Interface
V
+
–
DD
V
DD
INTERNAL BLOCK DIAGRAM
VPWR
VDD
GND
5.0 V
V
PWR
5.0 V
5.0 V
125 kΩ
V
DD
125 kΩ
V
DD
40 µA
Analog Mux
Output
WAKE
INT
CS
SCLK
SI
SO
AMUX
Figure 2. 33972 Simplified Internal Block Diagram
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
PIN CONNECTIONS
PIN CONNECTIONS
GND
SCLK
CS
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SO
VDD
AMUX
INT
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
Figure 3. 33972 Pin Connections
Table 2. 33972 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Formal Name Definition
1 GND Ground
2 SI SPI Slave In
3 SCLK Serial Clock
4 CS Chip Select
5 – 8
25
– 28
9 – 15,
18
– 24
SP0 – 3
SP4
– 7
SG0 – 6,
SG13
Programmable Switches
Switch-to-Ground Inputs
– 7
0
0
– 7
– 13
16 VPWR Battery Input
17 WAKE Wake-Up
29 INT Interrupt
30 AMUX Analog Multiplex Output
31 VDD Voltage Drain Supply
32 SO SPI Slave Out
Ground for logic, analog, and switch to battery inputs.
SPI control data input pin from MCU to 33972.
SPI control clock input pin.
SPI control chip select input pin from MCU to 33972. Logic [0} allows data to be
transferred in.
Programmable switch-to-battery or switch-to-ground input pins.
Switch-to-ground input pins.
Battery supply input pin. Pin requires external reverse battery protection.
Open drain wake-up output. Designed to control a power supply enable pin.
Open-drain output to MCU. Used to indicate input switch change of state.
Analog multiplex output.
3.3 / 5.0 V supply. Sets SPI communication level for SO driver.
Provides digital data from 33972 to MCU.
33972
Analog Integrated Circuit Device Data
4 Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
VDD Supply Voltage
CS, SI, SO, SCLK, INT, AMUX
(1)
WAKE
VPWR Supply Voltage
(1)
VPWR Supply Voltage at -40C
(1)
(1)
Switch Input Voltage Range
Frequency of SPI Operation (VDD = 5.0 V)
ESD Voltage
Human Body Model
(3)
(2)
Applies to all non-input pins
Machine Model
– -0.3 to 7.0
– -0.3 to 40 V
– -0.3 to 50 V
– -0.3 to 45 V
– -14 to 40 V
– 6.0 MHz
V
ESD
±2000
±2000
±200
Charge Device Model
Corner Pins
Interior Pins
750
500
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Case
Storage Temperature
Power Dissipation (TA = 25°C)
(4)
T
T
A
T
J
T
C
STG
P
D
- 40 to 125
- 40 to 150
- 40 to 125
- 55 to 150 °C
1.7 W
Thermal Resistance
Junction to Ambient
Junction to Lead
Peak Package Reflow Temperature During Reflow
(5), (6)
R
R
T
JA
θ
JL
θ
PPRT
74
25
Note 6.
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. ESD data available upon request.
3. ESD1 testing is performed in accordance with the Human Body Model (C
in accordance with the Machine Model (C
= 200 pF, R
ZAP
ZAP
= 0 Ω).
= 100 pF, R
ZAP
= 1500 Ω), and ESD2 testing is performed
ZAP
4. Maximum power dissipation at TJ = 150°C junction temperature with no heat sink used.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
V
°C
°C/W
°C
DC
DC
DC
DC
DC
V
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ V
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Supply Voltage
Supply Voltage Range Quasi-Functional
Fully Operational
Supply Voltage Range Quasi-Functional
Supply Current
All Switches Open, Normal Mode, Tri-State Disabled
Sleep State Supply Current
Scan Timer = 64 ms, Switches Open
Logic Supply Voltage
Logic Supply Current
All Switches Open, Normal Mode
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
SWITCH INPUT
Pulse Wetting Current Switch-to-Battery (Current Sink)
Pulse Wetting Current Switch-to-Ground (Current Source)
Sustain Current Switch-to-Battery Input (Current Sink)
Sustain Current Switch-to-Ground Input (Current Source)
Sustain Current Matching Between Channels on Switch-to-Ground I/Os
I
SUS(MAX)
I
-
I
SUS(MIN)
SUS(MIN)
X 100
(7)
(7)
≤ 5.25 V, 8.0 V ≤ V
DD
PWR
V
PWR (QF
V
PWR (FO
V
PWR (QF
I
PWR (ON
I
PWR (SS
V
DD
I
DD
I
DD(SS
I
PULSE
I
PULSE
I
SUSTAIN
I
SUSTAIN
I
MATCH
≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
)
)
)
)
)
)
5.5
8.0
26
– 2.0 4.0
40 70 100
3.1 – 5.25 V
– 0.25 0.5
– 10 20
12 15 18 mA
12 16 18 mA
1.8 2.0 2.2 mA
1.8 2.0 2.2 mA
– 2.0 4.0
= 13 V, TA = 25°C.
PWR
–
–
–
8.0
26
38/40
V
mA
µA
mA
µA
%
Input Offset Current When Selected as Analog
Input Offset Voltage When Selected as Analog
V
(SP&SGINPUTS)
to AMUX Output
Analog Operational Amplifier Output Voltage
Sink 250 µA
Analog Operational Amplifier Output Voltage
Source 250 µA
Switch Detection Threshold
33972 / 33972A
Switch Input Voltage Range
33972
33972A
Temperature Monitor
Temperature Monitor Hysteresis
(8), (9)
(9)
I
OFFSET
V
OFFSET
V
OL
V
OH
V
TH
V
T
LIM
T
LIM(HYS)
-2.0 1.4 2.0 µA
mV
-10 2.5 10
mV
– 10 30
V
V
- 0.1 – –
DD
V
3.70 4.0 4.3
IN
-14
-14
–
–
38
40
V
155 – 185 °C
5.0 10 15 °C
Notes
7. Device operational. Table parameters may be out of specification.
8. Thermal shutdown of 16 mA pullup and pulldown current sources only. 2.0 mA current source / sink and all other functions remain active.
9. This parameter is guaranteed by design but is not production tested.
33972
Analog Integrated Circuit Device Data
6 Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ V
≤ 5.25 V, 8.0 V ≤ V
DD
≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
PWR
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
Characteristic Symbol Min Typ Max Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds
SCLK, SI, Tri-State SO Input Current
0 V to VDD
CS Input Current
CS = V
DD
CS Pullup Current
CS = 0 V
SO High-State Output Voltage
I
SO (HIGH
= -200 µA
)
SO Low-State Output Voltage
I
SO (HIGH
= 1.6 mA
)
Input Capacitance on SCLK, SI, Tri-State SO
INT Internal Pullup Current
INT Voltage
INT = Open Circuit
INT Voltage
I
= 1.0 mA
INT
WAKE Internal Pullup Current
WAKE Voltage
WAKE = Open Circuit
WAKE Voltage
I
= 1.0 mA
WAKE
WAKE Voltage
Maximum Voltage Applied to WAKE Through External Pullup
Notes
10. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
11. This parameter is guaranteed by design but is not production tested.
(10)
(11)
V
INLOGIC
I
SCLK, ISI,
I
SO (TRI)
I
CS
0.8 – 2.2 V
-10 – 10
-10 – 10
I
CS
30 – 100
V
SO (HIGH
)
VDD - 0.8 – V
V
SO (LOW
)
– – 0.4
C
IN
– – 20 pF
– 15 40 100 µA
V
INT (HIGH)
VDD - 0.5 – V
V
INT (LOW)
– 0.2 0.4
I
WAKE (PU)
V
WAKE (HIGH)
20 40 100 µA
4.0 4.3 5.3
V
WAKE(LOW
)
– 0.2 0.4
V
WAKE(MAX
)
– – 40
= 13 V, TA = 25°C.
PWR
DD
DD
µA
µA
µA
V
V
V
V
V
V
V
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ V
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
Characteristic Symbol Min Typ Max Unit
SWITCH INPUT
Pulse Wetting Current Time
Interrupt Delay Time
Normal Mode
Sleep Mode Switch Scan Time
Calibrated Scan Timer Accuracy
Sleep Mode
Calibrated Interrupt Timer Accuracy
Sleep Mode
DIGITAL INTERFACE TIMING
Required Low-State Duration on V
V
≤ 0.2 V
PWR
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Falling Edge of SCLK
Required Setup Time
Falling Edge of SCLK to SI
Required Hold Time
SI, CS, SCLK Signal Rise Time
SI, CS, SCLK Signal Fall Time
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid
Notes
12. These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
13. This parameter is guaranteed by design but not production tested.
14. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
15. Time required for valid output status data to be available on SO pin.
16. Time required for output states data to be terminated at SO pin.
17. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
(12)
(14)
(14)
PWR
for Reset
(13)
(17)
≤ 5.25 V, 8.0 V ≤ V
DD
(15)
(16)
≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
PWR
t
PULSE (ON)
t
INT-DLY
15 16 20 ms
= 13 V, TA = 25°C.
PWR
– 5.0 16
t
SCAN
t
SCAN TIMER
100 200 300 µs
– – 10
t
INT TIMER
– – 10
t
RESET
– – 10
t
LEAD
100 – –
t
LAG
50 – –
t
SI (SU)
16 – –
t
SI (HOLD)
20 – –
t
R (SI)
t
F (SI)
t
SO (EN)
t
SO (DIS)
t
VALID
– 5.0 – ns
– 5.0 – ns
– – 55 ns
– – 55 ns
– 25 55 ns
µs
%
%
µs
ns
ns
ns
ns
33972
Analog Integrated Circuit Device Data
8 Freescale Semiconductor
TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VPWR
VDD
WAKE
INT
CS
CS
SCLK
SI
SO
t
SO(EN)
0.2 V
DD
0.7 V
0.2 V
t
LEAD
DD
DD
0.7 V
0.2 V
0.7 V
0.2 V
DD
DD
t
SI(SU)tSI(HOLD)
DD
MSB IN
DD
t
VALID
MSB OUT LSB OUT
t
LAG
t
SO(DIS)
Figure 4. SPI Timing Characteristics
Wake-Up From Interrupt
Timer Expire
SGn
Power-Up
Normal Mode
.
INT
CS
SGn
SGn Bit in SPI Word
Tri-State
Command
(Disable
Tri-State)
Command
Sleep Sleep Mode Normal
Command
Figure 5. Sleep Mode to Normal Mode Operation
Latch switch status
on falling edge of CS
Switch
Status
Switch
Status
Command
Figure 6. Normal Mode Interrupt Operation
Mode
Switch
Status
Command
Sleep Command
Switch state change with
CS LOW generates INT
Rising edge of CS does not
clear
INT because state change
occurred while CS
Switch closed “1”
1001
Switch
Status
Command
Sleep Mode
was LOW
Wake-Up From
Closed Switch
Normal
Mode
1
Switch
Status
Command
Sleep Command
Switch state change with
CS LOW generates INT
Switch open “0”
0
Switch
Status
Command
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
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