Freescale 33970 Technical Data

Freescale Semiconductor

Advance Information

Dual Gauge Driver Integrated

Document Number: MC33970

Rev. 3.0, 1/2007

Circuit with Improved Damping
Algorithms

This 33970 is a single-packaged, Serial Peripheral Interface (SPI)
controlled, dual step motor gauge driver integrated circuit (IC). This
monolithic IC consists of four dual output H-Bridge coil drivers and the
associated control logic. Each pair of H-Bridge dri ve rs is used to
automatically control the speed, direction, and magnitude of current
through the two coils of a two-phase instrumentation step motor,
similar to an MMT-licensed AFIC

The 33970 is ideal for use in automotive instrumentation systems
requiring distributed and flexible step motor gauge driving. The
device also eases the transition to step motors from air core motors
by emulating the air core pointer movement with little additional
processor bandwidth utilization.

Features

• MMT-Licensed Two-Phase Step Motor Compatible

• Minimal Processor Overhead Required

• Fully Integrated Pointer Movement and Position State Machine
with Air Core Movement Emulation

• 4096 Possible Steady State Pointer Positions

• 340° Maximum Pointer Sweep

• Fixed Maximum Acceleration and Deceleration of 4500°/s2

• Maximum Pointer Velocity of 400°/s

• Analog Microstepping (12 Steps/Degree of Pointer Movement)

• Pointer Calibration and Return to Zero

• SPI-Controlled 16-Bit Word

• Calibratable Internal Clock

• Low Sleep Mode Current

• Backward Compatible with MC33991

• Improved Pointer Movement, Diagnostics, and Return to Zero (RTZ)

• Pb-Free Packaging Designated by Suffix Code EG

6405.

IMPROVED GAUGE DRIVER

ORDERING INFORMATION

Device

MC33970DW/R2

MCZ33970EG/R2

33970

INTEGRATED CIRCUIT

DW SUFFIX

EG SUFFIX (Pb-FREE)

98ASB42344B
24-PIN SOICW

Temperature

Range (T

-40°C to 125°C 24 SOICW

)

A

Package

V

PWR

33970

V

5.0 V

Regulator

DD

MCU

Figure 1. 33970 Simplified Application Diagram

* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

VPWR

VDD

RTZ
RST
CS
SCLK
SI
SO

SIN0+

SIN0-

Motor 0

COS0+

COS0-

SIN1+

SIN1-

Motor 1

COS1+

COS1-

GND

INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VPWR

VDD

CS

SCLK

SO

RST

INTERNAL

REGULATOR

COS0

SPI

SI

LOGIC

STATE

MACHINE

UNDER

-

AND

OVERVOLTAGE

DETECT

ILIM

OVERTEMPERATURE

DETECT

SIGMA-DELTA

ADC

SIN0

COS1

H-BRIDGE

AND

CONTROL

SIN1

MULTIPLEXER

COS0+
COS0-

SIN0+
SIN0-

COS1+
COS1-

SIN1+
SIN1-

VDD

OSCILLATOR

AGND

GND (8)

RTZ

Figure 2. 33970 Simplified Internal Block Diagram

33970

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

PIN CONNECTIONS

COS0+

COS0-

SIN0+

SIN0-

GND
GND
GND
GND

CS

SCLK

SO

1
2
3
4
5
6
7
8
9
10
11

SI

12

24
23
22
21
20
19
18
17
16
15
14
13

COS1+
COS1­SIN1+
SIN1­GND
GND
GND
GND
VPWR
RST
VDD
RTZ

Figure 3. 33970 Pin Connections

Table 1. 33970 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.

Pin Number Pin Name Pin Function Formal Name Definition

1
2
3
4

5 – 8,

17–

20

9 CS Input Chip Select

10 SCLK Input Serial Clock

11 SO Output Serial Output

12 SI Input Serial Input

13 RTZ Output Multiplexed Output

14 VDD Input Voltage
15 RST Input Reset
16 VPWR Input Battery Voltage
21

22
23
24

COS0+
COS0−

SIN0+
SIN0−

GND Ground Ground

SIN1−

SIN1+
COS1−
COS1+

Output H-Bridge Outputs 0

Output H-Bridge Outputs 1

Each pin is the output pin of a half bridge, designed to source or sink
current.

These pins serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.

This pin is connected to a chip select output of a LSI IC.
This pin is connected to the SCLK pin of the master device and acts as a

bit clock for the SPI port.
This pin is connected to the SPI Serial Data Input pin of the master

device, or to the SI pin of the next device in a daisy chain.
This pin is connected to the SPI Serial Data Output pin of the master

device from which it receives output command data.
This is a multiplexed output pin, for the non-driven coil, during a Return to

Zero (RTZ) event.
This SPI and logic power supply input will work with 5.0 V supplies.
This input has an internal active pull-up.
Power supply.
Each of these pins are the output pin of a half bridge, designed to source

or sink current.

33970

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage

Steady State
Input Pin Voltage
SIN +/- COS +/- Continuous Per Output Current
ESD Voltage

(1)

(2)

(3)

Human Body Model

Machine Model

THERMAL RATINGS

Storage Temperature
Operating Junction Temperature
Thermal Resistance

Junction to Ambient

Junction to Lead

THERMAL RESISTANCE

Peak Package Reflow Temperature During Reflow

(4), (5)

Notes

1. Exceeding voltage limits on Input pins may cause permanent damage to the device.

2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature
will require maximum output current computation using package thermal resistances.

3. ESD1 testing is performed in accordance with the Human Body Model (C
accordance with the Machine Model (C

= 200 pF, R

ZAP

ZAP

= 0 Ω).

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

V

PWR(SUS)

I

OUTMAX

= 100 pF, R

ZAP

V
V

T

R
R

T

V

IN

ESD1
ESD2

STG

T

J

JA

θ

JL

θ

PPRT

-0.3 to 41

-0.3 to 7.0 V
40 mA

±2000

±200

-55 to 150 °C

-40 to 150 °C

°C/W
60
20

Note 5

= 1500 Ω), ESD2 testing is performed in

ZAP

V

V

°C

33970

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TA < 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

POWER INPUT

Supply Voltage Range

Fully Operational
Limited Operational

VPWR Supply Current

Gauge 1 and 2 Outputs ON, No Output Loads

VPWR Supply Current (All Outputs Disabled)

Reset = Logic [0], VDD = 5.0 V
Reset = Logic [0], VDD = 0 V

Overvoltage Detection Level
Undervoltage Detection Level
Logic Supply Voltage Range (5.0 V Nominal Supply)
Under VDD Logic Reset
VDD Supply Current

Sleep: Reset Logic [0]
Outputs Enabled

POWER OUTPUTS

Microstep Output (Measured Across Coil Outputs)
SIN0,1, ± (COS0,1, ±) (refer to Table 1)

R

= 200 Ω

OUT

Steps 6, 18 (0, 12)
Steps 5, 7, 17, 19 (1, 11, 13, 23)
Steps 4, 8, 16, 20 (2, 10, 14, 22)
Steps 3, 9, 15, 21 (3, 9, 15, 21)
Steps 2, 10, 14, 22 (4, 8,16, 20)
Steps 1, 11, 13, 23 (5, 7, 17, 19)
Steps 0, 12 (6, 18)

Full Step Active Output (Measured Across Coil Outputs)
SIN0, 1, ± (COS0, 1, ±) (see Figure 9, page 23)

Steps 1, 3 (0, 2)

Microstep, Full Step Output (Measured from Coil Low Side to Ground)
SIN0, 1, ± (COS0, 1, ±), I

Notes

6. Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reduction in drive voltage may result in a
loss of position control.

7. The logic will reset at some level below the specified Limited Operational minimum.

8. Outputs will disable and must be re-enabled via the PECCR command.

9. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.

(6), (7)

OUT

(8)

(9)

= 30 mA

= 25°C under nominal conditions unless otherwise noted.

A

V

PWR

I

PWR(ON)

6.5

4.0

–
–

26
26

– 4.0 6.0

I

PWSLP1

I

PWRSLP2

V

PWROV

V

PWRUV

V

DD

V

DDUV

I

DD(OFF)

I

DD(ON)

V

ST6

V

ST5

V

ST4

V

ST3

V

ST2

V

ST1

V

ST0

V

FS

–
–

42
15

60
25

26 32 38 V

5.0 5.6 6.2 V

4.5 5.0 5.5 V
– – 4.5 V

4.82

0.94 V

0.84 V

0.68 V

0.47 V

0.23 V

-0.1

–
–

ST6
ST6
ST6
ST6
ST6

40

1.0

5.3

0.97 V

0.87 V

0.71 V

0.50 V

0.26 V

0.0

ST6
ST6
ST6
ST6
ST6

65

1.8

6.0

1.0 V

0.96 V

0.8 V

0.57 V

0.31 V

0.1

ST6

ST6

ST6

ST6
ST6

4.9 5.3 6.0

V

LS

0.0 0.1 0.3

V

mA

µA

µA

mA

V

V

V

33970

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TA < 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

POWER OUTPUTS (continued)

Output Flyback Clamp
Output Current Limit (Output = VST6)
Overtemperature Shutdown
Overtemperature Hysteresis

CONTROL I/O

Input Logic High Voltage
Input Logic Low Voltage
Input Logic Voltage Hysteresis
Input Logic Pull Down Current (SI, SCLK)
Input Logic Pull-Up Current (CS, RST)
SO High-State Output Voltage (IOH = 1.0 mA)
SO Low-State Output Voltage (IOL = -1.6 mA)
SO Tri-State Leakage Current (CS ≥ 3.5 V)
Input Capacitance
SO Tri-State Capacitance

ANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT)

ADC Gain

(10), (13)

Notes

10. This parameter is guaranteed by design; however, it is not production tested.

11. VDD = 5.0 V.

12. Capacitance not measured. This parameter is guaranteed by design; however, it is not production tested.

13. Reference Figure 8, RTZ Accumulator (Typical)

(10)

(10)

(10)

(11)

(11)

(10)

(12)

(12)

= 25°C under nominal conditions unless otherwise noted.

A

V

FB

I

LIM

OT

OT

HYST

V

IH

V

IL

V

IN(HYST)

I

DWN

I

UP

V

SOH

V

SOL

I

SOLK

C

IN

C

SO

G

ADC

SD

– V

+ 0.5 V

ST6

+ 1.0 V

ST6

40 100 170 mA

155 – 180 °C

8.0 – 16 °C

2.0 – – V
– – 0.8 V
– 100 – mV

3.0 – 20 µA

5.0 – 20 µA

0.8 V

DD

– – V

– 0.2 0.4 V

-5.0 0 5.0 µA
– 4.0 12 pF
– – 20 pF

100 188 270 Counts/V/

ms

33970

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TA < 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT AND CLOCK TIMINGS

SIN, COS Output Turn ON Delay Time (Time from Rising CS Enabling
Outputs to Steady State Coil Voltages and Currents)

SIN, COS Output Turn OFF Delay Time (Time from Rising CS Disables
Outputs to Steady State Coil Voltages and Currents)

(14)

(14)

Uncalibrated Oscillator Cycle Time
Calibrated Oscillator Cycle Time

Cal Pulse = 8.0 µs, PECCR D4 = Logic [0]

Cal pulse = 8.0 µs, PECCR D4 = Logic [1]
Maximum Pointer Speed
Maximum Pointer Acceleration

SPI INTERFACE TIMING

(15)

(15)

(16)

Recommended Frequency of SPI Operation
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)

(17)

Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)

(17)

(17)

(17)

(17)

(17)

SO Rise Time

CL = 200 pF
SO Fall Time

CL = 200 pF
SI, CS, SCLK, Incoming Signal Rise Time

SI, CS, SCLK, Incoming Signal Fall Time
Falling Edge of RST to Rising Edge of RST (Required Setup Time)
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)

(18)

(18)

(17)

(17), (19)

(17)

Notes

14. Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.

15. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0

MHz. These are not 100 percent tested.

16. The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature
range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall
be fully functional for slower clock speeds. See

Figure 4 and 5.

17. The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.

18. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

19. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes

t

DLY (ON)

t

DLY (OFF)

t

CLU

t

CLC

V

MAX

A

MAX

f

SPI

t

LEAD

t

LAG

t

S

ISU

t

WSCLKH

t

WSCLKL

t

SI

(HOLD)

t

R

SO

t

F

SO

t

RSI

t

F

SI

t

W

RST

t

CS

t

EN

ms

– – 1.0

ms

– – 1.0

0.65 1.0 1.7 µs
µs

1.0

0.9

1.1

1.0

1.2

1.1
– – 400 °/s
– – 4500 °/s

– 1.0 3.0 MHz
– 50 167 ns
– 50 167 ns
– 25 83 ns
– – 167 ns
– – 167 ns
– 25 83 ns

ns

– 25 50

ns

– 25 50
– – 50 ns

– – 50 ns
– – 3.0 µs
– – 5.0 µs
– – 5.0 µs

2

33970

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TA < 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

(22)

(20)

(21)

t

SO(EN)

t

SO(DIS)

t

VALID

– – 145 ns
– 1.3 4.0 µs

– 65 105

Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid

0.2 V

≤ SO ≥ 0.8 VDD, CL = 200 pF

DD

Notes

20. Time required for output status data to be terminated at SO. 1.0 kΩ load on SO

21. Time required for output status data to be available for use at SO. 1.0 kΩ load on SO.

22. Time required to obtain valid data out from SO following the rise of SCLK.

ns

33970

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

RST

CS

SCLK

SI

t

WRST

0.7 V

0.2 V

DD

0.2 V

DD

t

EN

0.7 V

t

LEAD

DD

DD

0.7 V

0.2 V

DD

DD

TIMING DIAGRAMS

t

WSCLKh

t

LEAD

t

WSCLKl

t

SI(HOLD)

ELECTRICAL CHARACTERISTICS

0.7 V

DD

t

RSI

t

FSI

t

LAG

TIMING DIAGRAMS

t

CS

V

IN

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

Don’t CareValidValid Don’t CareDon’t Care

V

IL

SCLK

SO

Low-to-High

SO

High-to-Low

Figure 4. Input Timing Switching Characteristics

0.7 V

0.2 V

DD

t

FSI

1.0 V

DD

3.5 V

0.2 V

0.7 V

t

SO(EN)

DD

t

DD

t

SO(DIS)

t

RSI

VALID

50%

t

RSO

t

FSO

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

Figure 5. Valid Data Delay Time and Valid Time Waveforms

33970

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

This 33970 is a single-packaged, Serial Peripheral
Interface (SPI) controlled, dual step motor gauge driver
integrated circuit (IC). This monolithic IC consists of four dual
output H-Bridge coil drivers and the associated control logic.
Each pair of H-Bridge drivers is used to automatically control
the speed, direction, and magnitude of current through the
two coils of a two-phase instrumentation step motor, similar
to an MMT-licensed AFIC

6405.

FUNCTIONAL PIN DESCRIPTION

H-Bridge Outputs 0 (COS0+, COS0-, SIN0+, SIN0-)

Each pin is the output pin of a half bridge, designed to
source or sink current. The H-Bridge pins linearly drive the
sine and cosine coils of two separate step motors to provide
four-quadrant operation.

GROUND (GND)

These pins serve as the ground for the source of the low­side output transistors as well as the logic portion of the
device. They also help dissipate heat from the device.

CHIP SELECT (CS)

The CS pin enables communication with the master
device. When this pin is in a logic [0] state, the 33970 is
capable of transferring information to, and receiving
information from, the master. The 33970 latches data in from
the Input Shift registers to the addressed registers on the
rising edge of
when CS is logic [0]. When CS is logic high, signals at the
SCLK and SI pins are ignored and the SO pin is tri-stated
(high impedance).
state to a logic
internal pull-up (lUP) connected to the pin, as specified in the
section of the Static Electrical Characteristics table entitled

CONTROL I/O, which is found on page 6.

CS. The output driver on the SO pin is enabled

CS will only be transitioned from a logic [1]

[0] state when SCLK is a logic [0]. CS has an

SERIAL CLOCK (SCLK)

SCLK clocks the Internal Shift registers of the 33970
device. The Serial Input (SI) pin accepts data into the Input
Shift register on the falling edge of the SCLK signal, while the
Serial Output pin (SO) shifts data information out of the SO
Line Driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic [0] state whenever

CS makes any transition. SCLK has an internal pull down

the

), as specified in the section of the Static Electrical

(l

DWN

Characteristics table entitled
on page 6. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high impedance). Refer
to the data transfer timing diagrams in
on page 12.

CONTROL I/O, which is found

Figure 6 and Figure 7

The 33970 is ideal for use in automotive instrumentation
systems requiring distributed and flexible step motor gauge
driving. The device also eases the transition to step motors
from air core motors by emulating the air core pointer
movement with little additional processor bandwidth
utilization.

SERIAL OUTPUT (SO)

The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted
out. Those bits are followed by the message bits clocked in
FIFO, when the device is in a daisy chain connection or being
sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
high impedance state until the
state.

CS pin is put into a logic low

SERIAL INPUT (SI)

The SI pin is the input of the Serial Peripheral Interface
(SPI). Serial Input (SI) information is read on the falling edge
of SCLK. A 16-bit stream of serial data is required on the SI
pin, beginning with the most significant bit (MSB). Messages
that are not multiples of 16 bits (e.g., daisy chained device
messages) are ignored. After transmitting a 16-bit word, the

CS pin must be de-asserted (logic [1]) before transmitting a

new word. SI information is ignored when CS is in a logic high
state.

Multiplexed Output (RTZ)

This is a multiplexed output pin, for the non-driven coil,
during a Return to Zero (RTZ) event.

Voltage (VDD)

This SPI and logic power supply input will work with 5.0 V
supplies.

RESET (RST)

If the master decides to reset the device, or place it into a
sleep state, the

RST pin will force all internal logic to the known default

the
state. This input has an internal active pull-up.

RST pin is driven to a logic [0]. A logic [0] on

BATTERY VOLTAGE (VPWR)

Power supply.

33970

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

H-BRIDGE OUTPUTS 1 (SIN1-, SIN1+, COS1-,
COS1+)

Each of this pins is the output pin of a half bridge, designed

to source or sink current. The H-Bridge pins linearly drive the

sine and cosine coils of two separate step motors to provide
four-quadrant operation.

33970

Analog Integrated Circuit Device Data
Freescale Semiconductor 11