Freescale 33889 Technical Data

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Freescale Semiconductor

Technical Data

System Basis Chip with Low

Document Number: MC33889

Rev. 12.0, 3/2007

Speed Fault Tolerant CAN
Interface

An SBC device is a monolithic IC combining many functions
repeatedly found in standard microcontroller-based systems, e.g.,
protection, diagnostics, communication, power, etc. The 33889 is an
SBC having fully protected, fixed 5.0
current limit, over-temperature pre-warning and reset.

An output drive with sense input is also provided to implement a
second 5.0

V regulator using an external PNP. The 33889 has Normal,
Standby, Stop and Sleep modes; an internally switched high-side
power supply output with two wake-up inputs; programmable timeout
or window watchdog, Interrupt, Reset, SPI input control, and a low­speed fault tolerant CAN transceiver, compatible with CAN 2.0 A and
B protocols for module-to-module communications. The combination
is an economical solution for power management, high-speed
communication, and control in MCU-based systems.

Features

• VDD1: 5.0 V low drop voltage regulator, current limitation,

overtemperature detection, monitoring and reset function with total
current capability 200

mA

•V2: tracking function of VDD1 regulator; control circuitry for external

bipolar ballast transistor for high flexibility in choice of peripheral
voltage and current supply

• Four operational modes

• Low standby current consumption in Stop and Sleep modes

• Built-in low speed 125 kbps fault tolerant CAN physical interface.

• External high voltage wake-up input, associated with HS1 VBAT

switch

•150 mA output current capability for HS1 VBAT switch allowing

drive of external switches pull-up resistors or relays

• Pb-Free Packaging Designated by Suffix Code EG

V low drop-out regulator, with

33889

SYSTEM BASIS CHIP

DW SUFFIX

EG SUFFIX (PB-FREE)

PLASTIC PACKAGE

98ASB42345B
28-PIN SOICW

ORDERING INFORMATION

Device

MC33889BDW/R2

MCZ33889BEG/R2

MC33889DDW/R2

*MCZ33889DEG/R2

*Recommended for new designs

Temperature

Range (T

-40°C to 125°C 28 SOICW

)

A

Package

V

PWR

33889

VDD1

GND

RST
INT

CS
SCLK
MOSI
MISO

TXD
RXD

MCU

SCLK
MOSI
MISO

5.0 V

CS

SPI

Figure 1. 33889 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

VSUP

V2CTRL

V2

HS1

WDOG

RTH

CANH

CANL

RTL

L0

Wake-Up Inputs

L1

Local Module Supply

Safe Circuits

Twisted

Pair

V

CAN Bus

2

DEVICE VARIATIONS

DEVICE VARIATIONS

Table 1. Device Variations Between the 33889D and 33889B Versions

(1)

Device Part Number

Parameters Symbol Trait

Differential Receiver, Recessive To Dominant Threshold
(By Definition, V

DIFF

= V

CANH-VCANL

)

V

DIFF1

MC33889B

Min 3.2 V 3.5 V

Typ 2.6 V 3.0 V

(2)

MC33889D

Max 2.1 V 2.5 V

Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)

V

DIFF2

Min 3.2 V 3.5 V

Typ 2.6 V 3.0 V

Max 2.1 V 2.5 V

CANH Output Current (V

= 0; TX = 0.0)

CANH

I

CANH

Min 50 mA 50 mA

Typ 75 mA 100 mA

Max 110 mA 130 mA

CANL Output Current (V

= 14 V; TX = 0.0)

CANL

I

CANL

Min 50 mA 50 mA

Typ 90 mA 140 mA

Max 135 mA 170 mA

Detection threshold for Short circuit to Battery voltage

loop time Tx to Rx, no bus failure, ISO configuration

loop time Tx to Rx, with bus failure, ISO configuration

loop time Tx to Rx, with bus failure and +-1.5V gnd shift,
5

node network, ISO configuration

Minimum Dominant time for Wake up on CANL or CANH
(Tem Vbat mode)

Vcanh max Vsup/2 + 5V Vsup/2 + 4.55V

tLOOPRD max N/A 1.5us

tLOOPRD-F max N/A 1.9us

tLOOPRD/DR-F+GS N/A 3.6us

tWAKE min N/A 8

typ 30 16

max N/A 30

T2SPI timing

T2spi min not specified, 25us

25us

spec applied

DEVICE BEHAVIOR

CANH or CANL open wire recovery principle

Rx behavior in TermVbat mode

Reference MC33889B: on page

33

after 4 non

consecutive pulses

after 4 consecutive

pulses

Reference MC33889D: on page 34Rx recessive, no pulse Rx recessive, dominant

pulse to signal bus

traffic

Notes

1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B).

2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated
onto individual lines.

(2)

33889

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

INTERNAL BLOCK DIAGRAM

33889 Internal Block Diagram

INTERNAL BLOCK DIAGRAM

VSUP

HS1

L0

L1

CS

SCLK

MOSI

MISO

GND

HS1 Control

Programmable

Wake-Up Inputs

SPI

Interface

Dual Voltage Regulator

V

Voltage Monitor

SUP

V

Voltage Monitor

DD1

Mode Control

Fault Tolerant

V

SUP

V

2

Oscillator

Interrupt

Watchdog

Reset

CAN

Transceiver

V2CTRL

V2

VDD1

INT

WDOG

RST

TX

RX

RTH

CAN H

CAN L

RTL

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

PIN CONNECTIONS

PIN CONNECTIONS

RX

TX

VDD1

RST

INT
GND
GND
GND
GND

V2CTRL

VSUP

HS1

L0
L1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

WDOG

27

CS

26

MOSI

25

MISO

24

SCLK

23

GND

22

GND

21

GND

20

GND

19

CANL

18

CANH

17

RTL

16

RTH

15

V2

Figure 2. 33889 Pin Connections

Table 2. Pin Definitions

A functional description of each pin can be found in the Functional pin description section page 24.

Pin Pin Name

1

RX

2 TX Input Transmitter Data

3

VDD1

4 RST Output Reset

Pin

Function

Formal Name Definition

Output Receiver Data

Power

Voltage Regulator One

Output

CAN bus receive data output pin

CAN bus receive data input pin

5.0 V pin is a 2% low drop voltage regulator for to the microcontroller
supply.

This is the device reset output pin whose main function is to reset the
MCU.

5 INT Output Interrupt

This output is asserted LOW when an enabled interrupt condition
occurs.

6 -9,

GND Ground Ground

20 - 23

10 V2CTRL Output Voltage Source 2 Control

These device ground pins are internally connected to the package lead
frame to provide a 33889-to-PCB thermal path.

Output drive source for the V2 regulator connected to the external series
pass transistor.

11 VSUP Power

Voltage Supply

Supply input pin.

Input

12 HS1 Output High-Side Output

13 - 14

L0, L1

Input Level 0 - 1 Inputs

15 V2 Input Voltage Regulator Two

Output of the internal high-side switch.

Inputs from external switches or from logic circuitry.

5.0 V pin is a low drop voltage regulator dedicated to the peripherals
supply.

16 RTH Output RTH

17 RTL Output RTL

18

CANH

Output CAN High

19 CANL Output CAN Low

24

SCLK

Input System Clock

Pin for connection of the bus termination resistor to CANH.

Pin for connection of the bus termination resistor to CANL.

CAN high output pin.

CAN low output pin.

Clock input pin for the Serial Peripheral Interface (SPI).

33889

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

Table 2. Pin Definitions (continued)

A functional description of each pin can be found in the Functional pin description section page 24.

PIN CONNECTIONS

Pin Pin Name

Pin

Function

Formal Name Definition

25 MISO Output Master In/Slave Out

26 MOSI Input Master Out/Slave In

27 CS Input Chip Select

28 WDOG Output Watchdog

SPI data sent to the MCU by the 33889. When CS
is in the high impedance state.

is HIGH, the pin

LOW

SPI data received by the 33889.

The CS
the CS
bus.

input pin is used with the SPI bus to select the 33889. When

LOW

is asserted LOW, the 33889 is the selected device of the SPI

LOW

The WDOG output pin is asserted LOW if the software watchdog is not
correctly triggered.

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Max Unit

ELECTRICAL RATINGS

Supply Voltage at VSUP

Continuous voltage
Transient voltage (Load dump)

Logic Signals
(RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT)

Output current VDD1

HS1

Voltage
Output Current

L0, L1

DC Input voltage
DC Input current
Transient input voltage (according to ISO7637 specification) and with

external component per

Figure 3.

DC voltage at V2 (V2INT) V

DC Voltage On Pins CANH, CANL V

Transient Voltage At Pins CANH, CANL

0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms

V

Transient Voltage On Pins CANH, CANL

(Coupled Through 1.0 nF Capacitor)

V

SUP

-0.3 to 27

40

V

LOG

-0.3 to V

+0.3 V

DD1

I Internally Limited mA

V

I

V

WU

I

WU

V

TRWU

2INT

BUS

CANH/VCANL

V

TR

-0.2 to V

SUP

+0.3

Internally Limited

-0.3 to 40

-2.0 to 2.0

+-100

0 to 5.25 V

-20 to +27 V

-40 to +40 V

-150 to +100 V

V

V

A

V

mA

V

DC Voltage On Pins RTH, RTL V

Transient Voltage At Pins RTH, RTL

0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms

, V

RTL

V

RTH/VRTL

RTH

-0.3 to +27V V

-0.3 to +40 V

33889

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Max Unit

ESD voltage (HBM 100 pF, 1.5 k)

CANL, CANH, HS1, L0, L1
RTH, RTL
All other pins

ESD voltage (Machine Model) All pins, MC33889B

ESD voltage (CDM) All pins, MC33889D

Pins 1,14,15, & 28
All other pins

RTH, RTL Termination Resistance R

(3)

V

ESDH

±4.0

±3.0

±2.0

(3) (4)

(4)

V

ESD-MM

V

ESD-CDM

±200 V

750

500

T

500 to 16000 ohms

THERMAL RATINGS

Junction Temperature

Storage Temperature

Ambient Temperature (for info only)

Thermal resistance junction to gnd pin

T

J

T

S

T

A

(5)

R

THJ/P

-40 to 150

-55 to 165

-40 to 125

20

Notes:

3. Testing done in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), Machine Model (CZAP=200 pF, RZAP=0 ).

4. ESD machine model (MM) is for MC33889B only. MM is now replaced by CDM (Charged Discharged model).

5. Gnd pins 6,7,8,9,20, 21, 22, 23.

kV

V

°C

°C

°C

°C/W

1nF

LX

Transient Pulse

Generator

(note)

10 k

Gnd

Gnd

Note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.

Figure 3. Transient test pulse for L0 and L1 inputs

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics .

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

INPUT PIN (VSUP)

= 25°C under nominal conditions unless otherwise noted.

A

Nominal DC Voltage range

Extended DC Voltage range 1

Reduced functionality

Extended DC Voltage range 2

(6)

(8)

Input Voltage during Load Dump

Load dump situation

Input Voltage during jump start

Jump start situation

Supply Current in Sleep Mode

V

& V2 off, V

DD1

SUP

Supply Current in Sleep Mode

V

& V2 off, V

DD1

SUP

Supply current in sleep mode

V

& V2 off, V

DD1

SUP

(7)

≤ 12 V, oscillator running

(7)

≤ 12 V, oscillator not running

(7)

= 18 V, oscillator running

Supply Current in Stand-by Mode

Iout at V

= 40 mA, CAN recessive state or disabled

DD1

Supply Current in Normal Mode

Iout at V

Supply Current in Stop mode

I out V

running

Supply Current in Stop mode

Iout V

not running

Supply Current in Stop mode

Iout V

running

= 40 mA, CAN recessive state or disabled

DD1

(7),(9)

< 2.0 mA, V

DD1

(10)

< 2.0 mA, V

DD1

(10)

< 2.0 mA, V

DD1

(10)

DD1

DD1

DD1

on

(7),(9)

on

(7),(9)

on

(7)

(11)

(11)

(11)

(7),(9)

, V

≤ 12 V, oscillator

SUP

V

≤ 12V, oscillator

SUP

, V

= 18 V, oscillator

SUP

(10)

(10)

V

SUP

V

SUP-EX1

V

SUP-EX2

V

SUPLD

V

SUPJS

I

SUP

(SLEEP1)

I

SUP

(SLEEP2)

I

SUP

(SLEEP3)

I

SUP(STDBY

I

SUP(NORM)

I

SUP

(STOP1)

I

SUP

(STOP2)

I

SUP

(STOP3)

5.5 - 18 V

4.5 - 5.5 V

18 - 27 V

- - 40 V

- - 27 V

- 95 130 µA

- 55 90 µA

- 170 270 µA

) - 42 45 mA

- 42.5 45 mA

- 120 150 µA

- 80 110 µA

- 200 285 µA

Notes

6. V

7. Current measured at V

> 4.0 V, reset high, if R

DD1

SUP

pin.

STTH-2

selected and I

OUT VDD1

reduced, logic pin high level reduced, device is functional.

8. Device is fully functional. All modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs
operating, SPI read write operation. Over temperature may occur.

9. Measured in worst case condition with 5.0 V at V2 pin (V2 pin tied to VDD1).

10. Oscillator running means “Forced Wake-Up” or “Cyclic Sense” or “Software Watchdog” timer activated. Software Watchdog is
available in stop mode only.

11. V

is ON with 2.0 mA typical output current capability.

DD1

33889

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

Supply Fail Flag internal threshold

Supply Fail Flag hysteresis

(12)

Battery fall early warning threshold

In normal & standby mode

Battery fall early warning hysteresis

In normal & standby mode

OUTPUT PIN (VDD1)

(12)

(13)

VDD1 Output Voltage

I

from 2.0 to 200mA

DD1

5.5 V < V

4.5 V < V

Drop Voltage V

I

DD1

Drop Voltage V

I

= 50 mA

DD1

4.5 V < V

I

Output Current

DD1

SUP

SUP

SUP

= 200 mA

SUP

SUP

< 27 V
< 5.5 V

> V

> V

< 27 V

DDOUT

, limited output current

DDOUT

Internally limited

VDD1 Output Voltage in stop mode

Iout < 2.0 mA

V

THRESH

V

DETHYST

BF

EW

BF

EWH

V

DD1OUT

V

DD1DROP

V

DD1DP2

I

DD1

V

DDSTOP

1.5 3.0 4.0 V

- 1.0 - V

5.8 6.1 6.4 V

0.1 0.2 0.3 V

4.9

4.0

5.0

5.1

-

-

- 0.2 0.5 V

- 0.1 0.25 V

200 270 350 mA

4.75 5.00 5.25 V

V

I

stop output current to wake-up SBC

DD1

Default value after reset.

I

stop output current to wake-up SBC

DD1

I

over current wake deglitcher

DD1

(with I

DD1S-WU1

I

over current wake deglitcher

DD1

(with I

DD1S-WU2

selected)

selected)

(14)

(12)

(12)

Thermal Shutdown

(14)

I

DD1S-WU1

I

DD1S-WU2

I

DD1-DGIT11

I

DD1-DGIT2

T

SD

2.0 3.5 6.0 mA

10 14 18 mA

40 55 75 µs

- 150 - µs

160 - 190 °C

Normal or standby mode

Over temperature pre warning

T

PW

130 - 160 °C

VDDTEMP bit set

Temperature Threshold difference

TSD-T

PW

20 - 40 °C

Notes

12. Guaranteed by design

13. I

is the total regulator output current. VDD specification with external capacitor C ≥ 22µF and ESR < 1O ohm.

DD1

14. Selectable by SPI

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

Reset threshold 1

Default value after reset.

Reset threshold 2

(15)

Reset duration

VDD1 range for Reset Active

Reset Delay Time

Measured at 50% of reset signal.

Line Regulation

9.0 V < V

SUP

< 18, I

= 10 mA

DD

Line Regulation

5.5 V < V

SUP

< 27 V, I

DD

Load Regulation

1 mA < I

< 200 mA

IDD

Thermal stability

V

= 13.5 V, I = 100 mA

SUP

V2 REGULATOR (V2)

(17)

V2 Output Voltage

I2 from 2.0 to 200 mA

5.5 V < V

SUP

< 27 V

(15)

= 10 mA

(16)

V

RST-TH1

V

RST-TH2

4.5 4.6 4.7 V

4.1 4.2 4.3 V

RESET-DUR 0.85 1.0 2.0 ms

V

DD

t

D

1.0 - - V

5.0 - 20 µs

LR1 - 5.0 25 mV

LR2 - 10 25 mV

LD - 25 75 mV

THERMS - 5.0 - mV

V2 0.99 1.0 1.01 V

DD1

I2 output current (for information only)

I2 200 - - mA

Depending on the external ballast transistor

V2 CTRL sink current capability

V2LOW flag threshold

Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX = 5.0 V, CAN in Recessive State

Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX = 0.0 V, No Load, CAN in Dominant State

Internal V2 Supply Current (CAN in Receive Only Mode,
SBC in Normal mode). V

SUP

= 12 V

Internal V2 Supply Current (CAN in Bus TermVbat mode,
SBC in normal mode), V

SUP

= 12 V

I2

V2L

I

I

I

CTRL

V2RS

V2DS

I

V2R

V2BT

TH

10 - - mA

3.75 4.0 4.25 V

3.8 5.6 6.8 mA

4.0 5.8 7.0 mA

80 120 µA

35 60 µA

Notes

15. Selectable by SPI

16. Guaranteed by design

17. V2 TRACKING VOLTAGE REGULATOR - V2 specification with external capacitor

- option 1: C ≥ 22 µF and ESR < 10 ohm. Using a resistor of 2 kohm or less between the base and emitter of the external PNP is
recommended.

- option2: 1.0 µF < C < 22 µF and ESR < 10 ohm. In this case depending on the ballast transistor gain an additional resistor and
capacitor network between emitter and base of PNP ballast transistor might be required. Refer to Freescale application information
or contact your local technical support.

- option 3: 10uF < C < 22uF ESR > 0.2 ohms: a resistor of 2 kohm or less is required between the base and emitter of the external PNP.

33889

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

LOGIC OUTPUT PINS (MISO)

= 25°C under nominal conditions unless otherwise noted.

A

Low Level Output Voltage

I

= 1.5 mA

OUT

High Level Output Voltage

I

= -250 µA

OUT

Tri-state MISO Leakage Current

0.0 V < V

miso

< V

DD

LOGIC INPUT PINS (MOSI, SCLK, CS)

High Level Input Voltage

Low Level Input Voltage

Input Current on CS

VI = 4.0 V
VI = 1.0 V

Low Level Input Current CS

VI = 1.0 V

MOSI, SCLK Input Current

0.0 < V

IN

< V

DD

RESET PIN (RST)

High Level Output current

0.0 < V

out

< 0.7 V

DD

V

OL

V

OH

I

HZ

V

IH

V

IL

- - 1.0 V

V

DD1-0.9

- - V

-2.0 - +2.0 µA

0.7V

DD1

-0.3 - 0.3 V

- V

DD1

+0.3V

DD1

V

-100 - -20 µA

I

IH

I

IL

I

IL

I

IN

I

OH

-100 - -20 µA

-10 - 10 µA

-350 -250 -150 µA

Low Level Output Voltage (I0 = 1.5 mA)

5.5 v < V

1.0 V < V

SUP

DD1

< 27 V

Reset pull down current

V

I

PDW

OL

V

0.0

0.0

-

-

0.9

0.9

2.3 - 5.0 mA

WATCHDOG PIN (WDOG)

Low Level Output Voltage (I0 = 1.5 mA)

5.5 V < V

SUP

< 27 V

High Level Output Voltage (I0 = -250 µA)

V

OL

V

OH

0.0 - 0.9 V

V

-0.9 - V

DD1

DD1

V

INTERRUPT PIN (INT)

Low Level Output Voltage (I0 = 1.5 mA)

High Level Output Voltage (I0 = -250 µA)

V

OL

V

OH

0.0 - 0.9 V

V

-0.9 - V

DD1

DD1

V

HIGH-SIDE OUTPUT PIN (HS1)

R

at Tj = 25°C, and I

DSON

V

>9V

SUP

OUT

-150 mA

R

DSON25

- - 2.5 Ohms

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

R

at Tj = 125°C, and I

DSON

V

> 9.0 V

SUP

R

at Tj = 125°C, and I

DSON

5.5 V < V

SUP

< 9.0 V

OUT

OUT

-150 mA

-120 mA

= 25°C under nominal conditions unless otherwise noted.

A

R

DSON125

R

DON125-2

- - 5.0 Ohms

- 4.0 5.5 Ohms

Output current limitation

Over temperature Shutdown

Leakage current

Output Clamp Voltage at I

OUT

no inductive load drive capability

INPUT PINS (L0 AND L1)

L0 Negative Switching Threshold

5.5 V < V

6.0 V < V

18 V < V

SUP

SUP

SUP

< 6.0 V

< 18 V

< 27 V

L0 Positive Switching Threshold

5.5 V < V

6.0 V < V

18 V < V

SUP

SUP

SUP

< 6.0 V

< 18 V

< 27 V

L1 Negative Switching Threshold

5.5 V < V

6.0 V < V

18 V < V

SUP

SUP

SUP

< 6.0 V

< 18 V

< 27 V

L1 Positive Switching Threshold

5.5 V < V

6.0 V < V

18 V < V

SUP

SUP

SUP

< 6.0 V

< 18V

< 27 V

= -1.0 mA

(18)

O

I

LEAK

V

V

V

V

V

I

LIM

VT

CL

TH0N

TH0P

TH1N

TH1P

160 - 500 mA

155 - 190 °C

- - 10 µA

-1.5 - -0.3 V

V

1.7

2.0

2.0

2.0

2.4

2.5

3.0

3.0

3.1

V

2.2

2.5

2.5

2.75

3.4

3.5

4.0

4.0

4.1

V

2.0

2.5

2.7

2.5

3.0

3.2

3.0

3.7

3.8

V

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.7

4.8

Hysteresis

5.5 V < V

Input current

SUP

< 27 V

V

HYST

I

IN

0.6 1.0 1.3 V

-10 - 10 µA

-0.2 V < VIN < 40 V

CAN MODULE SPECIFICATION (TX, RX, CANH, CANL, RTH, AND RTL)

DC Voltage On Pins TX, RX

DC voltage at V2 (V2INT)

DC Voltage On Pins CANH, CANL

V

LOGIC

V2

V

INT

BUS

-0.3 V

+ 0.3 V

DD1

0.0 5.25 V

-20 +27 V

Notes

18. Refer to HS1 negative maximum rating voltage limitation of -0.2V.

33889

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

Transient Voltage At Pins CANH, CANL

0.0 < V

2-INT

< 5.5 V; V

≥ 0.0; T < 500 ms

SUP

Transient Voltage On Pins CANH, CANL (Coupled Through

1.0 nF Capacitor)

Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode) MC33889B

Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode) MC33889D

DC Voltage On Pins RTH, RTL

Transient Voltage At Pins RTH, RTL

0.0 < V

2-INT

< 5.5 V; V

≥ 0.0; T < 500 ms

SUP

TRANSMITTER DATA PIN (TX)

High Level Input Voltage

Low Level Input Voltage

TX High Level Input Current (VI = 4.0 V)

TX Low Level Input Current (VI = 1.0 V)

RECEIVE DATA PIN (RX)

High Level Output Voltage RX (I0 = -250 µA)

Low Level Output Voltage (I0 = 1.5 mA)

CAN HIGH AND CAN LOW PINS (CANH, CANL)

V

CANH/VCANL

V

TR

V

CANH

V

CANH

V

, V

RTL

V

RTH/VRTL

V

IH

V

IL

I

TXH

I

TXL

V

OH

V

OL

RTH

-40 40 V

-150 100 V

V

/2+3 V

SUP

V

/2+3 V

SUP

/2+5 V

SUP

/

SUP

2+4.55

-0.3 +27 V

-0.3 40 V

0.7*V

2

-0.3 0.3 * V

V2+0.3V V

2

-100 -50 -25 µA

-100 -50 -25 µA

V

- 0.9 V

2-INT

2-INT

0.0 0.9 V

V

V

V

Differential Receiver, Recessive To Dominant Threshold

(By Definition, V

DIFF

= V

CANH-VCANL

)

For 33889D
For 33889B

Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)

For 33889D
For 33889B

CANH Recessive Output Voltage

TX = 5.0 V; R

(RTH)

< 4.0 k

CANL Recessive Output Voltage

TX = 5.0 V; R

(RTL)

< 4.0 k

V

V

V

V

DIFF1

DIFF2

CANH

CANL

-3.5

-3.2

-3.5

-3.2

-3.0

-2.6

-3.0

-2.6

-2.5

-2.1

-2.5

-2.1

0.2 V

V

- 0.2 V

2-INT

V

V

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 13

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

CANH Output Voltage, Dominant

TX = 0.0 V; I

= -40 mA; Normal Operating Mode

CANH

(19)

CANL Output Voltage, Dominant

TX = 0.0 V; I

= 40 mA; Normal Operating Mode

CANL

CANH Output Current (V

= 0; TX = 0.0)

CANH

(19)

For 33889D

For 33889B

CANL Output Current (V

= 14 V; TX = 0.0)

CANL

For 33889D

For 33889B

Detection Threshold For Short-circuit To Battery Voltage
(Normal Mode)

Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode), MC33889B

Detection Threshold For Short-circuit To Battery Voltage
(Term VBAT Mode), MC33889D

CANH Output Current (Term V
Failure3)

CANL Output Current (Term V

V

= 12 V, Failure 4)

BAT

BAT

BAT

Mode; V

Mode; V

CANH

CANL

= 12 V,

= 0.0 V;

CANL Wake-Up Voltage Threshold

CANH Wake-Up Voltage Threshold

Wake-Up Threshold Difference (Hysteresis)

CANH Single Ended Receiver Threshold (Failures 4, 6, 7)

CANL Single Ended Receiver Threshold (Failures 3, 8)

CANL Pull Up Current (Normal Mode)

CANH Pull Down Current (Normal Mode)

Receiver Differential Input Impedance CANH / CANL

Differential Receiver Common Mode Voltage Range

(20)

CANH To Ground Capacitance

CANL To Ground Capacitance

C

CANL

to C

Capacitor Difference

CANH

CAN Driver Thermal Shutdown

Notes

19. For MC33889B, after 128 pulses on TX and no bus failure.

20. Guaranteed by design

V

V

V

I

I

CANH

CANH

CANL

CANH

CANL

, V

CANL

V2 - 1.4 V

1.4 V

50

50

50

50

100

75

140

90

130

110

170

135

7.3 7.9 8.9 V

VcanH Vsup/2+3 Vsup/2+5 V

VcanH Vsup/2+3

I

CANH

I

CANL

V

WAKE,L

V

WAKE,H

V

WAKEL

V

WAKEH

V

SE, CANH

V

SE, CANL

I

CANL,PU

I

CANH,PD

R

DIFF

V

COM

C

CANH

C

CANL

DC

t

CSD

-

CAN

2.5 3.0 3.9 V

1.2 2.0 2.7 V

0.2 V

1.5 1.85 2.15 V

2.8 3.05 3.4 V

45 75 90 µA

45 75 90 µA

100 300 kohm

-10 10 V

150 160 °C

5.0 10 µA

0.0 2.0 µA

Vsup/

2+4.55

50 pF

50 pF

10 pF

mA

mA

V

33889

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued).

Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40°C to 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T

Description Symbol Min Typ Max Unit

BUS TERMINATION PINS (RTH, RTL)

= 25°C under nominal conditions unless otherwise noted.

A

RTL to V2 Switch On Resistance

(I

< -10 mA; Normal Operating Mode)

OUT

RTL to BAT Switch Series Resistance (term V

RTH To Ground Switch On Resistance (I
Normal Operating Mode)

OUT

Mode)

BAT

< 10 mA;

R

RTL

R

RTL

R

RTH

10 30 90 ohms

8.0 12.5 20 kohm

10 30 90 ohm

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

V

From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values

SUP

noted reflect the approximate parameter means at T

Conditions Symbol Min Typ Max Unit

DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)

= 25°C under nominal conditions unless otherwise noted.

A

SPI operation frequency

SCLK Clock Period

SCLK Clock High Time

SCLK Clock Low Time

Falling Edge of CS to Rising

Edge of SCLK

Falling Edge of SCLK to Rising Edge of CS

MOSI to Falling Edge of SCLK

Falling Edge of SCLK to MOSI

MISO Rise Time (CL = 220 pF)

MISO Fall Time (CL = 220 pF)

Time from Falling or Rising Edges of CS to:

- MISO Low Impedance

- MISO High Impedance

FREQ - - 4.0 MHz

t

PCLK

t

WSCLKH

t

WSCLKL

t

lLEAD

t

LAG

t

SISU

t

SIH

t

RSO

t

fSO

250 - - ns

125 - - ns

125 - - ns

100 50 - ns

100 50 - ns

40 25 - ns

40 25 - ns

- 25 50 ns

- 25 50 ns

- -

t

SOEN

t

SODIS

50

50

ns

Time from Rising Edge of SCLK to MISO Data Valid

t

VALID

- - 50 ns

0.2 V1 ≤ SO ≥ 0.8 V1, CL = 200 pF

Delay between CS low to high transition (at end of SPI stop
command) and Stop or sleep mode activation

(21)

T

CS-STOP

18 - 34 µs

detected by V2 off

Interrupt low level duration

T

INT

7.0 10 13 µs

SBC in stop mode

Internal oscillator frequency

All modes except Sleep and Stop

(21)

O

SC-F1

- 100 - kHz

Notes

21. Guaranteed by design

33889

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

Table 5. Dynamic Electrical Characteristics (continued)

V

From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values

SUP

noted reflect the approximate parameter means at T

Conditions Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Internal low power oscillator frequency

Sleep and Stop modes

(22)

Watchdog period 1

Normal and standby modes

Watchdog period 2

Normal and standby modes

Watchdog period 3

Normal and standby modes

Watchdog period 4

Normal and standby modes

Watchdog period accuracy

Normal and standby modes

Normal request mode timeout

Normal request mode

Watchdog period 1 - stop

Stop mode

O

F1

NR

WD1

SC-F2

W

D1

W

D2

W

D3

W

D4

ACC

TOUT

STOP

- 100 - kHz

8.58 9.75 10.92 ms

39.6 45 50.4 ms

88 100 112 ms

308 350 392 ms

-12 - 12 %

308 350 392 ms

6.82 9.75 12.7 ms

Watchdog period 2- stop

WD2

STOP

31.5 45 58.5 ms

Stop mode

Watchdog period 3 - stop

WD3

STOP

70 100 130 ms

Stop mode

Watchdog period 4 - stop

WD4

STOP

245 350 455 ms

Stop mode

Stop mode watchdog period accuracy

F2

ACC

-30 - 30 %

Stop mode

Cyclic sense/FWU timing 1

CSFWU1 3.22 4.6 5.98 ms

Sleep and stop modes

Cyclic sense/FWU timing 2

CSFWU2 6.47 9.25 12 ms

Sleep and stop modes

Notes

22. Guaranteed by design

33889

Analog Integrated Circuit Device Data
Freescale Semiconductor 17

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

V

From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40°C to 150°C unless otherwise noted. Typical values

SUP

noted reflect the approximate parameter means at T

Conditions Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

Cyclic sense/FWU timing 3

Sleep and stop modes

Cyclic sense/FWU timing 4

Sleep and stop modes

Cyclic sense/FWU timing 5

Sleep and stop modes

Cyclic sense/FWU timing 6

Sleep and stop modes

Cyclic sense/FWU timing 7

Sleep and stop modes

Cyclic sense/FWU timing 8

Sleep and stop modes

Cyclic sense On time

in sleep and stop modes

Cyclic sense/FWU timing accuracy

in sleep and stop mode

CSFWU3 12.9 18.5 24 ms

CSFWU4 25.9 37 48.1 ms

CSFWU5 51.8 74 96.2 ms

CSFWU6 66.8 95.5 124 ms

CSFWU7 134 191 248 ms

CSFWU8 271 388 504 ms

t

ON

t

ACC

200 300 400 µs

-30 - +30 %

Delay between SPI command and HS1 turn on

Normal or standby mode, V

SUP

> 9.0 V

Delay between SPI command and HS1 turn off

Normal or standby mode, V

Delay between SPI and V2 turn on

SUP

> 9.0 V

(23)

(23)

(23)

t

S-HSON

t

S-HSOFF

t

S-V2ON

- - 22 µs

- - 22 µs

9.0 - 25 µs

Standby mode

Delay between SPI and V2 turn off

(23)

t

S-V2OFF

9.0 - 25 µs

Normal modes

Delay between Normal Request and Normal mode, after
W/D trigger command

t

S-NR2N

15 35 70 µs

Normal request mode

Notes

23. State Machine Timing - Delay starts at rising edge of CS (end of SPI command) and start of Turn on or Turn off of HS1 or V2.

33889

Analog Integrated Circuit Device Data

18 Freescale Semiconductor