Freescale 33887 Technical Data

Freescale Semiconductor

Technical Data

5.0 A H-Bridge with Load

Document Number: MC33887

Rev. 12.0, 2/2007

Current Feedback

The 33887 is a monolithic H-Bridge Power IC with a load current
feedback feature making it ideal for closed-loop DC motor control.
The IC incorporates internal control logic, charge pump, gate drive,
and low R
control inductive loads with continuous DC load currents up to 5.0
and with peak current active limiting between 5.2
loads can be pulse width modulated (PWM-ed) at frequencies up to
10 kHz. The load current feedback feature provides a proportional (1/
375th of the load current) constant-current output suitable for
monitoring by a microcontroller’s A/D input. This feature facilitates
the design of closed-loop torque/speed control as well as open load
detection.

A Fault Status output pin reports undervoltage, short circuit, and
overtemperature conditions. Two independent inputs provide polarity
control of two half-bridge totem-pole outputs. Two disable inputs
force the H-Bridge outputs to tri-state (exhibit high impedance).

The 33887 is parametrically specified over a temperature range of

≤ TA ≤ 125°C and a voltage range of 5.0 V ≤ V+ ≤ 28 V.

-40°C
Operation with voltages up to 40 V with derating of the specifications.

Features

• Fully specified operation 5.0 V to 28 V

• Limited operation with reduced performance up to 40 V

•120 mΩ R

• TTL/CMOS Compatible Inputs

• PWM Frequencies up to 10 kHz

• Active Current Limiting (Regulation)

• Fault Status Reporting

• Sleep Mode with Current Draw ≤50 µA (Inputs Floating or Set
to Match Default Logic States)

• Pb-Free Packaging Designated by Suffix Codes VW and EK

MOSFET output circuitry. The 33887 is able to

DS(ON)

A and 7.8 A. Output

Typical H-Bridge MOSFETs

DS(ON)

A,

ORDERING INFORMATION

Device

MC33887DH/R2
MC33887VW/R2
MC33887PNB/R2
MC33887DWB/R2
MCZ33887EK/R2

33887

H-BRIDGE

VW SUFFIX (Pb-FREE)

PNB SUFFIX

98ASA10583D

36-PIN PQFN

EK SUFFIX (Pb-FREE)

54-PIN SOICW-EP

Temperature

Range (T

-40°C to 125°C

DH SUFFIX

98ASH70273A

20-PIN HSOP

Bottom View

DWB SUFFIX

98ASA10506D

)

A

54 SOICW-EP

Package

20 HSOP

36 PQFN

6.0 V

33887

CCP

MCU

IN
OUT
OUT
OUT
OUT
OUT

A/D

FS
EN

IN1
IN2
D1
D2
FB

FB

Figure 1. 33887 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

V+

V+

OUT1

MOTOR

OUT2
PGND

AGND

INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

CCP VPWR

EN

IN1
IN2

D1
D2

FS
FB

8 µA

EACH)

(

25 µA

5.0 V

REGULATOR

CONTROL

LOGIC

Figure 2. 33887 Simplified Internal Block Diagram

CHARGE PUMP

GATE

DRIVE

OVER

TEMPERATURE

UNDERVOLTAGE

CURRENT

LIMIT,

OVERCURRENT

SENSE &

FEEDBACK

CIRCUIT

OUT1

OUT2

PGNDAGND

33887

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

Tab

PIN CONNECTIONS

FS

IN1

V+

V+
OUT1
OUT1

FB

PGND
PGND

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

ENAGND
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND

Tab

Figure 3. 33887 Pin Connections

Table 1. 33887 HSOP PIN DEFINITIONS

A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.

Pin Pin Name Formal Name Definition

1 AGND Analog Ground

2 FS Fault Status for H-Bridge

3 IN1 Logic Input Control 1

Low-current analog signal ground.

Open drain active LOW Fault Status output requiring a pull-up resistor to

5.0

V.

Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).

4 , 5, 16 V+ Positive Power Supply

6 , 7 OUT1 H-Bridge Output 1

8 FB Feedback for H-Bridge

9 – 12 PGND Power Ground

13 D2 Disable 2

14 , 15 OUT2 H-Bridge Output 2

17 CCP Charge Pump Capacitor

18 D1 Disable 1

19 IN2 Logic Input Control 2

20 EN Enable

Tab/Pad Thermal

Interface

Exposed Pad Thermal

Interface

Positive supply connections

Output 1 of H-Bridge.

Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.

High-current power ground.

Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When

Output 2 of H-Bridge.

External reservoir capacitor connection for internal charge pump capacitor.

Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.

Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).

Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).

Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.

D2 is Logic LOW, both outputs are tri-stated.

33887

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

PIN CONNECTIONS

Transp arent Top View of Package

V+

NC

D1

IN2

EN

V+
V+

NC

AGND

FS

NC

CCPV+OUT2

36353433323130

1
2
3
4
5
6
7
8
9

10

11

12131415161718

V+

IN1

V+

OUT1

OUT2NCOUT2

OUT1NCOUT1

OUT2

29

OUT1

28
27
26
25
24
23
22
21
20

19

NC
D2
PGND
PGND
PGND
PGND
PGND
PGND
FB
NC

Figure 4. 33887 Pin Connections

Table 2. PQFN PIN DEFINITIONS

A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.

Pin Pin Name Formal Name Definition

1, 7, 10, 16,

NC No Connect

19, 28, 31

2 D1 Disable 1

3 IN2 Logic Input Control 2
4 EN Enable

5, 6, 12, 13, 34, 35 V+ Positive Power Supply

8 AGND Analog Ground
9 FS Fault Status for H-Bridge

11 IN1 Logic Input Control 1

14, 15, 17, 18 OUT1 H-Bridge Output 1

20 FB Feedback for H-Bridge

No internal connection to this pin.

Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.

Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,

EN

logic LOW = Sleep Mode).
Positive supply connections.
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to

5.0

V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Output 1 of H-Bridge.
Current feedback output providing ground referenced 1/375th ratio of

H-Bridge high-side current.

21– 26 PGND Power Ground

27 D2 Disable 2

29, 30, 32, 33 OUT2 H-Bridge Output 2

36 CCP Charge Pump Capacitor

High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge

outputs. When

D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump

capacitor.

Pad Thermal

Interface

Exposed Pad Thermal

Interface

Exposed pad thermal interface for sinking heat from the device.
Note: Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.

33887

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

PIN CONNECTIONS

Transparent Top View of Package

PGND
PGND
PGND
PGND

NC
NC
NC

D2

NC
OUT2
OUT2
OUT2
OUT2

NC

V+
V+
V+

V+
NC
NC
NC
NC

CCP

D1
IN2
EN
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

.35

54

PGND

53

PGND

52

PGND

51

PGND

50

NC

49

NC

48

NC
FB

47
46

NC

45

OUT1
OUT1

44

OUT1

43

OUT1

42
41

NC

40

V+
V+

39
38

V+

37

V+
NC

36

NC
NC

34

NC

33

IN1

32

FS

31

AGND

30

NC

29

NC

28

Figure 5. 33887 Pin Connections

Table 3. SOICW-EP PIN DEFINITIONS

A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.

Pin Pin Name Formal Name Definition

1– 4, 51– 54 PGND Power Ground

5 – 7, 9, 14, 19 – 22,
27

– 29, 33 – 36, 41,

46, 48

– 50

NC No Connect

8 D2 Disable 2

10 – 13 OUT2 H-Bridge Output 2

15 – 18, 37 – 40 V+ Positive Power Supply

23 CCP Charge Pump Capacitor

High-current power ground.
No internal connection to this pin.

Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When

D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
Positive supply connections.
External reservoir capacitor connection for internal charge pump

capacitor.

24 D1 Disable 1

Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.

25 IN2 Logic Input Control 2
26 EN Enable

30 AGND Analog Ground
31 FS Fault Status for H-Bridge

Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,

EN

logic LOW = Sleep Mode).
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to

5.0

V.

32 IN1 Logic Input Control 1

Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).

33887

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

PIN CONNECTIONS

Table 3. SOICW-EP PIN DEFINITIONS

A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21.

Pin Pin Name Formal Name Definition

42 – 45 OUT1 H-Bridge Output 1

47 FB Feedback for H-Bridge

Pad Thermal

Interface

Exposed Pad Thermal

Interface

Output 1 of H-Bridge.
Current feedback output providing ground referenced 1/375th ratio of

H-Bridge high-side current.
Exposed pad thermal interface for sinking heat from the device.

Note Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.

33887

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Unit

ELECTRICAL RATINGS

Supply Voltage
Input Voltage
FS Status Output
Continuous Current
DH Suffix HSOP ESD Voltage

Human Body Model

Each Pin to AGND
Each Pin to PGND
Each Pin to V+
Each I/O to All Other I/Os

Machine Model

VW Suffix HSOP, SOICW-EP, and PQFN ESD Voltage

Human Body Model
Machine Model

THERMAL RATINGS

Storage Temperature
Operating Temperature

Ambient
Junction

Peak Package Reflow Temperature During Reflow

Notes

1 Performance at voltages greater than 28V is degraded.See Electrical Performance Curves on page 18 and 19 for typical performance.

Extended operation at higher voltages has not been fully characterized and may reduce the operational lifetime.
2 Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device.
3 Exceeding the pull-up resistor voltage on the open Drain FS pin may cause permanent damage to the device.
4 Continuous current capability so long as junction temperature is ≤ 150°C.
5 ESD1 testing is performed in accordance with the Human Body Model (C

accordance with the Machine Model (C
6 The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief

nonrepetitive excursions of junction temperature above 150

maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.)
7 Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

(1)

(2)

(3)

(4)

(5)

(5)

(6)

(7), (8)

= 200 pF, R

ZAP

ZAP

= 0 Ω).

V+ -0.3 to 40

V
I

V
V
V
V
V

V
V

T

T

V

IN
FS

OUT

ESD1
ESD1
ESD1
ESD1
ESD2

ESD1
ESD2

STG

T

A

T

J

PPRT

ZAP

= 100 pF, R

- 0.3 to 7.0 V

-0.3 to 7.0 V

5.0 A

±1000
±1500
±2000
±2000

±200

± 2000

± 200

- 65 to 150 °C

- 40 to 125

- 40 to 150

Note 8.

= 1500 Ω), ESD2 testing is performed in

ZAP

°C can be tolerated as long as duration does not exceed 30 seconds

V

V

V

°C

°C

33887

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MAXIMUM RATINGS (continued)

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Unit

THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS

Junction-to-Board (Bottom Exposed Pad Soldered to Board)

HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)

Junction-to-Ambient, Natural Convection, Single-Layer Board (1s)

HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)

Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)

(14)

HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)

Junction-to-Case (Exposed Pad)

(15)

HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)

Notes

9 The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.

10 Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual R

values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die
temperature represents ~

less than 5.0

°C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly.

16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R

11 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

12 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
13 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
14 Per JEDEC JESD51-6 with the board horizontal.
15 Indicates the maximum thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

(9), (10), (11), (12)

(13)

R

JB

θ

°C/W

~7.0
~8.0
~9.0

R

JA

θ

°C/W

~ 41
~ 50
~ 62

R

JMA

θ

°C/W

~ 18
~ 21
~ 23

R

JC

θ

°C/W

~ 0.8

~1.2
~2.0

(junction-to-PC board)

θ

JB

-total must be

JC

θ

33887

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER SUPPLY

Operating Voltage Range
Sleep State Supply Current

I

= 0 A, VEN = 0 V

OUT

(16)

(17)

V+ 5.0 – 28 V

I

Q (SLEEP)

– 25 50

µA

Standby Supply Current

I

= 0 A, VEN = 5.0 V

OUT

I

Q (STANDBY)

mA

– – 20

Threshold Supply Voltage

Switch-OFF
Switch-ON
Hysteresis

V+

(THRES-OFF)

V+

(THRES-ON)

V+

(HYS)

4.15

4.5

150

4.4

4.75
–

4.65

5.0
–

mV

CHARGE PUMP

Charge Pump Voltage

V+ = 5.0 V

8.0

V ≤ V+ ≤ 28 V

VCP - V+

3.35
–

–
–

–

20

CONTROL INPUTS

Input Voltage (IN1, IN2, D1, D2)

Threshold HIGH
Threshold LOW
Hysteresis

Input Current (IN1, IN2, D1)

VIN - 0.0 V

Input Current (D2, EN)

V D2 = 5.0 V

V

V
V

HYS

I

INP

I

INP

IH
IL

3.5
–

0.7

–
–

1.0

1.4

- 200 - 80 –

– 25 100

–

–

Notes

16 Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. See See Electrical Performance Curves on page 18 and 19 and

the See Functional Description on page 21 for information about operation outside of this range.

17 I

is with sleep mode function enabled.

Q (sleep)

V
V

V

V

µA

µA

33887

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 4. STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

POWER SUPPLY
POWER OUTPUTS (OUT1, OUT2)

Output ON-Resistance

5.0 V ≤ V+ ≤ 28 V, TJ = 25°C

8.0 V ≤ V+ ≤ 28 V, TJ = 150°C

5.0 V ≤ V+ ≤ 8.0 V, TJ = 150°C

(18)

= 25°C under nominal conditions unless otherwise noted.

A

R

DS(ON)

–
–
–

120

–
–

–
225
300

mΩ

Active Current Limiting Threshold (via Internal Constant OFF-Time
PWM) on Low-Side MOSFETs

(19)

High-Side Short Circuit Detection Threshold
Low-Side Short Circuit Detection Threshold
Leakage Current

V

= V+

OUT

= Ground

V

OUT

(20)

Output MOSFET Body Diode Forward Voltage Drop

I

= 3.0 A

OUT

Overtemperature Shutdown

Thermal Limit
Hysteresis

HIGH-SIDE CURRENT SENSE FEEDBACK

Feedback Current

I

= 0 mA

OUT

I

= 500 mA

OUT

I

= 1.5 A

OUT

I

= 3.0 A

OUT

I

= 6.0 A

OUT

FAULT STATUS

Fault Status Leakage Current

V

= 5.0 V

FS

Fault Status SET Voltage

(21)

(22)

(23)

I FS = 300 µA

I

LIM

I

SCH

I

SCL

I

OUT(LEAK)

V

F

T

LIM

T

HYS

I

FB

I

FS(LEAK)

V

FS(LOW)

5.2 6.5 7.8 A

11 – – A

8.0 – – A

–
–

100

30

200

60

– – 2.0

175

10

–

1.07

3.6

7.2

14.4

–
–

–

1.33

4.0

8.0
16

225

30

600

1.68

4.62

9.24

18.48

– – 10

– – 1.0

µA

V

°C

µA
mA
mA
mA
mA

µA

V

Notes

18 Output-ON resistance as measured from output to V+ and ground.
19 Active current limitation applies only for the low-side MOSFETs.
20 Outputs switched OFF with D1 or D2.
21 Fault Status output is an open Drain output requiring a pull-up resistor to 5.0 V.
22 Fault Status Leakage Current is measured with Fault Status HIGH and not SET.
23 Fault Status Set Voltage is measured with Fault Status LOW and SET with I

= 300 µA.

FS

33887

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values

noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

TIMING CHARACTERISTICS

PWM Frequency
Maximum Switching Frequency During Active Current Limiting
Output ON Delay

V+ = 14 V

Output OFF Delay

V+ = 14 V

I

Output Constant-OFF Time for Low-Side MOSFETs

LIM

I

Blanking Time for Low-Side MOSFETs

LIM

Output Rise and Fall Time

V+ = 14 V, I

Disable Delay Time
Power-ON Delay Time
Wake-Up Delay Time
Output MOSFET Body Diode Reverse Recovery Time

Notes

24 The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM

pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. See Typical Switching Waveforms,

25 The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces

a constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance
characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.

26 Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition

direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to
the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal
to the 10% point of the output response signal. See

27 I

LIM

the output bridge.

28 Load currents ramping up to the current regulation threshold become limited at the I

that ramps up to the I
shutdown circuitry to force the output into an immediate tri-state latch-OFF. See

mode may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to
progressively “fold back”, or decrease with temperature, until ~175
Permissible operation within this fold-back region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See

Figure 9, page 12.

29 I

LIM

comparators my have time to act.
30 Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 8, page 12.
31 Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See

Figure 7, page 12.

32 Parameter has been characterized but not production tested.
33 Parameter is guaranteed by design but not production tested.

(24)

(25)

(26)

f

PWM

f

MAX

t

D (ON)

– 10 – kHz
– – 20 kHz

– – 18

(26)

t

D (OFF)

– – 18

OUT

(27), (28)

(29), (28)

(30)

= 3.0 A

(31)

(32)

(32)

(33)

t

A

t

B

t F, t

R

t

D (DISABLE)

t

POD

t

WUD

t

R R

15 20.5 26
12 16.5 21

2.0 5.0 8.0
– – 8.0 µs

– 1.0 5.0 ms
– 1.0 5.0 ms

100 – –

Figures 12 through 19, pp. 14–17.

Figure 6, page 12.

Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated

value. The short circuit currents possess a di/dt

LIM

SCH

or I

threshold during the I

SCL

blanking time, registering as a short circuit event detection and causing the

LIM

Figures 10 and 11, page 13. Operation in Current Limit

°C is reached, after which the T

thermal latch-OFF will occur.

LIM

Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold

µs

µs

µs
µs

µs

ns

33887

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

5.0

TIMING DIAGRAMS

V

PWR

5.0 V

0

0

0 V

∞Ω

0Ω

50%

t

D(ON)

50%

90%

TIME

Figure 6. Output Delay Time

Figure 7. Disable Delay Time

t

D(OFF)

10%

V

PWR

t

F

90%

10%10%

0

t

R

90%

Figure 8. Output Switching Time

)
A

(
T

6.5

6.6

N
E
R
R
U
C

T

4.0

2.5

U
P

CURRENT (A)

T

,

U
O

LIM

I

,

,

X
A

LIM

M

I

I

150

160 175

TJ, JUNCTION TEMPERATURE (oC)

Operation within this region must be

limited to nonrepetitive events

not to exceed 30 seconds

Thermal Shutdown

Figure 9. Active Current Limiting Versus Temperature (Typical)

33887

Analog Integrated Circuit Device Data

12 Freescale Semiconductor