Freescale 33886 Technical Data

Freescale Semiconductor

Technical Data

5.0 A H-Bridge

The 33886 is a monolithic H-Bridge ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low R continuous inductive DC load currents up to 5.0 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz.

overtemperature conditions. Two independent inputs control the two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tri-state (exhibit high impedance).

-40°C up to 40 V with derating of the specifications. The IC is available in a surface mount power package with exposed pad for heatsinking.

Features

• Similar to the MC33186DH1 with Enhanced Features

• 5.0 V to 40 V Continuous Operation

•120 mΩ R

• TTL / CMOS Compatible Inputs

• PWM Frequencies up to 10 kHz

• Active Current Limiting via Internal Constant OFF-Time PWM (with

• Output Short Circuit Protection

• Undervoltage Shutdown

• Fault Status Reporting

• Pb-Free Packaging Designated by Suffix Code VW

MOSFET output circuitry. The 33886 is able to control

DS(ON)

A Fault Status output reports undervoltage, short circuit, and

The 33886 is parametrically specified over a temperature range of

≤ T

≤ 125°C, 5.0 V ≤ V+ ≤ 28 V. The IC can also be operated

A

H-Bridge MOSFETs

DS(ON)

Temperature-Dependent Threshold Reduction)

Document order number: MC33886

ORDERING INFORMATION

Device

MC33886DH/R2

MC33886VW/R2

Rev 7.0, 07/2005

33886

H-BRIDGE

VW SUFFIX (Pb-free)

DH SUFFIX

98ASH70702A

20-TERMINAL HSOP

Temperature

Range (T

- 40°C to 125°C 20 HSOP

)

A

Package

5.0 V

IN

OUT

MCU

OUT

Figure 1. 33886 Simplified Application Diagram

C

FS

IN1

IN2 D1

D2

CP

V+

33886

V+

OUT1

MOTOR

OUT2

PGND

AGND

INTERNAL BLOCK DIAGRAM

C

CP

Charge

Pump

V

V+

PWR

IN1 IN2

D1 D2

FS

80 µA

80 uA

(each)

25 uA

25 µA

5.0 V

Regulator

Gate Drive

Over-

Control

Over-

temperature

Logic

Undervoltage

Figure 2. 33886 Simplified Internal Block Diagram

Curre n t Li m it,

Current Limit,

Overcurrent

Short Circuit

Sense

Sense Circuit

Ci rcuit

PGNDAGND

OUT 1

OUT 2

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Analog Integrated Circuit Device Data

2 Freescale Semiconductor

TERMINAL CONNECTIONS

DNCAGND

IN2

D1

CCP

V+

OUT2

D2

PGND

FS

IN1

V+

OUT1

DNC

PGND

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Figure 3. 33886 Terminal Connections

Table 1. 33886 Terminal Definitions

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page

Terminal

Number

1 AGND Analog Ground

2 FS Fault Status for H-

Terminal

Name

Formal Name Definition

Low-current analog signal ground.

Open drain active Low Fault Status output requiring a pull-up resistor to 5.0 V.

Bridge

15.

3 IN1 Logic Input Control 1

4, 5, 16 V+ Positive Power Supply

6, 7 OUT1 H-Bridge Output 1

8, 20 DNC Do Not Connect

9 –12 PGND Power Ground

13 D2 Disable 2

14, 15 OUT2 H-Bridge Output 2

17 CCP Charge Pump Capacitor

18 D1 Disable 1

19 IN2 Logic Input Control 2

True logic input control of OUT1 (i.e., IN1 logic High = OUT1 logic High).

Positive supply connections.

Output 1 of H-Bridge.

Either do not connect (leave floating) or connect these terminals to ground in the application. They are test mode terminals used in manufacturing only.

Device high-current power ground.

Active Low input used to simultaneously tri-state disable both H-Bridge outputs. When D2

is logic Low, both outputs are tri-stated.

Output 2 of H-Bridge.

External reservoir capacitor connection for internal charge pump capacitor.

Active High input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is logic High, both outputs are tri-stated.

True logic input control of OUT2 (i.e., IN2 logic High = OUT2 logic High).

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Analog Integrated Circuit Device Data Freescale Semiconductor 3

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating Symbol Value Unit

Supply Voltage

Input Voltage

Status Output

FS

Continuous Current

(1)

(2)

(3)

ESD Voltage for DH Package

Human Body Model

Machine Model

(4)

(5)

ESD Voltage for VW Package

Human Body Model

Machine Model

(4)

(5)

Storage Temperature

Ambient Operating Temperature

(7)

Operating Junction Temperature

Terminal Soldering Temperature

(8)

DH Suffix

VW (Pb-Free Suffix)

Approximate Junction-to-Board Thermal Resistance (and Package Dissipation = 6.0 W)

(9)

V+ 40 V

V

I

OUT

V

ESD1

V

ESD2

V

ESD1

V

ESD2

T

STG

T

SOLDER

IN

FS

A

J

-0.1 to 7.0 V

7.0 V

5.0 A

(6)

±2000

±200

±2000

±200

-65 to 150 °C

-40 to 125 °C

-40 to 150 °C

220

260

R

JB

θ

~5.0

V

°C

°C/W

Notes

1. Exceeding the input voltage on IN1, IN2, D1, or D2

2. Exceeding the pull-up resistor voltage on the open drain FS

3. Continuous current capability so long as junction temperature is ≤ 150

4. ESD1 testing is performed in accordance with the Human Body Model (C

5. ESD2 testing is performed in accordance with the Machine Model (C

may cause a malfunction or permanent damage to the device.

terminal may cause permanent damage to the device.

°C.

ZAP

= 200 pF, R

ZAP

= 100 pF, R

ZAP

= 1500 Ω).

ZAP

= 0 Ω).

6. All terminals are capable of Human Body Model ESD voltages of ±2000 V with two exceptions pertaining only to the DH suffix package: to PGND is capable of ±1500 V and (2) OUT1 to AGND is capable of ±1000 V.

(1) D2

7. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heatsinking.

8. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits

may cause malfunction or permanent damage to the device.

9. Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual R

(junction-to-PC

θ

JB

board) values will vary depending on solder thickness and composition and copper trace.

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Analog Integrated Circuit Device Data

4 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

Power Supply

Operating Voltage Range

Standby Supply Current

V

= 5.0 V, I

EN

OUT

Threshold Supply Voltage

Switch-OFF

Switch-ON

Hysteresis

CHARGE PUMP

(10)

= 0 A

= 25°C under nominal conditions unless otherwise noted.

A

V+ 5.0 – 40 V

I

Q (standby)

––20

V+

(thres-OFF)

V+

(thres-ON)

V+

(hys)

4.15

4.5

150

4.4

4.75

–

4.65

5.0

–

mA

V

mV

Charge Pump Voltage

V+ = 5.0 V

8.0 V ≤ V+ ≤ 40 V

V

- V +

CP

3.35

–

20

CONTROL INPUTS

Input Voltage (IN1, IN2, D1, D2)

Threshold High

Threshold Low

Hysteresis

Input Current (IN1, IN2, D1)

VIN = 0 V

D2

Input Current

(12)

V D2 = 5.0 V

(11)

V

HYS

I

IN

I

D2

IH

IL

3.5

–

0.7

1.0

–

1.4

–

-200 -80 –

–25100

Notes

10. Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation > 28 V will cause some parameters to exceed listed min/max values. Refer to typical operating curves to extrapolate values for operation > 28 V but ≤ 40 V.

11. Inputs IN1, IN2, and D1 have independent internal pull-up current sources.

12. The D2

input incorporates an active internal pull-down current sink.

V

µA

33886

Analog Integrated Circuit Device Data Freescale Semiconductor 5

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.0 V reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

POWER OUTPUTS (OUT1, OUT2)

Output-ON Resistance

5.0 V ≤ V+ ≤ 28 V, TJ = 25°C

8.0 V ≤ V+

5.0 V ≤ V+

≤ 28 V, TJ = 150°C

≤ 8.0 V, TJ = 150°C

(13)

≤ V+ ≤ 28 V and -40°C ≤ T

= 25°C under nominal conditions unless otherwise noted.

A

≤ 125°C unless otherwise noted. Typical values noted

A

R

DS(ON)

–

120

–

mΩ

–

225

300

Active Current Limiting Threshold (via Internal Constant OFF-Time

(14)

PWM)

High-Side Short Circuit Detection Threshold

Low-Side Short Circuit Detection Threshold

Leakage Current

V

= V+

OUT

= GND

V

OUT

Output FET Body Diode Forward Voltage Drop

I

= 3.0 A

OUT

(15)

(16)

Switch-OFF

Thermal Shutdown

Hysteresis

FAULT STATUS

Fault Status Leakage Current

(17)

(18)

V FS = 5.0 V

Fault Status Set Voltage

(19)

I FS = 300 µA

I

LIM

I

SCH

I

SCL

I

OUT(leak)

V

F

T

LIM

T

HYS

I

FS(leak)

V

FS(LOW)

5.2 6.5 7.8

11 – –

8.0 – –

–

100

30

200

60

––2.0

175

–

15

–

––10

––1.0

µA

°C

µA

Notes

13. Output-ON resistance as measured from output to V+ and ground.

14. Product with date codes of December 2002, week 51, will exhibit the values indicated in this table. Product with earlier date codes may exhibit a minimum of 6.0 A and a maximum of 8.5 A.

15. Outputs switched OFF with D1 or D2

.

16. Parameter is guaranteed by design but not production tested.

17. Fault Status output is an open drain output requiring a pull-up resistor to 5.0 V.

18. Fault Status Leakage Current is measured with Fault Status High and not set.

19. Fault Status Set Voltage is measured with Fault Status Low and set with I

= 300 µA.

FS

A

V

33886

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

TIMING CHARACTERISTICS

OUT

(20)

(22)

= 3.0 A

(23)

PWM Frequency

Maximum Switching Frequency During Active Current Limiting

Output ON Delay

V+ = 14 V

Output OFF Delay

V+ = 14 V

Output Rise and Fall Time

V+ = 14 V, I

= 25°C under nominal conditions unless otherwise noted.

A

(21)

f

t

d

PWM

MAX

(ON)

––10kHz

––20kHz

––18

t

d (OFF)

––18

, t

t

f

r

2.0 5.0 8.0

µs

Output Latch-OFF Time

Output Blanking Time

Output FET Body Diode Reverse Recovery Time

Disable Delay Time

Short Circuit / Overtemperature Turn-

(25)

OFF Time

(26)

Power-OFF Delay Time

(24)

t

a

t

b

t

r r

t

d (disable)

t

FAULT

t

pod

15 20.5 26

12 16.5 21

100 – –

––8.0µs

–4.0–µs

–1.05.0ms

Notes

20. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer to Typical Switching Waveforms, Figures 10

through 17, pp. 10–11.

21. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.

22. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 4

23. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6

, page 8.

24. Parameter is guaranteed by design but not production tested.

25. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See

Figure 5

, page 8.

26. Increasing currents will become limited at I

state latch-OFF. See Figures 8 above 160

°C will cause the active current limiting to progressively “fold-back” (or decrease) to 2.5 A typical at 175°C where thermal

latch-OFF will occur. See Figure 7

and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature

, page 8.

. Hard shorts will breach the I

LIM

SCH

or I

limit, forcing the output into an immediate tri-

SCL

µs

ns

33886

Analog Integrated Circuit Device Data Freescale Semiconductor 7

TIMING DIAGRAMS

5.0

) V

(

2 N

I

,

1 N

I

V

0

V

)

PWR

V (

2

,

1 T U O

V

0

5.0 V

50%

t

d(ON)

50%

90%

TIME

Figure 4. Output Delay Time

t

d(OFF)

10%

0 V

∞Ω

0 Ω

Figure 5. Disable Delay Time

V

)

PWR

V

(

2

,

1 T U O

V

0

90%

t

f

10%

t

r

90%

Figure 6. Output Switching Time

) A

( T

6.5

6.6

N E R R U C

T

2.5

U

CURRENT (A)

P

,

T U

O

I

,

X A

M

I

LIM

160 175

TJ, JUNCTION TEMPERATURE (oC)

Thermal Shutdown

Figure 7. Active Current Limiting Versus Temperature (Typical)

33886

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

)

TIM

E

A (

T N E R R U C

T U P T

, CURRENT (A)

U O

,

OUT

D

I

A O

OUT

L

I

8.0

6.5

Diode Reverse

Re c o ve r y Sp i ke s

Load Capacitance and/or

Diode Reverse Recovery Spikes

I

Short Circuit Detect Threshold

SCL

Typ. Short Ckt. Detect Threshold

for Low-Side FETs

Typical Current Limiting Threshold

Typ. Curr ent Limit Threshold

PWM

Active

Current

Limiting

(See Figure 7)

(See Figure 6)

(See Figure 7)

Hard Short Detect an d Lat ch-OFF

Hard Short Detect and Latch-Off

0

N

I C

I G O

L ,

n

N

I

N

I C

I G O

L , 1 D

N

I C

I G O

L , 2

D

T U O

C

I G O

L , S

SF I

F

[1]

[0]

[1]

[0]

[1]

[0]

[1]

[0]

IN2 or IN1

IN1 OR IN 2

IN1 or IN2

IN2

Ou tp u ts

Outputs

Tristated

Tri-stated

IN1 IN2

IN1

IN2

Outputs

Tristated

Tri-stated

IN1 or IN2

IN2IN1

OR

IN2 or IN1

IN2 IN1OR

Outputs Operat ional

Outputs Operational

(per Input Contr ol Condition)

(per Input Control Condition)

Figure 8. Active Current Limiting Versus Time

OR IN1

) A

( T N

E R R U C

T U P T

, CURRENT (A)

U O

,

OUT

D

I

A O L

I

8.0

6.5

t

a

I

Short Circuit Detect Threshold

Overcurrent Minimum Threshold

SCL

ta = Output Latch-OFF Time

ta= Tristate Output OFF Time

t

b

= Output Blanking Time

t

= Current Limit Blank Time

b

Typical Current

Typical PWM Load

Limiting Waveform

Current Limiting Waveform

Hard Output

Hard Short Detect Short Latch-OFF

Latch-Off Prevented During t

b

TIME

Figure 9. Active Current Limiting Detail

33886

Analog Integrated Circuit Device Data Freescale Semiconductor 9

Freescale 33886 Technical Data

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 1. 33886 Simplified Application Diagram

INTERNAL BLOCK DIAGRAM

Figure 2. 33886 Simplified Internal Block Diagram

TERMINAL CONNECTIONS

Figure 3. 33886 Terminal Connections

Table 1. 33886 Terminal Definitions

MAXIMUM RATINGS

Table 2. Maximum Ratings

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

TIMING DIAGRAMS

Figure 4. Output Delay Time

Figure 5. Disable Delay Time

Figure 6. Output Switching Time

Figure 7. Active Current Limiting Versus Temperature (Typical)

Figure 8. Active Current Limiting Versus Time

Figure 9. Active Current Limiting Detail