Freescale 33780 Technical Data

Freescale Semiconductor

Advance Information

Dual DBUS Master with

Document Number: MC33780

Rev 4.0, 11/2006

Differential Drive and
Frequency Spreading

The 33780 is a master device for two differential DBUS buses. It
contains the logic to interface the buses to a standard serial
peripheral interface (SPI) port and the analog circuitry to drive data
and power over the bus as well as receive data from the remote slave
devices.

The differential mode of the 33780 generates lower electro­magnetic interference (EMI) in situations where data rates and wiring
make this a problem. Frequency spreading further reduces in­terference by spreading the energy across many channels, reducing
the energy in any single channel.

Features

• Two Independent DBUS I /Os

• Common SPI Interface for All Operations

• Open-Drain Interrupt Output with Pull-up

• Maskable Interrupts for Send and Receive Data Status

• Automatic Message Cyclical Redundancy Checking (CRC)

Generation and Checking

• Four-Stage Transmit and Receive Buffers

• 8- to 16-Bit Messages with 0- to 8-Bit CRC

• Independent Frequency Spreading for Each Channel

• Pb-Free Packaging Designated by Suffix Code EG

DIFFERENTIAL DBUS MASTER

ORDERING INFORMATION

Device

MC33780EG/R2
MCZ33780EG/R2

33780

EG (PB-FREE SUFFIX)

98ASB42567B
16-PIN SOICW

Temperature

Range (T

-40°C to 85°C 16 SOICW

)

A

Package

+5.0 V +25 V

MCU

VCC

SCLK

CS

MOSI
MISO

RST

INT

CLK

GND

VCC
SCLK

CS
MOSI

MISO
RST

INT
CLK

33780

VSUP

D0H
D0L

D1H
D1L

GND

Figure 1. 33780 Simplified Application Diagram

* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.

© Freescale Semiconductor, Inc., 2006. All rights reserved.

DSI/DBUS SLAVE

Twisted Pair

4.7 nF capacitors from D0H, D0L, D1H
and D1L to circuit ground are required
for proper operation.

33793

DSI/DBUS SLAVE

33793

INTERNAL BLOCK DIAGRAM

CLK

INTERNAL BLOCK DIAGRAM

VCC VSUP

Spreader

Protocol Engine

DSIF
DSIS

DSIR

DSIF
DSIS

DSIR

DBUS

Driver/Receiver

DBUS

Driver/Receiver

D0H
D0L

D1H
D1L

SCLK
MISO

MOSI

CS

INT

RST

SPI,

Registers and

Interrupt

Generator

Figure 2. 33780 Internal Block Diagram

T

LIM

GND
GND
GND

33780

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

PIN CONNECTIONS

PIN CONNECTIONS

RST

CS

INT
MOSI
SCLK
MISO

CLK

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND
D0L
D0H
VSUP
D1H
D1L
GND
VCC

Figure 3. 33780 Pin Connections

Table 1. 33780 Pin Definitions

A functional description of each pin can be found in the Functional Pin Descriptions section beginning on page 13.

Pin Pin Name Pin Function Formal Name Definition

1 RST Reset IC Reset

2 CS Input SPI Chip Select Input

3 INT Output Interrupt Output

4 MOSI Input Master Out Slave In

5 SCLK Input Serial Data Clock

6 MISO Output Master In Slave Out

7 CLK Input Clock Input
8 GND Ground Ground

9 VCC Input Logic Supply
10 GND Ground Power Ground
11 D1L Output Driver Low-Side Bus 1
12 D1H Output Driver High-Side Bus 1
13 VSUP Output Positive Supply for

Bus Output
14 D0H Output Driver High-Side Bus 0
15 D0L Output Driver Low-Side Bus 0
16 GND Ground Power Ground

A low level on this pin returns all registers to a known state as indicated
in the section entitled

Register and Bit Descriptions.

When this signal is high, SPI signals are ignored. Asserting this pin low
starts an SPI transaction. The SPI transaction is signaled as completed
when this signal returns high.

This output will be asserted low when an enabled interrupt condition
occurs. It contains a pullup current source that will perform a pullup when
unasserted.

SPI data into this IC. This data input is sampled on the positive edge of
SCLK.

Clocks in /out the data to/from the SPI. MISO data changes on the
negative transition of the SCLK. MOSI is sampled on the positive edge of
the SCLK.

SPI data sent to the MCU by this device. This data output changes on the
negative edge of SCLK. When

CS is high, this pin is high impedance.

4.0 MHz clock input.
Ground reference for analog and digital circuits.
Logic power source input.
Bus 1 power return.
Bus 1 low side.
Bus 1 high side.
This supply input is used to provide the positive level output of the bus.

Bus 0 high side.
Bus 0 low side.
Bus 0 power return.

33780

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Supply Voltages

V

SUP

Load Dump V
V

CC

(300 ms maximum)

SUP

Maximum Voltage on Logic Input /Output Pins
Maximum Voltage on DBUS Pins
Maximum DBUS Pin Current
Maximum Logic Pin Current
ESD Voltage 1

Human Body Model (HBM)
Machine Model (MM)
Charge Device Model (CDM)

THERMAL RATINGS

Storage Temperature
Operating Ambient Temperature
Operating Junction Temperature
Thermal Shutdown
Resistance, Junction-to-Ambient
Resistance, Junction-to-Board
Peak Package Reflow Temperature During Reflow

(2), (3)

Notes

1. ESD1 testing is performed in accordance with the Human Body Model (HBM) (C
performed in accordance with the Machine Model (MM) (C

= 200 pF, R

ZAP

2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

V

SUP

V

SUPLD

V

CC

– -0.3 to V

V

DBUS

I

DBUS

I

LOGIC

V

ESD

-0.3 to 26.5
40

-0.3 to 7.0
+ 0.3 V

CC

-0.3 to V

+ 0.3 V

SUP

400 mA

20 mA

±2000

±200

±750 for corner pins

±500 for others

T

STG

T

A

T

J

T

SD

R

JA

Θ

R

JB

Θ

T

PPRT

= 100 pF, R

ZAP

= 0 Ω); and Charge Body Model (CBM).

ZAP

-55 to 150 °C

-40 to 85 °C

-40 to 150 °C

155 to 190 °C

109 °C/W

50 °C/W

Note 3 °C

= 1500 Ω); ESD2 testing is

ZAP

V

V

33780

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ V
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

≤ 25 V,- 40°C ≤ T

SUP

≤ 85°C unless otherwise

A

POWER INPUT REQUIREMENTS (V

I

Supply Current (| I

VSUP

| ≤ 10 µA) (Test Mode, CLK = 4.0 MHz)

BUS

SUP

, VCC)

Idle, HiZ
Signal High, Signal Low

I

Supply Current (Test Mode, CLK = 4.0 MHz)

VCC

Signal High, Signal Low

MICROCONTROLLER INTERFACE (RST, CS, MOSI, SCLK, AND CLK)

I / O Logic Levels (RST, CS, MOSI, SCLK, and CLK)

Input High
Input Low

Input Hysteresis

Input Capacitance

(4)

(4)

RST, CS, MOSI, SCLK, and CLK

Output Low Voltage

MISO and INT Pins = 0.3 mA

Output High Voltage

MISO Pin = - 0.3 mA

Output Leakage Current

MISO Pin = 0 V
MISO Pin = V

CC

INT Pullup Current

V

= V

CC

- 1.0 V

OUT

SCLK, CS Pullup Current

V

= V

CC

- 1.0 V

OUT

RST Pulldown Current

V

= 1.0 V

OUT

CLK, MOSI Pulldown Current

V

= 1.0 V

OUT

BUS TRANSMITTER (D0H, D0L, D1H, D1L)

Output Bus Idle Voltage (Differential)

InH = -200 mA, InL = 200 mA

(5)

Output Signal High Voltage (Differential)

-12.5 mA ≤ InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA

(5)

Notes

4 Not measured in production.
5 InH = bus current at DnH, InL = bus current at DnL.
6V

DnD

= V

DnH

- V

DnL

.

I

VSUP

I

VCC

V
V

V

HYST

C

V

OL

V

OH

I

MISO

I

INTPU

I

PU

I

RSTPD

I

PD

V

DnD(

IDLE)

V

DnD (HIGH)

mA
–
–

6.5
15

10
23

mA

– 4.5 6.0

IH
IL

I

0.7
–
–

–
–

500

0.3

–

–

V
V

mV

CC
CC

pF

– 10 20

V

0 – 0.8

V

V

- 0.8 – V

CC

CC

µA

-10

-10

–
–

10
10

µA

-100 -75 -50
µA

-20 -10 -5.0
µA

4.0 7.0 10
µA

5.0 10 20

(6)

V

- 2.5 – –

SUP

(6)

V

V

4.175 4.5 4.825

33780

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ V

≤ 25 V,- 40°C ≤ T

SUP

≤ 85°C unless otherwise

A

noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Output Signal Low Voltage (Differential)

-12.5 mA ≤ InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA

(5)

Vmid, (DnH + DnL) / 2 (Voltage Halfway Between Bus High Side and
Bus Low Side)

VCM Peak-to-Peak, Vmid (Signal High) - Vmid (Signal Low)

(7)

Output High-Side (DnH) Idle Driver Current Limit (DnL open)

Source: DnH = 0 V
Sink: DnH = V

SUP

Output Low-Side (DnL) Idle Driver Current Limit (DnH open)

Source: DnL = 0 V
Sink: DnL = V

SUP

Output High-Side (DnH) Signal Driver Overcurrent Shutdown

Source: Signal High, Signal Low
Sink: Signal High, Signal Low

Output Low-Side (DnL) Signal Driver Overcurrent Shutdown

Source: Signal High, Signal Low
Sink: Signal High, Signal Low

Disabled High-Side (DnH) Bus Leakage (DnL open)

DnH = 0 V
DnH = V

SUP

Disabled Low-Side (DnL) Bus Leakage (DnH open)

DnL = 0 V
DnL = V

SUP

BUS RECEIVER (D0H, D0L, D1H, D1L)

Comparator Trip Point

Notes

7 Not measured in production.

V

DnD (LOW)

I

ICL (HIGH)

I

ICL (LOW)

I

SCL (HIGH)

I

SCL (LOW)

I

LK(HIGH)

I

LK(LOW)

COMP(TRIP) 5.0 6.0 7.0 mA

(6)

V

1.175 1.5 1.825

V

mid

V

CM

pp

V

/ 2 -

V

SUP

1.0

/ 2 V

SUP

SUP

2 + 1.0

/

– 0.3 – V

V

mA

-400
100

–
–

-200
–

mA

–

200

–
–

-100

400

mA

-100
30

–
–

-30

100

mA

-100
30

–
–

-30

100

mA

-1.0

-1.0

-0.18

0.25

1.0

1.0
mA

-1.0

-1.0

-0.4

0.08

1.0

1.0

33780

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ V
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

CLOCK

CLK Periods

Time High
Time Low

Period (System requirement)

CLK Transition (System requirement)

(8)

(8)

Time for Low-to-High Transition of the CLK Input Signal
Time for High-to-Low Transition of the CLK Input Signal

Reset Low Time

SPI INTERFACE TIMING

SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
SPI CS Lead Time
SPI CS Lag Time
SPI SCLK Time Between Bytes
SPI CS Time Between Bursts

(9)

(9)

(8)

(8)

Data Setup Time

MOSI Valid Before SCLK Rising Edge

(9)

Data Hold Time

MOSI Valid After SCLK Rising Edge
MISO Valid After SCLK Falling Edge

(9)

(8)

Data Valid Time

SCLK Falling Edge to MISO Valid, C = 100 pF

Output Disable Time

CS Rise to MISO Hi-Z

Rise Time (30% VCC to 70% VCC)

(8)

SCLK, MISO

Fall Time (70% VCC to 30% VCC)

(8)

SCLK, MISO

Notes

8 Not measured in production.
9 SPI signal timing from the production test equipment is programmed to ensure compliance.

tCLKHI

tCLKLO

tCLKPER

tCLKLH
tCLKHL

tRSTLO 100 – – ns

tCYC 200 – – ns

tLEAD 100 – – ns

tLAG 100 – – ns

tCSHI 80 – – ns

≤ 25 V, - 40°C ≤ TA ≤ 85°C unless otherwise

SUP

75
75

245

–
–

–
–

250

–
–

–
–

255

50
50

tHI 80 – – ns

tLO 80 – – ns

tHI 80 – – ns

tSU

25 – –

tH

tHO

t

V

25

–

0

–

–
–

– – 50

t

DIS

– – 100

t

R

– – 25

t

F

– – 25

ns

ns

ns

ns

ns

ns

ns

ns

33780

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ V

≤ 25 V, - 40°C ≤ TA ≤ 85°C unless otherwise

SUP

noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

BUS TRANSMITTER

(10), (13)

(14)

(14)

(10)

t

SLEW (IDLE)

t

SLEW (SIGNAL)

D

RATE

t

BIT

t

INTON

t

INTON

t

INTOFF

t

DBUSSTART1

t

DBUSSTART2

t

DVLD1

t

DVLD2

t

DVLD3

t

DVLD4

2.0 4.5 8.0 V/µs

3.0 4.5 8.0 V/µs

– – 150 kbps

6.67 – – µs
– – 1/3 * tBIT

+0.2

– – 0.2
– – 0.2 µs

1/3 * t
1/3 * t

0.25

0.25

BIT
BIT

–

–

–
–

6.0

0.8

0.8

0.8

2/3 * t
4/3 * t

6.56

1.3

1.3

1.3

BIT
BIT

Idle-to-Signal and Signal-to-Idle Slew Rate (12 ≤ V

SUP

≤ 25 V)

Signal High-to-Low and Signal Low-to-High Slew Rate
(See Data Valid DSIS to DnD Timing)

Communication Data Rate Capability

(13)

(Ensured by Transmitter Data

Valid and Receiver Delay Measurements)
Signal Bit Time (1 / D

INT Turn ON Delay, DBUS Transaction End to Receive FIFO
INT Low

INT Turn ON Delay (C = 100 pF)

INT Turn OFF Delay, CS/SCLK Rising Edge to INT High

(11), (15)

CS to INT Low

DBUS Start Delay, CS/SCLK Rising Edge to DBUS

RATE

(13)

)

(12)

(11), (13), (15)

Spread Spectrum Mode Disabled
Spread Spectrum Mode Enabled

Data Valid

(10), (12)

DSIF (CS) = 0.5 * VCC to DnD Fall = 5.5 V
DSIS (MOSI) = 0.5 * VCC to DnD Fall = 0.2 * ∆V
DSIS (MOSI) = 0.5 * VCC to DnD Rise = 0.8 * ∆V

DnD

DnD

DSIF (CS) = 0.5 * VCC to DnD Rise = 6.5 V

µs

µs

µs

µs

Signal Driver Overcurrent Shutdown Delay
Signal Low Time for Logic Zero

33.3% Duty Cycle

(16)

Signal Low Time for Logic One

66.7% Duty Cycle

(16)

t

OC

t0

L

O

t1

L

O

2.0 – 20 µs

2/3 * t

1/3 * t

-0.8 2/3 * t

BIT

-0.8 1/3 * t

BIT

-0.6 2/3 * t

BIT

-0.6 1/3 * t

BIT

BIT

BIT

µs

-0.4
µs

-0.4

Notes

10 C = 7.5 nF from DnH to DnL and 4.7 nF from DnH and DnL to GND, capacitor tolerance = ±10%.
11 In the case where the SPI write to DnL (initiating a DBUS transaction start or causing an interrupt) is the last byte in the burst sequence,

timing is from rising edge of

CS. Otherwise, timing is from the first SCLK rising edge of the next SPI burst byte.

12 Delays are measured in test mode to determine the delay for analog signal paths.
13 Not measured in production.
14 ∆V

DnD

= V

DnD(HIGH)

- V

DnD(LOW).

15 Internal digital delay only.
16 Guaranteed by design.

33780

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ V

≤ 25 V, - 40°C ≤ TA ≤ 85°C unless otherwise

SUP

noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

BUS RECEIVER

Receiver Delay Time (I

I

= -6.0 mA to DSIR (INT) = 0.5 * V

RSP

I

= -6.0 mA to DSIR (INT) = 0.5 * V

RSP

Receiver Delay Time (I

2.0

mA step)
I

RSP

I

RSP

(17)

= COMP(TRIP) to DSIR (INT) = 0.5 * V
= COMP(TRIP) to DSIR (INT) = 0.5 * V

= 0 mA / 11 mA step)

RSP

= COMP(TRIP) - 2.0 mA/COMP(TRIP) +

RSP

SPREAD SPECTRUM

Central Frequency Range
Bit Period Deviation (+/-) (f

CEN

Min ≤ f

CEN

DEV[1:0] = 10
DEV[1:0] = 01 @ f

Frame Jitter (Max) (f

=138.5KHz (Typ)

CEN

Min ≤ f

CEN

CEN

≤ f

CEN

DEV On
DEV Off

Notes

17 Delays are measured in test mode to determine the delay for analog signal path.

(17)

CC
CC

CC
CC

≤ f

Max)

CEN

Max) (PLL On)

t

DRH

t

DRL

t

DRH

t

DRL

f

CEN

t

DEV10

t

DEV01

J

FRDEVON

J

FRDEVOFF

250
250

500
500

–
–

–
–

750
750

1500
1500

132 – 148 kHz

400
800

–
–

–
–

–
–

600

1100

±1.0
±1.0

ns

ns

ns

µs

33780

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

TIMING DIAGRAMS

DSIS

DSIF

DnD

DSIR

5.0 V

0 V

5.0 V

0 V

V

SUP

6.5 V

5.5 V

4.5 V

3.9 V

2.1 V

1.5 V

I

OUT

6.0 mA
0 mA

5.0 V

0 V

t

CYC

t

DVLD1

t

CYC

t

CYC

t

CYC

Logic 1 Logic 0

t

t

SLEW(FRAME)

t

DVLD3

t

DVLD2

t1

LO

t

DRH

t

DRL

t

SLEW(SIGNAL)

t0

LO

DVLD4

Figure 4. DBUS Timing Characteristics

33780

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

DnH

V

V

V

V

DnL

DnH

+ 2.25 V

mid

+ 0.75 V

mid

- 0.75 V

mid

- 2.25 V

mid

V

V

SUP

V

SUP

mid

0 V

Figure 5. DBUS Normal Bus Waveforms

Overvoltage

Threshold

V

mid

V

mid

V

(Clamped)

mid

V

mid

V

mid

DnL

+ 2.25 V

+ 0.75 V

- 0.75 V

- 2.25 V

0 V

Figure 6. DBUS Overvoltage Bus Waveforms

33780

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

CS

SCLK

MOSI

MISO

X = Don’t care
V

V

V

IL

t

LEAD

V

IH

V

IL

t

V

IH

V

IL

t

OH

OL

A

X

V

V

= 70% VCC, VOH = 70% V

IH

= 30% VCC, VOL = 30% V

IL

SU

MSB

t

H

MSB

CC
CC

V

IH

V

t

CYC

t

HI

t

LO

t

V

t

F

V

IH

t

HO

t

R

V

IH

LSB

V

IL

LSB

LSB

t

LAG

t

DIS

IL

V

IH

V

OH

V

OL

Figure 7. SPI Interface Timing

DBUS

(DnH-DnL)

INT

CS

SCLK

MOSI

t

INTON

Figure 8. INT and Bus Start Timing

t

DBUSSTART

t

INTOFF

33780

Analog Integrated Circuit Device Data

12 Freescale Semiconductor