Power Management IC with Five
Regulated Outputs
Programmed Through 3-Wire
Document order number: MPC18730
Rev 1.0, 10/2005
18730
Serial Interface
The MPC18730 Power Management IC (PMIC) regulates five
independent output voltages from either a single cell Li-Ion (2.7
4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to
V input range).
2.2
The PMIC includes 2 DC-DC converters and 3 low drop out (LDO)
linear regulators. The output voltage for each of the 5 output voltages
is set independently through a 3-wire serial interface. The serial
interface also configures the PMIC's versatile start-up control system,
which includes multiple wakeup, sleep, standby, and reset modes to
minimize power consumption for portable equipment.
In single cell Li-Ion applications two DC-DC converters are
configured as buck (step-down) regulators. In single cell Ni-MH or dry
cell applications, one DC-DC converter is configured as a boost
(step-up) regulator, and the other as buck-boost regulator. The DCDC converters' output voltages have set ranges 1.613
V to 3.2 V at
up to 120 mA, and 0.805 V to 1.5 V up to 100 mA through the serial
interface.
Features
• Operates from single cell Li-Ion, Ni-MH, or Alkaline
• 2 DC-DC Converters
• 3 Low Drop Regulators
• Serial Interface Sets Output Voltages
• 4 Wake Inputs
• Low Current Standby Mode
• Pb-Free Packaging Designated by Suffix Code EP
2.7 V to 4.2 V Input
VO
VB
MPC18730
VB
VREF
V to
VCC1
SW1
POWER MANAGEMENT IC
EP SUFFIX
98ARL10571D
64-TERMINAL 0.5 mm PITCH
QFN
ORDERING INFORMATION
Device
MPC18730EP/R2-10°C to 65°C64 QFN
VO1
Temperature
Range (T
)
A
Programmable
1.613 V to 3.2 V
Programmable
0.805 V to 1.5 V
Package
RSTO1B
EXT_G_ON
VO
RSTO2B
MCU
CONTROL
LOGIC
INPUTS
GND
PGND
Figure 1. MPC18730 Simplified Application Diagram
* This document contains information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal
Number
43DW_2TOutputStep Down Top FET 2
44DW_2BOutputStep Down Bottom
45EXT_G_ONOutputGate Switch
46SREGC3PowerRegulator Capacitor 3
47SREGO3OutputRegulator Output 3
48SREGI3PowerRegulator Input 3
49SREGC2PowerRegulator Capacitor 2
50SREG2GOutputRegulator Gate Output
51SREGO2OutputRegulator Output 2
52SREGI2PowerRegulator Input 2
53SREGC1PowerRegulator Capacitor 1
54SREGO1OutputRegulator Output 1
55SREGI1PowerRegulator Input 1
56GNDGroundGround
57VREFOutputReference Voltage
58DATAInputData Signal
59STRBInputStrobe
60SCKINInputSerial Clock
61WDTInputWatch Dog Timer
62SEQSELInputSequence Input
63CLKINInputClock Input
64SLEEPInputSleep Signal
Terminal
Name
Terminal
Function
Formal NameDefinition
FET 2
2
Switching Power Supply Circuit 2 Step down Top side FET Gate Output
for Ni_mh
Switching Power Supply Circuit 2 Step down Bottom side FRT Gate
Output for Ni_mh
External Transistor Gate Signal Output
Series Pass Power Supply Circuit 3 External Feedback Connection
Series Pass Power Supply Circuit 3 Output
Series Pass Power Supply Circuit 3 Power Supply
Series Pass Power Supply Circuit 2 External Feedback Connection
Series Pass Power Supply Circuit 2 External Transistor Gate Signal
Output
Series Pass Power Supply Circuit 2 Output
Series Pass Power Supply Circuit 2 Power Supply
Series Pass Power Supply Circuit 1 External Feedback Connection
Series Pass Power Supply Circuit 1 Output
Series Pass Power Supply Circuit 1 Power Supply
GND
Reference Voltage Output
Serial Interface Data Signal Input
Serial Interface Strobe Signal Input
Serial Interface Clock Signal Input
Watchdog Timer Capacitor Connection
Start-Up Sequence Setting Input
External Synchronous Clock Signal Input
Sleep Signal Input
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor5
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
RatingsSymbolValueUnit
ELECTRICAL RATINGS
Power Supply Voltage
Analog Signal Input
(1)
Logic Signal Input
WAKE1~4B
CLR, SLEEP, CLKIN, SCKIN, DATA, STRB
VGSEL1,2
Output Power Current
V
Power Supply Circuit
CC1
V
Power Supply Circuit
CC2
(2)
SREG1 Power Supply Circuit
SREG2 Power Supply Circuit
SREG3 Power Supply Circuit
VG Power Supply Circuit
RSTO1B Power Supply Circuit
Open-Drain Output Apply Voltage
RSTO1B
LSWO
ESD Voltage
Human Body Model (HBM)
Machine Model (MM)
(3)
(4)
Charge Device Model (CDM)
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Thermal Resistance
(5)
Junction to Ambient
Lead Soldering Temperature
(6)
Notes
1. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.
2. Includes the series pass power supply circuit output current.
3. ESD1 testing is performed in accordance with the Human Body Model (C
4. ESD2 testing is performed in accordance with the Machine Model (C
module specification with a capacitor 0.01
µF connected from OUT to GND.
ZAP
= 200 pF, R
ZAP
5. Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7.
6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
V
B
V
INAN
V
ILRSTB
V
ILGC
V
ILGSEL
I
OVO1
I
OVO2
I
OREG1
I
OREG2
I
OREG3
I
OVG
I
ORSTB
V
IODR
V
IODV
V
ESD1
V
ESD2
V
CDM
T
A
T
J
T
STG
R
JA
θ
T
SOLDER
= 100 pF, R
ZAP
-0.5 to 5.0V
-0.5 to VO1+0.5V
-0.5 to V_STBY+0.5
-0.5 to VO1+0.5
-0.5 to VB+0.5
mA
120
100
80
100
80
8
-20
-0.5 to 3.3
-0.5 to 3.3
± 1500
± 200
± 750
°C
-10 to 65
150
-50 to 150°C
69°C/W
260°C
= 1500 Ω).
ZAP
= 0 Ω) and in accordance with the system
V
V
V
18730
Analog Integrated Circuit Device Data
6Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f
values noted reflect the approximate parameter means at T
CharacteristicSymbolMinTypMaxUnit
GENERAL
VB Power Supply Voltage
Power Supply Voltage 1
Power Supply Voltage 2
Series Regulator Input Voltage
Start-Up Voltage
Analog Signal Input
(10)
Logic Signal Input
RSTO1 ~ 4B
CLR, SLEEP, CLKIN, DATA, STRB and SCKIN
VGSEL1, 2
Output Power Current
V
Power Supply Circuit
CC1
V
Power Supply Circuit
CC2
SREG1 Power Supply Circuit
SREG2 Power Supply Circuit
SREG3 Power Supply Circuit
VG Power Supply Circuit
RSTO
Supply Current in Stand-by mode
VB Supply Current (VB = 1.2 V for Ni_MH)
(HVB = 3.5 V for Li-Ion)
Supply Current in Operating mode
VB Supply Current (VB = 1.2 V for Ni_MH)
(HVB = 3.5 V for Li-Ion)
Reference Power Supply Circuit
Output Voltage
Output Current
Switching Power Supply 1
V
Output Voltage (Io = 0~100 mA)
CC1
Notes
7. When applying voltage from an external source.
8. 0.3 V when VG is 4.5 V.
9. Provide 2 V or higher for the voltage difference (VG - VO1).
10. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.
11. Includes the series pass power supply circuit output current.
(7), (8)
(11)
(11)
= 27°C under nominal conditions unless otherwise noted.
A
V
LVB
V
HVB
V
SREGI
V
BST
V
IANA
V
ILRSTB
V
ILGC
V
ILGSEL
I
OVCC1
I
OVCC2
I
OSREG1
I
OSREG2
I
OSREG3
I
OVG
I
ORSTB
I
BSNi
I
BSLi
I
BNi
I
BLi
V
REF
I
OREF
V
CC1
STATIC ELECTRICAL CHARACTERISTICS
= 176.4 kHz unless otherwise noted. Typical
CLK
V
SREG
0.9
2.7
+0.2
(9)
V
1.2
3.5
SREG
+0.3 V
2.2
4.2
+0.4V
SREG
0.9--V
0-V
0
0
0
0
0
5
6
5
0
-5
-
-
-
-
1.255
-0.3
-
-
-
-
-
-
-
-
-
-
5
8
9
7
1.275
-
O1
V_STBY
VO1
VB
100
80
60
80
60
6
0
10
12
18
14
1.295
0.3
2.32.42.5V
V
V
V
mA
mA
mA
V
mA
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor7
STATIC ELECTRICAL CHARACTERISTICS
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f
= 176.4 kHz unless otherwise noted. Typical
CLK
values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.
CharacteristicSymbolMinTypMaxUnit
Switching Power Supply 2
V
Output Voltage (Io = 0~80 mA)
CC2
DW_2T Output Voltage
(I
= 400 µA)
sink
DW_2B Output Voltage
(I
= 400 µA)
sink
(12)
(12)
(I
(I
source
source
= 400 µA)
= 400 µA)
Series Pass Power Supply Circuit
SREG1 Control Voltage (Io = 5~60 mA)
SREG1-Error AMP Input offset voltage
SREG2 Control Voltage (Io = 6~80 mA)
SREG2-Error AMP Input offset voltage
SREG3 Control Voltage (Io = 5~60 mA)
SREG3-Error AMP Input offset voltage
SREG2G Output Voltage
(I
= 2.5 µA)
sink
(17)
(I
source
(13)
(14)
(13)
(15)
(13)
(16)
= 2.5 µA)
Power Switch On Resistance
V
Circuit
CC1
V
Circuit
CC2
VG Power Supply Circuit
(Io = 0~6 mA)
(Io = 0~6 mA)
C1L Output Voltage (I
(I
= 2.5 mA)
sink
(18)
(19)
source
= 2.5 mA)
VGH Voltage (Certified value)
V_STBY Output Voltage for Li_ion (Io = 300 µA)
(20)
Notes
12. Connect a transistor with gate capacity of 200 pF or smaller to DW_2T and DW_2B
13. If a capacitor with capacitance of 22µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC
when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is
connected as follows:
SREGI1 = 3.0V to 3.3V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.
SREGI2 = 3.0V to 3.3V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.
SREGI3 = 3.0V to 3.3V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.
14. Calculated by the right formula for input offset: SR1OFST=(Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k))
15. Calculated by the right formula for input offset: SR2OFST=(Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k))
16. Calculated by the right formula for input offset: SR3OFST=(Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k))
17. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.
18. When VGSEL1 is Low and VGSEL2 is Low, I/O=3mA or higher is certified by specification.
19. When VGSEL1 is High and VGSEL2 is Low, I/O=3mA or higher is certified by specification.
20. When HVB is 4.2V and the load from V_STBY is 0.5µA or higher.
Analog Integrated Circuit Device Data
Freescale Semiconductor13
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 18730 power management integrated circuit provides
five independent output voltages for the micro controller from
either a single cell Li-Ion or from a single cell Ni-MH or dry
cell. The PMIC includes two DC to DC converters and three
low drop out linear regulators. The output voltage for each of
the five output voltages is set independently through a 3-wire
serial interface. The PMIC has multiple wakeup, sleep, and
FUNCTIONAL TERMINAL DESCRIPTION
CLEAR TERMINAL (CLR)
This Clear input signal makes clear internal latches for
WAKE signal holding. The WAKE control circuit can not
receive another WAKE input until the latch is cleared by this
Clear input.
WAKE SIGNAL TERMINALS (WAKE1B, WAKE2B,
WAKE3B, WAKE4B) ... ACTIVE LOW
Any one WAKE input signal of these four WAKE inputs
awakes this device from sleep mode. The WAKE signals can
be made with external low side mechanical switch and
resistance that is pulled up to VSTB rail.
LOW-SIDE SWITCH OUTPUT TERMINAL (LSWO)
Low-Side switch output that is turned on with ‘CLR’ signal.
It can be used for external key input latches clear.
LOW VOLTAGE BATTERY TERMINAL (LVB)
This input terminal is used for temporarily power supply
while wake up for 1cell Ni-MH battery or 1cell dry cell battery
(= Low Voltage Battery) use. It has to be connected to VB rail.
When Li-Ion battery is used, the terminal has to be open.
HIGH VOLTAGE BATTERY TERMINAL (HVB)
This input terminal is used for temporarily power supply
while wake up for Li-Ion battery (= High Voltage Battery) use.
It has to be connected to the VB rail. When a Ni-MH battery
is used, the terminal has to be connected to ground level.
STANDBY VOLTAGE TERMINAL (V_STBY)
Standby Voltage is made from LVB or HVB that depends
on which battery is used. This voltage is used for internal
logic and analog circuit at standby (sleep) mode temporarily
before ‘VO1’ voltage is established.
VOLTAGE INPUT TERMINALS (VO1, VO2)
This power supply input terminal named ‘VO1 or VO2’ is
for internal logic and analog circuits and for input of ‘VCC1’
output via power switch. Input for ‘VCC2’ is ‘VO2IN’ terminal.
It is supplied from the output of Channel-1 or Channel-2 DC/
DC converter as ‘VO1 or VO2.
reset modes to minimize power consumption for portable
equipment. In single cell Li-Ion applications two DC-DC
converters are configured as buck regulators. In single cell
Ni-MH or dry cell applications, one DC-DC converter is
configured as a boost regulator, and the other as buck-boost
regulator.
VOLTAGE OUTPUT TERMINALS (VCC1, VCC2)
Output ‘VO1’ or ‘VO2’ voltage controlled internal power
switch.
POWER INPUT TERMINALS (VI1, VI2)
The power input terminals (VI1, VI2) are drain terminals on
the top side FET of the DC/DC converter switcher. They are
the power input for the buck converter and output for the
boost converter.
SWITCHING TERMINALS (SW1, SW2)
Switching Terminals (SW1, SW2) are the output of the half
bridge and connect to the external inductance.
POWER GROUND TERMINALS (PGND1, PGND2,
PGND3)
Ground level node for DC/DC converter and Charge Pump
portion.
INVERTED RESET OUTPUT TERMINALS (RSTO1B,
RSTO2B)
Reset signal output for external MPU or the something
controller. RSTO1B keeps ‘Low’ level while the VO1 voltage
is less than internal reference voltage. RSTO2B follows to
VO2 voltage.
RESET DELAY CAPACITOR TERMINALS (CRST1,
CSRT2)
The capacitor which is connected to this terminal decide
delay time to negate Reset signal from exceeding the
reference voltage level.
RESET 1 ADJUSTMENT TERMINAL (RST1ADJ)
Used to adjust the reset level with external resistance
which is connected to VO1 for RSTO1B.
DUTY CONTROL TERMINALS (DTC1, DTC2)
Connected external voltage to this terminal via
capacitance can control the duty of DC/DC converter
switching. Use of the terminal for this is not recommended.
18730
Analog Integrated Circuit Device Data
14Freescale Semiconductor
FUNCTIONAL TERMINAL DESCRIPTION
FUNCTIONAL DESCRIPTION
REFERENCE FEEDBACK TERMINALS (RF1, RF2)
Output node of internal error amp. for DC/DC converter 1
and 2. For phase compensation use.
INPUT MINUS TERMINALS (INM1, INM2)
Minus input of internal error amp. for DC/DC converter 1
and 2. For phase compensation use.
CHARGE PUMP CAPACITOR TERMINAL (C1L)
In case of use higher voltage than VG externally, connect
capacitance and diodes between VG. The charge pump
structure can output VG + VB - 2 x VF voltage. There is no
meaning for Ni-MH or dry cell battery, because the VB
voltage is almost same as 2 x VF voltage. Recommend to use
for Li-Ion battery use.
GATE VOLTAGE TERMINAL (VG)
Output terminal of boost converter for gate drive voltage.
The output voltage is decided by VGSEL input.
SWITCHING FOR GATE VOLTAGE TERMINAL
(SWG)
Switching terminal for VG boost converter. Connect to
external inductance.
BATTERY VOLTAGE TERMINAL (VB)
Power supply input that connects to Ni-MH or Dry cell or
Li-Ion battery.
VG SELECT TERMINALS (VGSEL1, VGSEL2)
VG output voltage is decided with these two bits input.
VOLTAGE INPUT FOR POWER SWITCH 2
TERMINAL (VO2IN)
Input of VCC2 output via power switch. Connect to VO2
terminal externally.
STEP DOWN FET GATE DRIVE TERMINALS
(DW_2T, DW_2B)
Gate drive output terminals for external FETs to use DC/
DC converter 2 as Buck / Boost converter.
GATE SWITCH TERMINAL (EXT_G_ON)
Gate drive output terminal for external low side switch. It
can be used for power switch turning On/OFF for remote
controller part.
Input the feed back voltage that divided SREGO voltage by
resistances.
Series regulator power input terminals. To be connected to
battery voltage in general.
GROUND TERMINAL (GND)
Ground terminal for logic and analog circuit portion (not
power portion). Recommend to connect to clean ground
which separated with power ground line.
REFERENCE VOLTAGE TERMINAL (VREF)
Output of internal reference voltage. It can be used
externally. Output current capacity is less than 300uA.
DATA INPUT TERMINAL (DATA)
Serial data input terminal. The latest 12 bits before strobe
signal are valid.
STROBE TERMINAL (STRB)
Strobe signal input terminal for serial I/F. It establishes the
input 12bits data to internal control registers.
SERIAL CLOCK TERMINAL (SCKIN)
Clock input terminal for serial I/F. Input data are taken in to
I/F with this clock.
WATCH DOG TIMER TERMINAL (WDT)
Watch dog timer prevent unstable wake up (flips between
wake-up and failure). If there is no ‘CLR’ input after any
WAKEnB input before this WDT is expired, this device move
to ‘SLEEP’ mode to prevent wake failure hanging-up
situation.
SEQUENCE SELECT TERMINAL (SEQSEL)
Select judgement Reset channel for wake-up complete
with this input. If this input level is VSTB voltage, this device
judges the wake-up completion with Reset2 (DC/DC2). If it is
Ground, judge with Reset1 (DC/DC1). See
13.
Table 7, on page
REGULATOR CONTROL TERMINALS (SREGC1,
SREGC2, SREGC3)
Feed back terminal for each series regulators. This
terminal voltage is compared with internal reference voltage.
Analog Integrated Circuit Device Data
Freescale Semiconductor15
CLOCK INPUT TERMINAL (CLKIN)
Clock input terminal for internal switching part. This device
has a oscillator internally, but can be used this input clock for
internal switching frequency. It is selected by Clock select bit.
Table 19, on page 26.
See
18730
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
SLEEP MODE TERMINAL (SLEEP)
The sleep input signal puts the device in sleep mode. All
output voltages are down, and internal current consumption
will be minimum.
18730
Analog Integrated Circuit Device Data
16Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
START-UP CONTROL INPUT (SYSTEM CONTROL)
The latch is set at the rising edge of any WAKE1B-4B input
pin, and WAKE(int) goes High. WAKE1~4B inputs consist of
OR logic. At this time, the input pin which went Low keeps
latched until CLR goes High. After the latch is reset by CLR,
WAKE(int) goes Low when SLEEP goes High. The latch is
also cleared and WAKE(int) goes Low when SLEEP goes
High before the latch is cleared by CLR. In this case, CLR
keeps negated while RSTO1B, 2B(Ext) is Low. SLEEP keeps
negated while RSTO1B, 2B(Ext) is Low or CLR is High. The
period of time for which CLR and SLEEP are negated can be
set by the SEQSEL pin. Refer to Truth
for the correspondence between the SEQSEL pin settings
and negation period.
WAKEB
CLR
WDT
WAKE(Int)
Table 5, on page 13
Time specified by WDT
If SLEEP goes High to place the chip into the standby
mode while any of the WAKEB pins is Low, the chip can be
awakened again. This may happen if, when an WAKEB pin
and LSWO are connected, SLEEP goes High earlier than the
period of time (*1) specified by the external component of the
WAKEB pin.
Also, if the period of time after WAKE(int) goes High until
CLR goes High from Low is longer than the time specified by
WDT, internal sleep will start up to place the chip into the
standby mode.
(*1: It is 30 µsec when a capacitor is not connected as the
external component.)
STANDBY POWER SUPPLY CIRCUIT
CLR
HVB
RST1B
RST1B(Int)
Standby
Power
Supply
Control
Figure 7. Standby Power Supply Circuit Diagram
Figure 6. Start-Up Timing Diagram
LSWO
Short-circuit VB and LVB, and connect a Schottky
diode between VB and V_STBY only when using
Ni_mh.
When using Li_ion, leave LVB open, and shortcircuit HVB and VB.
VO1
VB
V_STBY
VB
LVB
V_STBY
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
When RSTO1B(int) is Low, output LVB voltage to V_STBY
terminal. When RSTO1B(int) is High, output VO1 voltage to
V_STBY terminal. When CLR is Low, LSWO is open. When
RSTO1B(int) is High and CLR is High, LSWO output voltage
turns GND. When RSTO1B(int) is Low and RSTO1B is High,
discharge the external capacitor which is connected to
Table 8. HVB and LVB Connection
MODEHVBLVB
Li_ionVB
Ni_mhGNDVB
Notes
28. Externally connect to VB.
Table 9. V_STBY and LSWO Operation
INPUTOUTPUT
WAKE(Int)RSTO1B(Int)CLRV_STBYLSWO
LXXVBZ
HLXVBZ
HHLVO1Z
HHHVO1L
Z : High Impedance, X : Don’t care
V_STBY. When using Ni_mh, short-circuit VB and LVB to
external components and HVB to GND. When using Li_ion,
short-circuit HVB to VB, and leave LVB open. When using
Ni_MH, the VB voltage is output from V_STBY in Standby
mode. When using Li-Ion, 50% of the VB voltage is output to
V_STBY terminal in Standby Mode.
(28)
open
(28)
RESET CIRCUIT
CRST1, 2
VO1, 2 VG
RST1ADJ
(RSTO1B side only)
When the VO1 or VO2 voltage is higher than the reference
value, RSTO1B or 2B goes High. When RSTO1B(int) is Low
and RSTO1B is High, SLEEP(int) is forced to place the chip
into the standby mode.
Connect a capacitor between RST1ADJ and CRST. The
capacitor is not necessary if a resistor of 330KΩ or less is
inserted between RST1ADJ and VC1 for reset adjustment
VO1
BANDGAP
REFERENCE
Figure 8. Reset Circuit Block Diagram
VO1
RST1B, 2B
Reset
Control
RSTO1B, 2B(Int)
CRST1, 2
Connect the capacitor between RST1ADJ and RSTB as
directed below.
When SEQSEL is Low: Between RST1ADJ and CRST1
When SEQSEL is High: Between RST1ADJ and CRST2
Use a capacitor with approximately half of the
capacitance between CRST and GND
18730
Analog Integrated Circuit Device Data
18Freescale Semiconductor
RST1B(Int)
RST1B
SLEEP(Int)
Figure 9. Reset Timing Diagram
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER SUPPLY VO1, VO2: NI_MH
The VB voltage rises and is output to VI1. When
RSTO2B(int) is High, the power switch turns ON to output the
VO1 voltage to VCC1. Capacitance value which is connected
to VO1 should be higher than the capacitor connected to
VCC1.
Table 10. Output Voltage of VO1
Address : 0011(30)
B7B6B5B4B3B2B1S_Off_VO1VO1 [V]
LLLLLLLX1.613
LLLLLLHX1.625
LLLLLHLX1.638
LLLLHLLX1.663
LLLHLLLX1.713
LLHLLLLX1.813
LHLLLLLX2.013
HLLLLLLX2.413
HLLLLLHX2.425
HLLLLHLX2.438
HLLLHLLX2.463
HLLHLLLX2.513
HLHLLLLX2.613
HHLLLLLX2.813
HHHHHHHX3.200
Notes
29. Operation is not guaranteed when VO1 input voltage is 1.8 V or lower. By connecting a diode between
VI1 and VO1, VI1 can output voltage higher (with the voltage difference Vf) than VO1.
30. All combinations of input are not included.
The VB voltage rises or falls and is output to VI2. When
RSTO2B(int) is High, the power switch turns ON to output the
VO2IN voltage to VCC2. If you turn DDC2 OFF using the
register, the power switch 2 also turns OFF. Capacitance
value which is connected to VO2IN should be higher than the
capacitor connected to VCC2.
(29)
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Analog Integrated Circuit Device Data
Freescale Semiconductor19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 11. Output Voltage of VO2
Address : 0100(31)
B7B6B5B4B3B2B1S_Off_VO2VO2 [V]
L L LLLL LX0.805
L L LLLL HX0.811
LLLLLHLX0.816
LLLLHLLX0.827
LLLHLLLX0.849
LLHLLLLX0.893
L H LLLL LX0.980
H L LLLL LX1.155
H L LLLL HX1.161
HLLLLHLX1.166
HLLLHLLX1.177
HLLHLLLX1.199
HLHLLLLX1.243
H H LLLL LX1.330
H H HHHH HX1.500
Notes
31. All combinations of input are not included.
POWER SUPPLY VO1, VO2: LI-ION
The VB voltage falls and is output to VO1. When using
Li_ion, duty limit due to DTC1 is not applied to the switch.
When RSTO2B(int) is High, the power switch turns ON to
output the VO1 voltage to VCC1. Capacitance value which is
connected to VO1 should be higher than the capacitor
connected to VCC1.
The VB voltage falls using only the internal transistor and
is output to VO2. When using Li_ion, duty limit due to DTC2
is not applied to the switch, and DW_2T and DW_2B are Low.
When RSTO2B(int) is High, the power switch turns ON to
output the VO2IN voltage to VCC2. If you turn DDC2 OFF
using the register, the power switch 2 also turns OFF.
Capacitance value which is connected to VO2IN should be
higher than the capacitor connected to VCC2.
18730
Analog Integrated Circuit Device Data
20Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIES PASS POWER SUPPLY
The series pass outputs the SREGI1 voltage to SREGO1,
the SREGI2 voltage to SREGO2, and the SREGI3 voltage to
Table 12. Output Voltage of SREG1
Address : 0101(31)
B7B6B5B4B3B2B1ReservedSREG1 [V]
LLLLLLLH0.865
LLLLLLHH0.880
LLLLLHLH0.895
LLLLHLLH0.926
LLLHLLLH0.986
LLHLLLLH1.107
LHLLLLLH1.349
HLLLLLLH1.833
HLLLLLHH1.848
HLLLLHLH1.863
HLLLHLLH1.893
HLLHLLLH1.954
HLHLLLLH2.075
HHLLLLLH2.317
HHHHHHHH2.800
Notes
32. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to
REGC1 and 3 (65.14KΩ between SREGO1 and REGC1, 34.86KΩ between REGC1 and GND, 73.84KΩ
between SREGO3 and REGC3, and 26.16KΩ between REGC3 and GND).
33. All combinations of input are not included.
SREGO3. If you use MOSFET as the external component in
this case, connect the gate to SREG2G.
(32)
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Analog Integrated Circuit Device Data
Freescale Semiconductor21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 13. Output Voltage of SREG2
Address : 0110(31)
B7B6B5B4B3B2B1B0
LLLLLLLL0.011
LLLLLLLH0.022
LLLLLLHL0.033
LLLLLHLL0.055
LLLLHLLL0.098
LLLHLLLL0.186
LLHLLLLL0.361
LHLLLLLL0.711
HLLLLLLL1.411
HLLLLLLH1.422
HLLLLLHL1.433
HLLLLHLL1.455
HLLLHLLL1.498
HLLHLLLL1.586
HLHLLLLL1.761
HHLLLLLL2.111
HHHHHHHH2.800
Notes
34. All combinations of input are not included.
SREG2
[V]
Table 14. Output Voltage of SREG3
Address : 0111(31)
B7B6B5B4B3B2CP Off
LLLLLLXX2.080
LLLLLHXX2.091
LLLLHLXX2.102
LLLHLLXX2.125
LLHLLLXX2.170
LHLLLLXX2.260
HLLLLLXX2.440
HLLLLHXX2.451
HLLLHLXX2.462
HLLHLLXX2.485
HLHLLLXX2.530
HHLLLLXX2.620
HHHHHHXX2.800
Notes
35. The SREG1 and 3 output voltages are determined by the combination of external resistances
connected to REGC1 and 3 (65.14KΩ between SREGO1 and REGC1, 34.86KΩ between REGC1
and GND, 73.84KΩ between SREGO3 and REGC3, and 26.16KΩ between REGC3 and GND).
36. All combinations of input are not included.
EXTG OnSREG3
[V]
(35)
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Analog Integrated Circuit Device Data
22Freescale Semiconductor
VG GENERATOR
VG
VB
Start Up
VG
VG
Step-Up
Pre Driver
VG_select
VG_duty
VG
LG
PGND3
Figure 10. Circuit when using a Step-Up Converter
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VB
When WAKE (int) goes High from Low, the start-up circuit
raises the VB voltage and outputs it to VG, then outputs the
VG voltage when RSTO1B (int) goes High. The charge pump
circuit can be used for both Ni_mh and Li_ion by setting the
necessary registers. The charge pump circuit is disabled by
default.
VB
Start Up
VG
VG
VG_select
VG_duty
Step-Up
Pre Driver
Figure 11. Circuit When Using a Charge Pump
The VG voltage can be set to 6 V to 4.5 V according to the
combination of VGSEL1 and 2 pin connections. Refer to
Table 16, VG Voltage Settings and VGSEL1 and 2 Pin
Connection on page 24 for the VG voltage settings.
When using a charge pump, please refer to Figure 11.
VG
VB
CPoff
C1L
VG
LG
PGND3
VGH
VG
VB
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor23
Note : Do NOT change Reserved Register from default
value.
*1: Data write to this address (1000) is allowed for the
most significant two bits only. The least significant 6 bits are
only used for the factory test. When writing data, always write
0 to these six bits.
Name
Default
PSW1 : VCC1 Power Switch control
1 = Power Switch on
0 = Power Switch off
PSW2 : VCC2 Power Switch control
1 = Power Switch on
0 = Power Switch off
RSTO1B : RSTO1B Mask *1
1 = RSTO1B mask on
0 = RSTO1B mask off
VO2 : DC/DC Converter Channel 2 output Control *2
1 = DDC2 on
0 = DDC2 off
SREG1 : Series Pass Regulator Channel1 output Control
1 = Regulator on
0 = Regulator off
PSW1PSW2RSTO1BVCC2SREG1SREG2SREG3RSTO2B
11011110
SREG2 : Series Pass Regulator Channel2 output
Control *3
1 = Regulator off
0 = Regulator on
SREG3 : Series Pass Regulator Channel3 output Control
1 = Regulator on
0 = Regulator off
RSTO2B : RSTO2B Mask *1
1 = RSTO2B mask on
0 = RSTO2B mask off
*1: When switching the output voltage of VO1 (2), write 1
to the RSTO1B (2) Mask bit in advance to fix the rest output
to High for preventing erroneous operation.
*2: When turning DDC2 OFF, set the RSTO2B bit to High
Mask RSTO2B. If you turn DDC2 OFF, the power switch 2
to
also turns OFF.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor25
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
PACKAGING
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor31
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
32Freescale Semiconductor
PACKAGE DIMENSIONS
PACKAGING
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor33
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
34Freescale Semiconductor
PACKAGE DIMENSIONS
PACKAGING
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor35
REVISION HISTORY
REVISION HISTORY
RevisionDateDescription of Changes
1.0
10/2005• Initial Release
18730
Analog Integrated Circuit Device Data
36Freescale Semiconductor
NOTES
REVISION HISTORY
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor37
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