Freescale 18730 Technical Data

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Freescale Semiconductor

Technical Data

Power Management IC with Five
Regulated Outputs
Programmed Through 3-Wire

Document order number: MPC18730

Rev 1.0, 10/2005

18730

Serial Interface

The MPC18730 Power Management IC (PMIC) regulates five

independent output voltages from either a single cell Li-Ion (2.7

4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to
V input range).

2.2

The PMIC includes 2 DC-DC converters and 3 low drop out (LDO)
linear regulators. The output voltage for each of the 5 output voltages
is set independently through a 3-wire serial interface. The serial
interface also configures the PMIC's versatile start-up control system,
which includes multiple wakeup, sleep, standby, and reset modes to
minimize power consumption for portable equipment.

In single cell Li-Ion applications two DC-DC converters are
configured as buck (step-down) regulators. In single cell Ni-MH or dry
cell applications, one DC-DC converter is configured as a boost
(step-up) regulator, and the other as buck-boost regulator. The DC­DC converters' output voltages have set ranges 1.613

V to 3.2 V at
up to 120 mA, and 0.805 V to 1.5 V up to 100 mA through the serial
interface.

Features

• Operates from single cell Li-Ion, Ni-MH, or Alkaline

• 2 DC-DC Converters

• 3 Low Drop Regulators

• Serial Interface Sets Output Voltages

• 4 Wake Inputs

• Low Current Standby Mode

• Pb-Free Packaging Designated by Suffix Code EP

2.7 V to 4.2 V Input

VO

VB

MPC18730

VB

VREF

V to

VCC1

SW1

POWER MANAGEMENT IC

EP SUFFIX

98ARL10571D

64-TERMINAL 0.5 mm PITCH

QFN

ORDERING INFORMATION

Device

MPC18730EP/R2 -10°C to 65°C 64 QFN

VO1

Temperature

Range (T

)

A

Programmable

1.613 V to 3.2 V

Programmable

0.805 V to 1.5 V

Package

RSTO1B

EXT_G_ON

VO

RSTO2B

MCU

CONTROL
LOGIC
INPUTS

GND

PGND

Figure 1. MPC18730 Simplified Application Diagram

* This document contains information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.

© Freescale Semiconductor, Inc., 2005. All rights reserved.

VCC2

VO2

SW2

SREGI1

SREGO1

SREGI2

SREGO2

SREGI3

SREGO3

VG

SWG

VB

Programmable

0.865 V to 2.8 V

Programmable

0.011 V to 2.8 V

Programmable

2.08 V to 2.8 V

INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

HVB

VREF

LSWO

RSTO1B

CRST1

RST1ADJ

INM1

RF1

DTC1

RSTO2B

CRST2

INM2

RF2

VREF

LVB

Driver

RSTO1B(Int)

CLR

VO1

RESET
Block 1

VO1

RESET
Block 2

BANDGAP

REFERENCE

RSTO1B(Int)

RSTO2B(Int)

REF2

VMODE

VO1

RSTO1B(Int)

RSTO2B(Int)

VO1

RSTO2B(Int)

VMODE

VG

POWER

SWITCH1

VG

Step-UpDown

DC/DC

Converter

CH1

VG

POWER

SWITCH2

VG

Step-UpDown

DC/DC

Converter

CH2

VB

VB

LVB

VO1

V_STBY

VCC1

VO1

VI1

SW1

PGND1

VCC2

VO2IN

VO2

DW_2T

DW_2B

VI2

SW2

DTC2

SREGC1

SREGC1

SREGC2

SREGC3

WAKE1B
WAKE2B
WAKE3B
WAKE4B

SEQSEL

DATA

STRB

SCKIN

CLR

SLEEP

CLKIN

GND

VGSEL1

VGSEL2

WDT

V_STBY

VO1 VB

CONTROL

Control

Logic

REF4

REF5

RSTO1B(Int)

RSTO2B
(Int)

SEQSEL

REF2

REF1

REF3

REF DAC

REF3

VG_select

VG_duty

REF4

REF5

VG

Series Pass

Regulator1

VG

Series Pass

Regulator2

VG

Series Pass

Regulator3

VB

CLKIN

CPoff

VO1VB

Step- Up
DC/DC

Convertor

On

VREF

VG

VG

EXT gate

On

Buffer

PGND2

SREGI1

SREGO1

SREGI2

SREGO2

SREG2G

SREGI3

SREGO3

C1L

VG

SWG

PGND3

EXT_G_ON

Figure 2. MPC18730 Simplified Internal Block Diagram

18730

Analog Integrated Circuit Device Data

2 Freescale Semiconductor

CLR

WAKE4B

WAKE3B

WAKE2B

WAKE1B

LSWO

LVB

HVB

V_STBY

VO1

VCC1

VI1

SW1

SW1

PGND1

PGND1

TERMINAL CONNECTIONS

GND

VREF

DATA

STRB

SCKIN

CLKIN

SLEEP

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

19 20 21 22 23 24 25 26 27 28 29 30 31 32

18

17

WDT

SEQSEL

SREGI1

TOP VIEW

SREGO1

SREGC1

SREGO2

SREGI2

SREG2G

50

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

TERMINAL CONNECTIONS

SREGC2

49

SREGI3

SREGO3

SREGC3

EXT_G_ON

DW_2B

DW_2T

VO2

VO2IN

VCC2

VI2

SW2

SW2

PGND2

PGND2

RSTO2B

CRST2

33

VB

PGND3

VGSEL2

VGSEL1

INM2

RF2

DTC2

CRST1

RSTO1B

DTC1

RST1ADJ

INM1

C1L

SWG

RF1

VG

Figure 3. MPC18730 Terminal Connections

Table 1. MPC18730 Terminal Definitions

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.

Terminal

Number

1 CLR Input Clear Start-up Signal Input Latch/Clear

2 WAKE4B Input Wake Signal 4 Start-up Signal Input 4

3 WAKE3B Input Wake Signal 3 Start-up Signal Input 3

4 WAKE2B Input Wake Signal 2 Start-up Signal Input 2

5 WAKE1B Input Wake Signal 1 Start-up Signal Input 1

6 LSWO Output Low-Side Switch

7 LVB Input Low Voltage Battery VB Power Supply Connection for Ni_mh

8 HVB Input High Voltage Battery VB Power Supply Connection for Li_ion

9 V_STBY Output Standby Voltage V_STBY Voltage Output

Terminal

Name

Terminal
Function

Formal Name Definition

Low-Side Switch Output Terminal

Output

18730

Analog Integrated Circuit Device Data
Freescale Semiconductor 3

TERMINAL CONNECTIONS

Table 1. MPC18730 Terminal Definitions (continued)

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.

Terminal

Number

10 VO1 Input Voltage Input 1

11 VCC1 Output Voltage Output 1

12 VI1 Output Voltage Output 1

13 SW1 Power Switching 1

14 SW1 Power Switching 1

15 PGND1 Ground Power Ground 1

16 PGND1 Ground Power Ground 1

17 RSTO1B Output Inverted Reset

18 CRST1 Input Reset Delay

19 RST1ADJ Output Reset1 Adjustment

20 DTC1 Power Duty Control

21 RF1 Output Reference Feedback 1

22 INM1 Input Input Minus 1

23 C1L Power Charge Pump

24 VG Output Gate Voltage

25 SWG Power Switching

26 PGND3 Ground Power Ground 3

27 VB Power Battery Voltage

28 VGSEL2 Output VG Select 2

29 VGSEL1 Output VG Select 1

30 INM2 Input Input Minus

31 RF2 Output Reference Feedback 2

32 DTC2 Power Duty Control

33 CRST2 Input Reset Delay

34 RSTO2B Output Inverted Reset

35 PGND2 Ground Power Ground 2

36 PGND2 Ground Power Ground 2

37 SW2 Power Switching

38 SW2 Power Switching

39 VI2 Output Voltage Output

40 VCC2 Output Voltage Output

41 VO2IN Input Voltage Input

42 VO2 Input Voltage Input

Terminal

Name

Terminal
Function

Formal Name Definition

Output 1

Capacitor 1

Capacitor

Capacitor 1

Output 2

Switching Power Supply Circuit 1, VO1 Voltage Input, VO1 Power Supply

Power Switch 1 Output

Switching Power Supply Circuit 1 Output

Switching Power Supply Circuit 1 Coil Connection

Switching Power Supply Circuit 1 Coil Connection

Switching Power Supply Circuit 1 Power GND

Switching Power Supply Circuit 1 Power GND

Reset Circuit 1 Reset Signal Output

Reset Circuit 1 Reset Signal Delaying Capacitor Connection

Switching Power Supply Circuit 1 Reset Voltage Reference Output

Switching Power Supply Circuit 1 Maximum Duty Setting

Switching Power Supply Circuit 1 Error Amp Output

Switching Power Supply Circuit 1 Error Amp Inverse Input

VG Power Supply Circuit Charge Pump Capacitor Connection

VG Power Supply Circuit Voltage Output, Pre-Diver Circuit Power Supply

VG Power Supply Circuit Coil Connection

VG Power Supply Circuit Power GND

VB Power Supply Connection

VG Power Supply Circuit Output Voltage Setting 2

VG Power Supply Circuit Output Voltage Setting 1

Switching Power Supply Circuit 2 Error Amp Inverting Input

Switching Power Supply Circuit 2 Error Amp Output

Switching Power Supply Circuit 2 Maximum Duty Setting

Reset Circuit 2 Reset Signal Delay Capacitor Connection

Reset Circuit 2 Reset Signal Output

Switching Power Supply Circuit 2 Power GND

Switching Power Supply Circuit 2 Power GND

Switching Power Supply Circuit 2 Coil Connection

Switching Power Supply Circuit 2 Coil Connection

Switching Power Supply Circuit 2 Output

Power Switch 2 Output

Power Switch 2 Voltage Input

Switching Power Supply Circuit 2 VO2 Voltage Input

18730

Analog Integrated Circuit Device Data

4 Freescale Semiconductor

TERMINAL CONNECTIONS

Table 1. MPC18730 Terminal Definitions (continued)

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.

Terminal

Number

43 DW_2T Output Step Down Top FET 2

44 DW_2B Output Step Down Bottom

45 EXT_G_ON Output Gate Switch

46 SREGC3 Power Regulator Capacitor 3

47 SREGO3 Output Regulator Output 3

48 SREGI3 Power Regulator Input 3

49 SREGC2 Power Regulator Capacitor 2

50 SREG2G Output Regulator Gate Output

51 SREGO2 Output Regulator Output 2

52 SREGI2 Power Regulator Input 2

53 SREGC1 Power Regulator Capacitor 1

54 SREGO1 Output Regulator Output 1

55 SREGI1 Power Regulator Input 1

56 GND Ground Ground

57 VREF Output Reference Voltage

58 DATA Input Data Signal

59 STRB Input Strobe

60 SCKIN Input Serial Clock

61 WDT Input Watch Dog Timer

62 SEQSEL Input Sequence Input

63 CLKIN Input Clock Input

64 SLEEP Input Sleep Signal

Terminal

Name

Terminal
Function

Formal Name Definition

FET 2

2

Switching Power Supply Circuit 2 Step down Top side FET Gate Output
for Ni_mh

Switching Power Supply Circuit 2 Step down Bottom side FRT Gate
Output for Ni_mh

External Transistor Gate Signal Output

Series Pass Power Supply Circuit 3 External Feedback Connection

Series Pass Power Supply Circuit 3 Output

Series Pass Power Supply Circuit 3 Power Supply

Series Pass Power Supply Circuit 2 External Feedback Connection

Series Pass Power Supply Circuit 2 External Transistor Gate Signal
Output

Series Pass Power Supply Circuit 2 Output

Series Pass Power Supply Circuit 2 Power Supply

Series Pass Power Supply Circuit 1 External Feedback Connection

Series Pass Power Supply Circuit 1 Output

Series Pass Power Supply Circuit 1 Power Supply

GND

Reference Voltage Output

Serial Interface Data Signal Input

Serial Interface Strobe Signal Input

Serial Interface Clock Signal Input

Watchdog Timer Capacitor Connection

Start-Up Sequence Setting Input

External Synchronous Clock Signal Input

Sleep Signal Input

18730

Analog Integrated Circuit Device Data
Freescale Semiconductor 5

MAXIMUM RATINGS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage

Analog Signal Input

(1)

Logic Signal Input

WAKE1~4B

CLR, SLEEP, CLKIN, SCKIN, DATA, STRB

VGSEL1,2

Output Power Current

V

Power Supply Circuit

CC1

V

Power Supply Circuit

CC2

(2)

SREG1 Power Supply Circuit

SREG2 Power Supply Circuit

SREG3 Power Supply Circuit

VG Power Supply Circuit

RSTO1B Power Supply Circuit

Open-Drain Output Apply Voltage

RSTO1B

LSWO

ESD Voltage

Human Body Model (HBM)

Machine Model (MM)

(3)

(4)

Charge Device Model (CDM)

THERMAL RATINGS

Operating Temperature

Ambient

Junction

Storage Temperature

Thermal Resistance

(5)

Junction to Ambient

Lead Soldering Temperature

(6)

Notes

1. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.

2. Includes the series pass power supply circuit output current.

3. ESD1 testing is performed in accordance with the Human Body Model (C

4. ESD2 testing is performed in accordance with the Machine Model (C

module specification with a capacitor 0.01

µF connected from OUT to GND.

ZAP

= 200 pF, R

ZAP

5. Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7.

6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.

V

B

V

INAN

V

ILRSTB

V

ILGC

V

ILGSEL

I

OVO1

I

OVO2

I

OREG1

I

OREG2

I

OREG3

I

OVG

I

ORSTB

V

IODR

V

IODV

V

ESD1

V

ESD2

V

CDM

T

A

T

J

T

STG

R

JA

θ

T

SOLDER

= 100 pF, R

ZAP

-0.5 to 5.0 V

-0.5 to VO1+0.5 V

-0.5 to V_STBY+0.5

-0.5 to VO1+0.5

-0.5 to VB+0.5

mA

120

100

80

100

80

8

-20

-0.5 to 3.3

-0.5 to 3.3

± 1500

± 200

± 750

°C

-10 to 65

150

-50 to 150 °C

69 °C/W

260 °C

= 1500 Ω).

ZAP

= 0 Ω) and in accordance with the system

V

V

V

18730

Analog Integrated Circuit Device Data

6 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

GENERAL

VB Power Supply Voltage

Power Supply Voltage 1

Power Supply Voltage 2

Series Regulator Input Voltage

Start-Up Voltage

Analog Signal Input

(10)

Logic Signal Input

RSTO1 ~ 4B

CLR, SLEEP, CLKIN, DATA, STRB and SCKIN

VGSEL1, 2

Output Power Current

V

Power Supply Circuit

CC1

V

Power Supply Circuit

CC2

SREG1 Power Supply Circuit

SREG2 Power Supply Circuit

SREG3 Power Supply Circuit

VG Power Supply Circuit

RSTO

Supply Current in Stand-by mode

VB Supply Current (VB = 1.2 V for Ni_MH)

(HVB = 3.5 V for Li-Ion)

Supply Current in Operating mode

VB Supply Current (VB = 1.2 V for Ni_MH)

(HVB = 3.5 V for Li-Ion)

Reference Power Supply Circuit

Output Voltage

Output Current

Switching Power Supply 1

V

Output Voltage (Io = 0~100 mA)

CC1

Notes

7. When applying voltage from an external source.

8. 0.3 V when VG is 4.5 V.

9. Provide 2 V or higher for the voltage difference (VG - VO1).

10. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.

11. Includes the series pass power supply circuit output current.

(7), (8)

(11)

(11)

= 27°C under nominal conditions unless otherwise noted.

A

V

LVB

V

HVB

V

SREGI

V

BST

V

IANA

V

ILRSTB

V

ILGC

V

ILGSEL

I

OVCC1

I

OVCC2

I

OSREG1

I

OSREG2

I

OSREG3

I

OVG

I

ORSTB

I

BSNi

I

BSLi

I

BNi

I

BLi

V

REF

I

OREF

V

CC1

STATIC ELECTRICAL CHARACTERISTICS

= 176.4 kHz unless otherwise noted. Typical

CLK

V

SREG

0.9

2.7

+0.2

(9)

V

1.2

3.5

SREG

+0.3 V

2.2

4.2

+0.4 V

SREG

0.9 - - V

0 - V

0

0

0

0

0

5

6

5

0

-5

-

-

-

-

1.255

-0.3

-

-

-

-

-

-

-

-

-

-

5

8

9

7

1.275

-

O1

V_STBY

VO1

VB

100

80

60

80

60

6

0

10

12

18

14

1.295

0.3

2.3 2.4 2.5 V

V

V

V

mA

mA

mA

V

mA

18730

Analog Integrated Circuit Device Data
Freescale Semiconductor 7

STATIC ELECTRICAL CHARACTERISTICS

This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f

= 176.4 kHz unless otherwise noted. Typical

CLK

values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Switching Power Supply 2

V

Output Voltage (Io = 0~80 mA)

CC2

DW_2T Output Voltage

(I

= 400 µA)

sink

DW_2B Output Voltage

(I

= 400 µA)

sink

(12)

(12)

(I

(I

source

source

= 400 µA)

= 400 µA)

Series Pass Power Supply Circuit

SREG1 Control Voltage (Io = 5~60 mA)

SREG1-Error AMP Input offset voltage

SREG2 Control Voltage (Io = 6~80 mA)

SREG2-Error AMP Input offset voltage

SREG3 Control Voltage (Io = 5~60 mA)

SREG3-Error AMP Input offset voltage

SREG2G Output Voltage

(I

= 2.5 µA)

sink

(17)

(I

source

(13)

(14)

(13)

(15)

(13)

(16)

= 2.5 µA)

Power Switch On Resistance

V

Circuit

CC1

V

Circuit

CC2

VG Power Supply Circuit

(Io = 0~6 mA)

(Io = 0~6 mA)

C1L Output Voltage (I

(I

= 2.5 mA)

sink

(18)

(19)

source

= 2.5 mA)

VGH Voltage (Certified value)

V_STBY Output Voltage for Li_ion (Io = 300 µA)

(20)

Notes

12. Connect a transistor with gate capacity of 200 pF or smaller to DW_2T and DW_2B

13. If a capacitor with capacitance of 22µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC
when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is
connected as follows:
SREGI1 = 3.0V to 3.3V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.
SREGI2 = 3.0V to 3.3V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.
SREGI3 = 3.0V to 3.3V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.

14. Calculated by the right formula for input offset: SR1OFST=(Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k))

15. Calculated by the right formula for input offset: SR2OFST=(Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k))

16. Calculated by the right formula for input offset: SR3OFST=(Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k))

17. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.

18. When VGSEL1 is Low and VGSEL2 is Low, I/O=3mA or higher is certified by specification.

19. When VGSEL1 is High and VGSEL2 is Low, I/O=3mA or higher is certified by specification.

20. When HVB is 4.2V and the load from V_STBY is 0.5µA or higher.

V

CC2

V

DW2TH

V

DW2TL

V

DW2BH

V

DW2BL

V

SREG1

SR1OFST

V

SREG2

SR2OFST

V

SREG3

SR3OFST

SREG2GH

SREG2GL

R

VCC1

R

VCC2

VG_00

VG_10

VO11LH

VO11LL

VGH

V

LVB

1.05

5.2

0

5.2

0

2.7

-13.5

2.7

-17

2.7

-11

5

0

-

-

5.5

4.6

VB x 0.85

0

-

1.15

-

-

-

-

2.8

-

2.8

-

2.8

-

-

-

0.4

0.4

6.0

5.0

-

-

-

1.25

VG

0.3

VG

0.3

2.9

24.5

2.9

17

2.9

23

VG

0.5

0.6

0.6

6.5

5.4

VB

0.4

10.5

1.75 - 2.45 V

mV

mV

mV

V

V

V

V

V

V

Ω

V

18730

Analog Integrated Circuit Device Data

8 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f

= 176.4 kHz unless otherwise noted. Typical

CLK

values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Reset Circuit

Reset Voltage 1

Reset Voltage 2

Hysteresis Voltage 1 (@RST1)

Hysteresis Voltage 2 (@RST2)

RSTB (V

(I

= 2 mA)

sink

CRST (I

RSTB

= 100 µA)

sink

= 2.4 V)

High Level Threshold Voltage

Low Level Threshold Voltage

CRST Pull-Up Resistance

V_STBY Output Resistance

Output Resistance (VO1)

Output Resistance (VB)

LSWO Output Resistance

Output Resistance

Ext_G_ON

Ext_G_ON Output Voltage (I

(I

= 100 µA)

sink

source

= 100 µA)

Logic Input

"H" Level Input Voltage

"L" Level Input Voltage

"H" Level Input Voltage

"L" Level Input Voltage

"H" Level Input Voltage

"L" Level Input Voltage

"H" Level Input Current

"L" Level Input Current

Pull Up Resistance

Pull Down Resistance

(21)

(21)

(22)

(22)

(23)

(23)

(21), (23)

(23), (24)

(25)

(26)

Notes

21. Applied to WAKEB1 ~ 4 and SEQSEL.

22. Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN.

23. Applied to VGSEL1 and 2.

24. Applied to WAKEB1 ~ 3, CLR, SLEEP, CLKIN, DATA, STRB, SCKIN and SEQSEL.

25. Applied to WAKEB4.

26. Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN.

V

RST1

V

RST2

V

HYRS1

V

HYRS2

I

ORSTB1,2

V

OLRSTB1,2

V

OLCR1,2

V

IHCR1,2

V

ILCR1,2

R

PUPRC1,2

R

VO1

R

VB

R

LSWO

V

OHEXTG

V

OLEXTG

V

IHVS

V

ILVS

V

IH

V

IL

V

IHVB

V

ILVB

I

IH

I

IL

R

PUP

R

PDW

0.85 x VO1

0.80 x VO2

40

50

0

0

0

1.25

0.75

50

-

-

0.88 x VO1

0.85 x VO2

78

75

-

-

-

1.42

1.00

100

30

200

0.91 x VO1

0.90 x VO2

115

100

10

0.5

0.7

1.65

1.15

150

45

400

- 42 50 Ω

VG x 0.9

0

V_STBY - 0.2

-

1.5

-

VB - 0.2

-

-1

-1

410

330

-

-

-

-

-

-

-

-

-

-

590

480

VG

VG x 0.1

0.2

0.4

0.2

770

625

-

-

-

1

1

V

V

mV

mV

µA

V

V

V

V

KΩ

Ω

V

V

V

V

V

V

V

µA

µA

KΩ

KΩ

18730

Analog Integrated Circuit Device Data
Freescale Semiconductor 9

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, f

values noted reflect the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

OSCILLATOR

Internal Oscillation Frequency

MICRO CONTROLLER INTERFACE

Clock Signal Input

Serial Interface (Refer to Timing Chart below)

DATA Set Up Time

DATA Hold Time

SCKIN Clock Frequency

SCKIN 'H' Pulse Width

SCKIN 'L' Pulse Width

SCKIN Hold Time

STRB Set Up Time

STRB Pulse Width

Notes

27. Duty 50%.

(27)

= 27°C under nominal conditions unless otherwise noted.

A

= 176.4 kHz unless otherwise noted. Typical

CLK

f

f

f

t

wckh

t

t

t

t

ICK

CLK

t

t

sck

wckl

hck

ssb

wsb

s

h

150 200 250 kHz

- 176.4 - kHz

20

20

-

50

50

50

50

50

6.0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

nsec

nsec

MHz

nsec

nsec

nsec

nsec

nsec

18730

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

WAKE1~4(int)

FUNCTIONAL DIAGRAMS

FUNCTIONAL DIAGRAMS

CLKIN

V_STBY

VB

VG

RSTO1B(Int)

RSTO1B

VO1

VCC1

VO2

VB

VB

VB*1

CRST set value

INT

VO1

VB

VG

VO1

VO1

VO1

VO1

VO2

EXT

(Serial setting)

VB

VB

VB*1

VCC2

RSTO2B(Int)

RSTO2B

VSREG1~3

DATA

STRB

CLR

SLEEP

Standby Mode

*1: When using Ni_mh. High-Z when using Li_ion.

Figure 4. Power Supply Start-Up Timing Diagram

SEQSEL setting

Start-Up

VO2

VO1

CRST set value

VO1

DATA

SEQSEL setting

Operation Mode Standby Mode

18730

Analog Integrated Circuit Device Data
Freescale Semiconductor 11

FUNCTIONAL DIAGRAMS

SCKIN

DATA

STRB

t

ssb

t

s

t

wckh

A3

t

wckl

t

h

A2

D0

t

hck

t

wsb

Figure 5. Serial Interface Timing Diagrams

18730

Analog Integrated Circuit Device Data

12 Freescale Semiconductor