FPGANETWORKING SGA10GD Reference Manual
SGA10GD
Dual 10Gbps PCI Expressx8
Ethernet adapter
REFERENCE MANUAL
Ver.: 2009.09.29., Ver. 1.1
(C) BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS
DEPARTMENT OF TELECOMMUNICATIONS AND MEDIA
INFORMATICS
1
Contents
Contents...........................................................................................................................................................................................2
1. Introduction..................................................................................................................................................................................3
1.1 What is SGA10GD?...............................................................................................................................................................3
1.2 What is on-board?..................................................................................................................................................................3
1.3 Conformity.............................................................................................................................................................................4
2. Architecture..................................................................................................................................................................................5
2.1 Power Supply.........................................................................................................................................................................6
2.2 Clock sources.........................................................................................................................................................................7
2.3 Dual XFPs for 10Gbps Ethernet............................................................................................................................................8
2.4 PCI Express x8 endpoint......................................................................................................................................................10
2.5 DDR2 SODIMM RAM........................................................................................................................................................12
2.6 Feature Connector................................................................................................................................................................14
2.7 FPGA Programming.............................................................................................................................................................16
2.7.1 Programming through JTAG.........................................................................................................................................16
2.7.2 Programming from FLASH..........................................................................................................................................16
2.7.3 Partial reconfiguration...................................................................................................................................................17
2.8 Status LEDs.........................................................................................................................................................................17
4. FPGA test Cores.........................................................................................................................................................................18
4.1 PCIEX4 - Endpoint Block for PCI Express v. 1.6...............................................................................................................18
4.2 XAUI v. 8.1..........................................................................................................................................................................18
4.3 DDR2 - MIG v. 2.0 generated SODIMM teszt core............................................................................................................18
4.4 Clock domains......................................................................................................................................................................19
2
1. Introduction
1.1 What is SGA10GD?
SGA10GD is a PCI-Express x8 adapter card, primarily developed for 10Gbits
Ethernet network monitoring. It's on-board resources, and reconfigurability of its
FPGA extends its functionality beyond the 10G application,
1.2 What is on-board?
The figures below show the major on-board components.
Top side components:
1: Dual 10 Gigabit/sec XFP receptacle
2:
DDR2 RAM SODIMM Receptacle 1.8V
(Notebook RAM)
3: PCI Express x8 Edge Connector
4: Platform FLASH with initial FPGA core
5: 40 pin Berg type Feature Connector
10: XAUI/XFI converters
6: Xilinx Virtex-5 family FPGA device
7:
Switching regulators for 1.0, 1.8, 2.5,
3.3 Volts
8:
JTAG connector for programming the
FPGA or Flash
9:
Interface status LED's, RED/GREEN
pairs
11: Power connector
3
1.3 Conformity
SGA10GD aims the following Standards/Recommendations:
XFP 10 Gigabit Small Form Factor Pluggable Module
SFF Committee INF-8077i 10 Gigabit Small Form Factor Pluggable Module
...GBE Gigabit Ethernet (Optical/Copper)
IEEE Std 802.3 Carrier sense multiple access with collision detection
(CSMA/CD) access method and physical layer specifications
PCIE PCI Express
PCI-SIG PCI Express Base Specification Revision 1.0a
PCI-SIG PCI Express Card Electromechanical Specification Revision 1.0a
DDR2 Dual DataRate II. SDRAM and Modules
JEDEC JESD79-2D DDR2 SDRAM SPECIFICATION
JEDEC No.21C 4.20.11 200-Pin DDR2 SDRAM Unbuffered SODIMM Design
Specification. (Item #2017.10) Release No. 17
FC 40 pin Feature Connector
...PDH
ITU-T G.703 Physical/electrical characteristics of hierarchical digital interfaces
(.9 with passive feature card)
...HDD
NCITS 361-2002 AT Attachment with Packet Interface - 6
(ATA/ATAPI-6/UDMA5/UDMA100/UATA100 interface)
4
2. Architecture
The simple and robust architecture of SGA10GD is shown on the block diagram
below.
The heart of the board is a Xilinx Virtex-5 family FPGA device.
The PCB can accomodate two types of devices:
XC5VLX110T-2FF1136C (for SGA10GD board)
XC5VLX50T-1FF1136C (for SGA10GDL board)
The main characteristics of the devices are shown in the table below:
XC5VLX110TXC5VLX50T
Array metric 160x54 120x30
Slices 17280 7200
LUT RAM 1120 kBytes 480 kBytes
Block RAM 5.32 MBytes 2.16 MBytes
DSP slices 64 48
GTP Transceivers 16 (8 pairs) 12 (6 pairs)
Clock Management Tiles8 6
5
In addition, both types have
Clock Management Tiles (CMTs) having two Digital Clock Managers (DCM)
and a Phase Locked Loop per CMT
One PCI Express Endpoint Controller
4 Tri-mode (10/100/1000)Ethernet Media Access Controller (MAC)
2 Internal Configuration Acces Ports (ICAP)
Core logic can run at 550MHz internal clock speed
Two SGA10GD models can be produced depending on the insertion of FPGA type as
shown below:
Model FPGA
SGA10GD XC5VLX110T
SGA10GDLXC5VLX50T
The following sections detail the rest of the board's architectual elements.
2.1 Power Supply
The figure below shows the power distribution tree for SGA10GD.
The first stages consist of switching regulator modules (SWR), since on second
stages there are low drop-out (LDO) point of load (POL) type regulators.
6
Loading...