Force-Mos ME3902D, ME3902D-G Schematics

Dual N-Channel 30V (D-S) MOSFET, ESD Protection

ME3902D/ME3902D-G

GENERAL DESCRIPTION

The ME3902D is the Dual N-Channel logic enhancement mode

power field effect transistors are produced using high cell density,

DMOS trench technology. This high density process is especially

tailored to minimize on-state resistance. These devices are

particularly suited for low voltage application such as cellular phone

and notebook computer power management and other battery

powered circuits where high-side switching and low in-line power

loss are needed in a very small outline surface mount package.

PIN CONFIGURATION

(SOT-26)

Top View

FEATURES

● RDS(ON)= 68 mΩ @VGS=10V

● RDS(ON)= 78 mΩ @VGS=4.5V

● RDS(ON)= 135 mΩ @VGS=2.5V

● Super high density cell design for extremely low RDS(ON)

● Exceptional on-resistance and maximum DC current

capability

APPLICATIONS

● Power Management in Note book

● Portable Equipment

● Battery Powered System

● DC/DC Converter

● Load Switch

● DSC

● LCD Display inverter

Ordering Information: ME3902D (Pb-free)

ME3902D-G (Green product-Halogen free)

Absolute Maximum Ratings (T

Parameter Symbol

Drain-Source Voltage VDS 30 V

Gate-Source Voltage VGS ±12 V

Continuous Drain

A=25℃ Unless Otherwise Noted)

T

A=25℃

TA=70℃

Pulsed Drain Current IDM 12 A

A=25℃

Maximum Power Dissipation*

Operating Junction Temperature TJ -55 to 150

Thermal Resistance-Junction to Ambient*

T

TA=70℃

Maximum Ratings

D

I

D

P

θJA 120

R

3.1

2.5

1

0.7

Unit

A

W

℃

℃/W

*The device mounted on 1in2 FR4 board with 2 oz copper

Apr, 2014-Ver1.3

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Dual N-Channel 30V (D-S) MOSFET, ESD Protection

Electrical Characteristics (TA =25℃ Unless Otherwise Specified)

ME3902D/ME3902D-G

Symbol Parameter Limit Min Typ Max Unit

ST ATIC

GS=0V, ID=250μA

BVDSS Drain-Source Breakdown Voltage

V

30 V

VGS(th)

IGSS

IDSS Zero Gate Voltage Drain Current VDS=30V, VGS=0V 1

RDS(ON) Drain-Source On-Resistancea

VSD

DYNAMIC

Ciss

COSS
Crss

Qg Total Gate Charge

Qgs Gate-Source Charge

Qgd Gate-Drain Charge

td(on)

tr

td(off)

tf

Notes: a. Pulse test; pulse width ≦ 300us, duty cycle≦ 2%

Gate Threshold Voltage

Gate Leakage Current

Diode Forward Voltage

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

DS=VGS, ID=250μA

V

VDS=0V, VGS=±12V ±10

V

GS=10V, ID= 2.1A 52 68

VGS=4.5V, ID= 1.3A 60 78

VGS=2.5V, ID= 1A 97 135

IS=1.7A, VGS=0V 0.8 1.2 V

V

DS=15V, VGS=0V, f=1MHZ

V

DS=15V, VGS=4.5V, ID=2.1A

V

DD=15V, RL =15Ω

I

D=1A, VGEN=10V

G=6Ω

R

0.7 1.4 V

248

32

5.5

4.87

1.55

1.53

106

134

2740

791

μA

μA

mΩ

pF

nC

ns

b. Matsuki Electric/ Force mos reserves the right to improve product design, functions and reliability without notice.

Apr, 2014-Ver1.3

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