Force-Mos ME2306A, ME2306A-G Schematics
N-Channel 30V (D-S)MOSFET
ME2306A/ME2306A-G
GENERAL DESCRIPTION
The ME2306A is the N-Channel logic enhancement mode power field
effect transistors, using high cell density, DMOS trench technology.
This high density process is especially tailored to minimize on-state
resistance.
These devices are particularly suited for low voltage application such
as cellular phone, notebook computer power management and other
battery powered circuits, and low in-line power loss that are needed
in a very small outline surface mount package.
PIN CONFIGURATION
(SOT-23)
Top View
FEATURES
● RDS(ON)≦32mΩ@VGS=10V
● RDS(ON)≦38mΩ@VGS=4.5V
● RDS(ON)≦50mΩ@VGS=2.5V
● Super high density cell design for extremely low RDS(ON)
● Exceptional on-resistance and maximum DC current
capability
APPLICATIONS
● Power Management in Note book
● Portable Equipment
● Battery Powered System
● DC/DC Converter
● Load Switch
● DSC
● LCD Display inverter
Ordering Information: ME2306A (Pb-free)
ME2306A-G (Green product-Halogen free)
Absolute Maximum Ratings (TA=25℃ Unless Otherwise Noted)
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS ±12 V
Continuous Drain Current
Pulsed Drain Current IDM 21.5
Maximum Power Dissipation
Operating Junction and Storage Temperature Range TJ, Tstg -55 to 150
Parameter Symbol
TA=25℃
T
A=70℃
TA=25℃
T
A=70℃
Maximum Ratings
D
I
D
P
5.38
4.30
1.39
0.89
Unit
A
W
℃
Thermal Resistance-Junction to Ambient*
*The device mounted on 1in2 FR4 board with 2 oz copper
Oct, 2012-Ver4.6
θJA 90
R
℃/W
01
N-Channel 30V (D-S)MOSFET
ME2306A/ME2306A-G
Electrical Characteristics (TA =25℃ Unless Otherwise Specified)
Symbol Parameter Limit Min Typ Max Unit
STATIC PARAMETERS
GS=0V, ID=250μA
V(BR)DSS Drain-Source Breakdown Voltage
VGS(th) Gate Threshold Voltage
IGSS Gate-Body Leakage Current VDS=0V, VGS=±12V ±100 nA
V
DS=VGS, ID=250μA
V
30
V
0.7 1.4
IDSS Zero Gate Voltage Drain Current VDS=30V, VGS=0V 1
VGS=10V, ID= 4A 25 32
RDS(ON) Drain-Source On-Resistancea
VSD Diode Forward Voltage IS=1.25A, VGS=0V 0.8 1.2 V
DYNAMIC PARAMETERS
Qg
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Rg Gate Resistance f =1MHz
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
td(on)
tr
td(off)
Total Gate Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
VGS=4.5V, ID= 3.5A 29 38
V
GS=2.5V, ID= 2.8A 39 50
V
DS=15V, VGS=10V, ID=4A
DS=15V, VGS=0V, f=1MHZ
V
V
DD=15V, RL =15Ω
I
D=1A, VGEN=10V, RG=6Ω
15.5
3.2
3.5
0.7
480
70
18
8.5
17
31
μA
mΩ
nC
Ω
pF
ns
tf
Notes: a. Pulse test; pulse width ≦ 380us, duty cycle≦ 2%
b. Matsuki Electric/ Force mos reserves the right to improve product design, functions and reliability without notice.
Fall Time
3
Oct, 2012-Ver4.6
02
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