Force-Mos ME2306, ME2306-G Schematics

Jan,

N-Channel Enhancement Mode MOSFET

ME2306/ME2306-G

GENERAL DESCRIPTION

The ME2306 is the N-Channel logic enhancement mode power field

effect transistors, using high cell density, DMOS trench technology.

This high density process is especially tailored to minimize on-state

resistance.

These devices are particularly suited for low voltage application such

as cellular phone, notebook computer power management and other

battery powered circuits, and low in-line power loss that are needed

in a very small outline surface mount package.

FEATURES

● RDS(ON)≦37mΩ@VGS=10V

● RDS(ON)≦49mΩ@VGS=4.5V

● Super high density cell design for extremely low RDS(ON)

● Exceptional on-resistance and maximum DC current

capability

PIN CONFIGURATION

(SOT-23)

Top View

PIN DESCRIPTION

Pin Symbol Description

1 G Gate

Ordering Information: ME2306 (Pb-free)

ME2306-G (Green product-Halogen free)

Absolute Maximum Ratings (TA=25℃ Unless Otherwise Noted)

Drain-Source Voltage VDSS 30 V

Gate-Source Voltage VGSS ±20 V

Continuous Drain

Current(Tj=150℃)

Pulsed Drain Current IDM 20

Maximum Power Dissipation

Operating Junction Temperature TJ -55 to 150

Parameter Symbol Steady State Unit

TA=25℃

T

A=70℃

TA=25℃

T

A=70℃

Thermal Resistance-Junction to Ambient*

R

D

I

P

θJA

2 S Source
3 D Drain

4.7

3.7

D

T≦10 sec

Steady State 95

1.32

0.84

70

A

W

℃

℃/W

Thermal Resistance-Junction to Case*

*The device mounted on 1in2 FR4 board with 2 oz copper

2009-Ver4.2

θJC 65

R

℃/W

01

Jan,

N-Channel Enhancement Mode MOSFET

ME2306/ME2306-G

Electrical Characteristics (TA =25℃ Unless Otherwise Specified)

Symbol Parameter Limit Min Typ Max Unit

STATIC PARAMETERS

GS=0V, ID=250μA

V(BR)DSS Drain-Source Breakdown Voltage

VGS(th) Gate Threshold Voltage

IGSS Gate-Body Leakage Current VDS=0V, VGS=±20V ±100 nA

V

DS=VGS, ID=250μA

V

VDS=30V, VGS=0V 1

30

V

1 3

IDSS Zero Gate Voltage Drain Current

ID(ON) On-State Drain Currenta

RDS(ON) Drain-Source On-Resistancea

VSD Diode Forward Voltage IS=1.25A, VGS=0V 0.8 1.2 V

DYNAMIC PARAMETERS

Qg Total Gate Charge VDS=15V, VGS=10V, ID=4A

Qg Total Gate Charge

Qgs Gate-Source Charge

Qgd Gate-Drain Charge

Rg Gate Resistance f =1MHz
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance

td(on)

Turn-On Delay Time

V

DS=30V, VGS=0V

T

J=55℃

DS≧5V, VGS= 10V

V

VGS=10V, ID= 4A 25 37

V

GS=4.5V, ID= 3.5A 35 49

V

DS=15V, VGS=4.5V, ID=4A

DS=15V, VGS=0V, f=1MHZ

V

10

20 A

13

6.3

2.9

2.4

0.6

380

64

15

9

μA

mΩ

nC

Ω

pF

V

tr

td(off)

tf

Rise Time

Turn-Off Delay Time

Fall Time

DD=15V, RL =15Ω

D=1A, VGEN=10V, RG=6Ω

I

Notes: a. Pulse test: pulse width≦ 300us, duty cycle≦ 2%, Guaranteed by design, not subject to production testing.
b. Matsuki reserves the right to improve product design, functions and reliability without notice.

14

ns

33

3

2009-Ver4.2

02