Force Computers SYS68K/CPU-40, SYS68K/CPU-41 User Manual

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P/N 202368

FORCE COMPUTERS Inc./GmbH

This document shall not be duplicated, nor its contents used

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SYS68K/CPU-40/41

User’s Manual

Edition No. 8

February 1997

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INTRODUCTION

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TABLE OF CONTENTS

1. GENERAL INFORMATION ........................................... 1-1

1.1 Features of the CPU Board ........................................... 1-4

2. THE PROCESSOR ................................................. 2-1

2.1 The CPU 68040 ................................................... 2-1

2.2 The Shared RAM .................................................. 2-3

2.2.1 The DRM-01/4 ..................................................... 2-3

2.2.2 The DRM-01/16 .................................................... 2-4

2.2.3 The SRM-01/4 ..................................................... 2-5

2.2.4 The SRM-01/8 ..................................................... 2-6

2.3 The System EPROM ................................................ 2-7

2.4 The Local SRAM ................................................... 2-7

2.5 The Local FLASH EPROM ........................................... 2-7

2.6 The Boot EPROM .................................................. 2-7

2.7 The FGA-002 ..................................................... 2-8

2.8 The PI/T 68230 .................................................... 2-9

2.8.1 The I/O Configuration of PI/T1 ........................................ 2-10

2.8.2 The I/O Configuration of PI/T2 ........................................ 2-10

2.9 The Real Time Clock 72423 ......................................... 2-11

2.10 The DUSCC 68562 ................................................ 2-12

2.10.1 The I/O Configuration of DUSCC1 and DUSCC2 .......................... 2-13

2.11 The EAGLE Modules ............................................... 2-15

2.12 The VMEbus Interface .............................................. 2-15

2.13 The Monitor of the CPU board ........................................ 2-17

2.14 Default Jumper Settings on the CPU Board .............................. 2-18

3. SPECIFICATIONS OF THE CPU BOARD ................................ 3-1

4. ORDERING INFORMATION .......................................... 4-1

5. HISTORY OF MANUAL REVISIONS .................................... 5-1

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LIST OF FIGURES

Figure 1-1: Photo of the CPU Board ............................................. 1-2

Figure 1-2: Block Diagram of the CPU Board ...................................... 1-3

Figure 2-1: Location Diagram for All Jumperfields ................................. 2-20

Figure 2-2: The Front Panel of the CPU Board .................................... 2-21

LIST OF TABLES

Table 1-1: The Memory Map .................................................. 1-6

Table 1-2: The Base Addresses of the Local I/O Devices ............................. 1-7

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SECTION 1 INTRODUCTION

1. GENERAL INFORMATION

This CPU board is a high performance single board computer based on the 68040 microprocessor and the VMEbus. The board incorporates a modular I/O subsystem which provides a high degree of flexibility for a wide variety of applications. The CPU board can be used with or without an I/O subsystem, called an "EAGLE" module.

The board is able to hold a RAM Module which can be DRAM (CPU-40) or SRAM (CPU-41) based. The C PU-40/41 family design utilizes all of the features o f the powerful FORCE Gate Array (FGA-002).

Among its features is a 32-bit DMA controller which supports local (shared) memory, VMEbus and I/O data transfers for maximum performance, parallel real time operation and responsiveness.

The EAGLE modules are installed on the CPU board via the FLXi (FORC E Local eX pansion interface). This provides a full 32-bit interface between the base board and the EAGLE module I/O subsystem, providing a range of I/O options.

Four multiprotocol serial I/O channels, a parallel I/O channel and a Real Time Clock with on-board battery backup are installed on the base board which, in combination with EAGLE modules, make the CPU board a true single board computer system.

A broad range of operating systems and kernels is available for the CPU board. However, as with all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the two 16-bit wide EPROM sockets, which results in a 32-bit wide System EPROM area. This ensures that the board is supplied ready to use.

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

Figure 1-1: Photo of the CPU Board

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SECTION 1 INTRODUCTION

Figure 1-2: Block Diagram of the CPU Board

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

1.1 Features of the CPU 3Board

68040 microprocessor: 25.0 MHz on CPU-40B/41B/x 68040 microprocessor: 33.0 MHz on CPU-40D/41D/x Shared DRAM Module: 4 Mbyte DRAM with Burst Read/Write and Parity Generation and

Checking (DRM-01/4) 16 M byte DRAM with Burst Read/Write and Parity Generation and

Checking (DRM-01/16)

Shared SRAM Module: 4 Mbyte SRAM with Burst Read/Write (SRM-01/4)

8 Mbyte SRAM with Burst Read/Write (SRM-01/8)

32-bit high speed DMA controller for data transfers to/from the shared RAM, VMEbus memory and EAGLE modules; DMA controller is installed in the FGA-002.

Two system EPROM devices supporting 40-pin devices. Access from the 68040 using a 32-bit data path

One boot EPROM for local booting, initialization of the I/O chips and configuration of the FGA-002 128 Kbyte SRAM with on-board battery backup 128 Kbyte FLASH EPROM

FLXi interface for installation of one EAGLE module Four Serial I/O interfaces, configurable as RS232/RS422/RS485, available on the front panel 8-bit parallel interface with 4-bit handshake Two 24-bit timers with 5-bit prescaler One 8-bit timer Real Time Clock with calendar and on-board battery backup Full 32-bit VMEbus master/slave interface, supporting the following data transfer types:

# # #

A32, A24, A16 : D8, D16, D32 - Master A32, A24 : D8, D16, D32 - Slave UAT, RMW, ADO

FORCE Message Broadcast (FMB), two channels

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SECTION 1 INTRODUCTION

Features of the CPU Board (cont'd)

Four-level VMEbus arbiter SYSCLK driver VMEbus interrupter (IR 1-7) VMEbus interrupt handler (IH 1-7) Support for ACFAIL* and SYSFAIL Bus timeout counters for local and VMEbus access (15 µsec) VMEPROM, Real Time Multitasking Kernel with monitor, file manager and debugger

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

The following table summarizes the memory map of the CPU board.

Table 1-1: The Memory Map

Start End

Address Address

00000000 003FFFFF Shared Memory (4 Mbyte) 00000000 007FFFFF Shared Memory (8 Mbyte) or 00000000 00FFFFFF Shared Memory (16 Mbyte)

00400000 F9FFFFFF VMEbus Addresses (4 Mbyte Shared Memory)

A32: D32, D24, D16, D8

00800000 F9FFFFFF VMEbus Addresses (8 Mbyte Shared Memory)

A32: D32, D24, D16, D8

01000000 F9FFFFFF VMEbus Addresses (16 Mbyte Shared Memory)

A32: D32, D24, D16, D8 FA000000 FAFFFFFF Message Broadcast Area FB000000 FBFEFFFF VMEbus

A24: D32, D24, D16, D8

Type

FBFF0000 FBFFFFFF VMEbus

A16: D32, D24, D16, D8 FC000000 FCFEFFFF VMEbus

A24: D16, D8

FCFF0000 FCFFFFFF VMEbus

A16: D16, D8

FD000000 FEFFFFFF Reserved

FF000000 FF7FFFFF SYSTEM EPROM FF800000 FFBFFFFF Local I/O

FFC00000 FFC7FFFF LOCAL SRAM FFC80000 FFCFFFFF Local FLASH EPROM FFD00000 FFDFFFFF Registers of FGA-002 FFE00000 FFEFFFFF BOOT EPROM FF803E00 FF803FFF VMEbus Arbiter

FFF00000 FFFFFFFF Reserved

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SECTION 1 INTRODUCTION

This table gives a brief overview of the local I/O devices and the equivalent base address.

Table 1-2: The Base Addresses of the Local I/O Devices

BASE ADDRESS DEVICE

$FF803000 RTC 72423 $FF802000 DUSCC1 68562

$FF802200 DUSCC2 68562 $FF800C00 PI/T1 68230 $FF800E00 PI/T2 68230

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SECTION 1 INTRODUCTION

2. THE PROCESSOR

2.1 The CPU 68040

The 6 8 040 is a third generation full 32 bit enhanced microprocessor. The 68040 i s upward object code compatible with the 68030, 68020, 68010 and 68000 line of microprocessors.

The 68040 combines a central processing unit core, an instruction cache, a data cache, a memory management unit, and an enhanced bus controller.

This virtual memory processor utilizes multiple, concurrent execution units and a highly integrated architecture providing a high level of performance.

The 68040 processor combines a 68030 compatible integer unit, a 68881/68882 compatible floating point unit (FPU), memory management units (MMUs), and a 4 Kbyte instruction and data cache. Cache functionality is strengthened by the built-in on-chip bus snooping logic which instantly supports cache logic during multimaster applications.

Instruction administration is routed through both the integer unit and FPU, which link to the fully independent data and instruction memory units. Each memory unit consists of an MMU, an address translation cache (ATC), a main cache, and a snoop controller.

The internal blocks are designed to operate in parallel, allowing instruction execution to be overlapped. In addition, the internal caches, the on-chip memory management unit, and the enhanced bus controller operate parallel to one another.

The 68040 contains an enhanced bus controller that supports both synchronous/ asynchronous bus cycles and burst data transfers. It contains a nonmultiplexed address bus and data bus and supports 32 bits of address and data.

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

Features of the 68040

Nonmultiplexed 32 bit address and data buses 16 general purpose address and data registers (32 bit wide) 8 floating point data registers (80 bit wide) Two supervisor stack pointers (32 bit wide) 19 special purpose control registers 4 Kbyte instruction and 4 Kbyte data cache On-chip paged memory management unit Pipelined architecture with parallelism allowing accesses to internal caches, bus transfers, and

instruction execution in parallel

Synchronous bus cycles and burst read and write data transfers Complete floating point support given to the 68882 FPCP subset and software emulation 68030 compatible Low latency bus accesses to reduce cache miss penalty

Maximized throughput from the integer unit, FPU, MMU and bus controller 4 Gbyte direct addressing range

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SECTION 1 INTRODUCTION

2.2 The Shared RAM

On this CPU board the shared RAM is placed on a module to allow the adaption of DRAM or SRAM to the base board.

All signals which are needed t o control the shared RAM are available on the RAM module connector. Therefore RAM devices with different access times can also be used on this CPU board to take advantage of the 68040 with higher frequency if it becomes available.

2.2.1 The DRM-01/4

The DRM-01/4 is a 4 Mbyte RAM module which is used on the CPU-40B/4.

Features of the DRM-01/4

4 Mbyte DRAM Burst READ and Burst WRITE capability Parity Generation and Checking Asynchronous refresh is provided every 14µs

Accessible via VMEbus The access address for the 68040 is $00000000 to $003FFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

The DRAM module includes byte parity check for local and VMEbus accesses. If a parity error is detected on a VMEbus cycle, a BERR is forced to the VMEbus informing the requestor that a parity error has occ u r re d. On local accesses, a Transfer Error Acknowledge (TEA) is forced to the processor i f a parity error was detected.

The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal Cycles

CPU-40/B 25 MHz 4 1 3 0

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

2.2.2 The DRM-01/16

The DRM-01/16 is a 16 Mbyte RAM module which is used on the CPU-40B/16.

Features of the DRM-01/16

16 Mbyte DRAM

Burst READ and Burst WRITE capability

Parity Generation and Checking

Asynchronous refresh is provided every 14µs

Accessible via VMEbus The access address for the 68040 is $00000000 to $00FFFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040-B Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal

Cycles

CPU-40/B 25 MHz 4 1 3 0

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SECTION 1 INTRODUCTION

2.2.3 The SRM-01/4

The SRM-01/4 is a 4 Mbyte RAM module which is used on the CPU-41B/4.

Features of the SRM-01/4

4 Mbyte SRAM

Burst READ and Burst WRITE capability

Battery Backup via VMEbus

Accessible via VMEbus The access address for the 68040 is $00000000 to $003FFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

Pari t y check is not necessary for SRAM devices, because these components are protected against soft errors owing alpha emission. The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal Cycles

CPU-41/B 25 MHz 3 1 2 0

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

2.2.4 The SRM-01/8

The SRM-01/8 is an 8 Mbyte RAM module which is used on the CPU-41B/8.

Features of the SRM-01/8

8 Mbyte SRAM

Burst READ and Burst WRITE capability

Battery Backup via VMEbus

Accessible via VMEbus The access address for the 68040 is $00000000 to $007FFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be

read. Pari t y check is not necessary for SRAM devices, because these components are protected against soft

errors owing alpha emission. The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal

Cycles

CPU-41/B 25 MHz 3 1 2 0

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SECTION 1 INTRODUCTION

2.3 The System EPROM

The CPU board offers two 40-pin EPROM sockets for the installation of two 16-bit wide EPROM devices. The EPROMs present a full 32-bit data path to the processor enabling maximum performance. The following devices are supported in the system EPROM area:

Supported Device Types in the System EPROM Area:

Organization Total Memory Capacity

64K x 16 256 Kbytes 128K x 16 512 Kbytes 256K x 16 1 Mbyte 512K x 16 2 Mbytes

2.4 The Local SRAM

The CPU board contains a 128K * 8 bit SRAM. Battery backup is provided via the on-board battery or the VMEbus +5VSTDBY line.

2.5 The Local FLASH EPROM

A 128 Kbyte FLASH EPROM is included on the base board of the CPU-40 which can be used as additional data backup under conditions of power down for long periods. FLASH EPROM is ideal to hold details of the board status, such as software revision or user data which is to be kept permanently.

2.6 The Boot EPROM

The CPU board contains, in addition to the two system EPROMs, a single boot EPROM to boot the local microprocessor, initialize all I/O devices and program the board-dependent functions of the FGA-002. All basic initialization of the I/O devices and the FGA-002 are made through the boot EPROM.

In addition, the boot EPROM contains user utility routines, which may be called out of the user's application progr a m. These routi n es provide e asy software access to the fu nctionality of the FGA-002 (DMA controller, FORCE Message Broadcast, Interrupt Management, etc.).

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2.7 The FGA-002

One of the main features on this CPU board is the FGA-002 Gate Array with 24,000 gates and 281 pins. The FGA-002 controls the local bus and builds the VMEbus interface. It also includes a DMA controller, a complete interrupt handler, message broadcast interface (FMB), timer functions, mailbox locations, and a VMEbus interrupter. This gate array monitors the local bus, which in turn signifies that if any local I/O devi ce i s to be accessed, the gate array overrules all control signals, used address signals, and data signals.

The FGA-002 serves as a VMEbus manager. All VMEbus address and data lines are connected to the gate array through the buffers. Additional functions such as the VMEbus interrupt handler are also installed on t h e F GA - 0 02. The on-chip DMA controller can access the local memory, VMEbus memory, and onboard devices which are able to function in a DMA mode. The start address of the FGA-002 registers is $FFD00000. All registers of the gate array and associated functions are described in detail in the FGA-002 Users Manual. On the following page you will find a list of features for the FGA-002.

Features of the FGA-002

A complete functional description of the FGA-002 may be found in the FGA-002 Users Manual.

32 bit DMA Controller

2 Message Broadcast Channels (FMB)

8 Mailbox Interrupt Channels

One 8 bit timer

Complete Interrupt Management for VMEbus interrupts, ACFAIL, SYSFAIL, Onboard Interrupts and

FGA-002 internal interrupts

VMEbus interface including a single level arbiter

Decoding logic for accesses to the Shared Memory of the CPU board

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SECTION 1 INTRODUCTION

2.8 The PI/T 68230

The MC68230 Parallel Interface/Timer (PI/T) provides versatile double buffered parallel interfaces and an operating system oriented timer for MC68000 systems. The parallel interfaces operate in unidirectional or bidirectional modes, 8 or 16 bits wide. The PI/T timer contains a 24 bit wide counter and a 5 bit prescaler.

Features of the PI/T

MC68000 Bus Compatible

Port Modes Include: Bit I/O

Unidirectional 8 bit and 16 bit Bidirectional 8 bit and 16 bit

Selectable Handshaking Options

24 bit Programmable Timer

Software Programmable Timer Modes

Contains Interrupt Vector Generation Logic

Separate Port and Timer Interrupt Service Requests

Registers are Read/Write and Directly Addressable

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

2.8.1 The I/O Configuration of PI/T1

Port A is connected to the two 4 bit HEX rotary switches provided on the front panel for application dependent settings.

Port B is used for programming the local base address for A24 accesses from the VMEbus. Port C is used for port and timer interrupts and to control the RMC behavior of the board.

2.8.2 The I/O Configuration of PI/T2

Port A and the handshake lines are routed to a 24-pin header which allows the connection of a flat cable. 8 bits are connected to port A of the PI/T and can be used as inputs or outputs, with the remaining 4 bits being connected to the handshake pins of the PI/T. This port can be used to establish a "Centronics type" interface.

Port B allows the memory capacity of the Shared RAM to be read. Each CPU board of this type contains three readable status bits describing the memory capacity. In addition, the CPU board type can be read through the remaining 5 bits.

Port C grants the RAM type (DRAM/SRAM) burst and parity capability of the Shared RAM to be read. A "Powerup Reset" can be initiated by software.

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SECTION 1 INTRODUCTION

2.9 The Real Time Clock 72423

There is a Real Time Clock (RTC) 72423 installed on the CPU board. The CPU board contains a self supportive battery to sustain the RTC during power down.

Features of the RTC

Built-in quartz oscillator makes regulation unnecessary and allows easy design

Direct bus compatibility (120 ns access time)

Incorporated built-in time (hour, minute, second), and date (year, month, week, day) counters

12 hour and 24 hour clock switchover functions and automatic leap year setting

Interrupt masking

An error adjustment time function of 30 seconds

READ, WRITE, HOLD, STOP, RESET, and CHIP SELECT inputs

The C-MOS IC boasts low current consumption and features a backup function

A 24-pin

package

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

2.10 The DUSCC 68562

The Dual Universal Serial Communications Controller (DUSCC) 68562 is installed to communicate wi th terminals, computers, or other equipment.

The DUSCC is a single chip MOS-LSI communications device providing two independent, multiprotocol, full duplex receiver/transmitter channels in a single package. Each channel consists of a receiver, transmitter, 16-bit multifunction counter/timer, digital phaselocked loop (DPLL), parity/CRC generator and checker, and associated control circuits.

Features of the DUSCC

Dual full duplex synchronous/asynchronous receiver and transmitter

Multiprotocol operation consisting of:

BOP: HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link level

COP: BISYNC, DDCMP, X.21

ASYNC: 5-8 bit plus optional parity

Programmable data encoding formats: NRZ, NRZI, FM0, FM1, Manchester

4 character receiver and transmitter FIFOs

Individual programmable baud rate for each receiver and transmitter

Digital phase locked loop

User programmable counter/timer

Programmable channel modes full/half duplex, auto echo, local loopback

Modem control signals for each channel: RTS, CTS, DCD

CTS and DCD programmable autoenables for Receiver (RX) and Transmitter (TX)

Programmable interrupt on change of CTS or DCD

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SECTION 1 INTRODUCTION

2.10.1 The I/O Configuration of DUSCC1 and DUSCC2

The four cha nnels may be configured to function as a RS232 or RS422/RS485 compatible interface. Termination resistors can be installed to adapt various cable lengths and reduce reflections upon the selection of the RS422/RS485 compatible interface. The DUSCC can interrupt the local CPU at a specified programmable IRQ level.

I/O Signals for DUSCC1:

The I/O signal assignment of channel 1 to 2 is listed as follows:

Signal Input Output 9 Pin Micro Description

D-Sub Connector

DCD X 1 Data Carrier Detect RXD X 2 Receive Data

TXD X 3 Transmit Data DTR X 4 Data Terminal Ready GND 5 Signal GND DSR X X 6 Data Set Ready

RTS X 7 Request to Send

CTS X 8 Clear to Send GND 9 Signal GND

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The I/O signals of channel 1 can be connected to the VME connector P2 in parallel to the 9-pin Micro D-Sub connector as follows:

Signal Input Output VME Connector Description

DCD X c29 Data Carrier Detect RXD X c30 Receive Data

TXD X c31 Transmit Data DTR X c32 Data Terminal Ready DSR X X a29 Data Set Ready

RTS X a30 Request to Send

CTS X a31 Clear to Send GND a32 Signal GND

NOTE

This is only possible if these VMEbus P2 lines are not used by an EAGLE module.

I/O Signals for DUSCC2:

The I/O signal assignment of channels 3 and 4 is listed as follows:

Signal Input Output 9 Pin Micro Description

D-Sub Connector

DCD X 1 Data Carrier Detect RXD X 2 Receive Data

TXD X 3 Transmit Data DTR X 4 Data Terminal Ready GND 5 Signal GND DSR X X 6 Data Set Ready

RTS X 7 Request to Send

CTS X 8 Clear to Send GND 9 Signal GND

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SECTION 1 INTRODUCTION

2.11 The EAGLE Modules

EAGLE modules are I/O subsystems designed not only to increase the functionality of the board but to add the exact I/O features to fit the application requirement. EAGLE modules connect directly onto the FLXi of t he b as e board. FLXi and EAGLE modules will be a feature on future FORCE board generations to ensure continued flexibility.

If your CPU board is assembled with an EAGLE module please refer to the is shipped with this board and should be placed in

Section 6

of this manual.

"EAGLE Module"

manual which

2.12 The VMEbus Interface

The CPU board has a full 32-bit VMEbus interface. The address modifier codes for A16, A24 and A32 addressing are fully supported in master mode. In slave mode, the address modifiers for A32 and A24 are fully supported.

Read-Modify-Write cycles are fully supported to allow multiple CPU boards to be synchronized via the sha re d R AM. The FGA-002 determines whether or not an access to the shared RAM is allowed and, if allowed, controls the access cycle.

The CPU board provides an interrupt handler capability (IH 1-7) which can be enabled/disabled by programming the FGA-002. The CPU board also provides an interrupter function which enables the board to send interrupts to the VMEbus on seven programmable levels with a so ftware-programmable vector.

The following bus release modes are supported: RWD = Release When Done

ROR = Release On Request RBCLR = Release On Bus Clear RAT = Release After Timeout REC = Release Every Cycle ROACF = Release On ACFAIL*

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Each of the listed modes is software p r ogrammabl e i nside the g a t e a rray. The bus request level of the CPU board is jumper or software selectable (BRO-3).

The D MA controller installed in the FGA-002 on the CPU board is able to access the VMEbus interface independently from the microprocessor, enabling VMEbus communication to take place without impacting the processing capabilities of the rest of the board for number crunching or servicing on-board I/O.

A four level arbiter with round robin and prioritized round robin arbitration modes, a power monitor, a SYSRESET* generator, IACK* daisy chain driver and support for ACFAIL*, SYSFAIL* and SYSCLK complete the VMEbus interface.

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SECTION 1 INTRODUCTION

2.13 The Monitor of the CPU board

Every CPU board contains VMEPROM, a real time multitasking monitor debugger. It consists of a powerful real time kernel, file manager and monitor/debugger with 68040 line assembler/disassembler.

The monitor/debugger includes all functions to control the real time kernel and file manager as well as all tools required for program debugging such as breakpoints, tracing, memory display, memory modify and host communication.

VMEPR OM s upports several memory and I/O boards on the VMEbus to take full advantage of the file manager and kernel functions.

A built-in selftest checks all on-board devices and memory. This allows detection of any failures on the board.

Memory initialization and test commands offer easy installation of global memory in the environment on the local RAM and/or the VMEbus.

The one line assembler/disassembler is 68040 compatible and supports all 68040 commands in the original mnemonic described in the MC 68040 User's Manual.

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2.14 Default Jumper Settings on the CPU Board

The following are the default jumper settings and a location diagram displaying all jumpers.

Default Jumper Settings for the CPU

Jumperfield Description Default Schematics

Connection

B2 Reset Voltage Sensor --- SH4

B20 Backup Supply for Local SRAM and --- SH4

RTC via +5VSTDBY B2

B1 Backup Supply for Local SRAM and 1-2 SH4

RTC via Bat 1 B2

Default Jumper Settings for System EPROMs and SRAM/EEPROM

Jumperfield Description Default Schematics

Connection

B11 System EPROM device select 1-6 SH5

B16 FLASH EPROM write dis-/enable 1-2 SH4

Default Jumper Settings for Serial I/O (RS232)

Jumperfield Description Default Schematics

Connection

B3 Connector 1, PD1 2-15 SH6

(DUSCC1 Port #1) 8-9 B2

B4 Connector 2, PD2 2-15 SH6

(DUSCC1 Port #2) 8-9 B3

B5 Connector 1, PD1 --- SH6

(DUSCC1 Port #1) C2

B6 Connector 2, PD2 --- SH6

(DUSCC Port #2) C3

B7 Connector 3, PD3 2-15 SH7

(DUSCC2 Port #3) 8-9 B2

B8 Connector 4, PD4 2-15 SH7

(DUSCC2 Port #4) 8-9 B3

B9 Connector 3, PD3 --- SH7

(DUSCC2 Port #3), PD3 C2

B10 Connector 4, PD4 --- SH7

(DUSCC Port #4), PD4 C3

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SECTION 1 INTRODUCTION

Default Jumper Settings for VMEbus

Jumperfield Description Default Schematics

Connection

B19 Four level Arbiter Request Level 1-6 SH9

2-5 B4 3-4

B13 SYSCLK 1-8 SH10

SYSFAIL 2-7 C2 Receive VMEbus RESET 3-6 Drive VMEbus RESET 4-5

Default Jumper Settings for Test

Jumperfield Description Default Schematics

Connection

B17 Clock Signal to CPU 1-2 SH16

Headers for 12 Bit I/O and 8 Bit I/O

Jumperfield Description Default Schematics

Connection

B12 User I/O --- SH8

Default Jumper Setting for Parallel I/O (PI/T)

Jumperfield Description Default Schematics

Connection

B18 Interrupt Request, 2-3 SH8

Hardware Watchdog PI/T #2 D4

2-19

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

Figure 2-1: Location Diagram for All Jumperfields

2-20

Page 34

SECTION 1 INTRODUCTION

Figure 2-2: The Front Panel of the CPU Board

2-21

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

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2-22

Page 36

SECTION 1 INTRODUCTION

3. SPECIFICATIONS OF THE CPU BOARD

CPU Type 68040

CPU Clock Frequency CPU-40B/x 25.0 MHz

Shared DRAM Capacity with Parity CPU-40X/4 4 Mbytes

Shared SRAM Capacity CPU-41X/4 4 Mbytes

SRAM Capacity with On-board Battery Backup 128 Kbytes FLASH EPROM 128 Kbytes

Number of System EPROM Sockets 2 Data Path 32-Bits

Serial I/O Interfaces (68562) 4 RS232/RS422/RS485 Compatible 4 of 4

24-bit Timer with 5-bit Prescaler 2 8-bit Timer 1

Parallel I/O Interface (68230) 12 Lines

Real Time Clock with On-board Battery Backup 72423

VMEbus Interface A32, A24, A16:D8, D16, D32, UAT, RMW Master

A32, A24:D8, D16, D32, RMW Slave

CPU-40D/x 33.0 MHz

CPU-40X/16 16 Mbytes

CPU-41X/8 8 Mbytes

Four Level Arbiter Yes SYSCLK Driver Yes Mailbox Interrupts 8

FORCE Message Broadcast FMB FIFO 0 8 Bytes

VMEbus Interrupter/VMEbus and Local Interrupt Handler 1 to 7 All Sources can be Routed to a Software Programmable IRQ Level Yes

RESET/ABORT Switch Yes

VMEPROM Firmware Installed on All Board Versions 256 Kbytes

Power Requirements +5V min/max 5.2A/6.0A

Operating Temperature with Forced Air Cooling 0 to +50EC Storage Temperature -40 to +85EC Relative Humidity (noncondensing) 0 to 95% Board Dimensions 234x160mm/9.2x6.3in No. of Slots Used 1

FMB FIFO 1 1 Byte

+12V min/max 0.1A/0.3A

-12V min/max 0.1A/0.3A

3-1

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

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3-2

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SECTION 1 INTRODUCTION

4. ORDERING INFORMATION

SYS68K/CPU-40B/4-00 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-40B/4-01 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-40B/16-00 25.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-40B/16-01 25.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-40D/4-00 33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-40D/4-01 33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-40D/16-00 33.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-40D/16-01 33.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-41B/4-00 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-41B/4-01 25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-41B/8-00 25.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-41B/8-01 25.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-41D/4-00 33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

SYS68K/CPU-41D/4-01 33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/CPU-41D/8-00 33.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial I/O channels,

FLXi, VMEPROM. Documentation included.

4-1

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

SYS68K/CPU-41D/8-01 33.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial I/O channels,

EAGLE-01C (SCSI , floppy disk and Ethernet Interface), VMEPROM. Documentation included.

SYS68K/IOBP-1 Backpanel for single board computers providing SCSI and floppy disk drive connectors. SYS68K/CABLE MICRO-9 SET 1 Set o f t hr e e ada p t e r c a bles 9 - pin micro D- S ub ma le c onnector to 9-pin D-Sub female connector,

length 2 m.

SYS68K/CABLE MICRO-9 SET 2 Set of four a da pte r ca bl e s 9-pin micr o D- Sub ma l e connector to 25-pin D-Sub female connector,

length 2 m.

SYS68K/VMEPROM/40/UP VMEPROM update service for the SYS68K/CPU-40 series.

SYS68K/VMEPROM/UM VMEPROM User's Manual excluding the SYS68K/CPU-40 description.

SYS68K/CPU-40/UM User's Manual for the SYS68K/CPU-40 product, including VMEPROM User's Manual and

EAGLE-01C User's Manual (separately available as EAGLE-01C/UM).

SYS68K/FGA-002/UM User's Manual for the FGA-002 Gate Array.

4-2

Page 40

SECTION 1 INTRODUCTION

5. HISTORY OF MANUAL REVISIONS

Revision No. Description Date of Last Change

0 First Print. FEB/05/1991 1 The following sections/pages have been changed: APR/16/1991

Section 1: Page 2-16 (EPROM Description) Section 3: Pages 3-11, 3-12, 3-14, 3-15 (EPROM

Description)

Section 4: Page F-1 (EPROM Description) Sections 7, 8, and 9: These have been changed to

adapt to VMEPROM Version 2.74 Section 1: Chapter 3: Power Requirements for + 12V

AUG/23/1991

changed from 0.1A/0.5A to 0.1A/0.3A Section 3: Chapter 3.9.4 has been eliminated.

Chapter 3.9.12: New Board Identification. Chapter 3.9.16: 1 and 0 were switched.

2 Rework for PCB Revision 2 FEB/03/1992

Editorial changes throughout the manual.

3 MAY/05/1992

Section 3: Chapter 3.9.12: Board identification number has been corrected.

Section 5: Data Sheets updated. Section 3: Figures 3-8, 3-9, 3-13, 3-17 and 3-20 have

been corrected.

NOV/17/1992

Sections 7, 8 and 9: have been changed.

5 JUN/9/1993

Sections 1 and 4: A description of jumperfield B18 has been added.

6 NOV/18/1993

Sections 3 and 7: RTC programming example has been corrected in Section 3 and in a correction to the description of the Upper Rotary Switch has been added in Section 7.

5-1

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

7 MAR/14/1996

Section 3: DRM-01/4 and DRM-01/16 have been replaced by DRM-03 and DRM-05 respectively. Appendix F-2: The description of jumperfield B13 has been corrected.

8 Editorial Changes Febr/18/1997

5-2

Page 42

INSTALLATION

Page 43

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Page 44

W A R N I N G

TO AVOID MALFUNCTIONS AND COMPONENT DAMAGE, PLEASE READ THE COMPLETE INSTALLATION PROCEDURE BEFORE THE BOARD IS INSTALLED IN A VMEBUS ENVIRONMENT.

C A U T I O N

To ensure proper functioning of the product over its usual lifetime, take the following precautions before handling the board.

Malfunction or damage to the board or connected components: Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime.

! !

Before installing or uninstalling the board, read this Before installing or uninstalling the board, in a VME rack:

- Check all installed boards for steps that you have to take before turning off the power.

- Take those steps.

- Finally turn off the power.

- Before touching integrated circuits, ensure that you are working in an electrostatic free environment. Ensure that the board is connected to the VMEbus via all 2 connectors, the P1 and the P2, and that power is available on all ot them. When operating the board in areas of strong electromagnetic radiation, ensure that the board

- is bolted on the VME rack

- and shielded by closed housing.

Installation section

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Page 46

TABLE OF CONTENTS

1. GENERAL OVERVIEW ................................................... 1-1

1.1 The Rotary Switches ..................................................... 1-1

1.2 The Function Switch Positions .............................................. 1-1

1.3 Connection of the Terminal ................................................. 1-3

1.4 The Default Hardware Setup ............................................... 1-4

2. INSTALLATION IN THE RACK ............................................. 2-1

2.1 Power ON ............................................................. 2-1

2.2 Correct Operation ........................................................ 2-2

3. ENVIRONMENTAL REQUIREMENTS ........................................ 3-1

LIST OF FIGURES

Figure 1-1: Front Panel of CPU Board and the Rotary Switch Positions ................... 1-2

Figure 1-2: Pinout of the Micro D-Sub and D-Sub Connector for RS232 .................. 1-4

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Page 48

SECTION 2 INSTALLATION

1. GENERAL OVERVIEW

Easy installation of the CPU board is provided since the memory map, the I/O devices, and the interfaces are configured to communicate with a standard terminal containing RS232 interface.

The monitor (VMEPROM) boots up automatically with the setup of the rotary switches on the front panel.

1.1 The Rotary Switches

Two rotary switches are installed on the CPU board to configure the startup of the VMEPROM or a user program.

The following lists the default configuration for bootup.

Switch Hex Code

2$F 1$F

The different functions of the rotary switches are described in detail in the well as in the

Hardware User's Manual

of this particular CPU board.

Introduction to VMEPROM

1.2 The Function Switch Positions

The CPU board contains two function switches. These two switches are defined as RESET and ABORT. The RESET switch is located in the first and upper position, and the ABORT switch is located directly underneath in the second and lower position.

The two moveable positions of these switches are defined as "Up" and "Down". All function switches must be set to the position "Down" upon performing initial installation. Please toggle each of the switches before installing the board in the rack in order to detect mechanical

damage to the switches during transport.

1-1

Page 49

SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

Figure 1-1: Front Panel of CPU Board and the Rotary Switch Positions

1-2

Page 50

SECTION 2 INSTALLATION

1.3 Connection of the Terminal

The terminal must be connected to the 9-pin Micro D-Sub connector 1 on the CPU board. The board is delivered with a 9-pin Micro D-Sub to 9-pin D-Sub adapter cable. The following communication setup is used for interfacing the terminal. Please configure the terminal to

this setup. No Parity

8 Bits per character 1 Stop Bit 9600 Baud Asynchronous Protocol

The hardware interface is RS232 compatible. The following signals are supported on the 9-pin Micro D-sub connector on the front panel:

Signal Input Output Required 9 Pin Micro Description 9 Pin D-Sub of the

D-Sub Adapter Cable

Connector

DCD X 1 Data Carrier Detect 1 RXD X X 2 Receive Data 2

TXD X X 3 Transmit Data 3 DTR X 4 Data Terminal Ready 4 GND 5 Signal GND 5 DSR X X 6 Data Set Ready 6

RTS X X 7 Request to Send 7

CTS X X 8 Clear to Send 8 GND X 9 Signal GND 9

CAUTION

1) The terminal used must not drive a signal line which is marked to be an output of CPU board.

2) All signals marked as "Required" must be supported from the terminal to enable the transmission.

3) If the terminal is configured to the listed setup, please connect the 9-pin Micro D-Sub connector to the terminal with a cable which supports all of the required signals.

1-3

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

Figure 1-2: Pinout of the Micro D-Sub and D-Sub Connector for RS232

A) Micro DS UB Mal e Connect or Soldered

on the CPU Board

RS232

DCD

DSR

RTS

CTS

GND

RXD

TXD

DTR

GND

B) Micro DSUB and DSUB Female Connectors

on the Adapter/Terminal Cable

RS232

GND

CTS

RTS

DSR

DTR

TXD

RXD

DCD

1-4

Page 52

SECTION 2 INSTALLATION

1.4 The Default Hardware Setup

The VMEbus interface is configured to be used immediately, without any changes. This results in a default hardware setup which may conflict with other boards installed in the rack. The following signals are driven/received from the CPU board:

Signal Driven Received From

SYSCLK X FGA-002 Gate Array BR3* X FGA-002 Gate Array BR[3..0]* X 4 Level Arbiter BG[3..0]OUT* X 4 Level Arbiter ACFAIL* X FGA-002 Gate Array SYSFAIL* X FGA-002 Gate Array SYSRESET* X X FGA-002 Gate Array

CAUTION

1) The on-board four level arbiter is enabled and reacts on every Bus Request*.

2) The CPU board is configured as a slot 1 controller.

1-5

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1-6

Page 54

SECTION 2 INSTALLATION

2. INSTALLATION IN THE RACK

The CPU board can immediately be mounted into a VME rack at slot 1.

CAUTION

1) Switch off power before installing the board to avoid electrical damage to the components.

2) The CPU board contains a special ejector (the handles). The board must be plugged in, and the screws on the front panel tightened up to guarantee proper installation.

3) Unplug every other VMEbus board to avoid conflicts.

2.1 Power ON

Power to the VMEbus rack may be switched on when the board is correctly installed, the switches are in the correct positions, and the terminal is correctly configured and under power.

Initially, the green RUN LED will light up, and after one to three seconds the message "Wait until hard disk is up to speed" will be displayed. A few seconds later the VMEPROM banner should appear.

The terminal is now at the user's discretion. At this point, it is advised to make a few carriage returns, to obtain the question mark (?_

) prompt.

2-1

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

2.2 Correct Operation

To test the correct operation of the CPU board, the following command must be typed in:

? SELFTEST<cr>

It is a matter of a few seconds until all tests are completed. Once all tests are completed, the following messages will appear on the screen:

VMEPROM Hardware Selftest

I/O test . . . . . .passed

Memory test . . . . .passed

Clock test . . . . . .passed

Any errors will be reported as they occur.

If an e rr or message i s displayed, please refer to command description "

SELFTEST

Section 7, "Introduction to VMEPROM

" containing the

2-2

Page 56

SECTION 2 INSTALLATION

3. ENVIRONMENTAL REQUIREMENTS

This board was specified and tested for reliable operation under certain environmental conditions. Based on our performance tests, this board is capable of operating within the temperature range of 0 C to 50 C

when used inside of a FORCE TARGET-32 chassis. The following chart details the calculated rate of forced air cooling.

Rate of Forced Air Cooling

Air Cooling per Board Total Air Cooling - Target-32

5.5 CFM* = 0.0026 cubic meter/sec 131 CFM = 0.062 cubic meter/sec

275 LFM** = 1.4 meter/sec 275 LFM = 1.4 meter/sec * CFM = Cubic Feet per Minute ** LFM = Linear Feet per Minute

The TARGET-32 chassis performs forced air cooling using four axial fans. The amount of airflow needed for cooling and normal operation is reflected by certain factors such as ambient temperature, number and location of boards in the system, and outside heat sources. Sufficient air cooling is normally obtained when

5.5 CFM and 275 LFM is circulating around each board at an ambient temperature between 0 C and 50 C. Allowable storage temperatures may range between -40 C and 85 C. The rate of relative humidity (non-

condensing) should not be less than 5%, and should not exceed 95%. The following illustration is a pictorial view of the fan placement in the chassis.

3-1

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HARDWARE USER'S MANUAL

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Page 59

TABLE OF CONTENTS

1. GENERAL INFORMATION ............................................ 1-1

2. THE PROCESSOR ................................................. 2-1

2.1 The CPU 68040 ................................................... 2-1

2.1.1 Hardware Interface of the 68040 ....................................... 2-1

2.1.1.1 General Operation .................................................. 2-1

2.2 The Instruction Set ................................................. 2-1

2.3 Vector Table of the 68040 ............................................ 2-2

3. THE LOCAL BUS .................................................. 3-1

3.1 The FGA-002 Gate Array ............................................. 3-1

3.2 The Shared RAM .................................................. 3-2

3.2.1 General Operation .................................................. 3-2

3.2.2 Shared RAM Information ............................................. 3-2

3.2.3 The DRM-03 ...................................................... 3-4

3.2.4 RAM Type Information for the DRM-03 .................................. 3-5

3.2.5 Summary of the DRM-03 ............................................. 3-5

3.2.6 The DRM-05 ...................................................... 3-6

3.2.7 RAM Type Information for the DRM-05 .................................. 3-7

3.2.8 Summary of the DRM-05 ............................................. 3-7

3.2.9 The SRM-01/4 ..................................................... 3-8

3.2.10 RAM Type Information for the SRM-01/4 ................................. 3-9

3.2.11 Summary of the SRM-01/4 ........................................... 3-9

3.2.12 The SRM-01/8 ..................................................... 3-10

3.2.13 RAM Type Information for the SRM-01/8 ................................. 3-11

3.2.14 Summary of the SRM-01/8 ........................................... 3-11

3.3 The System EPROM Area ........................................... 3-12

3.3.1 Memory Organization of the System EPROM Area ........................ 3-12

3.3.2 Usable Device Types for the EPROM Area .............................. 3-15

3.3.3 Access Time Selection of the System EPROM Area ....................... 3-18

3.3.4 Address Map of the System EPROM Area ............................... 3-18

3.3.5 Summary of the EPROM Area ........................................ 3-18

3.4 The FLXibus ..................................................... 3-19

3.4.1 Introduction to the FLXibus .......................................... 3-19

3.5 The Local FLASH EPROM .......................................... 3-20

3.5.1 Memory Organization of the FLASH EPROM ............................. 3-20

3.5.2 Programming the FLASH EPROM ..................................... 3-21

3.5.3 Address Map of the FLASH EPROM ................................... 3-21

3.5.4 Summary of the Local FLASH Memory ................................. 3-21

3.5.5 Jumper Settings for B16 ............................................ 3-21

3.5.6 Location Diagram of Jumperfield B16 .................................. 3-22

3.6 The Local SRAM .................................................. 3-23

Page 60

3.6.1 Memory Organization of the User SRAM ................................ 3-23

3.6.2 The Address Map of the SRAM Area ................................... 3-26

3.6.3 Summary of the SRAM Area ......................................... 3-26

3.7 The Boot EPROM ................................................. 3-27

3.7.1 Summary of the Boot EPROM Area .................................... 3-27

3.8 The DUSCC 68562 ................................................ 3-29

3.8.1 Address Map of the DUSCC1 Registers ................................ 3-30

3.8.2 RS232 Hardware Configuration of Port #1 and #2 ......................... 3-32

3.8.3 Cable for the Micro D-Sub Connector .................................. 3-38

3.8.4 RS422/RS485 Hardware Configuration of Ports #1 and #2 .................. 3-38

3.8.5 RS232 and RS422/RS485 Driver Modules FH002 and FH003 ................ 3-45

3.8.6 Summary of DUSCC1 .............................................. 3-45

3.8.7 Address Map of the DUSCC2 Registers ................................ 3-46

3.8.8 RS232 Hardware Configuration of Ports #3 and #4 ........................ 3-48

3.8.9 Cable for the Micro D-Sub Connector .................................. 3-52

3.8.10 RS422/RS485 Hardware Configuration of Port #3 and #4 ................... 3-52

3.8.11 RS232 and RS422/RS485 Driver Modules FH002 and FH003 ................ 3-58

3.8.12 Summary of DUSCC2 .............................................. 3-58

3.9 The PI/T 68230 ................................................... 3-59

3.9.1 Address Map of the PI/T1 Registers ................................... 3-60

3.9.2 I/O Configuration of PI/T1 ........................................... 3-61

3.9.3 Rotary Switches .................................................. 3-62

3.9.4 Lock Cycles ...................................................... 3-64

3.9.5 Interrupt Request Signal ............................................ 3-65

3.9.6 A24 Slave Mode .................................................. 3-65

3.9.7 Reserved Lines ................................................... 3-65

3.9.8 Summary of PI/T1 ................................................. 3-66

3.9.9 Address Map of the PI/T2 Registers ................................... 3-67

3.9.10 I/O Configuration of PI/T2 ........................................... 3-68

3.9.11 Memory Size Recognition ........................................... 3-69

3.9.12 Board Identification ................................................ 3-69

3.9.13 Interrupt Request Signal ............................................ 3-69

3.9.14 12 Bit I/O Port .................................................... 3-70

3.9.15 MODLOW ....................................................... 3-72

3.9.16 RAM Module Configuration Signals .................................... 3-72

3.9.17 Timer IRQ/Reset .................................................. 3-73

3.9.18 PIRQ ........................................................... 3-73

3.9.19 Enable A24 Slave Mode ............................................ 3-73

3.9.20 Reserved Line .................................................... 3-74

3.9.21 Summary of PI/T2 ................................................. 3-74

3.10 The Real Time Clock (RTC) 72423 .................................... 3-75

3.10.1 Address Map of the RTC Registers .................................... 3-75

3.10.2 RTC Programming ................................................ 3-75

3.10.3 Summary of the RTC ............................................... 3-79

4. FUNCTION SWITCHES AND INDICATION LEDs .......................... 4-1

4.1 RESET Function Switch ............................................. 4-1

Page 61

4.2 ABORT Function Switch ............................................. 4-1

4.3 "RUN" LED ....................................................... 4-2

4.4 "BM" LED ........................................................ 4-2

4.5 Rotary Switches ................................................... 4-2

5. THE CPU BOARD INTERRUPT STRUCTURE ............................ 5-1

6. VMEBUS INTERFACE .............................................. 6-1

6.1 VMEbus Master Interface ............................................ 6-1

6.1.1 Data Transfer Size of the VMEbus Interface .............................. 6-1

6.1.2 Address Modifier Implementation ...................................... 6-4

6.2 VMEbus Slave Interface ............................................. 6-8

6.2.1 The Access Address ................................................ 6-8

6.2.2 Data Transfer Size of the Shared RAM .................................. 6-8

6.2.3 Address Modifier Decoding and A24 Slave Mode .......................... 6-8

6.3 The VMEbus Interrupt Handler ....................................... 6-11

6.4 VMEbus Arbitration ................................................ 6-12

6.4.1 Four Available VMEbus Arbiters ...................................... 6-12

6.4.2 The On-Board Four Level Arbiter ...................................... 6-12

6.4.3 The VMEbus Release Function ....................................... 6-18

6.4.3.1 Release Every Cycle (REC) .......................................... 6-18

6.4.3.2 Release on Request (ROR) .......................................... 6-18

6.4.3.3 Release After Timeout (RAT) ........................................ 6-18

6.4.3.4 Release on Bus Clear (RBCLR) ....................................... 6-19

6.4.3.5 Release When Done (RWD) ......................................... 6-19

6.4.3.6 Release Voluntary (RV) ............................................. 6-19

6.4.3.7 Release on ACFAIL (ACFAIL) ........................................ 6-19

6.5 The VMEbus Interrupter ............................................ 6-21

6.5.1 The Interrupt Generation Register ..................................... 6-21

6.5.2 The Interrupt Vector Register ........................................ 6-22

6.6 The SYSCLK Driver ............................................... 6-23

6.7 Exception Signals ................................................. 6-25

6.8 RESET Generation ................................................ 6-27

6.8.1 The Front Panel RESET Switch ...................................... 6-27

6.8.2 The Voltage Sensor Module FH001 .................................... 6-27

6.8.3 VMEbus RESET Conditions ......................................... 6-29

6.8.3.1 Receive RESET from VMEbus ....................................... 6-29

6.8.3.2 Drive RESET to VMEbus ............................................ 6-29

6.8.3.3 Default Configuration of Jumperfield B13 ................................ 6-29

6.8.4 The RESET Instruction ............................................. 6-31

iii

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LIST OF FIGURES

Figure 2-1: Jumper Setting for B17 .............................................. 2-3

Figure 2-2: Location Diagram of Jumperfields B17 .................................. 2-4

Figure 3-1: Memory Organization of the System EPROM Area ........................ 3-12

Figure 3-2: Location Diagram of the System EPROM Area ........................... 3-13

Figure 3-3: Configuration Jumper Settings of System EPROM Area Jumperfield B11 ....... 3-16

Figure 3-4: Location Diagram of Jumperfield B11 Configuration of the System EPROM Area . 3-17

Figure 3-5: Location Diagram of the Backup Supply Jumperfield B1 and B20 ............. 3-25

Figure 3-6: Location Diagram of the Boot EPROM ................................. 3-28

Figure 3-7: Location Diagram of the 0S Resistors R563 to R569 ....................... 3-34

Figure 3-8: RS232 Connection Between DUSCC1 and VMEbus Connector P2 ............ 3-35

Figure 3-9: RS232 Connection Between DUSCC1 and Micro D-Sub Connector ............ 3-35

Figure 3-10: Pinout of the Micro D-Sub and D-Sub Connector for RS232 ................. 3-35

Figure 3-11: Location Diagram of RS232 Configuration Jumperfields B3, B4, B5, and B6 ..... 3-37

Figure 3-12: Location Diagram of the 0S Resistors R563 to R569 ....................... 3-40

Figure 3-13: RS422/RS485 Connection between DUSCC1 and VMEbus Connector P2 ...... 3-41

Figure 3-14: RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors ............. 3-42

Figure 3-15: Location Diagram of RS422/RS485 Configuration Jumperfields B3, B4, B5, and B6

.................................................................... 3-43

Figure 3-16: Location Diagram of RS232/RS422/RS485 Driver/Receivers J20 and J21 plus

Resistor Arrays J22 and J23 ......................................... 3-44

Figure 3-17: Connection Between DUSCC2 and D-Sub Connector for RS232 .............. 3-49

Figure 3-18: Location Diagram of RS232 Configuration Jumperfields B7 through B10 ........ 3-50

Figure 3-19: RS232 Pinout of the Micro D-Sub and D-Sub Connectors ................... 3-51

Figure 3-20: Connection between DUSCC2 and Micro D-Sub Connector for RS422/RS485 . . . 3-53 Figure 3-21: Location Diagram of RS422/RS485 Configuration Jumperfields B7 through B10 . . 3-54

Figure 3-22: RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors ............. 3-55

Figure 3-23: Loc ation Diagram of RS232/RS422/RS485 Driver/Receiver J25/J26 and Resistor

Arrays J27/J28 ................................................... 3-57

Figure 3-24: CPU Board Front Panel and Rotary Switch Positions ....................... 3-63

Figure 3-25: Location Diagram of Header B12 ...................................... 3-71

Figure 3-26: RTC Programming Example ......................................... 3-76

Figure 3-27: Location Diagram of the Backup Supply Jumperfield B1 and B20 ............. 3-78

Figure 4-1: Front Panel of the CPU Board ......................................... 4-3

Figure 6-1: Requester/Arbiter Jumperfield B19 .................................... 6-16

Figure 6-2: Location Diagram of Jumperfield B19 .................................. 6-17

Figure 6-3: Usage of Jumperfield B13 ........................................... 6-23

Figure 6-4: Location Diagram of B13 ............................................ 6-24

Figure 6-5: Usage of Jumperfield B13 ........................................... 6-25

Figure 6-6: Location Diagram of Jumperfield B13 .................................. 6-26

Figure 6-7: Jumper Settings for Jumperfield B2 .................................... 6-27

Figure 6-8: Location Diagram of Jumperfield B2 ................................... 6-28

Figure 6-9: Location Diagram of Jumperfield B13 .................................. 6-30

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LIST OF TABLES

Table 2-1: Exception Vector Assignments ........................................ 2-2

Table 3-1: Address Map of the EPROM Area ..................................... 3-18

Table 3-2: Serial I/O Port #1 (DUSCC1) Register Address Map ....................... 3-30

Table 3-3: Serial I/O Port #2 (DUSCC1) Register Address Map ....................... 3-31

Table 3-4: Ports #1 and #2 (DUSCC1) Common Register Address Map ................. 3-31

Table 3-5: Default Setting of RS232 Configuration Jumperfields ....................... 3-38

Table 3-6: RS422/RS485 Configuration Jumperfield Settings ......................... 3-41

Table 3-7: PCB Locations for the RS232/RS422/RS485 Configuration .................. 3-42

Table 3-8: Serial I/O Port #3 (DUSCC2) Register Address Map ....................... 3-46

Table 3-9: Serial I/O Port #4 (DUSCC2) Register Address Map ....................... 3-47

Table 3-10: Ports #3 and #4 (DUSCC2) Common Registers Address Map ................ 3-48

Table 3-11: Default Setting of the RS232 Configuration Jumperfields .................... 3-51

Table 3-12: RS422/RS485 Configuration Jumperfield Setting .......................... 3-55

Table 3-13: PCB Locations for RS232/RS422/RS485 Configuration ..................... 3-56

Table 3-14: PI/T1 Register Layout .............................................. 3-60

Table 3-15: PI/T1 Interface Signals ............................................. 3-61

Table 3-16: PI/T2 Register Layout .............................................. 3-67

Table 3-18: PI/T2 Interface Signals ............................................. 3-68

Table 3-17: RTC Register Layout ............................................... 3-75

Table 6-1: Data Bus Size of the VMEbus ......................................... 6-2

Table 6-2: Defined VMEbus Transfer Cycles (D32 Mode) ............................. 6-3

Table 6-3: Defined VMEbus Transfer Cycles (D16 Mode) ............................. 6-3

Table 6-4: Address Ranges ................................................... 6-4

Table 6-5: Address Modifier Codes ............................................. 6-5

Table 6-6: Address Modifier Codes Used on the CPU Board .......................... 6-7

Table 6-7: VMEbus Slave AM Codes ........................................... 6-10

Table 6-8: VMEbus Arbiter/Requester Register Layout .............................. 6-13

Table 6-9: Description of Arbiter/Requester Register Bits ............................ 6-13

Table 6-10: Bit Settings for VMEbus Request Level ................................. 6-14

Table 6-11: Bit Settings for VMEbus Arbiter Mode .................................. 6-15

Table 6-12: Bus Release Functions ............................................. 6-20

Table 6-13: VMEbus Interrupter Registers ........................................ 6-21

Table 6-14: Description of the IRQ Generation Register .............................. 6-22

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SECTION 3 HARDWARE USER'S MANUAL

1. GENERAL INFORMATION

The board is able to hold a RAM Module which can be DRAM (CPU-40) or SRAM (CPU-41) based. The C PU-40/41 family design utilizes all of the features o f the powerful FORCE Gate Array (FGA-002).

Among its features is a 32-bit DMA controller which supports local (shared) memory, VMEbus and I/O data transfers for maximum performance, parallel real time operation and responsiveness.

Four multiprotocol serial I/O channels, a parallel I/O channel and a Real Time Clock with on-board battery backup are installed on the base board which, in combination with EAGLE modules, makes the CPU board a true single board computer system.

A broad range of operating systems and kernels is available for the CPU board. However, as with all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the 16-bit wide EPROM sockets, which results in a 32-bit wide System EPROM area. This ensures that the board is supplied ready to use.

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2. THE PROCESSOR

2.1 The CPU 68040

2.1.1 Hardware Interface of the 68040

The 6 8 0 40 uses a nonmultiplexed 32-bit address and 32-bit data bus. The 68040 does not support t he dynamic bus sizing like the 68020 or 68030. On this CPU board the dynamic bus sizing is built in external hardware (two programmable gate arrays). This means if the 68040 does a long word read from a byte device, the external hardware will fetch 4 bytes from this byte wide device, from a long word and acknowledge the access cycle to the 68040. Therefore all device drives within the 68020 or 68030 can be used on this CPU board. Please note that the 68040 has a 4 Kbyte instruction and a 4 Kbyte data cache which may cause problems.

2.1.1.1 General Operation

The CPU drives the address lines (A0-A31), the size lines (SIZ0, SIZ1) the transfer type (TT0-TT1) on every cycle, and modifier (TM0-2) signals independent of a cache hit or miss. These signals are used to decode the memory map of the CPU board.

The transfer start (TS) signals the hardware on the CPU board that the current cycle is not a cache cycle, and that the decoding outputs are valid.

The 32 data lines (D0-D31) are also driven from the processor on write cycles and sensed on read cycles. The si ze of the data transfer is defined by the SIZE output signals (always driven from the CPU when

master). The transfer acknowledge or the transfer error acknowledge signal (TA, TEA) or both terminate the transfer cycle. CPU 68040 cycles only allow a port width of 32 bits.

If an acc ess error occurs (TE A sensed from th e CPU), exception handling starts because the current cycle has been aborted (illegal transfer or wrong data).

During local bus operation, an access error will be generated if a device does not respond correctly. VMEbus transfers may also be aborted via a TEA (VMEbus : BERR*). The TA and TEA signal asserted simultaneously initiate a retry cycle.

2.2 The Instruction Set

For t h e 68040 instruction set and further information relative to programming, please refer to the 68040 User's Manual.

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2.3 Vector Table of the 68040

The following table lists all vectors defined and used by the 68040 CPU.

Table 2-1: Exception Vector Assignments

Vector Vector Offset Assignment

Number(s) (Hex)

0 000 Reset Initial Interrupt Stack Pointer 1 004 Reset Initial Program Counter 2 008 Access Fault (Bus Error) 3 00C Address Error

4 010 Illegal Instruction 5 014 Integer Divide by Zero 6 018 CHK, CHK2 Instruction 7 01C FTRAPcc, TRAPcc, TRAPV Instructions

8 020 Privilege Violation

9 024 Trace 10 028 Line 1010 Emulator (Unimplemented A-Line Opcode) 11 02C Line 1111 Emulator (Unimplemented F-Line Opcode)

12 030 (Unassigned, Reserved) 13 034 Defined for MC68020/MC68030, not for MC68040 14 038 Format Error 15 03C Uninitialized Interrupt

16-23 040-05C (Unassigned, Reserved)

24 060 Spurious Interrupt 25 064 Level 1 Interrupt Autovector 26 068 Level 2 Interrupt Autovector 27 06C Level 3 Interrupt Autovector

28 070 Level 4 Interrupt Autovector 29 074 Level 5 Interrupt Autovector 30 078 Level 6 Interrupt Autovector 31 07C Level 7 Interrupt Autovector

32-47 080-0BC TRAP #0-15 Instruction Vectors

48 0C0 FP Branch or Set on Unordered Condition 49 0C4 FP Inexact Result 50 0C8 FP Divide by Zero 51 OCC FP Underflow

52 ODO FP Operand Error 53 OD4 FP Overflow 54 0D8 FP Signaling NAN 55 ODC FP Unimplemented Data Type

56 0E0 Defined for MC68030 and MC68851, not for MC68040 57 0E4 Defined for MC68851, not for MC68040 58 0E8 Defined for MC68851, not for MC68040

59-63 0EC-0FC (Unassigned, Reserved)

64-255 100-3FC User Defined Vectors (192)

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For tes t purposes the clock signal for the microprocessor is connected via jumper B17 to the devices. When using the CPU board, this jumper must be inserted according to the following figure.

CAUTION

If jumper B17 is removed, damage may be caused to the devices on the CPU board.

Figure 2-1: Jumper Setting for B17

B17 ** o 2 1

+)))))))),+)))))))),

))))))))o **

.))))))))-.))))))))-

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Figure 2-2: Location Diagram of Jumperfields B17

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SECTION 3 HARDWARE USER'S MANUAL

3. THE LOCAL BUS

3.1 The FGA-002 Gate Array

The FGA-002 Gate Array featured on this CPU board has 24,000 gates and 281 pins. The FGA-002 Gate Array controls the local bus and builds the interface to the VMEbus. It also includes

a DMA controller, complete interrupt management, a message broadcast interface (FMB), timer functions, and mailbox locations.

This gate array monitors the local bus. This in turn signifies that if any local device is to be accessed, the gate array takes charge of all control signals in addition to used address and data signals.

The FGA-002 Gate Array serves as a manager for the VMEbus. All VMEbus address and data lines are connected to the gate array through the buffers. Additional functions such as the VMEbus interrupt handler are al so installed on the FGA-002 Gate Array. The SGL VMEbus arbiter in the FGA/002 must remain disabled because the 4 level VME arbiter of the CPU board is designed in a separate device and connected with the VME bus (please refer to chapter 6.4

The start address of the FGA-002 Gate Array registers is $FFD00000. All registers of the gate array and associated functions are described in detail in the FGA-002 Gate Array User's Manual.

VMEbus Arbitration

for further information).

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3.2 The Shared RAM

On this CPU board the shared RAM is placed on a module to allow the adaptation of DRAM or SRAM to the base board.

3.2.1 General Operation

The Shared RAM is accessible from the 68040 and from the VMEbus. The access address for the 68040 starts at $00000000. The access address for the VMEbus is softwar e programmable in 4 Kbyte steps. The defined memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

If an access from the VMEbus takes place the onboard logic requests the local bus mastership from the local arbiter via the FGA-002 Gate Array. After the arbiter has granted local bus mastership to the FGA-002 Gate Array, the access cycle is executed. A read cycle is terminated by latching all data from the memory; a write cycle is ended by storing the data in the memory cells. Both read and write cycles are terminated on the local bus side and the FGA-002 Gate Array immediately releases bus mastership to the CPU while completing the fully asynchronous VMEbus access cycle.

3.2.2 Shared RAM Information

The RAM module connector holds several signals which are software readable and inform the user concerning RAM type and functionality.

These pins are readable via the PI/T2 device which is installed on the CPU board. For base address and regi st er address information please refer to the chapter 3.9.9 further information.

Address Map of the PI/T2 Registers

for

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The f o llowing table shows the information which can be read and the corresponding PI/T bit. The RAM modules which are accessible are described in the following chapters which also contain the

Information

description.

RAM Type

RAM Type Information on PI/T2

PI/T Bit Name Value Description

PB0 MCD0 * Describes the memory size of the module. PB1 MCD1 * Please refer to the following chapters. PB2 MCD2 *

PC2 RAMTYP 0 SRAM

1 DRAM

PC4 BURST 0 Not available

1 Available

PC6 PARITY 0 Not available

1 Available

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3.2.3 The DRM-03

The following CPU board is assembled with the DRM-03.

CPU Board RAM Module RAM Capacity

CPU-40B/4/xx DRM-03/4 4 Mbyte

"xx" contains the EAGLE module number and is independent of the RAM module.

Features of the DRM-03

The access address for the 68040 is as follows:

The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

4 Mbyte DRAM Burst READ and Burst WRITE capability Parity Generation and Checking Asynchronous refresh is provided every 14µs Accessible via VMEbus

RAM Module Access Address

DRM-03/4 $ 0000 0000 .. $ 003F FFFF

The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

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Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal Cycles

CPU-40/B 25 MHz 4 1 3 0

3.2.4 RAM Type Information for the DRM-03

The following information can be read from the PI/T2.

RAM Type Information

PI/T Bit Name DRM-03/4

PB0 MCD4 1 PB1 MCD1 1 PB2 MCD2 0

PC2 RAMTYP 1 PC4 BURST 1 PC6 PARITY 1

3.2.5 Summary of the DRM-03

Capacity 4 Mbyte Port Data Width 32 bits Local Data Width 128 bits and 16 bit parity Burst Mode Supported Parity Mode Supported Device 256K x 18 Fast Page Mode Supported Transfers Byte, Word, Long word, Cache Line (16 bytes)

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3.2.6 The DRM-05

The following CPU boards are assembled with the DRM-05.

CPU Board RAM Module RAM Capacity

CPU-40B/16/xx DRM-05/16 16 Mbyte CPU-40B/32/xx DRM-05/32 32 Mbyte

"xx" contains the EAGLE module number and is independent of the RAM module.

Features of the DRM-05

The access address for the 68040 is as follows:

The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined mem or y ra nge can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

16 or 32 Mbyte DRAM Burst READ and Burst WRITE capability Parity Generation and Checking Asynchronous refresh is provided every 14µs Accessible via VMEbus

RAM Module Access Address

DRM-05/16 $ 0000 0000 .. $ 00FF FFFF DRM-05/32 $ 0000 0000 .. $ 01FF FFFF

The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

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Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal

Cycles

CPU-40/B 25 MHz 4 1 3 0

3.2.7 RAM Type Information for the DRM-05

The following information can be read from the PI/T2.

RAM Type Information

PI/T Bit Name DRAM-05/16 DRAM-05/32

PB0 MCD4 1 0 PB1 MCD1 0 0 PB2 MCD2 0 0

PC2 RAMTYP 1 1 PC4 BURST 1 1 PC6 PARITY 1 1

3.2.8 Summary of the DRM-05

Capacity 16 or 32 Mbyte Port Data Width 32 bits Local Data Width 128 bits and 16 bit parity Burst Mode Supported Parity Mode Supported Device 1M x 4 /4M x 1 Fast Page Mode Supported Transfers Byte, Word, Long word, Cache Line (16 bytes)

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SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

3.2.9 The SRM-01/4

The following CPU boards are assembled with the SRM-01/4.

CPU Board RAM Module

CPU-41B/4/xx SRM-01/4

"xx" contains the EAGLE module number and is independent for the RAM module.

The SRM-01/4 is a 4 Mbyte RAM module using Static Memory devices. The RAM module has the following features.

Features of the SRM-01/4

4 Mbyte SRAM Burst READ and Burst WRITE capability Battery Backup via VMEbus

Accessible via VMEbus The access address for the 68040 is $00000000 to $003FFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be read.

Pari ty check is not necessary for SRAM devices because these components are protected against soft errors owing to alpha emission. The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal Cycles

CPU-41/B 25 MHz 3 1 2 0

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3.2.10 RAM Type Information for the SRM-01/4

The following information can be read from the PI/T2.

RAM Type Information

PI/T Bit Name Value

PB0 MCD4 1 PB1 MCD1 1 PB2 MCD2 0

PC2 RAMTYP 0 PC4 BURST 1 PC6 PARITY 0

3.2.11 Summary of the SRM-01/4

Capacity 4 Mbytes Address Range $00000000 to $003FFFFF Port Data Width 32 bits Local Data Width 128 bits Burst Mode Supported Parity Mode Not necessary Device 128K x 8 Static RAM Supported Transfers Byte, Word, Long word, Cache Line (16 bytes)

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3.2.12 The SRM-01/8

The following CPU boards are assembled with the SRM-01/8.

CPU Board RAM Module

CPU-41B/8/xx SRM-01/8

"xx" contains the EAGLE module number and is independent for the RAM module.

The SRM-01/8 is an 8 Mbyte RAM module which is used on the CPU-41B/8.

Features of the SRM-01/8

8 Mbyte SRAM

Burst READ and Burst WRITE capability

Battery Backup via VMEbus

Accessible via VMEbus The access address for the 68040 is $00000000 to $007FFFFF. The access address for the VMEbus is programma ble in 4 Kbyte steps through the FGA-002. The defined

memory range can be write protected in coordination with the address modifier codes. For example, in supervisor mode the memory can be read and written, in user mode memory can only be

read. Pari ty check is not necessary for SRAM devices because these components are protected against soft

errors owing to alpha emission. The following chart lists the required CPU clock cycles and wait states for accessing the shared RAM.

Board 68040 Clock No. of CPU Clock No. of CPU Clock No. of Wait No. of Wait

Type Frequency Cycles Counted Cycles for States for States for

From TS to TA Burst Cycles Normal Cycles Burst Cycles

for Normal

Cycles

CPU-41/B 25 MHz 3 1 2 0

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3.2.13 RAM Type Information for the SRM-01/8

The following information can be read from the PI/T2.

RAM Type Information

PI/T Bit Name Value

PB0 MCD4 0 PB1 MCD1 1

PB2 MCD2 0 PC2 RAMTYP 0 PC4 BURST 1 PC6 PARITY 0

3.2.14 Summary of the SRM-01/8

Capacity 8 Mbytes Address Range $00000000 to $007FFFFF Port Data Width 32 bits Local Data Width 128 bits Burst Mode Supported Parity Mode Not necessary Device 128K x 8 Static RAM Supported Transfers Byte, Word, Long word, Cache Line (16 bytes)

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3.3 The System EPROM Area

The first two read cycles after RESET of the microprocessor are fetches of the Initial Interrupt Stack Pointer and the Initial Program Counter. These cycles are executed under addresses $0 and $4 respectively. A special control logic maps the System EPROM Area down to this address to start the CPU from the installed EPROMs. As a result of this downmapping, the first two long words in the EPROM must contain the following data:

$0 in EPROM Initial Interrupt Stack Pointer $4 in EPROM Initial Program Counter

The data path of the System EPROM A rea i s 32 b its wi de. The system EPROM consists of two 16 bit wide EPROM devices.

3.3.1 Memory Organization of the System EPROM Area

The memory organization of the System EPROM and the location number of the sockets are outlined in the following figure. The one after that shows the location diagram of the sockets.

Figure 3-1: Memory Organization of the System EPROM Area

Long Word Address

$FF00 0000

$FF00 0004

D31 D24 D23 D16 D15 D8 D7 D0

Byte 0 Byte 1 Byte 2 Byte 3

$FF00 0000 $FF00 0001 $FF00 0002 $FF00 0003

Byte 4 Byte 5 Byte 6 Byte 7

$FF00 0004 $FF00 0005 $FF00 0006 $FF00 0007

. . .

UU UM LM LL

J30 J30 J29 J29

UU = Upper Upper Byte in J30 UM = Upper Middle Byte in J30 LM = Lower Middle Byte in J29 LL = Lower Lower Byte in J29

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Figure 3-2: Location Diagram of the System EPROM Area

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The following read only cycles can be forced to the System EPROM Area:

Byte: 8 Bits

Word: 16 Bits ** Long Word: 32 Bits

The processor supports long word read instructions to odd addresses, resulting in byte and word accesses which meet the 68040 boundary requirements. If a user program must be burned into EPROMs for CPU board usage, the data bytes must be burned into the different chips as shown below.

Device Locations Address

UU, UM: XXX0 XXX1

J30 (UPPER) XXX4 XXX5

XXX8 XXX9

XXXC XXXD

LM, LL: XXX2 XXX3

J29 (LOWER) XXX6 XXX7

XXXA XXXB XXXE XXXF

CAUTION

1) The bus size of the System EPROM Area cannot be changed. Two EPROMs must always be used for proper operation.

2) Microprocessor interactive fetches can only be on addresses ($0,2,4,6, 8...). An Address Trap Error occurs if a program is started/executed on odd addresses ($1,3,5,7...).

3) Data can be read from any address; odd, even or unaligned in byte, word, or long word format.

4) Write cycles to the EPROM Area are forbidden.

5) All chips must be the same device type and access time for usage in System EPROM Area.

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Example for Data Transfers:

The following instruction is fully supported from the System EPROM Area: MOVE.X ($FF00 000Y), D0 X = B = Byte 1 Byte

X = W = Word 2 Bytes X = L = Long Word 4 Bytes

Y=0 Y=1 Y=2 Y=3

. . .

All combinations of the listed instructions are allowed and possible.

3.3.2 Usable Device Types for the EPROM Area

The following device types or equivalent are supported by the System EPROM Area:

Device Device Capacity Total Capacity Default Configuration

27210 64K x 16 256 Kbytes

272048 128K x 16 512 Kbytes X UNDEFINED 256K x 16 1 Mbyte UNDEFINED 512K x 16 2 Mbytes

The default configuration, using 27210 devices, is provided for the installation of VMEPROM. The following fig ure outlines the different jumper settings for the listed device types and the one to follow shows the location diagram of Jumperfield B11 for device dependent configuration. The Appendix of this Hardware User's Manual lists a table of the usable pinouts for the System EPROM Area if other devices than those listed must be used.

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Figure 3-3: Configuration Jumper Settings of System EPROM Area Jumperfield B11

Jumpersetting: Device: Organization:

B11

o o

o o o o

27C210 64K x 16

B11

))))

o o o o

27C2048 128K x 16

(DEFAULT)

B11

))))

o o

UNDEFINED 256K x 16

B11

))))

UNDEFINED 512K x 16

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Figure 3-4: Location Diagram of Jumperfield B11 Configuration of the System

EPROM Area

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3.3.3 Access Time Selection of the System EPROM Area

The access ti me of the System EPRO M Area is so ftware programmable in the FGA-002 Gate Array. It can be adapted to various access speeds of the EPROM devices. A complete description of the FGA-002 Gate Array can be found in the related manual.

3.3.4 Address Map of the System EPROM Area

The s tar t address of the System EPROM Area is mapped via the FGA-002 Gate Array and cannot be changed. The size of this memory area depends on the memory capacity of the used devices. T he following table lists the address map of the EPROM area.

Table 3-1: Address Map of the EPROM Area

Start Address End Address Used Device Total Capacity Default

Configuration

FF00 0000 FF03 FFFF 27210 256 KBYTES FF00 0000 FF07 FFFF 272048 512 KBYTES X FF00 0000 FF0F FFFF UNDEFINED 1 MBYTE FF00 0000 FF1F FFFF UNDEFINED 2 MBYTES

3.3.5 Summary of the EPROM Area

Not Allowed Access with Function Code 111 Usable Data Bits D00 - D31 Supported Port Size Long Word No. of Devices to be Installed 2 Upper Upper Byte J30

Upper Middle Byte J30 Lower Middle Byte J29 Lower Lower Byte J29

Maximum Capacity 2 Mbytes Default Configuration for 128K * 16 Devices Default Access Time 200ns Access Address Range $FF00 0000 START

$FF03 FFFF END

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3.4 The FLXibus

The CPU board can be used with or without an I/O subsystem, called an "EAGLE" Module. The EAGLE module increases the functionality of the board and adds extra I/O features to fit the application

requirement. EAGLE modules connect directly to the FLXi (FORCE Local eXpansion interface) of the base board.

If your CPU board is assembled with an EAGLE module please refer to the is shipped with this board and should be placed in

Section 6

of this manual.

"EAGLE Module"

manual which

3.4.1 Introduction to the FLXibus

The FLXi (FORCE Local eXpansion interface) is a 32 bit interface with non-multiplexed data and address lines.

An EAGLE module holds a FLXibus interface and an I/O interface (64 pins), which is directly connected to row a and row c of the VMEbus P2 connector.

The aim of the EAGLE module concept is to be more flexible in the I/O part of the board. This circumvents the complete redesign of a board if new I/O devices or customer specific solutions must be implemented. By having several modules available, the necessity of designing new boards is avoided.

The EAGLE module has the ability to become master of the FLXi and therefore the devices on the EAGLE module are able to transfer data to the "main memory" on the base board if they have DMA capability.

Features of the FLXibus

One or more identical or different EAGLE modules can be used on a base board. This CPU board is capable of holding one EAGLE module.

The EAGLE modules contain all necessary software which is stored in the on-board EPROMs. The EAGLE module can become bus master (e.g. for DMA transfers) on the base board. Interrupts to the base boards are supported. FLXibus definition is based on the 68020 asynchronous interface and supports frequencies up to

50 MHz.

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3.5 The Local FLASH EPROM

The CPU board holds a 128K x 8 FLASH EPROM which allows data storage without the need of a battery or supply via the +5VSTDBY VMEbus line.

3.5.1 Memory Organization of the FLASH EPROM

The FLASH EPROM is connected with the data lines D24 to D31. This device features a byte port. The cycle control chip (CCC) between the 68040 processor and the FGA-002 simulates the dynamic bus sizing, so that succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes for the FLASH EPROM. Byte, word, and long word accesses are managed by the dynamic bus sizing of the microprocessor. For further details, please refer to the CCC description.

Data can be read from any address; odd, even or unaligned in byte, word, or long word format, and written to any address in byte format.

Example for Data Transfers:

The following instruction is fully supported from the FLASH EPROM Area:

MOVE.X ($FFC8 000Y), D0 X = B = Byte 1 Byte

X = W = Word 2 Bytes X = L = Long Word 4 Bytes

Y = 0 Y = 1 Y = 2 Y = 3 . . .

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3.5.2 Programming the FLASH EPROM

The softwar e and hardware to erase and program the FLASH EPROM is installed on the CPU board. For detailed information on how to program the FLASH EPROM, please refer to the CPU-40 VMEPROM description which is located in

Before programming the FLASH EPROM the write protection jumper on jumperfield B16 must be set from 1-2 to 2-3. The following page shows the location of jumperfield B16.

Section 7

and

Section 8

of this manual.

3.5.3 Address Map of the FLASH EPROM

The address range of the FLASH EPROM Area is mapped via the FGA-002 and a PAL and is unchangeable.

3.5.4 Summary of the Local FLASH Memory

Not Allowed Access with Function Code 1 1 1 Supported Port Size Byte Capacity 128 Kbytes Chip Organization 128K x 8 Access Time 200ns Access Address $FFC80000 to FFC9FFFF

3.5.5 Jumper Settings for B16

** ** ** 1 ** o ** Write disabled = 1 ** o ** Write enabled ** ** ** Write Protection ** ** o ** (Default) ** o ** ** ** ** ** o ** ** o

+))))),+))))),

.)))))-.)))))-

+))))),+))))),

** ** ** **

.)))))-.)))))-

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3.5.6 Location Diagram of Jumperfield B16

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3.6 The Local SRAM

The SRAM allows the user to retain data even when the power supply is switched off. A battery provides the v o lt age for the SRAM standby mode. With Jumper B20, it is possible to select either the on board battery or the +5VSTDBY of the VMEbus for backup supply.

3.6.1 Memory Organization of the User SRAM

This device features a byte port. External hardware simulates the dynamic bus sizing, so that succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes for the Local SRAM. B yte, word , and long word accesses are managed by the dynamic bus sizing of the external hardware.

Data can be read from and written to any address; odd, even or unaligned in byte, word, or long word format.

Example for Data Transfers:

The following instruction is fully supported from the SRAM Area:

MOVE.X ($FFC0 000Y), D0 X = B = Byte 1 Byte

X = W = Word 2 Bytes X = L = Long Word 4 Bytes

Y = 0 Y = 1 Y = 2 Y = 3 . . .

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All combinations of the listed instructions are allowed and possible. This SRAM can be used to save special settings of the FGA-002 as described in

to VMEPROM

The following figure shows the location diagram of Jumperfield B20 for the backup supply. The default configuration uses the on board battery.

Please note that the Real Time Clock on the CPU board is supplied via the same jumperfield.

of this manual.

Section 7, Introduction

B1 B1

+))),

1 * o * Battery is connected to 1 * o * Battery is cut from * | * Backup Supply Line * * Backup Supply Line * o * (default) * o

.)))-

B20 B20

+))),

1 * o * +5VSTDBY is connected to 1 * o * +5VSTDBY is cut from * | * Backup Supply Line * * Backup Supply Line * o * * o * (default)

.)))-

NOTE

The battery is not installed on the CPU board to avoid damage during shipment.

CAUTION

If the special settings for the FGA-002 which are stored in the SRAM are used, these settings will be erased when

a) removing the jumper on jumperfield B1 or disassembling the battery

and

b) removing the jumper on jumperfield B20 or removing the board from the VMEbus.

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Figure 3-5: Location Diagram of the Backup Supply Jumperfield B1 and B20

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3.6.2 The Address Map of the SRAM Area

The address range of the SRAM Area is mapped via the FGA-002 and a PAL and is unchangeable. The SRAM is used by the boot software and therefore not fully available to the user. Please refer to the

002 User's Manual, Section 10, Boot Software

FGA-

3.6.3 Summary of the SRAM Area

Not Allowed Access with Function Code 111 Supported Port Size Byte Capacity 128 Kbytes Chip Organization 128K * 8 Devices Access Time 100ns Access Address $FFC0 0000 - $FFC1 FFFF

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3.7 The Boot EPROM

The CPU board contains one 28-pin EPROM which is used to boot up the processor and run a program to initialize register contents of the FGA-002 Gate Array. This program finishes in such a manner that the System EPROM appears to have booted the CPU Board. The device type of the Boot EPROM is 27512 with the total memory capacity of 64 Kbytes. The location is J15.

For more detailed information over the Boot EPROM, please refer to

Description

The figure on the page to follow displays the location of the Boot EPROM on the CPU board.

of the FGA-002 Users Manual.

Section 10, Boot Software

3.7.1 Summary of the Boot EPROM Area

Access Not Allowed with Function Code 111 Supported Port Size Byte No. of Devices to be installed 1 Maximum Capacity 64 Kbytes Default Access Time 200ns Access Address $FFE0 0000 - $FFE0 FFFF

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Figure 3-6: Location Diagram of the Boot EPROM

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3.8 The DUSCC 68562

The Dual Universal Serial Communications Controller 68562 (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multiprotocol, full duplex receiver/ transmitter channels in a single package. Each channel consists of a receiver, a transmitter, a 16 bit multifunction counter/timer, a digital phaselocked loop (DPLL), a parity/CRC generator and checker, and associated control circuits.

Features of the DUSCC

Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation consisting of: BOP: HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link level

COP: BISYNC, DDCMP, X.21 ASYNC: 5-8 bit plus optional parity

Programmable data encoding formats: NRZ, NRZI, FM0, FM1, Manchester 4 character receiver and transmitter FIFOs Individual programmable baud rate for each receiver and transmitter Digital phase locked loop User programmable counter/timer Programmable channel modes full/half duplex, auto echo, local loopback Modem control signals for each channel: RTS, CTS, DCD CTS and DCD programmable auto enables for Receiver (RX) and Transmitter (TX)

Programmable interrupt on change of CTS or DCD

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3.8.1 Address Map of the DUSCC1 Registers

The following tables contain the complete register map of the DUSCC1.

Table 3-2: Serial I/O Port #1 (DUSCC1) Register Address Map

Port Base Address: $FF802000

Address Offset Reset

HEX HEX Value

$FF802000 00 00 R /W DUSCMR1 Channel Mode Reg 1 $FF802001 01 00 R /W DUSCMR2 Channel Mode Reg 2 $FF802002 02 -- R /W DUSSS1R SYN1/Secondary Adr Reg 1 $FF802003 03 -- R /W DUSS2R SYN2/Secondary Adr Reg 2 $FF802004 04 0 0 R/W DUSTPR Transmitter Parameter Reg $FF802005 05 -- R /W DUSTTR Transmitter Timing Reg $FF802006 06 0 0 R/W DUSRPR Receiver Parameter Reg $FF802007 07 -- R /W DUSRTR Receiver Timing Reg $FF802008 08 -- R/W DUSCTPRH Counter/Timer Preset Reg H $FF802009 09 -- R/W DUSCTPRL Counter/Timer Preset Reg L $FF80200A 0A -- R/W DUSCTCR Counter/Timer Control Reg $FF80200B 0B 00 R/W DUSOMR Output and Miscellaneous Reg $FF80200C 0C -- R DUSCTH Counter/Timer High $FF80200D 0D -- R DUSCTL Counter/Timer Low $FF80200E 0E 00 R/W DUSPCR Pin Configuration Reg $FF80200F 0F -- R/W DUSCCR Channel Command Reg $FF802010 10 $FF802011 11 $FF802012 12 -- W DUSTFIFO Transmitter FIFO $FF802013 13 $FF802014 14 $FF802015 15 $FF802016 16 -- R DUSRFIFO Receiver FIFO $FF802017 17 $FF802018 18 0 0 R/W DUSRSR Receiver Status Reg $FF802019 19 0 0 R/W DUSTRSR Transmitter/Receiver Stat Reg $FF80201A 1A -- R/W DUSICTSR Input + Counter/Timer Stat Reg $FF80201C 1C 00 R/W DUSIER Interrupt Enable Reg

Mode Label Description

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Specifications and Main Features

Frequently Asked Questions

User Manual