Force SYS68K/CPU-30 R4 Technical Reference Manual

SYS68K/CPU-30 R4

Technical Reference Manual

Edition No. 2

February 1997

P/N 204030

FORCE COMPUTERS Inc./GmbH

All Rights Reserved

This document shall not be duplicated, nor its contents used

for any purpose, unless express permission has been granted.

Copyright by FORCE COMPUTERS

Table of Contents

TABLE OF CONTENTS

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 SYS68K/CPU-30 R4 Technical Reference Manual Set . . . . . . . . . . . . . . . . . . . 1

1.1.2 Overview of the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Overview of the SYS68K/CPU-30 R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.1 Features of the CPU-30 R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.5 History of Manual Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1 Caution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.2 Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Location Diagrams of the SYS68K/CPU-30 R4 Board . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1 Before Powering Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.3 Default Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.4.1 RESET and ABORT Keys. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.2 Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.4.3 Voltage Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.4 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.5 Two Rotary Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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2.5 Serial I/O Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.6 AUI-Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.7 SCSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.8 Parallel I/O (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.9 Connector Pinout for VMEbus P2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

2.10 Introduction to VMEPROM Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.10.1 Booting up VMEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.11 The SYS68K/IOBP-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1 SYS68K/CPU-30 R4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 The CPU 68030 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.1 Hardware Interface of the 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.2 The Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

3.2.3 Vector Table of the 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3 The Floating Point Coprocessor (FPCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.1 Features of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.2 Interfacing to the 68882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.3 Addressing the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.4 FPCP ID Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.5 Detection of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.6 Summary of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.4 The Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.4.1 The FGA-002 Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.4.2 Shared DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.4.2.1 Bank Selection of DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

3.4.3 Board Type with Memory Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

3.4.4 Reading the Shared RAM Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

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3.4.5 Shared RAM Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.6 Shared RAM Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.5 The System PROM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5.1 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5.2 Memory Organization of the System PROM Area . . . . . . . . . . . . . . . . . . . . . . 42

3.5.3 Read/Write to the System Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5.4 Programming the System Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3.5.5 Device Types for the System Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.5.6 Address Map of the System PROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.5.7 Summary of the PROM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6 The Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.1 The Boot PROM Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.1.1 Boot PROM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.1.2 Device Type Selection for Optional Boot PROM (Socket J28). . . . . . 46

3.6.1.3 Programming the Boot PROM Devices . . . . . . . . . . . . . . . . . . . . . . . .46

3.6.1.4 Programming Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.6.2 The Boot PROM Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.6.2.1 Address Map of the Default Boot PROM Socket J36 . . . . . . . . . . . . . 47

3.6.2.2 Opt. Boot PROM Addresses (J28), SW5-1=OFF . . . . . . . . . . . . . . . . 48

3.6.2.3 Opt. Boot PROM Addresses (J28), SW5-1=ON . . . . . . . . . . . . . . . . . 48

3.6.3 Summary of the Boot PROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.7 The Local SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.7.1 Memory Organization SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.7.2 Used Devices for SRAM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.7.3 Access Time Selection of the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7.4 Backup Power for the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

3.7.5 Summary of the SRAM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.8 The Real-Time Clock (RTC) 72423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.8.1 Address Map of the RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.8.2 RTC Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.8.3 RTC Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.8.4 Backup Power for the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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3.8.5 Summary of the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.9 The DUSCC 68562 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.9.1 Features of the DUSCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.9.2 Address Map of DUSCC #1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.9.3 Address Map of DUSCC #2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.9.4 Configuration of Serial I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.9.5 RS-232 and RS-422/485 Driver Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.9.6 RS-232 Configuration of Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.9.7 RS-422/RS-485 Hardware Configuration of Serial Ports . . . . . . . . . . . . . . . . .66

3.9.8 Termination Resistors for RS-422/RS-485 Configuration. . . . . . . . . . . . . . . . .67

3.9.9 Summary of DUSCC #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.9.10 Summary of DUSCC #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.10 The PI/T 68230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.10.1 Features of the PI/T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.10.2 Address Map of the PI/T #1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.10.3 I/O Configuration of PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

3.10.4 Rotary Switches at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

3.10.5 Floppy Disk Drive Control Lines at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . .71

3.10.6 DMA Control Lines at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.10.7 8-Bit User Defined I/O Port at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.10.8 Interrupt Request Signals of PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.10.9 Floating Point Coprocessor Sense Line at PI/T #1 . . . . . . . . . . . . . . . . . . . . . .73

3.10.10 Reserved Line at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.10.11 Summary of PI/T #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.10.12 Address Map of the PI/T #2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.10.13 I/O Configuration of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.10.14 12-Bit User I/O Port at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

3.10.15 Memory Size Identification at PI/T #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

3.10.16 Board Identification at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

3.10.17 Interrupt Request Signal of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

3.10.18 PC0-PC1 Hardware ID at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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3.10.19 Floppy Drive Ready Signal at PI/T #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.10.20 Floppy Drive Write Protect Signal at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.10.21 DMA Control Line at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.10.22 Flash Programming Control at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.10.23 Reserved Lines at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.10.24 Summary of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

3.11 SCSIbus Controller MB 87033/34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.1 Features of the 87033/34 SCSI Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.2 Address Map of MB 87033/34 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.3 The SCSI DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.3.1DMA Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.11.3.2DMA Transfer Programming Example . . . . . . . . . . . . . . . . . . . . . . . . 82

3.11.4 The SCSIbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.11.4.1SCSIbus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.11.4.2SCSIbus Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.11.4.3SCSIbus Terminator Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.11.5 Summary of the SCSIbus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.12 The Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12.1 Features of the FDC37C65C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12.2 Address Map of the FDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12.3 Data Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.12.4 Drive Select Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.12.5 Motor-On Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.12.6 DMA Control Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.12.7 Floppy Disk Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.12.7.1DMA Transfer Programming Example . . . . . . . . . . . . . . . . . . . . . . . . 86

3.12.8 Jumper Setting on the Floppy Disk Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.12.9 Summary of the Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

3.13 The Local Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.13.1 Features of the Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.13.1.1Ethernet Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

3.13.2 The Am7990 LANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.13.2.1Address Map of the LANCE Registers . . . . . . . . . . . . . . . . . . . . . . . . 89

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3.13.2.2The LANCE Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.13.2.3Summary of the LANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.13.3 The Am7992B Serial Interface Adapter (SIA) . . . . . . . . . . . . . . . . . . . . . . . . .90

3.13.4 Features of the Am7992B SIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.13.4.1The Am7992B Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

3.13.4.2The Am7992B Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

3.13.4.3Network Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

3.13.5 The LAN Buffer RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

3.13.6 Summary of the LAN RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

3.14 Function Switches and Indication LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

3.14.1 RESET Function Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

3.14.2 ABORT Function Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

3.14.3 "RUN" LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

3.14.4 "BM" LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

3.14.5 Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

3.14.6 Reserved Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

3.15 The CPU Board Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

3.16 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

3.17 VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

3.17.1 Data Transfer Size of the VMEbus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .96

3.17.2 Address Modifier Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

3.18 VMEbus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.18.1 The Access Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

3.18.2 Data Transfer Size of the Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

3.18.3 Address Modifier Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

3.19 The VMEbus Interrupt Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.19.1 VMEbus IACK Daisy Chain Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

3.20 VMEbus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.20.1 Single-Level VMEbus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

3.20.2 VMEbus Requester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

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3.20.3 VMEbus Release Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.20.3.1Release Every Cycle (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.20.3.2Release on Request (ROR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.20.3.3Release After Timeout (RAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.20.3.4Release on Bus Clear (RBCLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.20.3.5Release When Done (RWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

3.20.3.6Release on ACFAIL (ACFAIL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.20.3.7Summary of Release Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.20.4 VMEbus Grant Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.21 Slot-1 Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.21.1 Special Slot-1 Situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.21.2 Slot-1 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.21.3 Enabling the Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.21.4 The SYSCLK Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.21.5 VMEbus Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.22 Exception Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.22.1 The SYSFAIL* Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.22.2 The SYSRESET* Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.22.3 The ACFAIL* Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.23 Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.23.1 Front Panel Reset Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.23.2 The RESET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.23.3 Voltage Sensor Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4 Circuit Schematics and Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.1 Circuit Schematics of SYS68K/CPU-30 R4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.2 List of Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

4.2.1 RTC 72421. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.2.2 DUSCC 68562 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.2.3 PI/T TS68230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.2.4 SCSI 87033/34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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Table of Contents

4.2.5 FDC37C65C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

4.2.6 LANCE Am79C90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

4.2.7 SIA Am7992B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

4.2.8 Motorola MC68030 and MC68882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

5 VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.1 General Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.2 Features of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.3 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.4 Front Panel Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.4.1 RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.4.2 ABORT Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.4.3 Control Switches (Rotary Switches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

5.4.4 Default Memory Usage of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5.4.5 Default ROM Usage of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

6 Devices and Interrupts used by VMEPROM . . . . . . . . . . . . . . . . . . . . 133

6.1 Addresses of the On-board I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.2 On-board Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

6.3 Off-board Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

6.4 The On-board Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7 Concept of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.1 Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

7.2 Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

7.3 VMEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

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Table of Contents

8 Special VMEPROM Commands for CPU Boards . . . . . . . . . . . . . . . . 137

8.1 ARB - Set the Arbiter of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.2 CONFIG - Search VMEbus for Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

8.3 FERASE - Erase Flash Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8.4 FGA - Change Boot Setup for Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8.5 FLUSH - Set Buffered Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.6 FMB - FORCE Message Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

8.7 FPROG - Program Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

8.8 FUNCTIONAL - Perform Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

8.9 MEM - Set Data Bus Width of the VMEbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

8.10 SELFTEST - Perform On-board Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8.11 Installing a New Hard Disk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

9 Appendix to VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.1 Driver Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.1.1 VMEbus Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.1.2 SYS68K/SIO-1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.1.3 SYS68K/ISIO-1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

9.1.4 SYS68K/WFC-1 Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

9.1.5 SYS68K/ISCSI-1 Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

9.1.6 Local SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

9.2 S-Record Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

9.2.1 S-Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

9.3 System RAM Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

9.4 Task Control Block Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

9.5 Interrupt Vector Table of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

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Table of Contents

9.6 Benchmark Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

9.7 Modifying Special Locations in ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

9.8 Binding Applications to VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

9.8.1 General Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

9.8.2 Using External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

9.8.3 Using System Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

9.8.4 Binding the Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

10 Special FGA Boot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.1 AS - Line Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

10.2 CONT - Continue with Calling Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

10.3 DI - Disassembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

10.4 DRAMINIT - Initialize DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

10.5 FERASE - Erase Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

10.6 FPROG - Program Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

10.7 GO - Go to Subroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

10.8 LO - Load S-Records to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

10.9 NETLOAD - Load File via Network to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

10.10 NETSAVE - Save Data via Network to File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

10.11 SETUP - Change Initialization Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

10.12 SLOT - Change Slot Number and VMEbus Slave Address . . . . . . . . . . . . . . . . . . . . . .190

10.13 VMEADDR - Change VMEbus Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

11 The FGA Boot Utility Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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SYS68K/CPU-30 R4 Technical Reference Manual Table of Contents

List of Figures

Figure 1. Diagram of the CPU-30 R4 (Top View) .......................................................................... 13

Figure 2. Diagram of the CPU-30 R4 (Bottom View) .................................................................... 14

Figure 3. Front Panel ....................................................................................................................... 19

Figure 4. The 48-bit (6-byte) Ethernet address ............................................................................... 88

Figure 5. Functional Block Diagram of the Ethernet Interface ....................................................... 89

Figure 6. Boot up procedure .......................................................................................................... 178

Figure 7. Boot up procedure (continued) ...................................................................................... 179

Page xi

Table of Contents SYS68K/CPU-30 R4 Technical Reference Manual

List of Tables

Table 1. Specifications for the CPU-30 R4 Board........................................................................... 7

Table 2. Ordering Information......................................................................................................... 9

Table 3. History of Manual............................................................................................................ 10

Table 4. Default Switch Settings.................................................................................................... 15

Table 5. Front Panel Layout........................................................................................................... 18

Table 6. 9-pin D-Sub Connector Pinout (RS-232)......................................................................... 21

Table 7. 15-pin AUI-Ethernet Connector....................................................................................... 22

Table 8. Signal Assignment of the VME P2 Connector ................................................................ 24

Table 9. Rotary Switches ............................................................................................................... 25

Table 10. SYS68K/IOBP-1 Pin Assignment ................................................................................... 26

Table 11. SYS68K/CPU-30 R4 Memory Map ................................................................................ 30

Table 12. Exception Vector Assignments........................................................................................ 33

Table 13. Used Device Types for the Shared Memory.................................................................... 38

Table 14. Device Types used for System Flash Memory ................................................................ 44

Table 15. Address Map of the PROM Area..................................................................................... 44

Table 16. RTC Register Layout....................................................................................................... 54

Table 17. Serial I/O Port #4 (DUSCC #1) Register Address Map................................................... 59

Table 18. Serial I/O Port #1 (DUSCC #1) Register Address Map................................................... 60

Table 19. Ports #1 and #4 (DUSCC #1) Common Register Address Map...................................... 60

Table 20. Serial I/O Port #2 (DUSCC #2) Register Address Map................................................... 61

Table 21. Serial I/O Port #3 (DUSCC #2) Register Address Map................................................... 62

Table 22. Ports #2 and #3 (DUSCC #2) Common Register Address Map...................................... 62

Table 23. Switches & Module Assignment for Serial Port Configuration ...................................... 63

Table 24. PI/T #1 Register Layout................................................................................................... 69

Table 25. PI/T #1 Interface Signals.................................................................................................. 69

Table 26. Rotary Switch Signals Assignment.................................................................................. 70

Table 27. PI/T #2 Register Layout................................................................................................... 74

Table 28. PI/T #2 Interface Signals.................................................................................................. 75

Table 29. LANCE Register Layout.................................................................................................. 89

Table 30. Data Bus Size of the VMEbus (Master Interface) ........................................................... 96

Table 31. Defined VMEbus Transfer Cycles (D32 Mode).............................................................. 97

Table 32. VMEbus Transfer Cycles (D16 Mode)............................................................................ 97

Table 33. Address Ranges................................................................................................................ 97

Table 34. Address Modifier Codes .................................................................................................. 98

Table 35. Address Modifier Codes Used by the CPU Board........................................................... 99

Table 36. VMEbus Slave AM Codes............................................................................................. 101

Table 37. Bus Release Functions................................................................................................... 106

Table 38. Upper Rotary Switch (SW2).......................................................................................... 128

Table 39. Lower Rotary Switch (SW1).......................................................................................... 128

Table 40. RAM Disk Usage........................................................................................................... 128

Table 41. Program After Reset....................................................................................................... 129

Table 42. Boot an Operating System (if AUTOBOOT is selected)............................................... 129

Table 43. Examples in Using the Rotary Switches........................................................................ 129

Table 44. Main Memory Layout.................................................................................................... 130

Table 45. Layout of System Flash Memory................................................................................... 130

Table 46. On-board I/O Devices.................................................................................................... 133

Table 47. On-board Interrupt Sources............................................................................................ 133

Table 48. Off-board Interrupt Sources........................................................................................... 134

Table 49. User’s Patch Table......................................................................................................... 172

Page xii

SYS68K/CPU-30 R4 Technical Reference Manual Introduction

1 Introduction

1.1 Getting Started

This SYS68K/CPU-30 R4 Technical Reference Manual provides a
comprehensive guide to the CPU-30 R4 board you purchased from
FORCE COMPUTERS. In addition, each board delivered by FORCE
includes an Installation Guide.

CAUTION: Before installing the board, please read the complete
installation instructions.

1.1.1 SYS68K/CPU-30
R4 Technical
Reference Manual
Set

1.1.2 Overview of the Manual

When purchased from FORCE, this set includes the SYS68K/CPU-30 R4
Technical Reference Manual, a copy of the circuit schematics, and copies

of the following data sheets:

RTC 72421 FDC37C65C
DUSCC 68562 LANCE Am79C90
PI/T TS68230 SIA Am7992B
SCSI 87033/34 Motorola MC68030 and MC68882

1. The FDC37C65C is pin-to-pin compatible with Industry Standard
WD37C65C

Section 1 provides a brief overview of the product, the specifications, the
ordering information, and the publication history of the manual.
Information concerning the installation, default configuration,
initialization, and connector pinouts is included in Section 2. A detailed
hardware description is described in Section 3. The CPU board operates
under the control of VMEPROM, which is described in Sections 5, 6, 7,
8, and 9. There is additional space allocated in the manual for user notes,
modifications, etc.

1)

NOTE: Please take a moment to examine the Table of Contents of the

i

SYS68K/CPU-30 R4 Technical Reference Manual to see how this
documentation is structured. This will be of value to you when looking
for information in the future.

Page 1

Introduction SYS68K/CPU-30 R4 Technical Reference Manual

1.2 Overview of the SYS68K/CPU-30 R4

This CPU board is a high performance single-board computer based on
the 68030 microprocessor and the VMEbus. The CPU board also
includes an enhanced Floating Point Coprocessor 68882. The board
design utilizes all of the features of the powerful FORCE Gate Array
FGA-002.

The CPU-30 R4 provides an A32/D32 VMEbus interface including
DMA, up to 32 Mbyte shared DRAM on-board, up to 8 Mbyte System
Flash Memory, an Ethernet Interface, a single-ended SCSI interface, a
floppy interface, four RS-232 serial I/O channels, up to 256 Kbyte
SRAM and a Real-Time Clock, both with on-board battery backup.

Besides the CPU-30 R4, there will be a CPU-30Lite R4 without a
coprocessor, a SCSI, an Ethernet, and a floppy disk interface.

SEE ALSO: Please refer to Table 2, “Ordering Information,” on page 9

☞

for more detailed information.

1.2.1 Features of the CPU-30 R4

The shared DRAM is accessible from the 68030 CPU, the FGA-002
DMA controller, and also from other VMEbus masters.

The CPU-30 R4 has an Ethernet port and three serial ports available on
the front panel permitting a console port, download and data
communication channels. One further serial port, as well as the SCSI
interface and the Floppy interface are available via the 3-row VMEbus P2
connector. A 20-bit parallel interface and the three serial ports on the
front panel are available via the optional 5-row VMEbus P2 connector.

The main features of the SYS68K/CPU-30 R4 board are listed below.

Processor

- 68030 with 25 MHz frequency

- Flexible high bandwidth synchronous bus

- 68020 compatible integer unit

- Memory management unit

- Independent data and instruction memory management units

- Dual 256-byte on-chip caches for instructions and data

Page 2

- 4-Gbyte addressing range

- Upward user object code compatible with the 68020

SYS68K/CPU-30 R4 Technical Reference Manual Introduction

Coprocessor

- 68882 with 25 MHz frequency

- Pin- and SW-compatible with the MC68881

Main Memory

- 4, 8, 16, or 32 Mbyte of shared DRAM on-board

- Byte parity

VMEbus Interface

- Via FGA-002 in the 304-pin PQFP package

- Slot-1 detection switch enabled

- Master:

A32, A24, A16: D8, D16, D32, ADO, UAT, RMW
AM CODES:
Standard supervisory data/program access
Standard non-privileged data/program access
Short supervisory access
Short non-privileged access
Extended supervisory data/program access
Extended non-privileged data/program access

- Slave:

A32: D8, D16, D32, ADO, UAT, RMW
Access Address: SW programmable (FGA-002)
AM CODES:
Standard supervisory data/program access
Standard non-privileged data/program access
Extended supervisory data/program access
Extended non-privileged data/program access
SW programmable inside FGA-002 for DMA controller
Single-level arbiter
Request modes: ROR, RBCLR, REC, RAT
IACK daisy chain driver
FORCE Message Broadcast (FMB)

Page 3

Introduction SYS68K/CPU-30 R4 Technical Reference Manual

System Flash Memory

- 4 Mbyte Flash Memory is default configuration

- Up to 8 Mbyte Flash Memory

- 32-bit wide

- Reprogrammable on-board

- HW write protection

Ethernet Interface

- Via AM79C90

- Compatible with IEEE 802.3 Rev.0

- On-Chip DMA and buffer management

- 48-byte FIFO

- 24-bit wide linear addressing

- Network and packet error reporting

- Back-to-back reception with as little as 4.1

µ s inter-packet gaptime

- AUI Ethernet available on the front panel via a standard 15-pin D­Sub connector.

SCSI Interface

- Via MB87033/34

- Full support for SCSI control

- Service of either initiator or target device

- 8-byte data buffer register incorporated

- Transfer byte counter (28-bit)

- Independent control and data transfer bus

- On-chip single-ended drivers/receivers

- SCSI interface available on the VMEbus P2 connector

Floppy Disk Interface

- Via FDC37C65C (the FCD37C65C is pin-to-pin compatible with
Industry Standard WD37C65C)

- Available on VMEbus P2 connector

Page 4

SYS68K/CPU-30 R4 Technical Reference Manual Introduction

Boot ROM

- 128 -, 256 -, and 512 Kbyte of Flash Memory or up to 1 Mbyte OTP

- 8-bit wide

- Reprogrammable on-board in case of Flash Memory

- HW write protection in case of Flash Memory

- Two 32-pin PLCC sockets

Serial I/O Ports

- Via 68562 DUSCC

- Dual full-duplex asynchronous receiver and transmitter
(programmable)

- Multi-protocol operation enabling support of bit- or character­oriented protocols

- Additional software allows the support of HDLC, SDLC, BISYNC,
etc.

- Three ports available on the front panel via standard 9-pin D-Sub
connectors

- One port available on standard 3-row VMEbus P2 connector.

- All channels support RS-232 or RS-422 via the FORCE hybrids
FH-00x – as factory option also RS-485.

- RS-422 – and as factory option also RS-485 – terminations via
cable resistors

Parallel I/O

- Available via two 68230 PI/T

- 20-bit user I/O available on optional 5-row VMEbus P2 connector,
TTL level

SRAM

- 32-Kbyte or 128-Kbyte (assembly option) SRAM

- Optional 512-Kbyte SRAM in DIL package

- 8-bit wide

- On-board battery backup or backup via +5V-Stdby

- Socketed battery

Page 5

Introduction SYS68K/CPU-30 R4 Technical Reference Manual

RTC

- Real-Time Clock 72423

- IRQ capability

- Time of day and date counter included (year, month, week, day)

- Built-in quartz oscillator

- 12 hr/24 hr clock switch-over

- Automatic leap year setting

- CMOS design provides low power consumption during power­down mode

- On-board battery backup or backup via +5V-Stdby

- Socketed battery

Additional Features

- RESET/ABORT key

- Reset watchdog timer

- Status LEDs

- Rotary switches

Page 6

SYS68K/CPU-30 R4 Technical Reference Manual Introduction

1.3 Specifications

Table 1: Specifications for the CPU-30 R4 Board

CPU type 68030
CPU clock frequency 25 MHz
Shared DRAM capacity with parity

CPU-30ZBE R4

CPU-30BE/8 R4

CPU-30BE/16 R4

factory option
CPU-30Lite/4 R4
CPU-30Lite/8 R4

SRAM capacity with on-board battery backup 32 Kbyte

4 Mbyte

8 Mbyte
16 Mbyte
32 Mbyte

4 Mbyte

8 Mbyte

128 Kbyte SRAM (optional)

No. of system EPROM sockets
Data path

Serial I/O interfaces

RS-232/422/RS-485 compatible
Ethernet Interface

Ethernet SRAM buffer
Parallel I/O interface (optional) Via 68230 PI/T

Real-Time Clock with on-board battery backup RTC 72423
SCSI interface MB87033/34

Floppy disk interface FDC37C65C
24-bit timer with 5-bit prescaler

8-bit timer
VMEbus interface

A32,A24,A16:D8,D16,D32,ADO,UAT,RMW

A32:D8,D16,D32,ADO,UAT,RMW

4
32-bit

3 via the front panel and via
the 3-row VME P2 connec­tor and 1 via the optional
5-row VME P2 connector

via FORCE hybrids
AM7990

64 Kbyte

20 lines

Single-ended

2
1

Master
Slave

1)

ARBITER
SYSCLK driver
Mailbox interrupts

FORCE Message Broadcast

VMEbus interrupter (level programmable)
VMEbus and local interrupt handler
Programmable IRQ levels for all sources
Total number of IRQ sources

FMB-FIFO 0
FMB-FIFO 1

Single-level
yes
8

8 byte
1 byte

none
1 to 7
yes
42

Page 7

Introduction SYS68K/CPU-30 R4 Technical Reference Manual

Table 1: Specifications for the CPU-30 R4 Board (Continued)

RESET and ABORT switches yes
VMEPROM firmware installed on all board versions 512 Kbyte
Power requirements

+ 5 V max
+12 V max

- 12 V max

typical 2.3A
typical 0.4A
typical 0.1A

Operating temperature with forced air cooling
Storage temperature
Relative humidity (non-condensing in %)
(With a battery installed, the storage temperature is -40 to +60˚C)

Board dimensions 160 x 233 mm
No. of slots used 1

1. The FDC37C65C is pin-to-pin compatible with Industry Standard WD37C65C

0˚C to +55˚C

-40˚C to +85˚C
0 to 95%

Page 8

SYS68K/CPU-30 R4 Technical Reference Manual Introduction

1.4 Ordering Information

This page contains a list of the product names and their descriptions.

Table 2: Ordering Information

Product Name Product Description

CPU-30ZBE Rev. 4 68030/68882 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte

Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VME­bus interface, VMEPROM firmware. Installation Guide.

CPU-30BE/8 Rev. 4 68030/68882 CPU, 25 MHz, 8 Mbyte shared DRAM, 4 Mbyte

Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VME­bus interface, VMEPROM firmware. Installation Guide.

CPU-30BE/16 Rev. 4 68030/68882 CPU, 25 MHz, 16 Mbyte shared DRAM, 4 Mbyte

Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VME­bus interface, VMEPROM firmware. Installation Guide.

CPU-30Lite/4 Rev. 4 68030 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte Flash,

4 serial ports, 32-bit VMEbus interface, VMEPROM firmware,
Installation Guide.

CPU-30Lite/8 Rev. 4 68030 CPU, 25 MHz, 8 Mbyte shared DRAM, 4 Mbyte Flash,

4 serial ports, 32-bit VMEbus interface, VMEPROM firmware,
Installation Guide.

CPU-30/TM Rev. 4 Technical Reference Manual Set for the CPU-30 Rev. 4 including

a detailed hardware description, a VMEPROM User’s Manual and

a FGA-002 User’s Manual.
CABLE 9-25 SET Four cable adapters DSub-9 to DSub-25.
IOBP-1 I/O back panel board for VMEbus P2 with flat cable connectors for

SCSI, floppy and one serial I/O interface. Extends 4” behind P2.
IOBP-1 Serial Cable IOBP-1 cable to 3U backpanel for the 4th serial port of the

CPU-30.
IOPI-2 I/O back panel board for VMEbus P2 with flat cable connectors for

SCSI and floppy interface. Extends 3” behind P2.

Documentation included.
FH-002/SET 10 pcs. of Hybrid Modules for the Serial Interface to provide

RS-232
FH-003/SET 10 pcs. of Hybrid Modules for the Serial Interface to provide

RS-422.
FH-007/SET 10 pcs. of Hybrid Modules for the Serial Interface to provide

RS-485.
VxWorks/DEV 68K VxWorks development package for 68K based products.
VxWorks/BSP CPU-30 VxWorks board support package for CPU-30.
SYS68K/BusNet/VxWorks BusNet runtime package for VxWorks on 68K VMEbus boards.

Page 9

Introduction SYS68K/CPU-30 R4 Technical Reference Manual

1.5 History of Manual Publication

Below is a description of the publication history of this SYS68K/CPU-30
R4 Technical Reference Manual.

Table 3: History of Manual

Edition No. Description Date

1 First Print February 1996
2 Rotary switch description

in the section “VMEPROM”
has been corrected.
“Ethernet address” has
been changed. NETLOAD,
NETSAVE commands
have been extended.
“Erase flash memory”
description has been cor­rected.
Boot flash devices 256K * 8
have been replaced by
128K * 8 devices.

February 1997

Page 10

SYS68K/CPU-30 R4 Technical Reference Manual Installation

2 Installation

2.1 Introduction

This Installation Section provides guidelines for powering up the
SYS68K/CPU-30 R4 board. The Installation Section, which you have in
your hand now, appears both as Section 2 of the SYS68K/CPU-30 R4
Technical Reference Manual and as a stand-alone Installation Guide.
This stand-alone Installation Guide is delivered by FORCE
COMPUTERS with every board. The SYS68K/CPU-30 R4 Technical
Reference Manual provides a comprehensive hardware and software
guide to your board and is intended for those persons who require
complete information.

2.1.1 Caution CAUTION: Read the following safety note before handling the board.

To ensure proper functioning of the product over its usual lifetime, take
the following precautions before handling the board.

Electrostatic discharge and incorrect board installation and uninstallation
can damage circuits or shorten their lifetime.

• Before installing or uninstalling the board, read this Installation section.

• Before installing or uninstalling the board in a VME rack:

- Check all installed boards for steps that you have to take before
turning off the power.

- Take those steps.

- Finally turn off the power.

• Before touching integrated circuits, ensure that you are working in an
electrostatic free environment.

• Ensure that the board is connected to the VMEbus via both connectors,
the P1 and the P2 and that power is available on both.

• When operating the board in areas of strong electro-magnetic radiation,
ensure that the board

- is bolted on the VME rack

- and shielded by closed housing.

Page 11

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.1.2 Board Installation

☞

The installation of the board is easy, requiring only a power supply and a
VMEbus backplane. The power supply must meet the specifications
described in Table 1, “Specifications for the CPU-30 R4 Board,” on
page 7. The processor board requires +5 V supply voltage; ±12 V are
needed for the RS-232 serial interface and the Ethernet Interface.

For the initial power up, a terminal can be connected to the 9-pin D-Sub
microconnector of serial port 1, which is located on the front panel. The
serial port provides RS-232 interface signal level.

SEE ALSO: Before powering up check that the default switch settings
are correct as outlined in Section 2.3 ‘Default Switch Settings’.

2.2 Location Diagrams of the SYS68K/CPU-30 R4 Board

A location diagram showing the important components on the top side of
the CPU-30 R4 appears on the next page. On the page next to it, there is a
location diagram showing the bottom side of the CPU-30 R4.

SEE ALSO: Figure 2, “Diagram of the CPU-30 R4 (Bottom View),” on

☞

page 14 shows the location of all the switches on the board.

2.2.1 Before Powering Up

Both of these diagrams only show the components on the board which are
of interest to the user.

Before powering up, please make sure that the default switch settings are
all configured according to Table 4, “Default Switch Settings,” on
page 15. Since the board is configured for power up according to these
default settings, please check them before powering up your
SYS68K/CPU-30.

NOTE: The battery backup for SRAM and RTC is disabled with the

i

default switch setting. Stored data will be lost.

Page 12

SYS68K/CPU-30 R4 Technical Reference Manual Installation

Figure 1: Diagram of the CPU-30 R4 (Top View)

Reset
Switch

Abort
Switch

Run LED
BM LED

Rotary
Switches

{

SW3 SW4

FORCE Gate Array

FGA-002B

VME P1 Connector

MC68030

Processor

AUI­Ethernet

Serial
Port #3

Serial
Port #2

Serial
Port #1

SIA

7992

LANCE

7970

NVRAM

System Flash

J26

Boot EPROM

J25

Optional Boot EPROM

J28

J36

Optional
Boot PROM

Default
Boot PROM

DUS2

MC68882

Coprocessor

SCSI

87034

FDC

37C65C

PT1

VME P2 Connector

Optional

NVRAM

Battery

DUS1

PT2

Page 13

Installation SYS68K/CPU-30 R4 Technical Reference Manual

Figure 2: Diagram of the CPU-30 R4 (Bottom View)

NOTE: Pin 1 is always
located near the diagonal
line shown on each
switch and the OFF side
of the switch is also
always located near
the diagonal line.

Current PCB Revision of CPU-30 R4 Board

ON

4
3
2
1

OFF

SW8
SW6
SW7

SW5
SW13
SW11

SW12

Page 14

SYS68K/CPU-30 R4 Technical Reference Manual Installation

2.3 Default Switch Settings

The following table shows the default settings for all the switches on the
board. Please make sure you check the default settings before powering
up the board.

SEE ALSO: For the position of the switches on your CPU-30 R4 board,

☞

please see Figure 2, “Diagram of the CPU-30 R4 (Bottom View),” on
page 14.

Table 4: Default Switch Settings

Diagram of Switch

with Default Setting

SW5

OFFON

SW6

OFFON

Switches

SW5-1 OFF OFF = Boot PROM access to default Boot PROM and

4
3
2

SW5-2 OFF OFF = Optional Boot PROM Pinout for Flash PROM

1

SW5-3 OFF OFF = Write to Boot PROM enabled

SW5-4 OFF OFF = Write to System Flash Memory enabled

SW6-1 OFF

4

SW6-2 OFF

3

Default
Setting

SWITCH 5

SWITCH 6

Function

optional Boot PROM

ON = Boot PROM access to optional Boot PROM only

(Access to default Boot PROM is disabled)

ON = Optional Boot PROM Pinout for EPROM

ON = Write to Boot PROM disabled

ON = Write to System Flash Memory disabled

BUSTIMER (1:0)

SW6-1 OFF = VME Bustimer bit 1=1 OFF OFF 83.53ms
SW6-1 ON = VME Bustimer bit 1=0 OFF ON 1.30 ms

SW6-2 OFF = VME Bustimer bit 0=1
SW6-2 ON = VME Bustimer bit 0=0

SW6-1 SW6-2 Time

ON OFF 81.6 µs
ON ON 10.2 µs

2
1

SW6-3 OFF

SW6-4 OFF

SW6-3 OFF = VME BRSEL bit 1=1 SLOT-x detected, 10 : 2
SW6-3 ON = VME BRSEL bit 1=0 SLOT-x detected, 01 : 1

SW6-4 OFF = VME BRSEL bit 0=1 SLOT-1 detected, -- : 3
SW6-4 ON = VME BRSEL bit 0=0

SLOT, BRSEL (1:0) : VME BR

SLOT-x detected, 11 : 3

SLOT-x detected, 00 : 0

Page 15

Installation SYS68K/CPU-30 R4 Technical Reference Manual

Table 4: Default Switch Settings (Continued)

Diagram of Switch

with Default Setting

SW7

OFFON

SW8

OFFON

Switches

SW7-1 OFF OFF = RESET Switch enabled

4

SW7-2 OFF OFF = ABORT Switch enabled

3
2

SW7-3 OFF OFF = SCSI active termination enabled

1

SW7-4 OFF OFF = additional VME Bustimer enabled if VME slot-1

SW8-1 OFF OFF = VME slot-1 auto-detection enabled

4

SW8-2 OFF OFF = VME_SYSFAIL output enabled

3
2

SW8-3 OFF OFF = VME_SYSRESET output enabled

1

SW8-4 OFF OFF = VME_SYSRESET input enabled

Default
Setting

SWITCH 7

SWITCH 8

Function

ON = RESET Switch disabled

ON = ABORT Switch disabled

ON = SCSI active termination disabled

function detected (otherwise disabled)

ON = VME Bustimer disabled

ON = VME slot-1 function disabled

ON = VME_SYSFAIL output disabled

ON = VME_SYSRESET output disabled

ON = VME_SYSRESET input disabled

SW11

SWITCH 11

SW11-1 OFF OFF = Power backup from battery disabled

ON = Power backup from battery enabled

4
3
2
1

OFFON

SW11-2 OFF OFF = Power Backup from VME STBY disabled

ON = Power Backup from VME STBY enabled

SW11-3 OFF OFF = NVRAM supplied by Power Backup disabled

ON = NVRAM supplied by Power Backup enabled

SW11-4 OFF OFF = Default NVRAM access only

ON = Optional and default NVRAM access

Page 16

SYS68K/CPU-30 R4 Technical Reference Manual Installation

Table 4: Default Switch Settings (Continued)

Diagram of Switch

with Default Setting

SW12

OFFON

SW13

OFFON

Switches

SW12-1 OFF OFF = Serial channel 1 for RS-232 Hybrid FH-002

4

SW12-2 OFF OFF = Serial channel 2 for RS-232 Hybrid FH-002

3
2

SW12-3 OFF OFF = Serial channel 3 for RS-232 Hybrid FH-002

1

SW12-4 OFF OFF = Serial channel 4 for RS-232 Hybrid FH-002

SW13-1 OFF OFF = Timer IRQ enabled

4

SW13-2 OFF OFF = Watchdog reset disabled

3
2

SW13-3 OFF Reserved (must be OFF)

Default
Setting

SWITCH 12

SWITCH 13

Function

ON = Serial channel 1 for RS-422 Hybrid FH-003

ON = Serial channel 2 for RS-422 Hybrid FH-003

ON = Serial channel 3 for RS-422 Hybrid FH-003

ON = Serial channel 4 for RS-422 Hybrid FH-003

ON = Timer IRQ disabled

ON = Watchdog reset enabled

1

SW13-4 OFF Reserved (must be OFF)

Page 17

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.4 Front Panel

The table below outlines the layout on the front panel. Additionally, there
is a drawing of the front panel on the next page. The front panel devices
are briefly described on the pages following the drawing.

Table 5: Front Panel Layout

Device Function Name

Switch Reset RESET

Switch Abort ABORT

LED RUN/HALT RUN

LED VME BM BM

Rotary Switch 4-bit Input 2

Rotary Switch 4-bit Input 1

15-pin D-Sub connector AUI-Ethernet Interface L

9-pin D-Sub connector Serial Interface 3

9-pin D-Sub connector Serial Interface 2

9-pin D-Sub connector Serial Interface 1

Page 18

SYS68K/CPU-30 R4 Technical Reference Manual Installation

Figure 3: Front Panel

SYS68K/
CPU-30 R4

RESET

ABORT

RUN
BM

RESET and ABORT Keys

Status LEDs

2

Rotary Switches

1

L

3

15-pin D-Sub Connector

9-pin D-Sub Connector

2

1

9-pin D-Sub Connector

9-pin D-Sub Connector

Page 19

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.4.1 RESET and ABORT Keys

The RESET key generates an on-board reset. The ABORT key generates
an IRQ on a programmable level. Both keys can be disabled via the
switches described below:

SW7-1 Description

OFF (default) RESET key enabled
ON RESET key disabled

SW7-2 Description

OFF (default) ABORT key enabled
ON ABORT key disabled

2.4.2 Status LEDs The CPU-30 R4 includes two front panel LEDs: RUN/HALT LED and

BM LED.
The RUN/HALT LED displays the condition that the processor is halted

or reset is active and, in this case, the LED turns red. The RUN/HALT
LED turns green on normal operation.

The bus master BM LED is used to indicate VMEbus mastership of the
CPU-30 R4 and, in this case, the LED turns green.

2.4.3 Voltage Sensor The voltage sensor generates a power-up reset if the voltage level is

below 4.75 V.

2.4.4 Watchdog Timer

2.4.5 Two Rotary Switches

This timer can be enabled by software and will generate an NMI followed
by a power-up reset, when it is not retriggered.

SW13-2 Description

OFF (default) Watchdog reset disabled
ON Watchdog reset enabled

Two software readable four-bit rotary switches are installed on the board
and are accessible via the front panel.

Page 20

SYS68K/CPU-30 R4 Technical Reference Manual Installation

2.5 Serial I/O Channels

The CPU-30 R4 has three serial I/O channels available via 9-pin D-Sub
connectors on the front panel. All channels will support RS-232, RS-422
and RS-485 interfaces via the FORCE hybrids FH-00x. The default
configuration is RS-232.

The following table shows the pinout of the serial I/O channels for
RS-232.

Table 6: 9-pin D-Sub Connector Pinout1) (RS-232)

Pin Signal Direction Description

1 DCD in Data Channel Detector
2 RxD in Receive Data
3 TxD out Transmit Data
4 DTR out Data Terminal Ready
5 GND - Signal Ground
6 DSR in Data Set Ready
7 RTS out Request to Send
8 CTS in Clear to Send
9 GND* - Signal Ground

1. Default terminal port setup: 9600 Baud, 8 data bits, 1 stop bit, no parity.

6
7
8
9

1
2
3
4
5

NOTE: *With FH-002, this signal is provided by the hybrid being used.

i

The signal DTR is always driven active and the signal DSR is always
read active by software. The RS-232 interface on your current CPU-30
revision 4.x board is fully compatible to the RS-232 interface on the
earlier CPU-30 revision 3.2 board. However, the default jumper settings
prescribed for the earlier board must be used to obtain this functionality.

Page 21

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.6 AUI-Ethernet

The AUI-Ethernet Interface is available on the front panel via a 15-pin
D-Sub connector.

The unique Ethernet address is displayed by the banner when entering the
FGA Boot debugger. FGA Boot also provides a utility function to get the
CPU board’s Ethernet address: “#40 (0x28) Get Ethernet Number”.

The following table shows the pinout of the AUI-Ethernet connector.

Table 7: 15-pin AUI-Ethernet Connector

Pin Description

1 GND
2 Collision Detect+
3 Transmit Data+
4 GND
5 Receive Data+
6 GND
7 Not connected
8 GND

9 Collision Detect­10 Transmit Data­11 GND
12 Receive Data­13 +12V
14 GND
15 Not connected

1

8

9

15

Page 22

SYS68K/CPU-30 R4 Technical Reference Manual Installation

2.7 SCSI

The MB87033/34 provides an 8-bit single-ended SCSI interface. It is
routed to the VMEbus P2 connector.

The termination is switch selectable and "TERMPWR" is supported. The
following switches control the SCSI termination.

SW7-3 Description

OFF (default) SCSI active termination enabled
ON SCSI active termination disabled

NOTE: TERMPWR is always supplied; if termination power is supplied

i

externally by a source other than the VME connector, the active
termination is still maintained, although the VME may not be powered.

2.8 Parallel I/O (Option)

The parallel I/O signals are only available with the optional 5-row
VMEbus P2 connector.

Page 23

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.9 Connector Pinout for VMEbus P2

Table 8: Signal Assignment of the VME P2 Connector

PIN Row Z

(factory option)

1 PIT2 A0 SCSI Data 0 FDC RPM

2 GND SCSI Data 1 FDC HLOAD

3 PIT2 A1 SCSI Data 2 FDC DSEL2 TxD Port 1
4 GND SCSI Data 3 FDC INDEX RxD Port 1
5 PIT2 A2 SCSI Data 4 FDC DSEL1 RTS Port 1
6 GND SCSI Data 5 FDC DSEL2 CTS Port 1
7 PIT2 A3 SCSI Data 6 FDC DSEL1 DTR Port 1
8 GND SCSI Data 7 FDC MOTOR DCD Port 1

9 PIT2 A4 SCSI DP FDC DIREC GND Port 1
10 GND GND FDC STEPX TxD Port 2
11 PIT2 A5 GND FDC WDATA RxD Port 2
12 GND GND FDC WGATE RTS Port 2
13 PIT2 A6 TERMPWR FDC TRK00 CTS Port 2
14 GND GND FDC WPROT DTR Port 2
15 PIT2 A7 GND FDC RDATA DCD Port 2
16 GND SCSI ATN FDC SDSEL GND Port 2
17 PIT2 H1 GND FDC RDY TxD Port 3
18 GND SCSI BSY (RTS Port 2) RxD Port 3
19 PIT2 H2 SCSI ACK GND RTS Port 3
20 GND SCSI RST GND CTS Port 3
21 PIT2 H3 SCSI MSG (CTS Port 2) DTR Port 3
22 GND SCSI SEL GND DCD Port 3
23 PIT2 H4 SCSI CD GND GND Port 3
24 GND SCSI REQ (TxD Port 3) DSR Port 1
25 PIT1 H1 SCSI IO (RxD Port 3) DSR Port 2
26 GND (RTS Port 1) (RTS Port 3) DSR Port 3
27 PIT1 H2 GND (CTS Port 3) PIT1 C0
28 GND (CTS Port 1) (TxD Port 1) PIT1 C1
29 PIT1 H3 DSR Port 4 DCD Port 4

30 GND RTS Port 4 RxD Port 4 PIT1 C7
31 PIT1 H4 CTS Port 4 TxD Port 4 NC
32 GND GND Port 4 DTR Port 4 NC

Row A Row C Row D

(factory option)

NC

(TxD Port 2)

NC
(FDC EJECT)
(RxD Port 2)

PIT1 C4
(RxD Port 1)

Page 24

NOTE: The signals marked in parenthesis are only available with the use

i

of FH-002 hybrids, which are available at FORCE COMPUTERS.

SYS68K/CPU-30 R4 Technical Reference Manual Installation

2.10 Introduction to VMEPROM Firmware

The VMEPROM firmware is a full multitasking multiuser real-time
system. It is stored in the on-board System Flash Memory and provides
the following functionality:

- Configuration of the board

- Starting an application

- Application hooks

- Shell with over 80 commands

- Programming of Boot Flash devices.

2.10.1 Booting up VMEPROM

To start VMEPROM, the rotary switches must both be set to ‘F’:

Table 9: Rotary Switches

MODE 1 F
MODE 2 F

The different functions of the rotary switches are described in detail in
the VMEPROM section of the SYS68K/CPU-30 R4 Technical Reference

Manual.

Correct Operation

To test the correct operation of the CPU board, the following command
must be typed in:

# SELFTEST <CR>

The selftest command tests some I/O devices, the main memory and the
system timer tick interrupt. Depending on the size of the main memory, it
may last a different amount of time (count about one minute per
megabyte).
After all tests are done, the following message will appear on the terminal
screen:

VMEPROM Hardware Selftest

-------------------------

I/O test ........ passed

Memory test ..... passed

Clock test ...... passed

Page 25

Installation SYS68K/CPU-30 R4 Technical Reference Manual

2.11 The SYS68K/IOBP-1

FORCE COMPUTERS offers an IOBP-1 back panel for easy connection
of I/O signals through the VMEbus P2 connector. This board can be
plugged into the VMEbus P2 connector of a VMEbus board which
carries the SCSI, FDC, and serial I/O signals on the VMEbus P2. It
contains a SCSIbus connector (P2), a floppy disk interface connector
(P3), and a serial I/O connector (P5). All VMEbus P2 connector row A
and C pins are routed to the 64-pin male connector (P4). The pinout of
these connectors is shown in the following table.

Table 10: SYS68K/IOBP-1 Pin Assignment

PIN No.
IOBP-1

P1

32 1 DB 0 SCSI ­31 2 DB 1 SCSI GND
30 3 DB 2 SCSI - Drive Select 4 (2) FDC
29 4 DB 3 SCSI - Index FDC
28 5 DB 4 SCSI - Drive Select 1 FDC
27 6 DB 5 SCSI - Drive Select 2 FDC
26 7 DB 6 SCSI - Drive Select 3 (1) FDC
25 8 DB 7 SCSI - Motor On FDC
24 9 DB P SCSI - Direction In FDC
23 10 GND - Step FDC
22 11 GND - Write Data FDC
21 12 GND GND Write Gate FDC
20 13 TERMPWR SCSI - Track 000 FDC
19 14 GND - Write Protect FDC
18 15 GND - Read Data FDC
17 16 ATN SCSI - Side Select FDC
16 17 GND - FDC READY FDC
15 18 BSY SCSI ­14 19 ACK SCSI - GND
13 20 RST SCSI - GND
12 21 MSG SCSI ­11 22 SEL SCSI GND GND
10 23 C/D SCSI - GND

PIN No.

VMEbus

P2

9 24 REQ SCSI ­8 25 I/O SCSI ­726 ­6 27 GND - Reserved
5 28 - Reserved
4 29 DSR SER - DCD SER

Row A

Signal Mnemonic

Row B

Signal Mnemonic

Row C

Signal Mnemonic

Page 26

SYS68K/CPU-30 R4 Technical Reference Manual Installation

Table 10: SYS68K/IOBP-1 Pin Assignment (Continued)

PIN No.
IOBP-1

P1

PIN No.

VMEbus

P2

3 30 RTS SER - RXD SER
2 31 CTS SER GND TXD SER
1 32 GND SER - DTR SER

Row A

Signal Mnemonic

Row B

Signal Mnemonic

Row C

Signal Mnemonic

Page 27

Installation SYS68K/CPU-30 R4 Technical Reference Manual

Page 28

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3 Hardware Description

This CPU board is a high performance single-board computer based on
the 68030 microprocessor and the VMEbus. The CPU board also
includes an enhanced Floating Point Coprocessor 68882. The board
design utilizes all of the features of the powerful FORCE Gate Array
FGA-002.

Besides the CPU-30 R4, there will be a CPU-30Lite R4 without a
coprocessor, a SCSI, an Ethernet, and a floppy disk interface.

SEE ALSO: Please refer to Table 2, “Ordering Information,” on page 9

☞

for more detailed information.
The CPU-30 R4 provides an A32/D32 VMEbus interface including

DMA, up to 32-Mbyte shared DRAM on-board, up to 8-Mbyte System
Flash, an Ethernet Interface, a single-ended SCSI interface, a Floppy
interface, four RS-232 serial I/O channels, up to 256-Kbyte SRAM and a
Real-Time Clock, both with on-board battery backup.

The shared DRAM is accessible from the 68030 CPU, the FGA-002
DMA controller, and also from other VMEbus masters.

The CPU-30 R4 has an Ethernet port as well as three serial ports
available on the front panel permitting a console port, download and data
communication channels.

One serial port, as well as the SCSI interface and the Floppy interface are
available via the 3-row VMEbus P2 connector.

A 20-bit parallel interface and the three serial ports from the front panel
are available via the optional 5-row VMEbus P2 connector.

The CPU-30 R4 is fully software compatible to the CPU-30 R3 with the
exception of the floppy controller FDC37C65C, which has replaced the
WD1772.

Page 29

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.1 SYS68K/CPU-30 R4 Memory Map

Table 11: SYS68K/CPU-30 R4 Memory Map

Access

Address range Device

VMEbus

accessible

Cache

Burst

width

0000.0000
…00xF.FFFF

00

xx.

0000

…F9FF.FFFF

FB00.0000
…FBFE.FFFF

FBFF.0000
…FBFF.FFFF

FC00.0000
…FCFE.FFFF

FCFF.0000
…FCFF.FFFF

FD00.0000
…FEEF.FFFF

FEF0.0000
…FEF7.FFFF

???

FEF80.0000
…FEFF.FFFF

???

FF00.0000
…FF7F.FFFF

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16
16

16

DRAM: contributing to shared

Y Y Y 32/16/8
RAM, address range depends on
memory capacity

VME A32 extended address space

n/a N N 32/16/8
(consecutive to DRAM)

VME A24 standard address space n/a N N 32/16/8

VME A16 short address space n/a N N 32/16/8

VME A24 standard address space n/a N N 16/8

VME A16 short address space n/a N N 16/8

reserved n/a n/a n/a n/a

LAN - RAM N N N 32/16/8

LAN - Controller N N N 16

The System PROM Area: address
range depends on system flash ca-

N N N 32/16/8 RO

32 WO

pacity

FF80.0000
FF80.0BFF

FF80.0C00
…FF80.0DFF

FF80.0E00
…FF80.0FFF

FF80.1000
FF80.1FFF

Page 30

16
16

16

16

16
16

reserved n/a n/a n/a n/a

PIT1 N N N 8

16

PIT2 N N N 8

16

reserved n/a n/a n/a n/a

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Table 11: SYS68K/CPU-30 R4 Memory Map (Continued)

Access

Address range Device

VMEbus

accessible

Cache

Burst

width

FF80.2000
…FF80.21FF

FF80.2200
…FF80.23FF

FF80.2400
…FF80.2FFF

FF80.3000
…FF80.31FF

FF80.3200
…FF80.33FF

FF80.3400
…FF80.35FF

FF80.3600
…FF80.37FF

FF80.3800
…FF80.397F

FF80.397F
…FF80.39FF

FFC0.0000
…FFCF.FFFF

FFD0.0000
…FFDF.FFFF

FFE0.0000
…FFEF.FFFF

FFF0.0000
…FFFF.FFFF

16

16

16

16

16

16

16

16

16

16

16

16

16

DUSCC1 N N N 8

16

DUSCC2 N N N 8

16

reserved n/a n/a n/a n/a

16

Real-Time Clock – RTC 72423 N N N 8

16

reserved n/a n/a n/a n/a

16

SCSI-Controller N N N 8

16

reserved n/a n/a n/a n/a

16

The Floppy Disk Controller N N N 8

16

Slot-1 status register (RO) N N N 8 ro

16

Local SRAM N Y N 32/16/8

16

FGA-002 Gate Array internal reg. n/a N N 32/16/8

16

Boot PROM N N N 32/16/8

16

reserved n/a n/a n/a n/a

16

Page 31

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.2 The CPU 68030 Processor

3.2.1 Hardware Interface of the 68030

The 68030 uses a nonmultiplexed address and data bus. Asynchronous
signals allow easy interfacing to the outside world; synchronous signals
perform fast interaction.

The CPU drives the address signals (A0-A31), the size signals (SIZ0,
SIZ1) and the function code signals (FC0-FC2) on every cycle,
independent of a cache hit or miss. These signals are used to decode the
memory map of the CPU board.

The hardware on the CPU board is notified by the address and data strobe
signals that the current cycle is not a cache cycle, and that the decoding
outputs are strobed to be valid.

The 32 data lines (D0-D31) are also driven from the processor on write
cycles and sensed on read cycles.

The size of the data transfer is defined by the SIZE + A0 - A1 output
signals (always driven from the CPU). During asynchronous cycles the
data bus width is determined by the Data Size Acknowledge Input signals
(DSACK0, DSACK1). Synchronous cycles acknowledged by the
Synchronous Termination Input signal (STERM) acknowledge the
indicated data width during writes, whereas during reads a 4-byte width
is always acknowledged.

3.2.2 The Instruction Set

If a bus error occurs (BERR sensed from the CPU), exception handling
starts because the current cycle has been aborted (illegal transfer or
incorrect data).

On local bus operation, a bus error will be generated if a device does not
respond correctly.

VMEbus transfers may also be aborted via a BERR.

For the 68030 instruction set and further information relative to
programming, please refer to the 68030 User's Manual.

Page 32

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.2.3 Vector Table of the 68030

This table lists all vectors defined and used by the 68030 CPU.

Table 12: Exception Vector Assignments

Vector Number(s) Vector Offset (Hex) Assignment

0
1

2
3

4
5
6
7
8
9

10
11

12 030
13

14
15

000
004

008

00C

010
014
018

01C

020
024

028

02C

034
038

03C

16
16

16
16

16
16
16
16
16
16

16
16

16

16
16
16

Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter

Access Fault (Bus Error)
Address Error

Illegal Instruction
Integer Divide by Zero
CHK, CHK2 Instruction
FTRAPcc, TRAPcc, TRAPV Instructions
Privilege Violation
Trace

Line 1010 Emulator (Unimplemented A-Line Opcode)
Line 1111 Emulator (Unimplemented F-Line Opcode)

Unassigned, Reserved
Coprocessor Protocol Violation

Format Error
Uninitialized Interrupt

16-23 040

24
25
26
27
28
29
30
31

32-47 080

48
49
50
51
52
53
54
55

56
57
58

59-63

0EC

16

060
064
068

06C

070
074
078

07C

16

0C0
0C4
0C8

OCC

ODO

OD4

0D8

ODC

0E0
0E4
0E8

16

-05C

16
16
16
16
16
16
16
16

-0BC

16
16
16

16

16

16

16

16

16
16
16

-0FC

16

Unassigned, Reserved
Spurious Interrupt

Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector

16

TRAP #0-15 Instruction Vectors
FPCP Branch or Set on Unordered Condition

FPCP Inexact Result
FPCP Divide by Zero
FPCP Underflow
FPCP Operand Error
FPCP Overflow
FPCP Signalling NAN
FPCP Unimplemented Data Type

MMU Configuration Error
Defined for 68852, not used by 68030
Defined for 68852, not used by 68030

Unassigned, Reserved

16

64-255

100

16

-3FC

16

User Defined Vectors (192)

Page 33

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.3 The Floating Point Coprocessor (FPCP)

The CPU board contains a Floating Point Coprocessor (FPCP 68882).

3.3.1 Features of the 68882

- 8 floating point data registers supporting 80-bit extended precision
of real data (64-bit mantissa, 15-bit exponent, and one sign bit)

- Three registers for control, status and instruction address

- 67-bit arithmetic unit

- 67-bit barrel shifter

- 46 instructions with 35 arithmetic operations

- IEEE 754 compatible, including all requirements and suggestions

- Full set of trigonometric and transcendental functions

- Seven data types:

Byte Integer
Word Integer
Long Word Integer
Single Precision Real
Double Precision Real
Extended Precision Real
Packed Decimal Strings

Page 34

- 22 constants available in the on-chip ROM, including Pi, e, and
powers of 10

- Virtual memory/machine operations

- Efficient mechanism for procedure calls, context switches and
interrupt handling

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.3.2 Interfacing to the 68882

The 68882 is a non-DMA type coprocessor which uses a subset of the
general purpose coprocessor interface supported by the 68030.

Features of the interface implemented in the 68882 are as follows:

- Main processor and 68882 communicate via standard bus cycles.

- Main processor and 68882 communication is not dependent upon
instruction sets or internal details of individual devices (e.g.
instruction pipes or caches, addressing modes).

- The main processor and 68882 may operate at different clock
speeds.

- 68882 instructions utilize all addressing modes provided by the
main processor; all effective addresses are calculated by the main
processor at the request of the coprocessor.

- All data transfers are performed by the main processor at the
request of the 68882; thus memory management, bus errors,
address errors, and bus arbitration function as if the 68882
instructions are executed by the main processor.

- Overlapped (concurrent) instruction execution enhances throughput
while maintaining the programmer's model of sequential instruction
execution.

- Coprocessor detection of exceptions which require a trap to be
taken are serviced by the main processor at the request of the
68882; thus exception processing functions as if the 68882
instructions were executed by the main processor.

- Support of virtual memory/virtual machine systems is provided via
the FSAVE and FRESTORE instructions.

- Up to eight coprocessors may reside in a system simultaneously;
multiple coprocessors of the same type are also allowed.

- Systems may use software emulation of the 68882 without
reassembling or relinking user software.

For further details, please refer to the User's Manual of the 68881/68882.

Page 35

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.3.3 Addressing the 68882

3.3.4 FPCP ID Number

The 68882 is addressed via the function codes of the 68030 and a part of
the address bus. This is done automatically within the opcodes generated
by most 68030/68882 floating-point compilers and assemblers.

The following table lists the conditions for addressing the 68882.

Signal Value Description

FC0
FC1
FC2

A13
A14
A15

A16
A17
A18
A19

1
1
1

1
0
0

0
1
0
0

CPU Space Cycles

Coprocessor ID = 1

Coprocessor Access Cycle

All instructions for the FPCP must include the coprocessor ID (001).
Please note that the VMEPROM Assembler supports this function by
default.

3.3.5 Detection of the 68882

3.3.6 Summary of the 68882

The SENSE pin of the FPCP is connected to PI/T #1. This allows
automatic detection whether or not the 68882 is installed.

CAUTION: PI/T #1 pin PC6/PIACK must be programmed as an input.

PC6 Function

0 FPCP installed
1 FPCP not installed

Allowed Function Codes 1 1 1 (CPU Space Cycle)
Coprocessor ID 0 0 1
Usable Data Bits D0 - D31
Supported Transfer Types Byte

Word
Long Word

Page 36

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.4 The Local Bus

3.4.1 The FGA-002 Gate Array

3.4.2 Shared DRAM The CPU board contains a Shared dynamic RAM area with a capacity of

The CPU board also contains the FGA-002 Gate Array with 24,000 gates
and 304 pins.

The FGA-002 Gate Array controls the local bus and builds the interface
to the VMEbus. It also includes a DMA controller, complete interrupt
management, a message broadcast interface (FMB), timer functions, and
mailbox locations.

The gate array monitors the local bus. This in turn signifies that if any
local device is to be accessed, the gate array takes charge of all control
signals in addition to used address and data signals.

The FGA-002 Gate Array serves as a manager for the VMEbus. All
VMEbus address and data lines are connected to the gate array through
the buffers. Additional functions such as the VMEbus interrupt handler
and arbiter are also installed on the FGA-002 Gate Array.

The start address of the FGA-002 Gate Array registers is FFD0.0000
All registers of the gate array and associated functions are described in
detail in the FGA-002 Gate Array User’s Manual.

4, 8, 16 or 32 Mbytes. The Shared RAM area is optimized for fast
accesses from the 68030 CPU and the DMA controller in the FGA-002
Gate Array. The Shared RAM is also accessible by other VMEbus
masters.

16

.

The Shared RAM area is arranged in 36-bit wide memory banks. There
may be one or two of these banks on the CPU board, depending on the
overall memory capacity delivered. Each 36-bit wide bank is separated
into 32 data bits and 4 parity bits. A parity bit checks every eight
consecutive data bits (byte parity). Advanced on-board memory control
logic routes data to and from the on-board 68030 CPU, the DMA
controller, and the VMEbus interface.

For every read cycle, regardless of size (byte, word, long-word or cache
line) and regardless of master (68030, DMA or VMEbus), all 32 bits of
data and 4 bits of parity are read from the Shared RAM array. The 32 data
and 4 parity bits are stored in transceivers.

Parity is regenerated in FGA-002 and compared to the parity bits read
from memory. If a mismatch is found on an accessed byte, an error will
be flagged. A synchronous termination signal (STERM) is asserted, and
the cycle completes.

Page 37

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

Write cycles are handled differently. In the case of a long-word access
aligned to a 4-byte boundary, the DRAM can be written immediately.
The parity info generated by FGA-002 will be written additionally to the
DRAM. A synchronous termination signal (STERM) is asserted, and the
cycle completed.

For all other write cycles (byte, word, long-word unaligned), the
momentary valid parity info stored in DRAM must be read. Then the
write to RAM Memory will be performed. Therefore, only the necessary
data will be written, the remaining data already stored in DRAM will stay
unmodified. Additionally, the new parity info generated by FGA-002 will
be merged with the read parity info from DRAM and finally all four
parity bits are written to DRAM. The synchronous termination signal
(STERM) will be generated to complete the cycle.

All write cycles are terminated before they are fully processed to allow
the master writing to DRAM to continue its operations (write posting).

3.4.2.1 Bank Selection

of DRAM

The bank selection depends on memory size. The Dual-Banks
architecture implements an interleaved organized DRAM (four
consecutive bytes located in bank A, the next four consecutive bytes
located in bank B, ...). The Single-Bank architecture implements a non­interleaved organized DRAM.

Table 13: Used Device Types for the Shared Memory

DRAM Device Device Capacity Total Capacity Bank Supported Product

1M * 4 FPM

1M * 4 FPM 18 * 1 Mbit * 4 8 Mbyte 2 CPU-30BE/8 R4
4M * 4 FPM 9 * 4 Mbit * 4 16 Mbyte 1 CPU-30BE/16 R4
4M * 4 FPM 18 * 4 Mbit * 4 32 Mbyte 2 factory option
1M * 4 FPM 9 * 1 Mbit * 4 4 Mbyte 1 CPU-30Lite/4 R4
1M * 4 FPM 18 * 1 Mbit * 4 8 Mbyte 2 CPU-30Lite/8 R4

1. FPM: Fast Page Mode

Shared RAM byte parity generation and check work for both local and
VMEbus accesses. If a parity error is detected during a VMEbus slave
read access, the CPU board drives BERR, informing the VMEbus master
about the parity error. On all local accesses, a normal STERM will be
generated, plus an interrupt on a software programmable level. The
access address is stored inside the FGA-002 Gate Array allowing easy
software controlled detection of the cycle which caused the parity error.

1)

9 * 1 Mbit * 4 4 Mbyte 1 CPU-30ZBE R4

Page 38

The Shared RAM is accessed from the VMEbus via FGA-002. The start
and end access addresses are programmable in 4 Kbyte steps. The

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

defined memory range can be write protected in coordination with the
VMEbus Address Modifier codes. For example, in privileged mode the
memory could be read and written, while in non-privileged mode the
memory could only be read, or a non-privileged access could be
prohibited altogether.

When the gate array detects a VMEbus access cycle to the programmed
address range of the Shared RAM, it requests local bus mastership from
the CPU. After the CPU has granted local bus mastership to the
FGA-002, the VMEbus access cycle is executed and all data is latched
(read cycles), or stored to RAM (write cycles). The read and write cycle
is then terminated and the FGA-002 immediately releases local bus
mastership back to the CPU. Simultaneously, it completes the fully
asynchronous VMEbus access cycle. The early completion of the
memory read or write cycle allows the CPU to continue processing while
the FGA-002 independently manages the VMEbus transaction overhead.

A programmable bit within the FGA-002 may be used to disable the early
bus release option. With early release disabled, the FGA-002 retains local
bus mastership until the VMEbus cycle is finished. This guarantees that
no other local bus master (CPU or DMA controller) will access the
Shared RAM until the VMEbus cycle is complete. In the case of a read­modify-write (RMW) cycle by another VMEbus master to the Shared
RAM, the FGA-002 will perform both transactions (a read followed by a
write) without releasing the local bus, thus guaranteeing that the cycle is
indivisible.

3.4.3 Board Type with Memory Capacity

In short, the early release option allows the CPU access to the Shared
RAM sooner, but sacrifices the guaranteed indivisibility of VMEbus
RMW cycles. Because the 68030 CPU includes an on-chip cache
memory, this may not affect CPU performance at all.

The following table lists the CPU board type with the memory capacity
of the Shared RAM.

Board Type CPU Frequency DRAM Capacity

CPU-30ZBE R4 25 MHz 4 Mbytes
CPU-30BE/8 R4 25 MHz 8 Mbytes

CPU-30BE/16 R4 25 MHz 16 Mbytes

factory option 25 MHz 32 Mbytes
CPU-30Lite/4 R4 25 MHz 4 Mbytes
CPU-30Lite/8 R4 25 MHz 8 Mbytes

Page 39

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.4.4 Reading the Shared RAM Capacity

☞

3.4.5 Shared RAM Addressing

The amount of Shared RAM may be read via three input pins from Port B
of PI/T #2. The table below summarizes the encoding of these three bits.

B2 B1 B0 Memory Capacity

0 0 0 32 Mbytes
0 0 1 16 Mbytes
0 1 0 8 Mbytes
0 1 1 4 Mbytes
1 - - Reserved

SEE ALSO: Please refer to Section 3.10.13, ‘I/O Configuration of PI/T
#2,’ on page 74 for more detailed information.

The access address of the Shared RAM is programmable within the
FGA-002 Gate Array. The default address range of the 4 Mbyte DRAM
array is from 0000.000016 to 003F.FFFF16. The default address range of
the 32 Mbyte DRAM array is 0000.0000

to 01FF.FFFF16. It is possible

16

to program nearly any address range desired in the FGA-002.

☞

3.4.6 Shared RAM Performance

Start Address End Address Memory Capacity

0000.0000

0000.0000

0000.0000

0000.0000

16

16

16

16

01FF.FFFF
00FF.FFFF
007F.FFFF
003F.FFFF

16

16

16

16

32 Mbytes
16 Mbytes

8 Mbytes
4 Mbytes

The access address of the Shared RAM from the VMEbus is also
programmable via FGA-002. That is the address range that other
VMEbus masters must use in order to access the Shared RAM on the
CPU board. This is not necessarily the same address range used by the
CPU for local accesses.

SEE ALSO: Please refer to Section 3.18, ‘VMEbus Slave Interface,’ on
page 101 for more information.

The memory interface logic controlling the Shared RAM array is
optimized for fast accesses from the 68030 CPU, providing the highest
possible performance. Because the 68030 CPU contains an on-chip data
and instruction cache, many CPU accesses are cache line "burst fills".
These burst transactions attempt to read 16 consecutive bytes into the
68030, using four 4-byte cycles.

Page 40

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

The first read cycle of such a burst usually requires 5 CPU clock cycles
(200 nanoseconds at 25 MHz). Due to the optimized design of the
memory control logic, each subsequent cycle only requires 1 CPU clock
cycle (40 nanoseconds) to complete. This is commonly called a "5-1-1-1"
burst transfer. Overall, the total cache line "burst fill" operation requires 8
clock cycles to transfer 16 bytes, providing a memory bandwidth of over
50 Mbytes/second.

Not all CPU accesses are burst transfers. Single read and write
transactions are also supported at the fastest possible speed. A single read
or write access (1, 2, or 4 bytes) requires 5 CPU clock cycles. Distributed
asynchronous refresh is provided every 14 microseconds and an access
during a pending refresh cycle may be delayed by a maximum of five
additional clock cycles.

Page 41

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.5 The System PROM Area

The first two read cycles after reset of the microprocessor are operand
fetches of the Initial Interrupt Stack Pointer (ISP) and the Initial Program
Counter (IPC). These operands are always fetched from addresses

0000.0000

3.5.1 Initialization Special control logic in FGA-002 maps the Boot PROM (not the System

Flash Memory) down to this address to allow the 68030 to boot from a
single byte-wide PROM. This facilitates debugging and low-level
program development. However, when the initialization routines in the
Boot PROM are completed, control is transferred to the System Flash
Memory in such a way that the 68030 appears to have been booted from
the System Flash Memory, not the Boot PROM. For this reason, the
System Flash Memory must also have the ISP and IPC loaded at address

0000.0000

and 0000.000416, respectively.

16

and 0000.000416, respectively.

16

3.5.2 Memory Organization of the System PROM Area

3.5.3 Read/Write to the System Flash Memory

0000.0000

0000.0004

in System Flash Memory: Initial Interrupt Stack Pointer

16

in System Flash Memory: Initial Program Counter

16

The data path of the System Flash Memory is 32-bit wide, separated into
4-byte paths. Each byte path is connected to one Flash Memory device.

Read cycles with any port size are allowed. Write cycles are flagged by
the FGA-002 Gate Array with BERR. A programmable bit within the
FGA-002 may be used to enable write operation to the System Flash
Memory. In this case the FGA-002 will respond with an asynchronous
data acknowledge (DSACK0, DSACK1). The write takes affect to the
System Flash Memory depending on switch SW5-4.

SW5-4 Description

OFF (default) Write to System Flash Memory enabled
ON Write to System Flash Memory disabled

Page 42

The status of SW5-4 is connected to PI/T #2.
Pin PC4 on the PI/T #2 interface signal protects the write to the System

Flash Memory and must be programmed as an input.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

The encoding of these bits is shown in the table below.

PC4 Function

0 Write to System Flash Memory unprotected
1 Write to System Flash Memory protected

CAUTION: Writes to the System Flash Memory must always be
performed with a 4-byte wide port size and must be aligned on 4-byte
boundaries.

3.5.4 Programming the System Flash Memory

☞

For correct programming, a communication sequence to the Flash
devices must be used which is defined by the manufacturer of the Flash
device.

SEE ALSO: For further details, please refer to the data sheets for Flash
devices in Section 4, ‘Circuit Schematics and Data Sheets,’ on page 115.

This communication sequence has to be performed on every byte path.
Besides the communication sequence, a programming voltage Vpp of

12V must be applied to the Flash device. The Vpp is generated by the
CPU-30 R4 and is controlled by PI/T #2.

CAUTION: PI/T #2 pin PC6 must be programmed as an output.

PC6 Function

0 Vpp on
1 Vpp off

The Vpp generator is shared between the System Flash Memory and the
default Boot PROM socket.

Page 43

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.5.5 Device Types for the System Flash Memory

3.5.6 Address Map of the System PROM Area

The following device types or equivalent are used by the System Flash
Memory:

Table 14: Device Types used for System Flash Memory

Device Device Capacity Total Capacity Device Speed

28F008SA 1M * 8 4 Mbytes 120 ns x

29F016 2M * 8 8 Mbytes 120 ns

The default configuration using 28F008SA devices is provided for
programming VMEPROM.

The start address of the System PROM Flash Area is mapped via the
FGA-002 Gate Array and cannot be changed. The size of this memory
area depends on the memory capacity of the devices used. The following
table lists the address map for the usable device types.

Default

Configuration

Table 15: Address Map of the PROM Area

Start Address End Address Used Device Total Capacity

Default

Configuration

3.5.7 Summary of the PROM Area

FF00.0000
FF00.0000

Not Allowed Access with Function Code 111
Usable Data Bits D00 - D31
Supported Port Size (read) Long, Word, Byte
Supported Port Size (write) Long (aligned!)
No. of Devices 4
Capacity 4 Mbytes
Default Configuration for 28F008A Devices
Default Access Time 120 ns
Access Address Range FF00.000016 - FF3F.FFFF

16

16

FF3F.FFFF
FF7F.FFFF

28F008SA 4 Mbytes x

16

29F016 8 Mbytes

16

16

Page 44

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.6 The Boot PROM

The CPU board contains one or two 32-pin PROMs which are used to
boot up the processor and initialize register contents of the FGA-002
Gate Array. This program finishes in such a manner that the 68030
microprocessor appears to have booted from the System Flash Memory.
The Boot PROM devices are located in 32-pin PLCC sockets at location
J28 or J36.

Because the 68030 will unconditionally boot from the Boot PROM
memory after every power up or reset, there must always be a working
Boot PROM device installed in the CPU board.

During the bootup procedure, the FGA-002 will map all addresses to the
Boot PROM memory with the exception of FGA-002 internal registers.
After bootup the Boot PROM will be accessible at address FFE0.0000
The start address of the Boot PROM is fixed and cannot be changed.

16

.

3.6.1 The Boot PROM Sockets

☞

3.6.1.1 Boot PROM

Selection

The Boot PROM area is located in two 32-pin PLCC sockets. One socket,
the default Boot PROM socket, allows the usage of 12V programmable
Flash devices. The second socket, the optional Boot PROM socket,
allows the usage of 5V programmable Flash devices. Alternatively,
EPROM devices (e.g. OTP) can be used.

SEE ALSO: For information on which devices may be used, please see
the tables in Section 3.6.2, ‘The Boot PROM Address Map,’ on page 47.

The Boot PROM socket selection is controlled by switch SW5-1.

SW5-1 Description

OFF (default) Default Boot socket J36 enabled with start address at FFE0.000016,

Optional Boot socket J28 enabled with start address at FFE8.0000

ON Default Boot socket J36 disabled,

Optional Boot socket J28 enabled with start address at FFE0.0000

16

16

Page 45

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.6.1.2 Device Type

Selection for

The optional Boot PROM socket supports the use of

Optional Boot
PROM (Socket J28)

- Programmable 5V Flash devices

- EPROM (OTP)

- EEPROM

This is controlled by switch SW5-2.

SW5-2 Description

OFF (default) Optional Boot PROM (Socket J28) supports

5V Flash device (programmable) and
12V Flash device (non-programmable)

ON Optional Boot PROM (Socket J28) supports

EPROM (OTP) or
EEPROM (writeable)

3.6.1.3 Programming

the Boot
PROM Devices

☞

The programming of Boot PROM devices is supported for the default
Boot PROM (socket J36) for 12V Flash devices and for the optional Boot
PROM socket J28 for 5V Flash or EEPROM devices.

For correct programming, a communication sequence to the Boot PROM
devices must be used which is defined by the manufacturer of the device.

SEE ALSO: For further details, please refer to the data sheets in
Section 4, ‘Circuit Schematics and Data Sheets,’ on page 115.

The programming to the Boot PROM devices is dependent on switch
SW5-3.

SW5-3 Description

OFF (default) Write to Boot PROM devices enabled
ON Write to Boot PROM devices disabled

The status of switch SW5-3 is connected to the PI/T #2.

CAUTION: PI/T #2 pin PC2 must be programmed as an input.

Page 46

PC2 Function

0 Write to Boot PROM unprotected
1 Write to Boot PROM protected

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.6.1.4 Programming

Flash Devices

3.6.2 The Boot PROM Address Map

3.6.2.1 Address Map of

the Default Boot
PROM Socket J36

Besides the communication sequence, a programming voltage Vpp of
12V must be applied to the default Boot PROM (socket J36). Vpp is
generated by the CPU-30 R4 and is controlled by PI/T #2.

PC6 Function

0 Programming voltage enabled (Vpp = ON)
1 Programming voltage disabled (Vpp = OFF)

The Vpp generator is shared between the System Flash Memory and the
default Boot PROM socket.

CAUTION: PI/T #2 pin PC6 must be programmed as an output.

Boot PROM access to default Boot PROM and optional Boot PROM
(Boot PROM selection switch SW5-1 in position OFF)

Used Device Device Type Start Address End Address Total Capacity

28F512A 12V Flash FFE0.0000
28F010A " FFE0.0000
28F020A " FFE0.0000

16

16

16

FFE0.FFFF
FFE1.FFFF
FFE3.FFFF

16

16

16

64K * 8
128K * 8 x
256K * 8

CAUTION: The default Boot PROM socket is disabled with "ON"­position of the Boot PROM selection switch SW5-1.

Default

Configuration

Page 47

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.6.2.2 Opt. Boot PROM Addresses (J28), SW5-1=OFF

Used Device Device Type Start Address End Address Total Capacity

29F010 5V Flash FFE8.0000
29F040 " FFE8.0000
28C512 12V Flash FFE8.0000

28C010 " FFE8.0000
28F512A " FFE8.0000
28F010A " FFE8.0000
28F020A " FFE8.0000

27C010 EPROM/OTP FFE8.0000

27C020 " FFE8.0000

27C040 " FFE8.0000

27C080 " FFE8.0000

Boot PROM access to default Boot PROM and optional Boot PROM
(Boot PROM selection switch SW5-1 in position OFF)

Default

Configuration

16

16

16

16

16

16

16

16

16

16

16

FFE9.FFFF
FFEF.FFFF
FFE8.FFFF
FFE9.FFFF
FFE8.FFFF
FFE9.FFFF
FFEB.FFFF
FFE9.FFFF
FFEB.FFFF
FFEF.FFFF

FFEF.FFFF

16

16

16

16

16

16

16

16

16

16

16

128K * 8
512K * 8

64K * 8

128K * 8

64K * 8
128K * 8
256K * 8

O p t i o n a l

128K * 8
256K * 8
512K * 8

1)

1M * 8

1. The upper 512K of the 1M * 8 are not accessible in this mode.

3.6.2.3 Opt. Boot PROM Addresses (J28), SW5-1=ON

Used Device Device Type Start Address End Address Total Capacity

29F010 5V Flash FFE0.0000
29F040 " FFE0.0000
28C512 12V Flash FFE0.0000

28C010 " FFE0.0000
28F512A " FFE0.0000
28F010A " FFE0.0000
28F020A " FFE0.0000

27C010 EPROM/OTP FFE0.0000

27C020 " FFE0.0000

Boot PROM access to optional Boot PROM only. Access to default Boot
PROM is disabled. (Boot PROM selection switch SW5-1 in position ON)

Default

Configuration

16

16

16

16

16

16

16

16

16

FFE1.FFFF
FFE7.FFFF
FFE0.FFFF
FFE1.FFFF
FFE0.FFFF
FFE1.FFFF
FFE3.FFFF
FFE1.FFFF
FFE3.FFFF

128K * 8

16

512K * 8

16

16

16

16

16

16

16

16

64K * 8

128K * 8

64K * 8
128K * 8
256K * 8
128K * 8
256K * 8

O p t i o n a l

Page 48

27C040 " FFE0.0000
27C080 " FFE0.0000

16

16

FFE7.FFFF
FFEF.FFFF

512K * 8

16

16

1M * 8

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.6.3 Summary of the Boot PROM Area

Not Allowed Access with Function Code 111
Supported Port Size Byte
Maximum Capacity 1 Mbyte
Default Access Time 200 ns
Access Address FFE0.000016 - FFEF.FFFF
No. of Devices to be Installed 1 or 2

16

Page 49

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.7 The Local SRAM Memory

The SRAM memory is dedicated to the on-board default SRAM and an
optional SRAM.

For the optional SRAM there are two 32-pin DIL socket positions
available. The socket position J87 allows the usage of a 28-pin SRAM or
a 32-pin SRAM with a high active chip select for pin 30. The socket
position J88 allows the usage of a 32-pin SRAM. The default SRAM is
located in socket position J86.

The SRAM address map between the default and the optional SRAM can
be controlled by switch SW11-4.

3.7.1 Memory Organization SRAM

SW11-4

OFF FFC0.0000

ON FFC8.0000

Default SRAM Optional SRAM

Start Address of

16

16

FFC0.0000

Disabled

16

The SRAM memory at sockets J86, J87 and J88 allows the user to retain
data when the power supply is switched off. A backup provides the
current for the SRAM standby mode.

The local SRAM memory is connected to the local 8-bit data bus,
providing a byte-wide port. Succeeding bytes seen by the microprocessor
are handled in the same manner as succeeding bytes for the local SRAM
memory.

Byte, word, and long-word accesses are managed by the dynamic bus
sizing of the microprocessor. For further details, please refer to the
manual of the microprocessor.

Data can be read from and written to any address; odd, even or unaligned
in byte, word, or long-word format.

Page 50

Example of Data Transfers:

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

The following instruction is fully supported from the SRAM memory
area:

MOVE.X ($FFC0 000Y), D0

X = B = Byte 1 Byte
X = W = Word 2 Bytes
X = L = Long Word 4 Bytes

Y = 0
Y = 1
Y = 2
Y = 3
.
.
.

All combinations of the listed instructions are allowed and possible.

3.7.2 Used Devices for SRAM Area

The default SRAM capacity is 32 Kbyte. The following low power
device types (marked with -L or -LL) are supported by the J87 socket
position. The package type must be either 28-pin DIL or 32-pin DIL.

Device Device Capacity

KM 62256L

MB 84256L

M5M 5256L

KM 681000L 128K * 8

M5M 510008L 128K * 8

1. These devices must be installed with pin 1, 2,
31, 32 left free.

1)

1)

1)

32K * 8
32K * 8

32K * 8

Default

Configuration

O p t i o n a l

The following DIL-device types are supported by the J88 socket position.

Device Device Capacity

M5M 5408L 512K * 8 Optional

Default

Configuration

CAUTION: A device can only be assembled in either socket J87 or J88.

Page 51

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

NOTE: The setup parameters of FGA-002 are stored in the SRAM

i

located in the lower half of the SRAM address space. If the optional
SRAM is enabled, the setup parameters of the optional SRAM will be
used.

3.7.3 Access Time Selection of the SRAM Area

3.7.4 Backup Power for the SRAM Area

The access time of the SRAM area is software programmable in the
FGA-002 Gate Array. Four fixed access times are available: 2.0, 1.0, 0.5
and 0.25 microseconds.

There are two sources for backup power. One from the VMEbus
+5VSTDBY line and the other one from a CR2032-type lithium battery
installed in the battery socket at location BAT 1.

Backup power from the VMEbus +5VSTDBY line is enabled by
SW11-2. Backup power from the battery is enabled by SW11-1.

The SRAM memory, both the default SRAM (on-board) and the optional
SRAM (sockets J87 and J88) are powered by backup power circuitry.
This maintains the power supply for the SRAM memory to retain its non­volatile storage.

Under normal operation the backup power circuitry connects the +5V
power supply to the SRAM memory. When the main +5V supply fails,
backup power may be supplied from one of two alternate sources. The
VMEbus +5VSTDBY line may be used to provide backup power under
power-fail conditions. The switchover from normal +5V to +5VSTDBY
is fully automatic; whichever voltage is higher will be available to the
SRAM memory.

Page 52

As a second alternative, the backup power may be supplied by battery.
Should the +5V and/or +5VSTDBY supplies drop below approximately
+3.3 volts, the on-board battery will be used.

This is controlled for +5VSTDBY by switch SW11-2.

SW11-2 Description

OFF (default) Backup from +5VSTDBY for RTC and SRAM disabled
ON Backup from +5VSTDBY for RTC and SRAM enabled

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Backup from the battery is controlled by switch SW11-1 and SW11-3.

3.7.5 Summary of the SRAM Area

SW11-1 SW11-3

OFF OFF x

OFF ON

ON OFF Backup from battery enabled for RTC,

ON ON Backup from battery enabled for RTC and SRAM

Not Allowed Access with Function Code 111
Supported Port Size Byte
Default Access Time 100ns
Access Address FFC0.000016 - FFCF.FFFF
Capacity of Default SRAM 32 Kbytes
Maximum Capacity of Optional SRAM 512 Kbytes

Default

Position

Description

Backup from battery disabled for RTC and SRAM

but disabled for SRAM

16

Page 53

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.8 The Real-Time Clock (RTC) 72423

There is an RTC 72423 installed on the CPU board, containing its own
crystal to maintain accurate time and date. A battery is provided on the
CPU board to allow the RTC to run even under power-down conditions.

3.8.1 Address Map of the RTC Registers

The RTC 72423 has a 4-bit data bus. It must be accessed in byte mode
and the upper four bits (4..7) are "don't care" during read and write
accesses. The base address of the RTC is FF80.3000

. The following

16

table shows the register layout of the RTC 72423.

Table 16: RTC Register Layout

Default

I/O Base Address:
Offset:
Name:

Address

(HEX)

FF803000
FF803001
FF803002
FF803003
FF803004
FF803005
FF803006
FF803007
FF803008
FF803009
FF80300A
FF80300B
FF80300C
FF80300D
FF80300E
FF80300F

Offset Label Description

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F

$FF80 0000
$0000 3000
RTC

RTC1SEC
RTC10SEC
RTC1MIN
RTC10MIN
RTC1HR
RTC10HR
RTC1DAY
RTC10DAY
RTC1MON
RTC10MON
RTC1YR
RTC10YR
RTCWEEK
RTCCOND
RTCCONE
RTCCONF

1 Second Digit Register
10 Second Digit Register
1 Minute Digit Register
10 Minute Digit Register
1 Hour Digit Register
PM/AM and 10 Hour Digit Register
1 Day Digit Register
10 Day Digit Register
1 Month Digit Register
10 Month Digit Register
1 Year Digit Register
10 Year Digit Register
Week Register
Control Register D
Control Register E
Control Register F

3.8.2 RTC Programming

Page 54

☞

The following programming example shows how to read from or write to
the RTC. Please note that the RTC must be stopped prior to reading the
date and time registers.

SEE ALSO: For further details, please refer to the RTC 72423 data sheet
in Section 4, ‘Circuit Schematics and Data Sheets,’ on page 115.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.8.3 RTC Programming Example

/*****************************************
** read RTC 72423 and load to RAM **
** 30-Oct-87 M.S. **
*****************************************/

setclock(sy)
register struct SYRAM *sy;
{
register struct rtc7242 *rtc = RTC2;
register long count=100000l;

rtc->dcontrol = 1; /* hold clock */
while(count--)
if(rtc->dcontrol&0x02)
break;
if(!count)
{ printf("\nCannot read Realtime Clock");
rtc->dcontrol = 0;
return; }
sy->_ssec[0] = (unsigned char)((rtc->sec10reg&0x07)*10 +
(rtc->sec1reg&0x0f));
sy->_smin = (unsigned char)((rtc->min10reg&0x07)*10 +
(rtc->min1reg&0x0f));
sy->_shrs = (unsigned char)((rtc->hou10reg&0x03)*10 +
(rtc->hou1reg&0x0f));
sy->_syrs[0] = (unsigned char)((rtc->yr10reg&0x0f)*10 +
(rtc->yr1reg&0x0f));
sy->_sday = (unsigned char)((rtc->day10reg&0x03)*10 +
(rtc->day1reg&0x0f));
sy->_smon = (unsigned char)((rtc->mon10reg&0x01)*10 +
(rtc->mon1reg&0x0f));
rtc->dcontrol = 0; /* start clock */
}

/*****************************************
** write RTC 72423 from RAM **
** 30-Oct-87 M.S. **
*****************************************/

writeclock(sy)
register struct SYRAM *sy;
{
register struct rtc7242 *rtc = RTC2;
register long count=100000l;

rtc->dcontrol = 1; /* hold clock */
while(count--)
if(rtc->dcontrol&0x02)
break;
if(!count)
{ printf("\nCannot read Realtime Clock");
rtc->dcontrol = 0;
return; }

Page 55

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

rtc->fcontrol = 5;
rtc->fcontrol = 4; /* 24-hour clock */
rtc->sec10reg = sy->_ssec[0]/10;
rtc->sec1reg = sy->_ssec[0]%10;
rtc->min10reg = (char)(sy->_smin/10);
rtc->min1reg = (char)(sy->_smin%10);
rtc->hou10reg = (char)(sy->_shrs/10);
rtc->hou1reg = (char)(sy->_shrs%10);
rtc->yr10reg = sy->_syrs[0]/10;
rtc->yr1reg = sy->_syrs[0]%10;
rtc->day10reg = sy->_sday/10;
rtc->day1reg = sy->_sday%10;
rtc->mon10reg = sy->_smon/10;
rtc->mon1reg = sy->_smon%10;
rtc->dcontrol = 0; /* start clock */
}

3.8.4 Backup Power for the RTC

There are two sources for backup power. One from the VMEbus
+5VSTDBY line and the other one from a CR2032-type lithium battery
installed in the battery socket at location BAT 1.

Backup power from the VMEbus +5VSTDBY line is enabled by
SW11-2. Backup power from the battery is enabled by SW11-1.

The RTC is powered by backup power circuitry. This circuitry maintains
power supply for the RTC to guarantee continuous operation.

Under normal operation the backup power circuitry connects the +5V
power supply to the RTC. When the main +5V supply fails, backup
power may be supplied from one of two alternate sources. The VMEbus
+5VSTDBY line may be used to provide backup power under power-fail
conditions. The switchover from normal +5V to +5VSTDBY is fully
automatic; whichever voltage is higher will be available to the RTC.

As a second alternative, the backup power may be supplied by an on­board lithium battery. Should the +5V and/or +5VSTDBY supplies drop
below approximately +3.3 volts, the on-board battery will be used.

This is controlled for +5VSTDBY by switch SW11-2.

Page 56

SW11-2 Description

OFF (default) Backup from +5VSTDBY for RTC and SRAM disabled
ON Backup from +5VSTDBY for RTC and SRAM enabled

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Backup from the battery is controlled by switch SW11-1 and SW11-3.

3.8.5 Summary of the RTC

SW11-1 SW11-3

OFF OFF x

OFF ON

ON OFF Backup from battery enabled for RTC,

ON ON Backup from battery enabled for RTC and SRAM

Device 72423 RTC
Access Address FF80.3000
Access Mode Byte only
Supported Transfers Byte only, 4 LSB
Battery Type CR2032
Interrupt Request Level Software programmable
FGA-002 Interrupt Request Channel Local IRQ #0

Default

Position

Description

Backup from battery disabled for RTC and SRAM

but disabled for SRAM

16

Page 57

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.9 The DUSCC 68562

The Dual Universal Serial Communications Controller 68562 (DUSCC)
is a single-chip MOS-LSI communications device that provides two
independent, multiprotocol, full duplex receiver/transmitter channels in a
single package. Each channel consists of a receiver, a transmitter, a 16-bit
multifunction counter/timer, a digital phase locked loop (DPLL), a
parity/CRC generator and checker, and associated control circuits.

3.9.1 Features of the DUSCC

- Dual full-duplex synchronous/asynchronous receiver and
transmitter

- Multiprotocol operation consisting of:

BOP: HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link
level

COP: BISYNC, DDCMP, X.21
ASYNC: 5-8 bit plus optional parity

- Programmable data encoding formats: NRZ, NRZI, FM0, FM1,
Manchester

- 4 character receiver and transmitter FIFOs

- Individual programmable baud rate for each receiver and
transmitter

- Digital phase locked loop

- User programmable counter/timer

- Programmable channel modes full/half duplex, auto echo, local
loopback

- Modem control signals for each channel: RTS, CTS, DCD

- CTS and DCD programmable auto enables for receiver and
transmitter

Page 58

- Programmable interrupt on change of CTS or DCD

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.9.2 Address Map of DUSCC #1 Registers

Port Base Address: $FF80 2000

Address

(HEX)

$FF802000
$FF802001
$FF802002
$FF802003
$FF802004
$FF802005
$FF802006
$FF802007
$FF802008
$FF802009
$FF80200A
$FF80200B
$FF80200C
$FF80200D
$FF80200E
$FF80200F
$FF802010
$FF802011
$FF802012
$FF802013
$FF802014
$FF802015
$FF802016
$FF802017
$FF802018
$FF802019
$FF80201A
$FF80201C

The following tables contain the complete register map of DUSCC #1.
The first table pertains only to registers for Port #4, the second table for
Port #1, and the third table for registers common to both Port #1 and
Port #4.

Table 17: Serial I/O Port #4 (DUSCC #1) Register Address Map

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1C

Reset
Value

00
00

--

-­00

-­00

--

--

--

-­00

--

-­00

--

--

--

00
00

-­00

Mode Label Description

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R

R
R/W
R/W

W

R

R/W
R/W
R/W
R/W

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

DUSTFIFO

DUSRFIFO

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Channel Mode Reg 1
Channel Mode Reg 2
SYN1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Transmitter FIFO

Receiver FIFO

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

Page 59

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

Table 18: Serial I/O Port #1 (DUSCC #1) Register Address Map

Port Base Address: $FF80 2020

Address

(HEX)

$FF802020
$FF802021
$FF802022
$FF802023
$FF802024
$FF802025
$FF802026
$FF802027
$FF802028
$FF802029
$FF80202A
$FF80202B
$FF80202C
$FF80202D
$FF80202E
$FF80202F
$FF802030
$FF802031
$FF802032
$FF802033
$FF802034
$FF802035
$FF802036
$FF802037
$FF802038
$FF802039
$FF80203A
$FF80203C

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1C

Reset
Value

00
00

--

-­00

-­00

--

--

--

-­00

--

-­00

--

--

--

00
00

-­00

Mode Label Description

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R

R
R/W
R/W

W

R

R/W
R/W
R/W
R/W

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

DUSTFIFO

DUSRFIFO

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Channel Mode Reg 1
Channel Mode Reg 2
SYN1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Transmitter FIFO

Receiver FIFO

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

Table 19: Ports #1 and #4 (DUSCC #1) Common Register Address Map

Port Base Address: $FF80 2000

Address

(HEX)

$FF80201B
$FF80201E
$FF80201F
$FF80203E

Offset

(HEX)

1B
1E
1F
3E

Reset
Value

00
0F
00
0F

Mode Label Description

R/W
R/W
R/W

R

DUSGSR
DUSIVR
DUSICR
DUSIVRM

General Status Register
Interrupt Vec Reg Unmodified
Interrupt Control Register
Interrupt Vec Reg Modified

Page 60

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.9.3 Address Map of DUSCC #2 Registers

Port Base Address: $FF80 2200

Address

(HEX)

$FF802200
$FF802201
$FF802202
$FF802203
$FF802204
$FF802205
$FF802206
$FF802207
$FF802208
$FF802209
$FF80220A
$FF80220B
$FF80220C
$FF80220D
$FF80220E
$FF80220F
$FF802210
$FF802211
$FF802212
$FF802213
$FF802214
$FF802215
$FF802216
$FF802217
$FF802218
$FF802219
$FF80221A
$FF80221C

The following tables contain the complete register map of DUSCC #2.
The first table pertains only to registers for Port #2, the second table for
Port #3, and the third table for registers common to both Port #2 and
Port #3.

Table 20: Serial I/O Port #2 (DUSCC #2) Register Address Map

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1C

Reset
Value

00
00

--

-­00

-­00

--

--

--

-­00

--

-­00

--

--

--

00
00

-­00

Mode Label Description

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R

R
R/W
R/W

W

R

R/W
R/W
R/W
R/W

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

DUSTFIFO

DUSRFIFO

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Channel Mode Reg 1
Channel Mode Reg 2
SYN1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Transmitter FIFO

Receiver FIFO

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

Page 61

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

Table 21: Serial I/O Port #3 (DUSCC #2) Register Address Map

Port Base Address: $FF80 2220

Address

(HEX)

$FF802220
$FF802221
$FF802222
$FF802223
$FF802224
$FF802225
$FF802226
$FF802227
$FF802228
$FF802229
$FF80222A
$FF80222B
$FF80222C
$FF80222D
$FF80222E
$FF80222F
$FF802230
$FF802231
$FF802232
$FF802233
$FF802234
$FF802235
$FF802236
$FF802237
$FF802238
$FF802239
$FF80223A
$FF80223C

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1C

Reset
Value

00
00

--

-­00

-­00

--

--

--

-­00

--

-­00

--

--

--

00
00

-­00

Mode Label Description

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R

R
R/W
R/W

W

R

R/W
R/W
R/W
R/W

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

DUSTFIFO

DUSRFIFO

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Channel Mode Reg 1
Channel Mode Reg 2
SYN1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Transmitter FIFO

Receiver FIFO

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

Table 22: Ports #2 and #3 (DUSCC #2) Common Register Address Map

Port Base Address: $FF80 2200

Address

(HEX)

$FF80221B
$FF80221E
$FF80221F
$FF80223E

Offset

(HEX)

1B
1E
1F
3E

Reset
Value

00
0F
00
0F

Mode Label Description

R/W
R/W
R/W

R

DUSGSR
DUSIVR
DUSICR
DUSIVRM

General Status Register
Interrupt Vec Reg Unmodified
Interrupt Control Register
Interrupt Vec Reg Modified

Page 62

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.9.4 Configuration of Serial I/O Ports

Serial ports #1 and #4 are controlled by DUSCC #1 at location J90. Serial
ports #2 and #3 are controlled by DUSCC #2 at location J89. In both
cases, the DUSCC is connected to a local 8-bit data bus and is accessible
via byte transfers.

The RS-232 interfaces of port #1, #2, #3 and #4 are identical except that
port #4 is wired directly to the VMEbus P2 connector, while ports #1
through #3 are wired to 9-pin D-Sub connectors labeled "1" through "3"
on the front panel of the CPU board and to the optional 5-row VMEbus
P2 connector. As a factory option, ports #1 through #3 may also be
connected to the default assembled 3-row VMEbus P2 connector.

In the sections that follow the figures will refer to the hardware
configuration switches and to the serial driver/receiver hybrid sockets.
For reference, the switches and hybrids are assigned to the serial ports
according to the following table.

Table 23: Switches & Module Assignment for Serial Port

Configuration

DUSCC Channel Hybrid Switch SW12- Port

#1 A J118 4 "4"
#1 B J119 1 "1"

3.9.5 RS-232 and RS-422/485 Driver Modules

3.9.6 RS-232 Configuration of Serial Ports

#2 A J123 3 "2"
#2 B J124 2 "3"

In order to conserve board space and to simplify varying the serial
interfaces, FORCE Computers has developed RS-232 and RS-422/485
hybrid modules: the FH-002 and FH-003.

These 21-pin single in-line (SIL) modules are installed in sockets so that
they may be easily changed to meet specific application needs. Please
refer to the preceding table for the assignment of hybrid modules to serial
ports.

By default, all four serial ports are configured for RS-232 compatibility.
For proper RS-232 operation, the correct driver/receiver hybrid module
must be installed (FH-002), and the serial interface switches SW12-1 –
SW12-4 must be configured for RS-232. The default switch setting is
detailed below.

Page 63

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

The serial ports may be configured for RS-232 or RS-422/485.

SW12-1 Description

OFF (default) RS-232 support for port #1

FH-002 hybrid must be installed for J118

ON RS-422/485 support for port #1

FH-003 hybrid must be installed for J118

SW12-2 Description

OFF (default) RS-232 support for port #3

FH-002 hybrid must be installed for J124

ON RS-422/485 support for port #3

FH-003 hybrid must be installed for J124

SW12-3 Description

OFF (default) RS-232 support for port #2

FH-002 hybrid must be installed for J123

ON RS-422/485 support for port #2

FH-003 hybrid must be installed for J123

SW12-4 Description

OFF (default) RS-232 support for port #4

FH-002 hybrid must be installed for J126

ON RS-422/485 support for port #4

FH-003 hybrid must be installed for J126

When a serial port is configured for RS-232 operation, its I/O signals will
be connected to the front panel DB-9 connector as follows (ports #1, #2
and #3 only):

1)

9-pin D-Sub

Connector

1
2
3
4
5
6
7
8
9

Description

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND (supplied by FH-002)
Data Set Ready
Request to Send
Clear to Send
Signal GND

(x)

1)

Output

x
x

x

x
x

(x)

x

(x)

Signal Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

1. As a factory option signals marked in brackets may be connected to the 9-pin
D-Sub connector.

Page 64

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

When serial port #4 is configured for RS-232 operation, its I/O signals
will be connected to the VME P2 connector as follows:

Signal Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS

1. As a factory option signals marked in brackets may be connected to the 9-pin

D-Sub connector.

1)

x
x

(x)

x

Output

x
x

(x)
(x)

1)

VME

Connector P2

C29
C30
C31
C32
A32
A29
A30
A31

Description

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND (supplied by FH-002)
Data Set Ready
Request to Send
Clear to Send

NOTE: For the connection to the IOBP-1 back panel, please refer to

i

Section 2.11, ‘The SYS68K/IOBP-1,’ on page 26.

When the serial ports #1, #2 and #3 are configured for RS-232 operation,
its I/O signals will be connected to the optional 5-row VME P2 connector
as follows:

Port Signal Input

1)

Output

1)

VME

Connector P2

Description

1 DCD

RXD
TXD
DTR
GND
DSR
RTS
CTS

2 DCD

RXD
TXD
DTR
GND
DSR
RTS
CTS

3 DCD

RXD
TXD
DTR
GND
DSR
RTS
CTS

1. As a factory option, signals marked in brackets may be connected to the 9-pin D-Sub

connector.

(x)

(x)

(x)

x
x

x
x

x

x
x

x

x

x
x

(x)

x

(x)

x
x

(x)

x

(x)

x
x

(x)

x

(x)

D8
D4
D3
D7
D9

D24

D5
D6

D15
D11
D10
D14
D16
D25
D12
D13

D22
D18
D17
D21
D23
D26
D19
D20

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND (supplied by FH-002)
Data Set Ready
Request to Send
Clear to Send

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND (supplied by FH-002)
Data Set Ready
Request to Send
Clear to Send

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND (supplied by FH-002)
Data Set Ready
Request to Send
Clear to Send

Page 65

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.9.7 RS-422/RS-485
Hardware
Configuration
of Serial Ports

☞

It is possible to configure any or all of the four serial ports to be RS-422
compatible or – as factory option – RS-485 compatible. By default, all
four serial ports are configured for RS-232 operation. For proper RS­422/485 operation, the correct driver/receiver hybrid module must be
installed (FH-003), and the serial interface switches must be properly
configured.

SEE ALSO: For a list of the serial interface switches on the CPU board,
please refer to Section 3.9.6, ‘RS-232 Configuration of Serial Ports,’ on
page 63.

The RS-422 compatible interface supports TXD, RXD, RTS, CTS with
differential outputs and inputs. Each port occupies the same nine pins of
the D-Sub connector as in the RS-232 compatible configuration, but with
a different signal association.

When a serial port is configured for RS-422 operation, its I/O signals will
be connected to the front panel DB-9 connector as follows (ports #1, #2
and #3 only):

x
x

x
x

9-pin D-Sub

Connector

1
2
3
4
5
6
7
8
9

Description

Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send
Signal GND

Signal Input Output

TXD-

RTS­CTS+
RXD+

RXD­TXD+
RTS+

CTS-

GND-

x
x
x

x

Page 66

When serial port #4 is properly configured for RS-422 operation, its I/O
signals will be connected to the VME P2 connector as follows:

Signal Input Output

TXD-

RTS­CTS+
RXD+

RXD­TXD+
RTS+

CTS-

x
x
x

x

x
x

x
x

VME

Connector P2

C29
C30
C31
C32
A32
A29
A30
A31

Description

Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

When the serial ports #1, #2 and #3 are configured for RS-422 operation,
its I/O signals will be connected to the optional 5-row VME P2 connector
as follows:

VME

Port Signal Input Output

Connector P2 Description

3.9.8 Termination
Resistors for
RS-422/RS-485
Configuration

1 TXD-

RTS-

CTS+

RXD+

RXD­TXD+
RTS+

CTS-

2 TXD-

RTS-

CTS+

RXD+

RXD­TXD+
RTS+

CTS-

3 TXD-

RTS-

CTS+

RXD+

RXD­TXD+
RTS+

CTS-

x
x
x

x

x
x
x

x

x
x
x

x

x
x

x
x

x
x

x
x

x
x

x
x

D8
D4
D3
D7
D9

D24

D5
D6

D15
D11
D10
D14
D16
D25
D12
D13

D22
D18
D17
D21
D23
D26
D19
D20

Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send

Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send

Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send

If termination resistors are necessary to compensate for various cable
lengths and to reduce signal reflections, it must be done externally from
the CPU-30 R4 (e.g. via a cable connector).

The resistor value is user application dependent, but a recommended
value is 1000 Ohms.

3.9.9 Summary of DUSCC #1

Device 68562 DUSCC
Access Address FF80.2000
Port Width Byte
Interrupt Request Level Software programmable
FGA-002 Interrupt Level Local IRQ #4

16

Page 67

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.9.10 Summary of DUSCC #2

Device 68562 DUSCC
Access Address FF80.2200
Port Width Byte
Interrupt Request Level Software programmable
FGA-002 Interrupt Channel Local IRQ #5

3.10 The PI/T 68230

The MC68230 Parallel Interface/Timer provides versatile double
buffered parallel interfaces and an operating system oriented timer. The
parallel interfaces operate in unidirectional or bidirectional modes, either
8 or 16 bits wide. The PI/T contains a 24-bit wide counter and a 5-bit
prescaler.

3.10.1 Features of the PI/T

16

- MC68000 Bus Compatible

- Port Modes Include:
Bit I/O
Unidirectional 8 bit and 16 bit
Bidirectional 8 bit and 16 bit

- Selectable Handshaking Options

- 24-bit Programmable Timer

- Software Programmable Timer Modes

- Contains Interrupt Vector Generation Logic

- Separate Port and Timer Interrupt Service Requests

- Registers are Read/Write and Directly Addressable

Page 68

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.10.2 Address Map of the PI/T #1 Registers

PI/T #1 is accessible via the 8-bit local I/O bus (byte mode). The
following table shows the register layout of the PI/T #1.

Table 24: PI/T #1 Register Layout

Default
I/O Base Address:
Offset:
Name:

Address

(HEX)

FF800C00
FF800C01
FF800C02
FF800C03
FF800C04
FF800C05
FF800C06
FF800C07
FF800C08
FF800C09
FF800C0A
FF800C0B
FF800C0C
FF800C0D
FF800C10
FF800C11
FF800C12
FF800C13
FF800C14
FF800C15
FF800C16
FF800C17
FF800C18
FF800C19
FF800C1A

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A

Reset
Value

00
00
00
00
00
00
00
00

--

--

--

--

--

-­00
0F

--

--

--

--

--

--

--

-­00

$FF80 0000
$0000 0C00
PI_T1

Label Description

PIT1 PGCR
PIT1 PSRR
PIT1 PADDR
PIT1 PBDDR
PIT1 PCDDR
PIT1 PIVR
PIT1 PACR
PIT1 PBCR
PIT1 PADR
PIT1 PBDR
PIT1 PAAR
PIT1 PBAR
PIT1 PCDR
PIT1 PSR
PIT1 TCR
PIT1 TIVR
PIT1 CPR
"
"
"
PIT1 CNTR
"
"
"
PIT1 TSR

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register

Count Register

Timer Status Register

"
"
"

"
"
"

3.10.3 I/O Configuration of PI/T #1

☞

The following table lists all I/O signals connected to PI/T #1. The
functions of these signals are described in the corresponding chapter.

SEE ALSO: Additional information is provided in the PI/T data sheet,
included in Section 4, ‘Circuit Schematics and Data Sheets,’ on
page 115.

Table 25: PI/T #1 Interface Signals

Pin Function In/Out

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Rotary Switch 1
"
"
"
Rotary Switch 2
"
"
"

I
I
I
I
I
I
I
I

Page 69

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

Table 25: PI/T #1 Interface Signals (Continued)

Pin Function In/Out

H1

User I/O via optional B5 or optional 5-row VME P2 connector

H2

"

H3

"

H4

"

I

I/O

I

I/O

3.10.4 Rotary Switches at PI/T #1

PB0
PB1
PB2

1)

PB3

1)

PB4

PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

1. reserved

Floppy Disk Drive Control
"
"
"
"
"
DMA Controller Control
"

User I/O via optional B5 or optional 5-row VME P2 connector
"
Not Used, Reserved
Timer Interrupt Request
User I/O via optional B5 or optional 5-row VME P2 connector
Port Interrupt Request
68882 FPCP Sense
User I/O via optional B5 or optional 5-row VME P2 connector

O
O
O

I

I
O
O
O

I/O
I/O

-

O

I/O

O

I

I/O

PA0-PA7 lines:
There are two rotary switches installed on the front panel of the CPU

board. The position of each switch can be read in via port A of PI/T #1.
Each rotary switch provides four bits of data. Therefore, each switch has

16 possible positions and the value printed on the switch (i.e., 0-9 and
A-F) can be read from the lines PA0-PA3 (SW1) and PA4-PA7 (SW2) of
PI/T #1.

Page 70

The following table lists the input signals of PI/T #1 in relation to the
rotary switch signals.

Table 26: Rotary Switch Signals Assignment

Port A Bit Switch Bit

A0 "1" 0
A1 "1" 1
A2 "1" 2
A3 "1" 3
A4 "2" 0
A5 "2" 1
A6 "2" 2

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Table 26: Rotary Switch Signals Assignment (Continued)

Port A Bit Switch Bit

A7 "2" 3

NOTE: The rotary switches serve a special function in conjunction with

i

the RESET and ABORT switches. This functionality is built into the
Boot EPROM and is described in detail in the Boot Software description
of the FGA-002 User’s Manual.

For application programs, the rotary switches can be used as a general
purpose input channel for diagnostics, configuration selection, or
automatic system boot with different configurations.

VMEPROM uses the rotary switches for automatic configuration.

3.10.5 Floppy Disk Drive Control Lines at PI/T #1

PB0-PB5:

These lines control the FDC37C65C floppy disk drive interface. They
perform the functions listed in the table below.

Pin Signal Name

PB0 DCHGEN
PB1 DRV
PB2 PCVAL
PB3 Reserved
PB4 Reserved
PB5 EJECT

1. factory option

Pins PB3 and PB4 of PI/T #1 are reserved. They must be programmed for
input.

As a factory option the EJECT line (PB5) may be used as an output. This
signal is shared with the HLOAD signal of the Floppy Controller.

1)

☞

SEE ALSO: Please refer to Section 3.12, ‘The Floppy Disk Controller,’
on page 84 for more information.

Page 71

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.10.6 DMA Control Lines at PI/T #1

i

3.10.7 8-Bit User Defined I/O Port at PI/T #1

PB6, PB7:

These lines control the local peripheral bus when the DMA controller is
active. The signal PC6 controls the direction of the DMA transfer (read
vs. write). The PC7 signal selects the target of the DMA transfer (SCSI
controller or Floppy controller). The following table clarifies all four
possible combinations.

PB7 PB6 Function

0 0 DMA write to SCSI
0 1 DMA read from SCSI
1 0 DMA write to FDC
1 1 DMA read from SCSI

NOTE: An additional DMA control line is described in Section 3.10.21,
‘DMA Control Line at PI/T #2,’ on page 78.

PC0, PC1, PC4, PC7, H1-H4: (FACTORY OPTION)

This 8-bit input port may be available (as a factory option) at the 16-pin
connector B5 and may be available (as a factory option) at the 5-row
VME P2 connector. Four bits are connected to port C of PI/T #1 and can
be used as inputs or outputs. The remaining four bits are connected to the
handshake pins of PI/T #1. Handshake pins H2 and H4 may be used as
either inputs or outputs. Handshake pins H1 and H3 may only be used as
inputs.

Page 72

PI/T #1 B5 VME P2 I/O

H1 4 Z25 I
H2 3 Z27 I/O
H3 2 Z29 I
H4 1 Z31 I/O
C0 8 D27 I/O
C1 7 D28 I/O
C4 6 D29 I/O
C7 5 D30 I/O

The connector B5 (factory option) provides, besides the 8-bit user port
signals, a power signal GND on pins 9, 10, 11, 12, 13, 14, 15, and 16.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.10.8 Interrupt Request Signals of PI/T #1

TOUT:

The PI/T #1 pin PC3 is used as an interrupt request output. The 24-bit
timer can generate interrupt requests at a software programmable level.
This interrupt request line is connected to the IRQ #2 of the FGA-002.

PIRQ:

The PI/T #1 pin PC5 may be used as a port interrupt request output.
Normally, this pin is not used. However, PC5 may be used to generate an
additional interrupt if switch SW13-1 is OFF. In this case, the Port
Interrupt Request and the Timer Interrupt Request will use the same
FGA-002 interrupt channel. Therefore, they will generate interrupts at the
same interrupt priority level, and the user's software may need to poll the
PI/T device to determine the actual cause of the interrupt. For
compatibility with earlier boards, this pin is normally not used.

SW13-1 Function

OFF (default) Port Interrupt Disabled
ON Port Interrupt Enabled

NOTE: There is another timer interrupt signal at PI/T #2 which doesn’t

i

have anything to do with these signals of PI/T #1.

3.10.9 Floating Point
Coprocessor Sense
Line at PI/T #1

3.10.10 Reserved Line at PI/T #1

PC6:

This line reports whether or not an FPCP is installed on the CPU board.

PC6 Function

0 FPCP Installed
1 FPCP Not Installed

PC2:

This line is not used. In order to retain compatibility with earlier and
future versions, this line should not be used in any applications.

Page 73

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.10.11 Summary of PI/T #1

3.10.12 Address Map of the PI/T #2 Registers

Device 68230 PI/T
Access Address FF80.0C00
Port Width Byte
Interrupt Request Level Software programmable
FGA-002 Interrupt Channel (Timer IRQ) Local IRQ #2

16

The PI/T2 is accessible via the 8-bit local I/O bus (byte mode). The
following table shows the register layout of PI/T2.

Table 27: PI/T #2 Register Layout

Default
I/O Base Address:
Offset:
Name:

Address

(HEX)

FF800E00
FF800E01
FF800E02
FF800E03
FF800E04
FF800E05
FF800E06
FF800E07
FF800E08
FF800E09
FF800E0A
FF800E0B
FF800E0C
FF800E0D
FF800E10
FF800E11
FF800E12
FF800E13
FF800E14
FF800E15
FF800E16
FF800E17
FF800E18
FF800E19
FF800E1A

Offset

(HEX)

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A

Reset
Value

00
00
00
00
00
00
00
00

--

--

--

--

--

-­00
0F

--

--

--

--

--

--

--

-­00

$FF80 0000
$0000 0E00
PI_T2

Label Description

PIT2 PGCR
PIT2 PSRR
PIT2 PADDR
PIT2 PBDDR
PIT2 PCDDR
PIT2 PIVR
PIT2 PACR
PIT2 PBCR
PIT2 PADR
PIT2 PBDR
PIT2 PAAR
PIT2 PBAR
PIT2 PCDR
PIT2 PSR
PIT2 TCR
PIT2 TIVR
PIT2 CPR
"
"
"
PIT2 CNTR
"
"
"
PIT2 TSR

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register

Count Register

Timer Status Register

"
"
"

"
"
"

3.10.13 I/O Configuration of PI/T #2

☞

Page 74

The following table lists all I/O signals connected to PI/T #2. The
functions of these signals are described in the corresponding chapter.

SEE ALSO: Additional information is provided in the PI/T data sheet,
included in Section 4, ‘Circuit Schematics and Data Sheets,’ on
page 115.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Table 28: PI/T #2 Interface Signals

Pin Function In/Out

PA0

User I/O via optional B6 or optional 5-row VME P2 connector

PA1

"

PA2

"

PA3

"

PA4

"

PA5

"

PA6

"

PA7

"

H1

User I/O via optional B6 or optional 5-row VME P2 connector

H2

"

H3

"

H4

"

PB0

Memory Size

PB1

"

PB2

"

PB3

Board ID

PB4

"

PB5

"

PB6

"

PB7

"

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I

I/O

I

I/O

I
I
I
I
I
I
I
I

3.10.14 12-Bit User I/O Port at PI/T #2

PC0

Hardware ID

PC1

Hardware ID

PC2

Status of write protection for (default and optional) Boot PROMs

PC3

Timer Interrupt Request

PC4

Status of write protection for SYSTEM-Flash Memory

PC5

DMA control

PC6

Flash programming voltage control

PC7

Unused, reserved

I
I
I

O

I
O
O

I

PA0-PA7, H1-H4:

This 12-bit I/O port may be available (as a factory option) at a 16-pin
connector B6 and may be available (as a factory option) at the 5-row
VME P2 connector, providing a convenient connection for a flat cable.
Eight bits are connected to port A of PI/T #2 and can be used as inputs or
outputs. The remaining four bits are connected to the handshake pins of
PI/T #2. This port can be used to build a Centronics type interface.

Page 75

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

PI/T #2 Connection B6 VME-P2

3.10.15 Memory Size Identification at PI/T #2

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

H1
H2
H3
H4

10

11

12

13

14

15

Z1

7

6

5

4

3

2

Z3
Z5
Z7

Z9
Z11
Z13
Z15

Z17
Z19
Z21
Z23

The connector B6 (factory option) provides, besides the 12-bit user port
signals, power signals. The +5V power on pin 1 and pin 16 is protected
by a non destroyable 1A-fuse. The GND power is connected at pin 8 and
pin 9.

PB0-PB2:

From these lines, the on-board Shared RAM capacity can be read in by
software. The following assignment is defined:

3.10.16 Board Identification at PI/T #2

B2 B1 B0 Memory Capacity

0 0 0 32 Mbytes
0 0 1 16 Mbytes
0 1 0 8 Mbytes
0 1 1 4 Mbytes
1 0 0 Reserved

PB3-PB7:

From these lines, the CPU board identification number can be read in by
software. Every CPU board has a unique number. Different versions of
one CPU board (i.e. different speeds, capacity of memory, or modules)
contain the same identification number. In the case of the CPU-30 R4, the
number is ten ("10" decimal or 0A

hexadecimal "01010" binary).

16

Page 76

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.10.17 Interrupt Request Signal of PI/T #2

TOUT:

PI/T #2 pin PC3 is used as a Timer Interrupt Request output. The 24-bit
timer can generate interrupt requests at a software programmable
interval. The Timer Interrupt Request line is connected to the local IRQ
#3 of the FGA-002. Optionally, the Timer Interrupt Request may be used
as a "watchdog" reset generator.

If the PI/T #2 Timer Interrupt Request line is connected as a watchdog
reset generator, then the user can program the 24-bit timer to generate a
local hardware reset whenever the timer counts down to zero. This allows
the user to implement a simple watchdog timer. In normal operation, the
timer would never expire. Instead, the user's software (for example, a
background system task) would constantly restart the timer. Should the
timer fail to be restarted, the PI/T will generate a low level on the Timer
Interrupt Request output pin. That will trigger the Reset Generator,
resetting the entire CPU board. The watchdog reset generator option is
enabled and disabled via a switch at location SW13-2.

SW13-2 Description

OFF (default) Watchdog Timer Disabled
ON Watchdog Timer Enabled

i

3.10.18 PC0-PC1 Hardware ID at PI/T #2

3.10.19 Floppy Drive Ready Signal at PI/T #2

NOTE: There is another timer interrupt signal at PI/T #1 which doesn’t

have anything to do with these signals of PI/T #2.

To allow simple detection of different hardware implementations, a
hardware ID-number can be read in on the PI/T #2 pins PC0-PC1.

PC1 PC0 Description

1 1 Revision 1, 2, 3
1 0 Revision 4
0 1 Reserved
0 0 Reserved

PC2:

From this line the status of the write protection for the Boot PROM
devices may be monitored.

Page 77

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

CAUTION: PI/T #2 pin PC2 must be programmed as an input.

PC2 Function

0 Write to Boot PROM unprotected
1 Write to Boot PROM protected

3.10.20 Floppy Drive
Write Protect
Signal at PI/T #2

3.10.21 DMA Control Line at PI/T #2

PC4:

From this line the status of the write protection for the System Flash
Memory may be monitored.

CAUTION: PI/T #2 pin PC4 must be programmed as an input.

PC4 Function

0 Write to System Flash Memory unprotected
1 Write to System Flash Memory protected

CAUTION: Writes to the System Flash Memory must always be
performed with a 4-byte wide port size and must be aligned on 4-byte
boundaries.

PC5:

This line controls the local devices when a DMA transfer is in progress.
When the DMA controller accesses a local device (SCSI or FDC), this
line must be set to "0".

3.10.22 Flash Programming Control at PI/T #2

Page 78

☞

SEE ALSO: There are two other DMA Control Lines (controlling the
local peripheral bus) which are described in Section 3.10.6, ‘DMA
Control Lines at PI/T #1,’ on page 72.

PC6:

A 12V-Vpp-Generator must be controlled to support programming of the
System Flash Memory and the Boot PROM memory in the default Boot
PROM socket.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

CAUTION: PI/T #2 pin PC6 must be programmed as an output.

PC6 Function

0 Vpp on
1 Vpp off

The Vpp generator is shared between the System Flash Memory and the
default Boot PROM socket.

SEE ALSO: For further information please refer to Section 3.5, ‘The

☞

System PROM Area,’ on page 42 and to Section 3.6.1.4, ‘Programming
Flash Devices,’ on page 47.

3.10.23 Reserved Lines at PI/T #2

3.10.24 Summary of PI/T #2

PC7:

These lines are not used. In order to retain compatibility with earlier and
future versions, these lines should not be used in any applications.

Device 68230 PI/T
Access Address FF80.0E00
Port Width Byte
Interrupt Request Level Software programmable
FGA-002 Interrupt Channel Timer IRQ: Local IRQ #3

16

Page 79

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.11 SCSIbus Controller MB 87033/34

The MB 87033/34 SCSI Controller, with its up to 4 Mbytes/s data
transfer rate, is installed on the CPU to interface directly to SCSI
Winchester disks, optical drives or tape streamers.

All I/O signals are available on the user defined pins of the VMEbus P2
connector. The I/O signal assignment is compatible with the SYS68K/
ISCSI-1 Controller which allows the use of the SYS68K/IOBP-1 for
interconnection to mass storage devices.

SEE ALSO: For further information please refer to Section 9.1.5,

☞

‘SYS68K/ISCSI-1 Disk Controller,’ on page 153 and to Section 2.11,
‘The SYS68K/IOBP-1,’ on page 26.

The SCSI Controller on the CPU board is fully supported by the installed
real-time monitor debugger VMEPROM.

3.11.1 Features of the 87033/34 SCSI Controller

3.11.2 Address Map of MB 87033/34 Registers

☞

- Functional superset of the MB87031 SCSI Controller

- Direct interface to SCSI bus devices with on-chip drivers

- Full support for SCSI control

- Service of either initiator or target device

- Eight byte data buffer register incorporated

- Transfer byte counter (24 bit)

- Independent control and data transfer bus

- Asynchronous data transfer speed of 2 Mbytes/s

- Synchronous data transfer speed up to 4 Mbytes/s

The registers of the MB 87033/34 are accessible via the 8-bit local data
bus (byte mode).

SEE ALSO: Additional information is provided in the MB 87033/34
data sheet, included in Section 4, ‘Circuit Schematics and Data Sheets,’
on page 115.

3.11.3 The SCSI DMA Controller

Page 80

The 8-bit DMA channel of the SCSI Controller is directly connected to
the installed DMA Controller (inside FGA-002 Gate Array) allowing
data transfer with a maximum speed of 4 Mbyte/s.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

The DMA Controller includes a 32-byte FIFO which waits until the 32
bytes are filled and then requests local bus mastership for an eight cycle
data transfer (32 bit in parallel).

In addition to the 32-byte DMA FIFO, the DMA channel includes a
second FIFO (8 bytes deep) to fill the DMA FIFO if the DMA transfer to
main memory is taking place. This allows continuous data transfer on the
local DMA bus with a data rate of 4 Mbyte/s without any timing gaps in
between.

This technique permits the CPU to perform in a real time capacity
because the ratio of CPU and DMA operation at the maximum SCSI data
transfer rate of 4 Mbyte/s is 73% for the CPU, 20% for the DMA
Controller and 7% for arbitration overhead. If the data transfer rate is less
than 4 Mbyte/s, the percentage range of CPU operation increases and the
DMAC range decreases while the overhead of 7% remains unchanged.

3.11.3.1DMA Control

Lines

Two output pins of PI/T #1 and one output pin of PI/T #2 are used to
control the data direction, to start the DMA Controller, and select the
local peripheral devices.

PI/T #1 Port B bits 6 and 7 control the local devices when DMA transfers
are initiated. The following table shows which bit selects the direction of
the DMA transfer and which bit selects the FDC or SCSI Controller.

PB7 PB6 Function

0 0 DMA write to SCSI
0 1 DMA read from SCSI
1 0 DMA write to FDC
1 1 DMA read from FDC

Port C bit 5 of PI/T #2 controls the local devices in case of direct memory
access (DMA) as shown in the following table.

PC5 Function

0 DMA active
1 DMA is not active

The listing below provides a programming example for DMA transfers.

Page 81

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.11.3.2DMA Transfer

Programming
Example

*--------------------------------------------------------------­* DATA OUTPUT TO SCSI TARGET, USING THE MB87033/34 AND THE
* FGA-002 DMA CHANNEL
*---------------------------------------------------------------

:
BCLR #$07,PBDR+PI_T ;SELECT DMA WORKS WITH SCSI
BCLR #$06,PBDR+PI_T ;SELECT TRANSFER DMA TO SCSI
* THE FOLLOWING AUX VALUES ARE ONLY VALID FOR THE CPU-30 !
MOVE.B #$00,FGA02+AUXPINC ;AUX PIN CONTROL
MOVE.B #$30,FGA02+AUXDST ;AUXDSTSTART
MOVE.B #$45,FGA02+AUXDTE ;AUXDSTTERM
MOVE.B #$00,FGA02+AUXDSTR ;AUXDSTWEX
MOVE.L #BCOUNT,FGA02+DMABCNT ;BYTE COUNT
MOVE.L #SADDR,FGA02+DMASADR ;DMA SOURCE ADDR
MOVE.B #$C5,FGA02+DMASATR ;DMA SOURCE ATTRIBUTE (DPR)
MOVE.B #$C8,FGA02+DMADATR ;DMA DEST ATTRIBUTE (AUX)
MOVE.B #$41,FGA02+DMAGEN ;DMA GENERAL CONTROL
:
MOVE.B #$00,SCSI+TMODREG ;SET SCSI TRANSFER MODE
MOVE.B #$80,SCSI+SCMDREG ;SCSI COMMAND
BCLR #$00,PCDR+PI_T2 ;SET TO DMA ACTIVE
MOVE.B #$01,FGA02+DMARUNC ;START DMA CONTROLLER
WAIT TST.B FGA02+DMARUNC ;POLL ON DMA READY
BMI.B WAIT
BSET #$00,PI_T2+PCDR ;SET TO CPU ACTIVE
:

3.11.4 The SCSIbus

3.11.4.1SCSIbus

Configuration

Communication on the SCSIbus is only allowed between two SCSI
devices at any given time. There may be a maximum of eight SCSI
devices. Each SCSI device has a SCSI ID bit assigned. When two SCSI
devices communicate on the SCSIbus, one acts as an initiator, and the
target performs the operation. A SCSI device usually has a fixed role as
an initiator or target, but some devices may be able to assume either role.

An initiator may address up to seven peripheral devices that are
connected to a target. An option allows the addressing of up to 2048
peripheral devices per target using extended messages.

Of the eight SCSI devices supported on the SCSIbus, there can be any
combination of initiators and targets. Certain SCSIbus functions are
assigned to the initiator and other functions are assigned to the target. The
initiator may arbitrate for the SCSIbus and select a particular target. The
target may request the transfer of COMMAND, DATA, STATUS, or
other information on the data bus, and in some cases, it may arbitrate for
the SCSIbus and reselect an initiator for the purpose of continuing an
operation.

Page 82

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

Information transfers on the data bus are asynchronous and follow a
defined REQ/ACK handshake protocol. One byte of information may be
transferred with each handshake. An option is defined for synchronous
data transfer.

3.11.4.2SCSIbus Signal

Termination

3.11.4.3SCSIbus

Terminator
Power

Each SCSIbus signal should be terminated at the physical start and the
physical end of the SCSIbus. Therefore, the CPU-30 R4 provides
circuitry for active termination.

Active termination can be controlled by switch SW7-3.

SW7-3 Description

OFF Active SCSI termination on

ON Active SCSI termination off

The power for the terminator of any SCSI device will be provided from
the CPU board directly, or from the SCSIbus itself. If termination power
is not delivered from any other SCSI device, it is delivered from the CPU
board.

The TERMPWR (terminator power) supply from the CPU board is
protected by a self resetting fuse (1A max) and a diode in series, as
defined in the SCSI specification.

The on-board terminators will draw power from the SCSIbus
TERMPWR.

3.11.5 Summary of the SCSIbus Controller

Device MB 87034
Access Address FF80.3400
Port Width Byte
Interrupt Request Level Software Programmable
FGA-002 Interrupt Request Channel Local IRQ #7

16

Page 83

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

3.12 The Floppy Disk Controller

The CPU board contains a single chip floppy controller, the
FDC37C65C. The FDC is connected to the DMA controller of the
FGA-002 Gate Array. The installed driver/receiver circuits allow direct
connection of 3 1/2" and 5 1/4" inch floppy drives. All I/O signals are
available on the VMEbus P2 connector. The I/O signal assignment is
compatible to the SYS68K/ISCSI-1 controller, which allows the use of
the SYS68K/IOBP-1 and IOPI-2 for interconnection to mass storage
devices.

3.12.1 Features of the FDC37C65C Controller

3.12.2 Address Map of the FDC

☞

- Built-in data separator

- Built-in write precompensation

- 128-, 256-, 512- or 1024-byte sector lengths

- 3 1/2" or 5 1/4" single and double density

- Programmable stepping rate (2 to 6 ms)

The registers of the FDC are accessible via the 8 bit local I/O bus (byte
mode). The following table shows the register layout of the FDC37C65C
for the CPU-30 R4.

SEE ALSO: Additional information is provided in the FDC37C65C data
sheet included in Section 4, ‘Circuit Schematics and Data Sheets,’ on
page 115.

FF80.380016Read Main Status Register

(Write is illegal)

FF80.380116Read Data Register

Write Date Register

FF80.388016Read DCHG Register

Write Data Rate Selection Register

3.12.3 Data Rate Support

☞

Page 84

FF80.390016Write Digital Output Register

(Read is illegal)

The FDC37C65C allows two Data Rate Selection Options controlled via
the Data Rate Selection Register. The CPU-30 R4 supports the 16 MHz
and 9.6 MHz options.

SEE ALSO: For further details please refer to Section 4, ‘Circuit
Schematics and Data Sheets,’ on page 115.

SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.12.4 Drive Select Support

3.12.5 Motor-On Support

3.12.6 DMA Control Lines

The CPU-30 R4 supports two drive selects - DSEL 1 and DSEL 2 which
are generated by the FDC37C65C-Controller.

The FDC37C65C Floppy Controller provides two signals for motor
control. On the CPU-30 R4 they are tied together to build the Motor-On
Signal.

Two output pins of PI/T #1 and one output pin of PI/T #2 are used to
control the data direction, to start the DMA Controller, and to control the
used local devices.

PI/T #1 Port B bits 6 and 7 control the local devices in case of direct
memory access (DMA). The following table shows which bit selects the
direction of the DMA transfer and which bit selects the FDC or SCSI
Controller.

PB7 PB6 Function

0 0 DMA write to SCSI
0 1 DMA read from SCSI

☞

3.12.7 Floppy Disk Connector Assignment

1 0 DMA write to FDC
1 1 DMA read from FDC

Port C bit 5 of PI/T #2 controls the local devices in case of direct memory
access (DMA) as shown in the following table.

PC5 Function

0 DMA active
1 DMA is not active

SEE ALSO: The listing in Section 3.12.7.1, ‘DMA Transfer
Programming Example,’ on page 86 provides a programming example
for DMA transfers.

Signal VME P2 Connector

RDY C17
SDSEL C16
RDATA C15

Page 85

Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual

Signal VME P2 Connector

WPROT C14
TRU00 C13
WGATE C12
WDATA C11
STEPX C10
DIRBC C9
MOTOR C8
DSEL1 C5, (C7)
DSEL2 C6, (C3)
INDEX C4

1)

2)

i

3.12.7.1DMA Transfer

Programming
Example

HLOAD
(EJECT)

RPM C1

1. Backward compatibility to DSEL3

2. backward compatibility to DSEL4

3. factory option

3)

C2

NOTE: For the connection to the IOBP-1 back panel, please refer to
Section 2.11, ‘The SYS68K/IOBP-1,’ on page 26.

*--------------------------------------------------------------­* READ DATA FROM FLOPPY, USING THE FDC AND THE FGA-002
* DMA CHANNEL
*--------------------------------------------------------------­ :
BSET #$07,PI_T1+PBDR(A4) ;SELECT DMA WORKS WITH FDC
BSET #$06,PI_T1+PBDR(A4) ;SELECT TRANSFER FDC TO DMA
* THE FOLLOWING AUX VALUES ARE FOR CPU-30 ONLY !!!
MOVE.B #$00,FGA02+AUXPINC ;AUX PIN CONTROL
MOVE.B #$07,FGA02+AUXSST ;AUXSRCSTART
MOVE.B #$03,FGA02+AUXSTE ;AUXSRCTERM
MOVE.B #$0F,FGA02+AUXSRCW ;AUXSRCWEX
MOVE.L #BCOUNT,FGA02+DMABCNT ;BYTE COUNT
MOVE.L #DADDR,FGA02+DMADADR ;DESTINATION ADDRESS
MOVE.B #$C8,FGA02+DMASATR ;DMA SOURCE ATTRIBUTE (AUX)
MOVE.B #$C5,FGA02+DMADATR ;DMA DEST ATTRIBUTE (DPR)
MOVE.B #$81,FGA02+DMAGEN ;DMA GENERAL CONTROL
MOVE.B #$01,FGA02+DMARUNC ;START DMA CONTROLLER
MOVE.B #$88,FDC+FCMDREG ;READ SECTOR COMMAND
BCLR #$00,PI_T2+PCDR ;SET TO DMA ACTIV
WAIT TST.B FGA02+DMARUNC ;WAIT UNTIL DMA IS READY
BMI.S WAIT
BSET #$05,PI_T2+PCDR ;SET TO CPU ACTIVE
:

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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description

3.12.8 Jumper Setting on the Floppy Disk Drive

CAUTION: If the floppy disk drive contains a jumper which connects

the floppy disk drive frame electrically with DC ground, insertion of this
jumper is not allowed and can cause damage.

3.12.9 Summary of the Floppy Disk Controller

Device FDC37C65C
Access Address FF80.3800
Port Width Byte
Interrupt Request Level Software programmable
FGA-002 Interrupt Request Channel Local IRQ #1

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