FLY SX240 Service Manual

SP-770 AS Manual

(GSM/GPRS Cellular Phone)

SKYSPRING & VITELCOM

CONTENTS

SECTION1. SP-770 PRODUCT OVERVIEW

1. RF Transceiver Part

1.1 Introduction

1.1.1 Features

1.1.2 Applications

1.1.3 General Description

1.1.4 MT6120 Function Block Diagram

1.2 Functional Description

1.2.1 Receiver

1.2.2 Transmitter

1.2.3 TX VCO

1.2.4 Frequency Synthesizer

1.2.4.1 Synthesizer System Description

1.2.4.2 Synthesizer Frequency Programming for RX Mode

1.2.4.3 Synthesizer Frequency Programming for TX Mode

1.2.4.4 Digital Calibration Loop

1.2.4.5 Fast-Acquisition System

1.2.4.5 Voltage Control Crystal Oscillator

1.2.4.6 Regulator

2. BASEBAND Part

2.1 Introduction

2.1.1 Platform

2.1.2 Memory

2.1.3 Multi-media

2.1.4 Connectivity and Storage

2.1.5 Audio

2.1.6 Radio

2.1.7 Debug function

2.1.8 Power Management

2.1.9 Package

2.2 Platform Features

2.2.1 General

2.2.2 MCU subsystem

2.2.3 External Memory Interface

2.2.4 User Interface

2.2.5 Security

2.2.6 Connectivity

2.2.7 Power management

2.2.8 Test and Debug

2.3 Modem Feature

2.3.1 Radio Interface and Baseband Front End

2.3.2 Voice and Modem Codec

2.3.3 Voice interface and Voice Front End

2.4 Multi-media Features

2.4.1 LCD/NAND Flash Interface

2.4.2 LCD Controller

2.4.3 Image serial Processor

2.4.4 Graphic Compression

2.4.5 JPEG Decoder

2.4.6 JPEG Encoder

2.4.7 Image Data Processing

2.4.8 MPEG-4/H.263. CODEC

2.4.9 TV-OUT

2.4.10 2D Accelerator

2.4.11 Audio Codec

2.4.12 Audio Interface and Audio Front End

2.5 General Description

3. Power Management System

3.1. Feature

3.2. Application

3.3. General Description

3.4. Detailed Description Overview

3.4.1 Low Dropout Regulator ( LDOs) and Reference

3.4.2 Digital Core LDO (Vcore)

3.4.3 Digital IO LDO (Vio)

3.4.4 Analog LDO ( Va )

3.4.5 TCXO LDO (Vtcxo)

3.4.6 RTC LDO (Vrtc)

3.4.7 Memory LDO (Vm)

3.4.8 SIM LDO (Vsim)

3.4.9 Reference Voltage Output (Vref)

3.4.10 SIM Card Interface

3.4.11 Vibrator, Alerter, LED Switches

3.5 Power Sequence and Protection Logic

3.5.1 Under voltage Lockout (UVLO)

3.5.2 Deep Discharge Lockout (DDLO)

3.5.3 Reset

3.5.4 Over temperature Protection

3.5.5 Battery Charger

4. POWER AMPLIFIER FOR GSM850 / DCS1800 / PCS1900

4.1 Block Diagram and Description

5. EXTERNAL DEVICE PART

5.1 External memory

5.1.1 Feature

5.1.2 Block Diagram & Description

5.2 Parallel memory

5.2.1 Feature

5.2.2 Block Diagram & Description

5.3 LCD Module

5.3.1 Feature

5.3.2 Block Diagram & Description

5.4 CAMERA IMAGE SENSOR

5.4.1 Block Diagram & Description

SECTION2. SCHEMATIC LAYOUT

1. MAIN PART SCHEMATIC LAYOUT

1.1 BASEBAND PART

1.2 MMI PART

1.3 RF PART

2. MAIN-KEY PART SCHEMATIC LAYOUT

3. LCD SCHEMATIC LAYOUT

SECTION3. PCB LAYOUT

1. MAIN PCB

1.1 Location Map of Main PCB Top

1.2 Location Map of Main PCB Bottom

2. MAIN-KEY PCB

2.1 Location Map of Main KEY PCB Top

2.2 Location Map of Main KEY PCB Bottom

3. LCD PCB

SECTION4. MECHANICAL ASSEMBLY

SECTION5. ALIGNMENT PROCEDURE

1. RECOMMENDED TEST EQUIPMENT

2. CONNECTION OF TEST EQUIPMENT

3. LOGIC PART TROUBLESHOOTING

4. RF PART TROUBLESHOOTING

SECTION6. EQUIPMENT REPARE PROCEDURE

1. No Power On with Battery Applied

2. LCD display and backlight error

3. Key pushing error and LED not in operation

4. Vibrator not in operation
5 MP3 Play not in operation

6. Camera Play not in operation.

7. FM Radio Play Error
8 Charging error

9. Bluetooth error

10. GSM RX/TX Power

SECTION7. How to use Flash Tool Manual

1. Introduction

2. Operating Environment

3. Installation

4. Setting.

5. Downloading

SECTION8. How to use Meta Tool Manual

1. Introduction

2. Operating Environment

3. Installation

4. Settings.

5. How to make the back up NVRAM data (system parameters)

6. How to restore the back up NVRAM data into target.

SECTION1. SP 770 PRODUCT OVERVIEW

1. RF Transceiver Part

1.1 Introduction

1.1.1 Feature

Receiver

- Very low IF architecture

- Tri- band differential input LNAs

- Quadrature RF mixers

- Fully integrated channel filter

- More than 100 dB gain

- More than 110 dB control range

- Image-reject down conversion to baseband

Transmitter

- Precision IQ modulator

- Translation loop architecture

- Fully integrated wideband TX VCO

- Fully integrated TX loop filter

Frequency Synthesizer

- Single integrated, fully programmable fractional-N synthesizer

- Fully integrated wideband RF VCO

- Fast settling time suitable for multi-slot GPRS application
Voltage Control Crystal Oscillator (VCXO)

- 26 MHz crystal oscillator capable of supporting 13MHz / 26 MHz output clock

- Programmable capacitor array for coarse tuning

- Internal varactor for fine tuning
Regulators

- Built-in low-noise, low-dropout (LDO) regulators
Low power consumption
QFN (Quad Flat Non-lead) Package 56-pin SMD
3-wire serial interface
MT6120 is fabricated using a 0.35 µm BiCMOS process

1.1.2 Applications
GSM 850 / PCS 1900 dual -band handsets
GSM 850 / DCS 1800 / PCS 1900 triple-band handsets

1.1.3 General Description
MT6120 is a highly integrated RF transceiver IC for multi-band Global Systems for
Mobile communication (GSM) and General Packet Radio Service (GPRS) cellular system
applications. The MT6120 includes four LNAs, two RF quadrature mixers, an integrated
channel filter, programmable gain amplifiers (PGA), an IQ demodulator for the receiver,
a precision IQ modulator with offset PLL for the transmitter, two internal TXVCOs, a
VCXO, on-chip regulators, and a fully programmable sigma-delta fractional-N
synthesizer with an on-chip RF VCO. The MT6120 also includes control circuits to
enable different operating modes. The device is housed in a 56-pin QFN SMD package

with a down set paddle for additional grounding .A functional block diagram of the
MT6120 and its pin assignment are shown in Figure 1.

1.1.4 MT6120 Function Block Diagram

Figure 1 MT6120 Function Block Diagram

1.2 Functional Description

1.2.1 Receiver

The receiver section of MT6120 includes Tri-band low noise amplifiers (LNAs), RF
quadrature mixers, an on-chip channel filter, Programmable Gain Amplifiers (PGAs),
quadrature second mixers, and a final low-pass filter. The very low-IF MT6120 uses
image-rejection mixers and filters to eliminate interference. With accurate RF
quadrature signal generation and mixer matching techniques, the image rejection of the
MT6120 can reach 35 dB for all bands. The fully integrated channel filters rejects
interference, blocking signals, and images without any external components Compared
to a direct conversion receiver (DCR), MT6120’s very low-IF architecture improves
the blocking rejection, AM suppression, as well as the adjacent channel interference
performance. Moreover, the very low-IF architecture eliminates the need for
complicated DC offset calibration that is necessary in a DCR architecture. In addition,
the common-mode balance requirement of the SAW filter input is relaxed. The
MT6120 provides the analog IQ baseband output without any extra frequency
conversion components.
The MT6120 includes Three differential LNAs for GSM 850 (869 MHz – 893 MHz),
DCS 1800 (1805 MHz-1880 MHz) and PCS 1900 (1930 MHz –1990 MHz). The
differential inputs are matched to 200 Ω SAW filters using LC networks. The gain of
the LNAs can be controlled either high or low for an additional 35 dB dynamic range
control. Following the LNAs are the image-rejection quadrature RF mixers that down­convert the RF signal to the IF frequency. No external components are needed at the
output of the RF mixers.
The IF signal is then filtered and amplified through an image-rejection filter and a PGA.
The multi-stage PGA is implemented between filtering stages to control the gain of the
receiver. With 2 dB gain steps, a 78 dB dynamic range of the PGA ensures a proper
signal level for demodulation. The quadrature 2nd mixers are provided on-chip to
down convert IF signal to baseband in an analog differential IQ format.

1.2.2 Transmitter

The MT6120 transmitter section consists of two on-chip TX VCOs, buffer amplifiers, a
down-converting mixer, a quadrature modulator, an analog phase detector (PD) and a
digital phase frequency detector (PFD), each with a charge pump output and on chip
loop filter. The dividers and loop filters are used to achieve the desired IF frequency
from the down-conversion mixer and quadrature modulator. For a given transmission
channel, the transmitter will select one of the two different TX reference dividing
numbers. These built-in components, along with an internal voltage controlled
oscillator (TX VCO) and a loop filter, implement a translation loop modulator. The TX
VCO output is fed to the power amplifier (PA). A control loop, implemented externally,
is used to control the PA’s output power level.

1.2.3 TX VCO

Two power VCOs are integrated with OPLL to form a complete transmitter circuit. The
TX VCO output power is typically 9 dBm with +/- 2.5dB variation /
GSM850 bands and +8 dBm output power with +/- 2dB variation in DCS1800/

PCS1900 bands over extreme temperature conditions. Inside the chip, the VCO
differential output signals are fed into the output buffer, the OPLL input feedback
buffer, and the calibration circuit. The off chip signal is transformed into a single ended
output which needs impedance matching to 50Ωto drive the power amplifier. Like RF
VCO, the oscillation bandwidth is partitioned into 128 (or 64) sub-bands for DCS/ PCS
TX VCO to cover the process and temperature variation. Calibration process begins
after a period of programmable time when the on chip TX VCO regulator is turned on.
Total calibration time needs about 60us maximally and the frequency error after
calibration is within +/-5 MHz. For Vtune=1.2 V, the variation of kvco is about 14%
and 40% for GSM and DCS/PCS TX VCO, respectively, across the desired frequency
range.

1.2.4 Frequency Synthesizer

1.2.4.1 Synthesizer System Description
The MT6120 includes a frequency synthesizer with a fully integrated RF VCO to
generate RX and TX local oscillator frequencies. The PLL locks the RF VCO to a
precision reference frequency at 26 MHz. In order to reduce the inherent spur caused
by fractional-N synthesizers, a 3rd-order sigma-delta modulator with dithering
function is used to generate the prescaler divider number N. The prescaler is based
on a multi-modulus architecture with programmable divider numbers ranging from 64
to 127. A conventional digital-type PFD with a charge pump is used for phase
comparison in the PLL. By changing the output current of the charge pump, the phase
detector gain can be programmed from75/π µA/rad to 600/π µA/rad.
To reduce the acquisition time or to enable fast settling time for multi-slot data
services such as GPRS, a digital loop (calibration loop) along with a fast-acquisition
system are implemented in the synthesizer. Once the synthesizer is programmed, the
RF VCO is pre-set to the vicinity of the desired frequency by a digital calibration loop.
After the calibration, a fast-acquisition system is utilized for a period of time to
facilitate fast locking. Once the acquisition is done, the PLL reverts back to the normal
operation mode.

1.2.4.2 Synthesizer Frequency Programming for RX Mode
The frequency ranges of the synthesizer for RX mode are
RX mode GSM 850 1737 MHz ~ 1788 MHz
DCS 1800 1805 MHz ~ 1880 MHz
PCS 1900 1930 MHz ~ 1990 MHz.
And the divider number N can be decided by the following procedure.

1. Calculate LO frequency fVCO from RX channel frequency fCH
fVCO = 2 * fCH – 200k for GSM 850 and E-GSM 900
fVCO = fCH – 100k for DCS 1800 and PCS 1900

2. Calculate Nint and Nfrac
N = 64 + Nint + Nfrac/5200 = fVCO/26M Nint and Nfrac are integers
0 ≤ Nfrac < 5200

3. Use the binary equivalents of Nint and Nfrac to program registers CW1-N_INT

and CW1-N_FRA.

1.2.4.3 Synthesizer Frequency Programming for TX Mode
The frequency ranges of the synthesizer for TX mode are
TX mode GSM850 1813 MHz ~ 1868 MHz
DCS1800 1881 MHz ~ 2008 MHz
PCS1900 2035 MHz ~ 2149 MHz
And the divider number N can be decided by the following procedure.

1. Set the divider ratio D1 of TX reference divider = 11

2. Calculate LO frequency fVCO from TX channel frequency fCH
fVCO = 2 * D1 * fCH / (D1-1) for GSM850
fVCO = D1 * fCH / (D1-1) for DCS1800 and PCS1900

3. Calculate Nint and Nfrac
N = 64 + Nint + Nfrac/5200 = fVCO/26M Nint and Nfrac are integers
0 ≤ Nfrac < 5200

4. If Nfra < 400 or Nfra > 4800, re-set D1 = 9 and repeat Step 2 and 3 to get new
Nint and Nfrac.

5. Use the binary equivalents of Nint and Nfrac to program registers CW1-N_INT
and CW1-N_FRA.

1.2.4.4 Digital Calibration Loop
The MT6120 uses a digital calibration technique to reduce the PLL settling time.
Once the RF synthesizer is programmed through a 3-wire serial interface, the
calibration loop is activated. The main function of the calibration loop is to preset
the RF VCO to the vicinity of the desired frequency quickly and correctly, thus
aiding the PLL to settle faster.
On the other hand, since a large portion of initial frequency error is dealt with by
the integrated calibration loop, the overall locking time can be drastically reduced,
irrespective of the desired frequency.

1.2.4.5 Fast-Acquisition System
After the digital calibration loop presets the RFVCO, the RF synthesizer reverts to
the PLL operation and a fast-acquisition system is activated. For faster settling, the
charge pump current is set to a higher current than normal setting for a period of
time, typically, 20 µs or 60 µs.

1.2.4.5 Voltage Control Crystal Oscillator
Voltage Control Crystal Oscillator (VCXO) consists of an amplifier, a buffer, and a
programmable capacitor array. The VCXO provides the MT6120 with a selectable
reference frequency of either 13 MHz or 26 MHz.
The amplifier is designed to be in series resonance with a standard 26 MHz crystal.
The crystal is connected from the input pin XTAL of amplifier to ground through a
series load capacitance. The buffer provides a typical 600 mVpp voltage swing at
either 13 MHz or 26 MHz. It is designed to drive a tuned load to improve harmonic
contents and reduce the oscillator current consumption. The capacitor array, from

0.0625 pF to 4 pF in steps of 0.0625 pF, is used to shunt the series load capacitor
for coarse tuning and remove any fixed offsets due to crystal manufacturing
variations. An internal varactor that provides fine tuning combines with the

capacitor array. As an alternative, the reference frequency can be provided by an
external 26 MHz VCTCXO module. When pin VCXOCXR is tied to the VCCVCXO
supply, the XTAL pin will accept an external signal. Furthermore, the VCXO control
pin can be tied to VCCVCXO to prevent the current leakage during the sleep mode
operation.

1.2.4.6 Regulator
The MT6120 internal regulators provide low noise, stable, temperature and process
independent supply voltages to critical blocks in the transceiver. An internal P­channel MOSFET pass transistor is used to achieve a low dropout (LDO) voltage of
less than 150 mV in all regulators.

2. BASEBAND Part

2.1 Introduction

MT6228 is a feature-rich extremely powerful single-chip solution for high–end

GSM/GPRS mobile phones. Based on 32 bit ARM7EJ-STM RISC processor, MT6228’s
superb processing power along with high bandwidth architecture and dedicated
hardware support provides an unprecedented platform for high performance GPRS
Class 12 MODEM and leading-edge multimedia applications. Overall, MT6228 presents
a revolutionary platform for multimedia-centric mobile devices.
Typical application diagram is shown in Figure 2

Figure2 Typical application of MT6228

2.1.1 Platform
MT6228 is capable of running the ARM7EJ-Stm RISC processor at up to 104Mhz, thus
providing fast data processing capabilities. In addition to high clock frequency,
separate CODE and DATA caches are also added to further improve the overall system
efficiency.
For large amount of data transfer, high performance DMA (Direct Memory Access) with
hardware flow control is implemented, which greatly enhances the data movement
speed while reducing MCU processing load.
Targeted as a media-rich platform for mobile applications, MT6228 also provides
hardware security digital rights management for copyright protection. For future
safeguarding, and to protect manufacture’s development investment, hardware flash
content protection is also provided to prevent unauthorized porting of software load.

2.1.2 Memory
To provide the greatest capacity for expansion and maximum bandwidth for data
intensive applications such as multimedia features. MT6228 supports up to 4 external
state-of-the art devices through its 8/16-bit host interface.
High performance devices such as Mobile RAM, and Cellular RAM are supported for
maximum bandwidth.
Traditional devices such as burst/page mode Flash, page mode SRAM, and Pseudo
SRAM are also supported. For greatest compatibility, the memory interface can also be
used to connect to legacy devices such as Color/Parallel LCD, and multi-media
companion chip are all supported through this interface. To minimize power
consumption and ensure low noise, this interface is designed for flexible I/O voltage
and allows lowering of supply voltage down to 1.8V. The driving strength is
configurable for signal integrity adjustment. The date bus also employs retention
technology to prevent the bus from floating during turn over.

2.1.3 Multi-media
The MT6228 multi-media subsystem provides connection to CMOS image sensor and
supports resolution up to 3M pixels. With its advanced image signal and data
processing technology, MT6228 allows efficient processing of image and data. It also
has built-in JPEG CODEC and MPEG-4 CODEC, thus enabling real-time recording and
playback of high-quality images and video. Hardware MPEG4 accelerator supports
playback in VGA mode at 15fps, and encoding in CIF at 15fps. Videophone functionality
is also provided. Moreover, high quality de-blocking filter is provided to remove
blocking artifacts in video playback. GIF decoder and PNG decoder are implemented as
well for fast image decoding. MT6228 supports TV-OUT capability, thus allowing the
mobile handset to connect to TV screen via NTSC/PAL connections.
In addition to advanced image and video features, MT6228 also utilizes high resolution
DAC, digital audio, and audio synthesis technology to provide superior audio features
for all future multi-media needs.

2.1.4 Connectivity and Storage
In order to take advantage of its incredible multimedia strengths, MT6228 incorporates
myriads of advanced connectivity and storage options for data storage and
communication. MT6228 supports UART, Fast IrDA. USB 1.1 Full speed OTG, SDIO,
Bluetooth and WIFI Interface, and MMC/SD/MS/MS Pro storage systems, All these
interfaces provide MT6228 users with the highest degree of flexibility in implementing
solutions suitable for the targeted application. To achieve a complete user interface,
MT6228 also brings together all the necessary peripheral blocks for multi-media
GSS/GPRS phone. The peripheral blocks includes the Keypad Scanner with the
capability to detect multiple key presses, SIM Controller, Alerter, Real Time Clock,
PWM, Serial LCD controller, and General Purpose Programmable I/Os.

Furthermore, to provide more configuration and bandwidth for multi-media products,

and additional 18-bit parallel interface is incorporated, This interface enables
connection to LCD panels as well as connection to NAND flash devices for additional
multi-media data storage.

2.1.5 Audio
Using a highly integrated mixed-signal Audio Front-End, the MT6228 architecture
allows for easy audio interfacing with direct connection to the audio transducers. The
audio interface integrates D/A and A/D Converters for Voice band, as well as high
resolution Stereo D/A Converters for Audio band. In addition, MT6228 also provides
Stereo Input and Analog Mux.

MT6228 supports AMR codec to adaptively optimize speech and audio quality.

Moreover, HE-AAC codec is implemented to deliver CD-quality audio at low bit rates.

On the whole, MT6228's audio features provide a right solution for multi-media

applications.

2.1.6 Radio
MT6228 integrates a mixed-signal Baseband front-end in order to provide a well­organized radio interface with flexibility for efficient customization. It contains gain and
offset calibration mechanisms, and filters with programmable coefficients for
comprehensive compatibility control on RF modules. This approach also allows the
usage of a high resolution D/A Converter for controlling VCXO or crystal, thus
reducing the need for expensive TCVCXO. MT6228 achieves great MODEM
performance by utilizing 14-bit high resolution A/D Converter in the RF downlink path.
Furthermore, to reduce the need for extra external current-driving component, the
driving strength of some BPI outputs is designed to be configurable

2.1.7 Debug Function
The JTAC interface enables in-circuit debugging of software program with the
ARM7EJ-S core. With this standardized debugging interface, the MT6228 provides
developers with a wide set to options in choosing ARM development kits from different
third party vendors.

2.1.8 Power Management
The MT6228 offers various low-power features to help reduce system power
consumption. These features include Pause Mode of 32KHz clocking at Standby State,
Power Down Mode for individual peripherals, and Processor Sleep Mode. In addition,
Mt6228 is also fabricated in advanced low leakage CMOS process, hence providing an
overall ultra low leakage solution.

2.1.9 Package
The MT6228 device is offered in a 13mm x 13mm, 314-ball, 0.65mm pitch,
TFBGA package.

2.2 Platform Features

2.2.1 General
Integrated voice-band, audio-band and base-band analog front ends.
TFBGA 13mm X 13mm, 314-ball, 0.65 mm pitch package

2.2.2 MCU Subsystem

-ARM7EJ-s 32-bit RISC processor

-High performance multi-layer AMB bus

-Java hardware acceleration for fast Java-based games and applets

-Operating frequency: 26/52/104 Mhz

-Dedicated DMA bus

-14DMA channels

-1M bits on-chip SRAM

-256k bits CODE cache

-64K bits DATA cache

-On-chip boot ROM for Factory Flash programming

-Watchdog timer for system crash recovery

-3 sets of General Purpose Timer

-Circuit Switch Data coprocessor

-Division coprocessor

-PPP Framer coprocessor

2.2.3 External Memory Interface

-Supports up to 4 external devices

-Supports 8-bit or 16-bit memory components with maximum size of up to 64M byte

each

-Supports Mobile RAM, and Cellular RAM

-Supports Flash and SRAM/PSRAM with Page Mode or Burst Mode

-Industry standard Parallel LCD Interface

-Supports multi-media companion chips with 8/16 bits data width

-Flexible I/O voltage of 1.8V ~ 2.8V for memory interface

-Configurable driving strength for memory interface

2.2.4 User Interfaces

-6-row X 7-column keypad controller with hardware scanner

-Supports multiple key presses for gaming

-SIM/USIM Controller with hardware T=0/T=1 protocol control

-Real Time Clock (RTC) operating with a separate power supply

-General Purpose I/Os (GPIOs)

-2 sets of Pulse With Modulation (PWM) Output

-Alerter Output with Enhanced PWM or PDM

-8 external interrupt lines

2.2.5 Security

-Cipher : supports AES, DES/3DES

-Hash : supports MD5, SHA-1

-Supports security key and 20 bit chip unique ID

2.2.6 Connectivity

-3 UARTS with hardware flow control and speed up to 921600 bps

-IrDA modulator/demodulator with hardware framer. Supports SIR/MIR/FIR operating

speeds

-Full-speed USB 1.1 OTG capability. Supports device mode, Limited host mode, and

dual-role OTG mode.

-Multi Media card/secure Digital Memory Card/Memory stick Pro host controller with
flexible I/O voltage Power

-support SDIO interface for SDIO peripherals as well as WIFI connectivity

-DAI/PCM and 12S interface for Audio application

2.2.7 Power Management

-Power Down Mode for analog and digital circuits

-Processor Sleep Mode

-Pause Mode of 32KHZ clocking at standby state

-7 channel Auxiliary 10-bit A/D Converter for charger and battery monitoring and
photo sensing

2.2.8 Test and Debug

-Built –in digital and analog loop back modes for both Audio and Baseband Front-End

-DAI port complying with GSM Rec.11.10

-JTAG port for debugging embedded MCU

2.3 MODEM Features

2.3.1 Radio Interface and Baseband front End

-GSMK modulator with analog I and Q channel outputs

-10-bit D/A Converter for uplink baseband I and Q signal

-14-bit high resolution A/D converter for downlink baseband I and Q signal.

-Calibration mechanism of offset and gain mismatch for baseband A/D Converter and
D/A Converter

-10-bit D/A Converter for Automatic Power control.

-13-bit high resolution D/A Converter for Automatic Frequency Control

-Programmable Radio RX filter

-2 Channels Baseband Serial Interface(BSI)with 3-wire control

-Bi-directional BSI interface. RF chip resister read access with 3-wire or 4-wire
interface

-10-pin baseband Parallel Interface (BSI) with programmable driving strength
Multi-band support

2.3.2 Voice and Modem CODEC

-Dial tone generation

-Voice memo

-Noise Reduction

-Echo Suppression

-Advanced Sidetone Oscillation Reduction

-Digital sidetone generator with programmable gain

-Two programmable acoustic compensation filters

-GSM/GPRS quad vocoders for adaptive multi rate (AMR), enhanced full rate(EFR),full
rate(FR) and half rate(HR).

-GSM channel coding, equalization and A5/1 and A5/2 ciphering

-GPRS GEA1 and GEA2 ciphering

-Programmable GSM/GPRS Modem

-Packet Switched Data with CS1/CS2/CS3/CS4 coding schemes

-GSM Circuit Switch Data

-GPRS Class 12

2.3.3 Voice interface and Voice Front End

-Two microphone inputs sharing one low noise amplifier with programmable

- Gain control(AGC) mechanism.

-Voice power amplifier with programmable

-Second order Sigma-Delta A/D Converter for voice uplink path

-D/A Converter for voice downlink path

-Supports half-duplex hands-free operation

-Compliant with GSM 03.50

2.4 Multi-Media Feature

2.4.1 LCD/NAND flash Interface

-Dedicated Parallel Interface supports 3 external devices with 8/16 bit NAND flash
Interface 8/9/16/18 bit Parallel Interface, and Serial interface for LCM

-Built –in NAND Flash controller with 1-bit ECC for mass storages.

2.4.2 LCD Controller

-Supports simultaneous connection to up to 3 parallel LCD and 2 Serial LCD module

-Supports LCM format: RGB332, RGB444, RGB565, RGB666, RGB888.

-Supports LCD module with maximum resolution up to 800*600 at 24bpp.

-Per pixel alpha channel.

-True color engine

-Supports hardware display rotation.

-Capable combining display memories with up to 6 blending layers.

2.4.3 Image Signal Processor

- 8/10 bit Bayer format image input.

-Capable of processing image of size up to 3m pixels.

-Color Correction Matrix.

-Gamma Correction

-Automatic Exposure Control

-Automatic

2.4.4 Graphic Compression

-GIF Decoder

-PNG Decoder

2.4.5 JPEG Decoder

-ISO/IEC 10918-1 JPEG Baseline and Progressive modes

-Supports all possible YUV formats, including grayscale format

-Supports a;; DC/AC Huffuman table parsing

-Supports all quantization table parsing

-Supports restart interval

-supports SOS, DHT, DQT and DRI marker parsing

-IEEE Std 1180-1990 IDCT Standard Compliant

-Supports progressive image processing to minimize storage space requirement

-Supports reload-able DMA for VLD stream

2.4.6 JPEG Encoder

-ISO/IEC 10918-1 JPEG baseline mode

-ISO/IEC 10918-2 Compliance

-Supports YUV422 and YUV420 and grayscle formats

-Supports JFIF

-Standard DC and AC Huffman tables

-Provides 4 levels of encode quality

-Support continuous shooting

2.4.7 Image Data Processing

-Support Digital Zoom

-Support RGB888/565, YUV444 image processing

-High throughput hardware scaler, Capable of tailoring image to arbitrary size

-Horizontal scaling in averaging method

-Simultaneous scaling for MPEG-4 encode and LCD display

-YUV and RGB color space conversion

-Pixel format transform

-Boundary padding

-Pixel processing: hue/saturation/intensity/color adjustment, Gamma correction and
grayscale/invert/sepia-tone effects

-Hardware accelerated image editing

-Photo frame capability

-RGB thumbnail data output

2.4.8 MPEG-4/H.263 CODEC

-Hardware Video CODEC

-ISO/IEC 14496-2 simple profile:

decode @ level 0/1/2/3
encode @ level 0

-ITU-T H.263 profile 0 @ level 10

-Max decode speed is VGA @ 15fps

-Max encode speed is CIF @ 15fps

-Support VGA mode encoding

-Horizontal and Vertical De-blocking filter in video playback

-Encoder resync marker and HEC

-Supported visual tools for decoder: I-VOP, P-VOP, AC/DC prediction, 4-MV, Error

Resilience, Short Header

-Error Resilience for decoder: Slice

-Resynchronization, Data Partitioning, Reversible VLC

-Supported visual tools for encoder: I-VOP, P-VOP, Half-pel, DC prediction, -

Unrestricted MV, Reversible VLC, Short Header

-Supports encoding motion vector of range up to -64/+63.6 pixels

-HE-AAC decode support

-AAC/AMR/WB-AMR audio decode support

-AMR/WB-AMR audio encode support

2.4.9 TV-OUT

-Supports NTSC/PAL formats (interlaced mode)

-10 bit video DAC with 2x oversampling

-Support one composite video output

2.4.10 2D Accelerator

-Support 32-bpp ARGB8888 and 24bpp RGB888 and 16-bpp RGB565 and 8-bpp index

color modes

-Supports SVG Tiny

-Rectangle gradient fill

-BitBlt: muti-Bitblt with7 rotation

-Alpha blending wit 7 rotation

-Line drawing: normal line, dotted line, anti-aliasing

-Circle drawing

-Bezier curve drawing

-Triangle flat fill

-Font caching: normal font, Italic front

-Command queue with max depth of 2047

2.4.11 Audio CODEC

-Support HE-AAC codec decode

-Support AAC codec decode

-Wavetable synthesis with up to 64 tones

-Advanced wavetable synthesizer capable of generating simulated stereo

-Wavetable including GM full set of 128 instruments and 47 sets ofpercussions

-PCM Playback and Record

-Digital Audio Playback

2.4.12 Audio Interface and Audio Front End

-Supports I2S interface

-High resolution D/A Converters for Stereo Audio playback

-Stereo analog input for stereo audio source

-Analog multiplexer for Stereo Audio

-Stereo to Mono Conversion

2.5 General Description
Figure 2 details the block diagram of MT6228. Based on a dual-processor architecture,
MT6228 integrates both an ARM7EJ-S core and a digital signal processor core.
ARM7EJ-S is the main processor that is responsible for running high-level GSM/GPRS
protocol software as well as multi-media applications. The digital signal processor
handles the low-level MODEM as well as advanced audio functions. Except for some
mixed-signal circuitries, the other building blocks in MT6228 are connected to either
the microcontroller or the digital signal processor.
Specifically, MT6228 consists of the following subsystems:

-Microcontroller Unit (MCU) Subsystem - includes and ARM7EJ-S RISC processor and

its accompanying memory management and interrupt handling logics.

-Digital Sinal Processor (DSP) Subsystem - includes a DSP and its accompanying

memory, memory controller, and interrupt controller.

-MCU/DSP Interface - where the MCU and the DSP exchange hardware and software

information.

-Microcontroller Peripherals - includes all user interface modules and RF control

interface modules.

-Microcontroller Coprocessors - runs computing-intensive processes in place of

Microcontroller.

-DSP Peripherals - hardware accelerators for GSM/GPRS channel codec.

-Multi-media Subsystem - integrates several advanced accelerators to support multi-

media applications.

-Voice Front End - the data path for converting analog speech from and to digital

speech.

-Audio Front End - the data path for converting stereo audio from stereo audio source

-Video Front End - the data path for converting video signal to NTSL/PAL format.

-Baseband Front End - the data path for converting digital signal from and to analog

signal of RF modules.

-Timing Generator-generates the control signals related to the TDMA frame timing.

3. Power Management System

3.1 Features

-Handles all GSM Baseband Power Management

-2.8V to 5.5V Input Range

-Charger Input up to 15V

-Seven LDOs Optimized for Specific GSM Subsystems

-High Operation Efficiency and Low Stand-by Current

-Li-Ion and NiMH Battery Charge function

-SIM Card Interface

-Three Open-Drain Output Switches to Control the LED, Alerter and Vibrator

-Thermal Overload Protection

-Under Voltage Lock-out Protection

-Over Voltage Protection

-Power-on Reset and Start-up Timer

-48-Pin QFN Package

3.2 Applications

-GSM/GPRS Mobile Handsets

-Basic Phone and High-end Phone

3.3 General Description
The MT6305 is a power management system chip optimized for GSM handsets, especially
those based on the MediaTek MT6120 system solution. It contains seven LDOs, one to
power each of the critical GSM sub-blocks. Sophisticated controls are available for
power-up during battery charging, keypad interface, and RTC alarm. The MT6305 is
optimized for maximum battery life, featuring a ground current of only 107µA and 187µA
when the phone is in standby and operation respectively.
The MT6305 battery charger can be used with lithium ion (Li+) and nickel metal hydride
(NiMH) batteries.
The MT6305 contains three open-drain output switches for LED, alerter and vibrator
control. The SIM interface provides the level shift between SIM card and microprocessor.
The MT6305 is available in 48-pin QFN package. The operating temperature range is
from -25°C to +85°C.

3.4 Detailed Description Overview

The MT6305 is a power management chip optimized for use with GSM baseband chipsets

in handset applications. Figure 1 shows the block diagram of the MT6305.
The MT6305 contains several blocks:

-Seven Low Dropout Regulators (Core, Digital IO, Analog, Crystal Oscillator, Real­Time Clock,Memory, SIM)

-SIM Card Interface

-Vibrator, Alerter, and LED Drivers

-Power Sequence and Protection Logic

-Reset Generator

-Under voltage Lockout

-Deep Discharge Lockout

-Battery

Figure3. Function Block diagram

3.4.1 Low Dropout Regulator ( LDOs ) and Reference
The MT6305 Integrates seven LDOs that are optimized for their given functions by
balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and
output noise.

3.4.2 Digital Core LDO (Vcore)
The digital core LDO is a regulator that could source 200mA (max) with 1.8V output
voltage. It supplies the baseband circuitry in the handset. The LDO is optimized for
very low quiescent current.

3.4.3 Digital IO LDO (Vio)

The digital IO LDO is a regulator that could source 100mA (max) with 2.8V output

voltage. It supplies the baseband circuitry in the handset. The LDO is optimized for
very low quiescent current and will power up at the same time as the digital core LDO.

3.4.4 Analog LDO ( Va )

The analog LDO is a regulator that could source 150mA (max) with 2.8V output voltage.
It supplies the analog sections of the baseband chipsets. The LDO is optimized for low
frequency ripple rejection in order to reject the ripple coming from the RF power
amplifier burst frequency at 217Hz.

3.4.5 TCXO LDO (Vtcxo)

The TCXO LDO is a regulator that could source 20mA (max) with 2.8V output voltage.
It supplies the temperature compensated crystal oscillator, which needs its own ultra
low noise supply and very good ripple rejection ratio.

3.4.6 RTC LDO (Vrtc)

The RTC LDO is a regulator that could source 200µA (max) with 1.5V output voltage. It
charges up a capacitor-type backup coin cell to run the real-time clock module. The
LDO features the reverse current protection and is optimized for ultra low quiescent
current since it is always on except battery voltage below 2.5V.

3.4.7 Memory LDO (Vm)

The memory LDO is a regulator that could source 150mA (max) with 1.8V or 2.8V
output voltage selection based on the supply specs of memory chips. It supplies the
memory circuitry in the handset. The LDO is optimized for very low quiescent current
and will power up at the same time as the digital core LDO.

3.4.8 SIM LDO (Vsim)

The SIM LDO is a regulator that could source 20mA (max) with 1.8V or 3.0V output
voltage selection based on the supply specs of subscriber identity modules (SIM) card.
It supplies the SIMs in the handset. The LDO is controlled independently of the others
LDO.

3.4.9 Reference Voltage Output (Vref)

The reference voltage output is a low noise, high PSRR and high precision reference
with a guaranteed accuracy of 1.5% over temperature. It is used as system reference
in MT6305 internally. However for accurate specs of every LDO output voltage, avoid
loading the reference voltage and bypass it to GND with 100 nF minimum.

3.4.10 SIM Card Interface

The SIM card interface circuitry of MT6305 meets all ETSI and IMT-2000 SIM
interface requirements. It provides level shifting needs for low voltage GSM controller
to communicate with either 1.8V or 3V SIM
cards. All SIM cards contain a clock input, a reset input, and a bi-directional data

input/output. The clock and reset inputs to SIM cards are level shifted from the supply
of digital IO (Vio) of baseband chipset to the SIM supply (Vsim). The bi-directional data
bus is internal pull high with 20kohm resistor on the controller side and with 10kohm
resistor on the SIM side. All pins that connect to the SIM card (Vsim, SRST, SCLK, SIO)
withstand over 5kV of human body mode ESD. In order to ensure proper ESD
protection, careful board layout is required.

3.4.11 Vibrator, Alerter, LED Switches

Three built-in open-drain output switches drive the vibrator motor, alerter beeper and
LEDs in the handset. Each switch is controlled by baseband chipset with enable pins.
The switch of LED can sink 150mA to drive up to 10 LEDs simultaneously for backlight.
The switch of vibrator can sink 250mA for a vibrator motor. The switch of alerter can
sink 300mA to drive the beeper. And all the open-drain output switches are high
impedance when disable.

3.5 Power Sequence and Protection Logic
The MT6305 handles the powering ON and OFF of the handset. It is possible to start the
power on sequence in three different ways:

-Pulling PWRKEY low

-Pulling PWRBB high

-CHRIN exceeds Chr Det threshold
Pulling PWRKEY low is the normal way of turning on the handset. This will turn on Vcore,
Vio, Vm LDOs as long as the PWRKEY is held low. The Vtcxo and Va LDOs is turned on
when SRCLKEN is high. The microprocessor then starts and pulls PWRBB high after
which PWRKEY can be released. Pulling PWRBB high will also turn on the handset. This
is the case when the alarm in the RTC expires.
Applying an external supply on CHRIN will also turn the handset on. If MT6305 is in the
UVLO state, applying the adapter will not start up the LDOs.

3.5.1 Under voltage Lockout (UVLO)

The UVLO function in the MT6305 prevents startup when initial voltage of the main
battery is below the 3.2V threshold. When the battery voltage is greater than 3.2V,
the UVLO comparator trips and the threshold is reduced to 2.9V. This allows the
handset to start normally until the battery decays to below 2.9V. Once the MT6305
enters UVLO state, it draws very low quiescent current, typically 30µA. The RTC LDO
is still running until the DDLO disables it. In this mode the MT6305 draws 5µA of
quiescent current.

3.5.2 Deep Discharge Lockout (DDLO)

The DDLO in the MT6305 has two functions:

-To turn off the Vrtc LDO.

-To shut down the handset when the software fails to turn off the phone when the
battery drops below 3.0V. The DDLO will shut down the handset when the battery
falls below 2.5 V to prevent further discharge and damage to the cells.

3.5.3 Reset
The MT6305 contains a reset circuit that is active at both power-up and power-down.
The RESET pin is held low at initial power-up, and the reset delay timer is started. The
delay is set by an external capacitor on RSTCAP:

(1) At power-off, RESET will be kept low.

3.5.4 Over temperature Protection

If the die temperature of MT6305 exceeds 165°C, the MT6305 will disable all the
LDOs except the RTC LDO. Once the over temperature state is resolved, a new power
on sequence is required to enable the LDOs.

3.5.5 Battery Charger

The MT6305 battery charger can be used with Li-ion and NiMH batteries. BATUSE
pin can set MT6305 to fit the battery type. When BATUSE is set low, Li-ion battery is
used. When BATUSE is set high, then NiMH battery is used. MT6305 charges the
battery in three phases: pre-charging, constant current mode charging, and constant
voltage mode charging. Figure 2 shows the flow chart of charger behavior. The
circuitry of MT6305 combines with a PMOS transistor, diode, current-sense resistor
externally to form a simple and low cost linear charger shown in Figure 4. MT6305 is
available pulsed top-off charging algorithm by the CHRCNTL pin control from
baseband chipset.

Figure4. Battery Charger Flow chart

4. POWER AMPLIFIER FOR GSM850 / DCS1800 / PCS1900

4.1 Block Diagram and Description

The SKY77328 Power Amplifier Module (PAM) is designed in a low profile (1.2 mm),
compact form factor for quad-band cellular handsets comprising GSM850, DCS1800, and
PCS1900 operation. The PAM also supports Class 12 General Packet Radio Service (GPRS)
multi-slot operation.

The module consists of separate GSM850 PA and DCS1800/PCS1900 PA blocks,
impedance-matching circuitry for 50 Ω input and output impedances, and a Power
Amplifier Control (PAC) block with an internal current-sense resistor. The custom BiCMOS
integrated circuit provides the internal PAC function and interface circuitry. Fabricated
onto a single Gallium Arsenide (GaAs) die, one Heterojunction Bipolar Transistor (HBT) PA
block supports the GSM850 bands and the other supports the DCS1800 and PCS1900 bands.
Both PA blocks share common power supply pins to distribute current. The GaAs die, the
Silicon (Si) die, and the passive components are mounted on a multi-layer laminate
substrate. The assembly is encapsulated with plastic overmold.

RF input and output ports of the SKY77328 are internally matched to a 50 Ω load to reduce
the number of external components for a quad-band design. Extremely low leakage current
(2.5 µA, typical) of the dual PA module maximizes handset standby time. The SKY77328
also contains band-select switching circuitry to select GSM (logic 0) or DCS/PCS (logic 1)
as determined from the Band Select (BS) signal. In Figure 1 below, the BS pin selects the
PA output (DCS/PCS OUT or GSM850 OUT) and the Analog Power Control (VAPC) controls

the level of output power.

The VBATT pin connects to an internal current-sense resistor and interfaces to an
integrated power amplifier control (iPAC™) function, which is insensitive to variations in
temperature, power supply, process, and input power. The ENABLE input allows initial
turn-on of PAM circuitry to minimize battery drain.

5. EXTERNAL DEVICE PART

5.1 External memory (4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA)

5.1.1 Feature

- 1.8V power supply.

- LVCMOS compatible with multiplexed address.

- Four banks operation.

- MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

- EMRS cycle with address key programs.

- All inputs are sampled at the positive going edge of the system clock.

- Burst read single-bit write operation.

- Special Function Support.

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

-. DS (Driver Strength)

-. DPD (Deep Power Down)

- DQM for masking.

- Auto refresh.

- 64ms refresh period (8K cycle)

- Commercial Temperature Operation (-25°C ~ 70°C).

- Extended Temperature Operation (-25°C ~ 85°C).

- 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).

5.1.1 Block Diagram & Description

The K4n56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM

organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high

performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock and I/O
transactions are possible on every clock cycle. Range of operating frequencies,
programmable burst lengths and programmable latencies allow the same device to be
useful for a variety of high bandwidth and high performance memory system
applications

.

5.2 Parallel memory (128M x 8 Bit /256M x 8 Bit NAND Flash Memory)

5.2.1 Feature

• Voltage Supply

-1.8V device (9F1G08R0A): 1.65V~1.95V

-3.3V device K9F1G08U0A): 2.7 V ~3.6 V

• Organization

- Memory Cell Array : (128M + 4,096K)bit x 8bit

- Data Register : (2K + 64)bit x8bit

- Cache Register : (2K + 64)bit x8bit

• Automatic Program and Erase

- Page Program : (2K + 64)Byte

- Block Erase : (128K + 4K)Byte

• Page Read Operation

- Page Size : 2K-Byte

- Random Read : 25µs(Max.)

- Serial Access : 30ns(Min.) - 3.3v device
50ns(Min.) -1.8v device

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Cache Program Operation for High Performance Program

• Intelligent Copy-Back Operation

• Unique ID for Copyright Protection

• Package :

- K9F1G08X0A-JCB0/JIB0
63- Ball FBGA (9.5 x 12) - Pb-free Package

- K9F1G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1G08U0A-FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0A-F(WSOPI ) is the same device as
K9F1G08U0A-P(TSOP1) except package type.

- K9K2G08U1A-ICB0/IIB0
52-ULGA (12X17X0.65mm)

5.2.2 Block Diagram & Description

Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND
cell provides the most cost-effective solution for the solid state mass storage market. A
program operation can be performed in typical 200µs on the 2112-byte page and an
erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data
page can be read out at 30ns(50ns with 1.8V device) cycle time per byte. The I/O pins
serve as the ports for address and data input/output as well as command input. The on­chip write controller automates all program and erase functions including pulse repetition,
where required, and internal verification and margining of data. Even the write-intensive
systems can take advantage of the K9F1G08X0A′s extended reliability of 100K
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping­out algorithm. The K9F1G08X0A is an optimum solution for large nonvolatile storage
applications such as solid state file storage and other portable applications requiring
non-volatility.

5.3 LCD Module

5.3.1 Feature

- Display mode: Main LCD - Transmissive TN ( Twisted Nematic ) mode 262K colors
Sub LCD - Transmissive TN ( Twisted Nematic ) mode 262k colors

- LCD Driver IC: Main LCD – S6D0129 (1 chip for Gate & Source Driver )
Sub LCD – LGDP4511 (1 chip for Gate & Source Driver )

- Interface : Main LCD – 18 bit CPU interface

Sub LCD – 18 bit CPU interface

- Backlight: 4 White LED(2 way)

- Sleep, Still, Moving mode display

- Low power consumption driving ( Line Inversion )

- Mobile Phone Application

5.3.2 Block Diagram & Description

The NM220DT1 module is a Color Active Matrix Liquid Crystal Display with an Light

Emission Diode(LED) Back Light system. The matrix employs a-Si Thin Film Transistor
as the active element. It is a transmissive type display operating in the normally white
mode. This TFT-LCD has a 2.2 inch diagonally measured active display area with 240 *
RGB * 320 resolution and a 1.2 inch sub LCD diagonally measured active display area
with 128 * RGB * 128 resolution. Each pixel is divided into R,G,B dots which are
arranged in vertical stripes. Gray scale or the brightness of the dots color is determined
with a 6 bit gray scale signal for each dot, thus, presenting a palette of more than
262,144 colors.

5.4 CAMERA IMAGE SENSOR

5.4.1 Block Diagram & Description

The MT9T012 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between 6MHz and 27MHz. The
maximum pixel rate is 64 megapixels/second, corresponding to a pixel clock rate of 64
MHz. The core of the sensor is a 3-megapixel active-pixel array. The timing and
control circuitry sequences through the rows of the array, resetting and then reading
each row in turn. In the time interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is controlled by varying the time
interval between reset and readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain (providing offset correction and
gain), and then through an ADC. The output from the ADC is a 10-bit value for each
pixel in the array. The ADC output passes through a digital processing signal chain
(which provides further data path corrections and applies digital gain).
The pixel array contains optically active and light-shielded (“dark”) pixels. The dark
pixels are used to provide data for on-chip offset-correction algorithms (“black level”
control). The sensor contains a set of control and status registers that can be used to
control many aspects of the sensor behavior including the frame size, exposure and gain
setting. These registers can be accessed through a two-wire serial interface.
The output from the sensor is a Bayer pattern; alternate rows are a sequence of either
green/red pixels or blue/green pixels. The offset and gain stages of the analog signal

chain provide per-color control of the pixel data.
The control registers, timing and control and digital processing functions shown in
BLOCK DIAGRAM are partitioned into two logical parts:

• A sensor core which provides array control and data path corrections. The output of
the sensor core is a 10-bit parallel pixel data stream qualified by an output data clock
(PIXCLK), together with LINE_VALID and FRAME_VALID signals.

• Additional functionality is required to support the SMIA standard. This includes a
horizontal and vertical image scaler, a limiter, a data compressor, an output FIFO,and a
serialiser.

A flash output strobe is provided to allow an external Xenon or LED light source to
synchronize with the sensor exposure time. Additional I/O signals support the provision
of an external mechanical shutter.

SECTION2. SCHEMATIC LAYOUT

1. MAIN PART SCHEMATIC LAYOUT

1.1 BASEBAND PART

1.2 MMI PART

1.3 RF PART

2. MAIN-KEY PART SCHEMATIC LAYOUT

3. LCD

SECTION3. PCB LAYOUT

1. MAIN PCB

1.1 Location Map of Main PCB Top

1.2 Location Map of Main PCB Bottom

2. MAIN-KEY PCB

2.1 Location Map of Main KEY PCB Top

2.2 Location Map of Main KEY PCB Bottom

3. LCD PCB

SECTION4. MECHANICAL ASSEMBLY

SECTION5. ALIGNMENT PROCEDURE

1. RECOMMENDED TEST EQUIPMENT

Model No. Description Maker Remark

GSM Mobile Station

8960(5515C)

TDS 340A Oscilloscope Tektronix

FLUKE 87 Digital Multi-meter Fluke

E3631A DC Power Supply Agilent

Others Accessory

Test Set

Agilent

Interface Connector
RF Connector

2. CONNECTION OF TEST EQUIPMENT

5515C
Mobile Station

Product Service Tool

E3631A
Power Supply

PHONE

RS-232C

SP770

3. LOGIC PART TROUBLESHOOTING

3.1. Troubleshooting 1 <Power sequence>

Power O n E rro r

Is the battery

installed properly?

YES

C905 voltage is 2.8v?

YES

U950 operate

properly?

YES

Does S-Crystal (Y930)
ocillate in 32.768kHz?

YES

R824 voltage is 2.8?

YES

NO

NO

NO

NO

NO

Reinstall the battery

Check peripheral

circuitry of u900

Check C950 : 2.8V
Check peripheral
control port of U950

Check peripheral

circuitry of Y930

Check peripheral

circuitry of U820

Does U900 op erate

properly?

YES

C809 voltage is 2.8?

YES

END

NO

NO

Check peripheral

circuitry of u900

Check peripheral

circuitry of U800

3.2. Troubleshooting 2 <LCD Display/ Backlight error>

3.3. Troubleshooting 3 <Key push error >

3.4. Troubleshooting 4 <Vibrator error >

3.5. Troubleshooting 5 <MP3 Play error >

3.6. Troubleshooting 6 <Camera Preview error >

3.7. Troubleshooting 7 <FM Radio Play error>

3.8. Troubleshooting 8 <Charging error>

Charging error

Is the battery

installed properly?

YES

Is charger output

voltage correct?

YES

Can see upper 4.8V

at Q800 .3PIN?

YES

Charging normal state?

YES

END

NO

NO

NO

NO

1.Reinstall the battery

2.Check if battery
voltage is under 2.4V

Check voltage of
J600.14 pin 5~5.3V

Check Q800 and U800

Check U800 and U900

3.9. Troubleshooting 9 <Bluetooth error>

4. RF PART TROUBLESHOOTING

4.1 Troubleshooting 10 [RX path check]

4.2 Troubleshooting 11 [TX path check]

SECTION6. EQUIPMENT REPARE PROCEDURE

1. No Power On with Battery Applied

A. Power check

1. Check Battery voltage: 3.4 ~ 4.2V

2. Check to see if ZD670 cathode voltage is 3.4 ~ 4.2V

3. Check to see if C905 voltage is 2.8V

4. Check to see if Y930 clock is 32.768khz

5. Check to see if U950 works properly

6. Check to see if R824 voltage is 2.8v

7. Check to see if C809 voltage is 2.8v

2. LCD display and backlight error

A. LCD display error

1. Check to see if LCD control signal and data signal are correct

at the B to B connector (J631)

2. Check to see if B to B FPCB state is alright

3. Check to see if FPCB connecter contact is alright with J631

4. Check LCD Module state and Replace the LCD Module

B. Backlight error

1. Check the NO.1 pin signal at U510 high.

2. Check to see if L510 voltage is 3.4 ~ 4.2V

3. Replace LCD module

3. Key pushing error and LED not in operation

A. Key pushing error and LED not in operation at LCD Module

1. Check J631 connector contact is correct.

2. Check to see if the MP3/CAM dome sheet contact is correct

3. Check to see if R524 voltage is 2.8V

4. Check to see if R660/R661 voltage is 3.4V~4.2V

B. Main-Key pushing error and LED not in operation

1. Check J630 connector contact is correct.

2. Check to see if the MAIN-KEY dome sheet contact is correct

3. Check to see if the 18 pin at J630 voltage is 3.3v

4. Vibrator not in operation

1. Check to see if Gate pin voltage at Q540pin is 2.8V.

2. Check to see if Board to Board connector is correct.

3. Check the path from Q540 to vibrator

4. Check to see if there is no short between vibrator wire and mechanical parts.

5 MP3 Play not in operation

1. Check to see if NO.1 pin signal at U990 is high

2. Check to see if U990 peripheral circuit at the LCD module is correct

3. Check to see if audio path between speaker and U990 is correct.

6. Camera Play not in operation.

1. Check to see if C882 voltage is 3.3V.

2. Check to see if C651 voltage in the LCD Module is 2.8V.

3. Check to see if NO.9 pin voltage at J650 in the LCD Module is 1.8V.

4. Check to see if Camera control signal and data signal are correct

at the B to B connector (J631)

5. Check to see if the 24pin connector contact in the camera module is correct

6. Replace Camera Module

7. FM Radio Play Error

1. Check to see if the I2c_CLK/DATA signal of FM Radio is correct

2. Check to see if the C712 clock is 32.768khz

3. Check the value of L712/C718/C717 is same with FM Radio matching value at

schematic

8 Charging error

1. Check to see if the battery voltage is under 2.4 voltage

2. Check to see if the charger out voltage is 5-5.3v

9. Bluetooth error

1. Check to see if Drain pin at Q870 voltage is 2.8

2. Check to see if U700 peripheral circuit is correct

3. Check the matching value of C701/L700/L701 is same with the value at schematic

10. GSM RX/TX Power

* Check to see if Battery power is 3.8V.

* E5515C: Sector Power –85 dBm

1. Check to see if the clock of U15 is 32.768khz

2. Check to see if C315 frequency is 26Mhz

3. Check to see if the one pin signal NO1-5 is high at U16

4. Check to see if the No3 or 4 pin signal high at 130

5. Check the Antenna matching value is same with matching value at schematic

6. Check to see if the each band antenna is correct.

SECTION7. How to use Flash Tool Manual

1. Introduction

Flash Tool is an app. That downloads binary data to a target mobile phone. Installed and
Operated on a PC. The program employs the boot ROM (BROM_DLL) and Download
Agent(DA) program to download and read files on the target’s flash memory via an RS­232 connection.

2. Operating Environment

2.1 System Requirements

• OS

- Windows ME or 2000, XP for PC

• Hardware

- PC

- LT cable which is served by Skyspring & vitelcom.

3. Installation

3.1 Tool Components

Flash Tool requires four parts; Flash_tool.exe, BROM DLL, DA and scatter file.

3.1.1 Flash_Tool.exe
The Flash_Tool.exe file contains the user interface app. for Flash Tool. The UI requires
the boot ROM DLL to perform all Flash Tool operations.

3.1.2 Boot ROM DLL(brom.dll)
Brom.dll I s the kernel library for Flash_Tool.exe, charged with performing boot ROM
handshaking, DA downloading and DA handshaking.

3.1.3 Download Agent (DA)
Flash Tool downloads the DA to target’s internal SRAM and executes DA on the target.
DA handshakes with Flash Tool to perform Download. We have to use
MTK_AllInOne_DA.bin for downloading.

3.1.4 Scatter file
We need it to a download binary file.

4. Settings.

4.1 Flash Tool setting

1) Firstly, Check values of the setting in an Options menu

- Baud Rate : We can support 921600 baud rate using our LT cable

- COM Port : Set up COM port for connection between mobile phone and PC.

- Operation method : Select “NFB”

- Base band chip option : Select “Check base band chip ECO version”

2) Download Agent & Scatter-loading

- Download Agent : Select “MTK_AllInOne_DA.bin” file

- Scatter-loading : Open scatSM770.txt for downloading binary file

5. SW Downloading

1) Connect LT-cable to the PC.

2) Press the Download button

3) Connect LT-cable to the target mobile phone with power off.

4 Completion of downloading

5. Memory Formatting

1) Connect LT-cable to the PC.

2) Press the Format button, and then you can see a below picture.

3) Press OK button.

SECTION8. How to use Meta Tool Manual

1. Introduction

This document is META(Mobile Engineering Testing Architecture) for service center
note. META for service center consists of two kinds of functions.
The part for “Update parameter” is only served in this document.

2. Operating Environment

2.1 System Requirements

• OS

- Windows ME or 2000, XP for PC

• Hardware

- PC

- USB cable which is served by Skyspring & vitelcom.

3. Installation

3.1 Execute “setup.exe”

First of all let you execute “setup.exe” to start installing META.

The install shield will help you to install META step by step.

It will register “control.dll” automatically (Fig. 1 ~ 5)

Fig. 1 Please click [Next >] button.

Fig. 2 Please select a directory to install and click [Next >] button again.

Fig. 3 Please confirm installation setting and click [ Install ] button.

Fig. 4 The Installation is complete, please click [ Finish ] button.

4. Settings

4.1 META Tools setting

1) Com port setting
Select com port to use.

Fig. 5 COM port

5. How to make the back up NVRAM data (system parameters)

5.1 Connect with target

You have to connect target to PC using USB cable after all of settings is complete.

So you can see Fig. 8.

Fig. 8 Connect with target

5.2 Update parameters

You should enable to two parameters (TX IQ/IMEI/ Barcode) before back up NVRAM DB or
download NVRAM DB. And then, click “Change NVRAM DB” button to select
database_classb file for current SW version.

(Warning: You have to use database_classb file for current SW version in the phone.)

5.3 Back up NVRAM data from target

Please, click “Upload from flash” button to save NVRAM data from target as a file.

5.4 Save back up NVRAM data as a file.

Save back up NVRAM data from target as a file.

6. How to restore the back up NVRAM data into target.

6.1 Connect with target

You have to connect target to PC using USB cable after all of settings is complete.

So you can see Fig. 9.

Fig. 9 Connect with target

6.2 Update parameters

You should enable to two parameters (TX IQ/IMEI/ Barcode) before back up NVRAM DB or
download NVRAM DB. And then, click “Change NVRAM DB” button to select
database_classb file for current SW version.

(Warning: You have to use database_classb file for current SW version in the phone.)

6.3 Load from file for downloading to flash

Click “Load from file” button for downloading to flash.

6.4 Download to flash

Click “download to flash” button, and then updating parameters is complete.