SL300V Technical Manual
1. Product Specification
2. Mechanical Construction
3. Circuit Description
4. IC Information
5. Spare Part List
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Section 1 – Product Specification
Contents Page
SL300V specifications ..…...…………..…………………………………………… 1.1
Standard charger …………………………..…………………………………………. 1.4
Batteries ………………………………..…………….………………………………… 1.5
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Section 2 – Mechanical Construction
Contents Page
Disassembly ……………………………………………………………………………... 2.1
Phone disassembly …………………………..……………………………….……… ... 2.2
Phone Assembly ………………………………………………………………………… 2.6
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Section 3 – Circuit Description
Contents Page
Baseband section ……………………………………………………………………… 3.1
MT6227 ( GSM/GPRS Baseband processor ) …………..……………………… 3.1
MT6318BN ( GSM Power Management System ) ……………………………… 3.38
SL300V-2.0M ( C-MOS Camera Module ) ………………………………………… 3.42
LRS18CA( MCP ) …………………………………………..……………………….… 3.43
HY27US08121A( Nand Flash EEPROM ) ……………………………………… 3.44
RF section .................................................................................................................. 3.46
MT6120 ( RF Transceiver IC ) ……………………………………...……………… 3.46
RF3146 ( QUAD-BAND Power Amplifier Module ) …………………………. 3.49
LMSP54HA-348TEMP ( Antenna Switch Module for Tri Band ) …………… 3.51
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Section 4 – IC Information
Contents Page
Pin out for U 204 …………………………………………………………...……….….. 4.1
Pin out for U 203 …………………………………………………………...……….….. 4.2
Pin out for BAT 100 …………………………………………………………...……….. 4.3
Pin out for U 109 ……………………………………………………………...……….. 4.4
Pin out for U 150 ……………………………………………………………...……….. 4.5
Pin out for CON 103 …………………………………………………………...……….. 4.6
Pin out for U 601 …………………………………………………………...……….….. 4.7
Pin out for U 600……………………………………………………...……….……….. 4.8
Pin out for U 50…………………………………………………………...……….….. .. 4.9
Pin out for U 201…………………………………………………………...……….….. 4.10
Pin out for F 100…………………………………………………………...……….…… 4.12
Pin out for U 101…………………………………………………………...……….…… 4.13
Pin out for U 103…………………………………………………………...……….…… 4.16
Pin out for U 800 ………………………………………………………………………… 4.17
Pin out for D103, D104, D110 …………………………………………………………… 4.21
Pin out for D111 – D116 ………………………………………………………………. 4.22
Pin out for ZD102 – ZD106 …………………………………………………………… 4.23
Pin out for D102, D605 ………………………………………………………..……..... 4.24
Pin out for U200 …………………..…………………………………………………….. 4.25
Pin out for U100 ……………………………………………………………………........ 4.27
Pin out for U110 ……………………………………………………………………........ 4.38
Pin out for U106 ……………………………………………………………………........ 4.40
Pin out for U3 ………………………………………………………………………........ 4.41
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Section 5 – Spare Part List
Contents Page
SL300V Part List ………………………………………………………………………... 5.1
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Model SL300V Version V_1.0
Prepared by H/W Date 2008.05.23
Subject Technical Manual Page 1/5
SL300V Specifications
General specification Trial Band EGSM Class 4/DCS & PCS
class1 handheld cellular telephone
Type approval No. SL300V
Dimensions (mm): Including 500mAh Li-Ion battery
Weight: Including 500mAh Li-Ion battery
Display type Main LCD
Display capacity 176x220 dots, Dithering 262K color, full
Display icons Soft icons: Signal, Battery, Message
Normal operating temperature
Keyboard 24 keys comprising:
1,2,3,4,5,6,7,8,9,*,0,#
YES(SEND), NO(END/ POWER),
Navigation-Key
Standard: 92 (L) x 48 (W) x 15.3 (D)
Standard: about 80 grammes
1.9 Inch Dithering 262K TFT color
graphics display
graphical
Vibration, Alarm, Call divert & barring, ,
Broadcast
-20°C to +60°C
2 Soft-Key
including LED backlight
Shot-Key, Volume-Key(UP&DOWN)
Ring tones 30 user selectable tones and off
Battery types Standard:500mAh Li-Ion(Min)
Talk time: 500mAh Li-Ion battery 2¹ - 3² hours approximately
Standby time: 500mAh Li-Ion battery 140 hours approximately
Note²: Measured on EGSM 900 with power level 5
Note²: Measured on DCS & PCS 1900 with power level 0
Battery rapid charging time: 500mAh Li – Ion(standard)
The talk and standby times are subject to
network conditions.
1½-2 hours to >90% of full capacity
Charging Voltage 5.0V
Nominal battery voltage: 500mAh Li - Ion 3.8V
Battery charging CC and CV Mode
Antenna type Intenna Type
(subject to network implementation) 16X16,10X12,8X8 Numeral display
8x8,10x10,11x11,12x12,13x14 Roman
display
Support Phase 2 plus Feature
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64 Poly stereo sounds
Graphics and animated icons
Phone memory location (200
numbers)
Dynamic text display
Easy text input (T9)
SIM application tool kit
External interface connections RS232, USB
Number of channels EGSM:174 Channel
DCS : 374 Channel
PCS: 299 Channels
Operating frequency range - transmitter EGSM TX : 880MHz to 915MHz
DCS TX : 1710MHz to 1785MHz
PCS TX: 1850 MHz to 1910 MHz
Operating frequency range - receiver EGSM RX : 925MHz to 960MHz
DCS RX : 1805MHz to 1880MHz
PCS RX: 1930 MHz to 1990 MHz
Model SL300V Version V_1.0
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Battery Connector
Function Description
1 VBat Battery Supply Pin(Right)
2 Battery ID Battery ID Resistor Pin 10Kohm(Middle)
3 GND GND(Left)
Connector layout
Pin description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USBPWR/VCHA USB Power Input
EJ_OUT_L Cradle Audio Output
RXD Serial Interface RX
EJ_IN Cradle Enable/ Mic Input
USBPWR/VCHA USB Power Input
VBAT Battery Voltage +3.8V
VBAT Battery Voltage +3.8V
EJ_OUT_R Cradle Audio Output
TXD Serial Interface TX
GND GND
P_ON/OFF Power On/Off Pin
USBDP USB D+ Input/Output
USBDM USB D- Input/Output
USBPWR USB Power Input
Model SL300V Version V_1.0
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Standard charger
SL300V is supplied with a linear charger as standard. The charger is connected to the transceiver
through the bottom port.
Charging of the battery can only be carried out when the battery is fitted to the phone. There are no
serviceable parts within the main plug.
Input parameter Type Value Unit
Input voltage min 90 V
nom 230 V
max 264 V
Input frequency min 47 Hz
nom 50 Hz
max 63 Hz
Input current max 200 mA
Efficiency min >55 %
Output parameter Type Value Unit
Output current(CV) min 0.650 A
max 0.800 A
(CC) min 0.000 A
max 0.650 A
Output voltage(CV) min 3.0 V
max 4.9 V
(CC) min 4.9 V
max 5.3 V
Connector 14 Pin Bottom Connector
Cable length 1.9 m.
Model SL300V Version V_1.0
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Batteries
Standard Battery 500mAh Li-Ion(Min)
Type: Lithium Ion Rechargeable Battery
Capacity 25°C: 500mAh
Standby time: up to 100 hours.
Talk time (1800MHZ): 30dBm: 2.5 hours 3 hours*
Charging time: 1½-2 hours approximately to full capacity.
Charge temperature: 0 to +45°C.
Discharge temperature: -20 °C to +60°C.
Cycle life 100% cap. to 80% cap. 500 cycles.
Energy Density 344Wh/I 150Wh/kg
Dimension (W x H x L): 3.6 T x 34 W x 43 L mm.
Weight: 14.0 g.
*Operating times depend on network and usage. Variability will occur. DTX +40% (included).
Storage temperature:
Short period <1 month: -20°C to +45°C.
Long period <1 year: -20°C to +25°C.
Model SL300V Version V1.0
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Disassembly
This section covers the assembly and disassembly of SL300V phone. In order to carry out the
assembly or disassembly the following precautions should be taken:
1. A Plus screwdriver is required to remove the four retaining screws, which holds the two casings
together. Ensure that the screwdriver is narrow enough to reach the screws without causing
damage to the casing parts.
2. The phone should always be placed on a soft surface to minimise the risk of damage being
caused to the casing, window and keypad. If the PCB is to be removed, then care should be taken
not to stress or scratch the exposed LCD.
3. Observe anti-static precautions when handling the main PCB or any of its components.
4. Repairs carried out by unauthorised persons will result in the warranty on the unit becoming
void.
5. Do not use solvents to clean any of the casing parts or the LCD window.
Phone disassembly
1. Battery Cover Disassembly
A. Shove battery cover out along the direction of arrow and remove battery cover.
B. Push up battery along the direction of arrow and remove battery.
2. SIM card & TF card & caps & screws & rear cover Disassembly
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A. Remove SIM card
B. Remove TF card
C. Remove four caps and four screws. Carefully separate two covers
(front and rear)
3. Side key & Camera key & Disassembly
A. Remove side key and camera key along the arrow direction.
4. Main PCB & Main keypad & Cap IO Disassembly
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Separate Main PCB manual ASS’Y, Main keypad ASS’Y and Cap IO ASS’Y from front
cover.
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5. Front cover & Deco rail Disassembly
A. Unscrew four slide unit screws from front cover
B. Remove deco rail from front cover.
6. Slide unit & Stopper & Back cover Disassembly
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A. Remove two caps and four screws and carefully separate two covers
(top and back)
B. Unscrew six slide unit screws and remove slide unit
C. Remove slide unit
D. Pull off four stoppers from back cover
7. Lcd module & Keypad Disassembly
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A. Remove LCD manual ASS’Y from top cover.
B. Remove keypad from top cover..
8. Deocration top cover and Main window Disassembly
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A. Pull off decoration top cover from top cover
B. Pull off main window from Top cover.
Phone Assembly
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1. Top cover assembly
A. Attach the D/T decoration slide key on the top cover
B. Attach the decoration slide key by heat
C. Attach the mesh receiver on the top cover.
D. Attach the D/T decoration top cover on the top cover.
2. LCD manual ASS’Y & slide keypad ASS’Y assembly
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A. Thrust four stoppers in stopper hole.
B. Assemble the magnetic in magnetic position.
C. Assemble the slide unit with back cover.
D. Screw up six slide unit screws.
E. Attach the D/T decoration back cover.
F. Attach the decoration back cover.
3. LCD manual ASS’Y & slide keypad ASS’Y assembly
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A. Group the slide keypad ASS’Y into the top cover.
B. Group the LCD manual ASS’Y into the top cover.
C. Attach the cushion LCD on the LCD glass.
D. Attach the main window on the top cover.
E. Group the decoration top cover on the top cover.
4. Slide ASS’Y assembly
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A. Group the back cover.
B. Screw up four screws.
C. Attach the two cap screws.
5. Front cover & Deco rail Assembly
Model SL300V Version V1.0
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A. Group the front cover with Deco rail.
B. Screw up four slide unit screws.
6. Main PCB & Main keypad Assembly
Model SL300V Version V1.0
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A. Group the main keypad ASS’Y, cap IO ASS’Y and main PCB manual ASS’Y with
front cover.
7. Side key ASS’Y & Camera key ASS’Y Assembly
A. Group the side key ASS’Y and camera key ASS’Y along the arrow direction.
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9. Sim card & screw & caps & rear cover Assembly
A. Assemble the rear cover.
B. Screw up four screws and put in five caps.
C. Put the TF card and SIM card in.
10. Battery & Battery Cover Assembly
Model SL300V Version V1.0
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A. Put the battery in.
B. Put the battery in and shove battery cover in along the direction of arrow.
MODEL SL300V VERSION V_1.0
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Baseband section
This document provides a description of the baseband section of the SL300V. Most design decisions
are explained, but no detailed calculations are included. Total chip solutions(MT6227, MT6305,
MT6120) except for RF Power Amplifier(RF3146) are from Media Tek, Taiwan.
I. MT6227 ( GSM/GPRS Baseband Processor )
1. System Overview
The Revolutionary MT6227 is a leading edge single-Chip solution for GSM/GPRS mobile phones targeting
TM
the emerging applications in digital audio and video. Based on 32bit ARM7EJ-S
MT6227 not only features high performance GPRS Class 12 MODEM, but also provides comprehensive
and advanced solutions for handheld multi-media.
The Figure 1 is shown Typical Application for MT6227.
RISC processor,
Figure 1 : Typical Application for MT6227
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Figure 2 is shown the Block Diagram of MT6227 for detailly.
Figure 2 : Block Diagram of MT6227
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2. Product Description
Pin Outs
One type of Package for this product, TFBGA 13x13mm, 296balls, 0.65mm pitch package, is offerd.
Pin outs and the top view are illustrated in Figure 3,4.
Figure 3 . MT6227 Pin Out(Top View).
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-. Top and Bottom View
Top Masking Definition
Figure 4.Top and Bottom View
Figure 5. Top masking definition
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Pin Description
-. JTAG Port
-. RF Parallel Control Unit
-. RF Serial Control Unit
-. PWM Interface
-. Serial LCD/PM IC Interface
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-. Parallel LCD/Nand_Flash Interface
-. SIM Card Interface
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-. Dedicated GPIO Interface
-. Miscellaneous
-. Key Pad Interface
-. External Interrupt Interface
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-. External Memory Interface
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-. USB Interface
-. Memory Card Interface
-. UART Interface
-. Digital Audio Interface
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-. Image Sensor Interface
-. Analog Interface
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-. VCXO Interface
-. RTC Interface
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-. Supply Voltages
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-. Analog Supplies
3. Micro-Controller Unit Subsystem
Figure 6 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6227. The Subsystem
utilizes a main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus master controlling
the whole subsystem. The processor communicates with all the other on-chip modules via the two-level
system buses: AHB Bus and APB Bus. All bus transactions originate from bus masters, while salves can
only respond to requests from bus masters. Before data transfer can be established, bus master must ask for
bus ownership. This is accomplished by request-grant handshaking protocol between masters and arbiters.
Figure 6. Block Diagram of MCU in MT6227
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3.1 Processor Core
The Micro-Controller Unit subsystem in MT6227 uses the 32-bit Arm7EJ-S RISC processor that is based
on the Von Neumann architecture with a single 32-bit data bus carrying both instructions and data. The
memory interface of ARM7EJ-S is totally compliant to AMBA based bus system, which allows direct
connection to the AHB Bus.
3.2 Memory Management
The processor core of MT6227 supports only memory addressing method for instruction fetch and data
access. It manages a 32bit address space that has addressing capability up to 4GB. System RAM, System
ROM , Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space,
as depicted in Figure 7.
Figure 7. Memory Layout of MT6227
External Memory Access
To allow external access, The MT6227 outputs 26bits(A25~A0) of address line along with 8 selection
signals that correspond to associated memory blocks. This is, MT6227 can support up to 8 MCU
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addressable external components. The data width of internal system bus is fixed at 32bit wide, while the
data width of the external components can be either 8 or 16 bits.
Factory Programming
The configuration for factory programming is shown in Figure 8. Usually the factory programming host
connects with MT6227 via the UART interface. In order to have it work properly, the system should boot
up from Boot Code. That is, IBOOT should be tied to GND. The download speed can be up to 921K bps
while MCU is running at 26Mhz. After the system has reset, the Boot Code will guide the processor to run
the Factory Programming software placed in System ROM. Then, MT6227 will start and continue to poll
the UART1 port until valid information is detected. The first information received on the UART1 will be
used to configure the chip for factory programming. The Flash downloader program is then transferred in
to System RAM or external SRAM.
Figure 8. Factory Programming
3.3 Bus System
Two levels of bus hierarchy are employed in the Micro-Controller Unit Subsystem of MT6227. As depicted in
Figure5, AHB Bus and APB Bus serve as system backbone and peripheral buses, while an APB bridge connects
these two buses. Both AHB and APB Buses operate at the same clock rate as processor core.
The APB Bridge is the only bus master residing on the APB Bus. All APB slaves are mapped onto memory
block MB8 in MCU 32bit addressing space. A central address decoder is implemented inside the bridge to
generate select signals for individual peripherals. In addition, since the base address of each APB slave has been
associated with select signals, the address bus on APB will contain only the value of offset address. The base
address and data width of each peripheral are listed in below table.
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3.4 Direct Memory Access
A generic DMA controller is placed on Layer2 AHB Bus to support fast data transfer send to off-load the
processor. With this controller, specific devices on AHB or APB buses can benefit greatly from quick
completion of data movement from or to memory modules such as Internal System Ram or External Sram.
Such generic DMA Controller can also be used to connect any two devices other than memory module as
long as they can be addressed in memory space.
Figure 9. Variety data paths of DMA transfer.
3.5 Interrupt Controller
Figure 10 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller
processes all interrupt sources coming from external lines and internal MCU peripherals. Since ARM7EJ-S
core supports two levels of interrupt latency. This controller generates two request signals : FIQ for fast,
low latency interrupt request and IRQ for more general interrupts with lower priority.
Figure 10. Block Diagram of Interrupt controller.
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External Interrupt
This interrupt controller also integrates an External Interrupt controller that can support up to 4 interrupt
requests coming from external sources, the EINT0~3 and 4 wake up interrupt requests. The four external
interrupts can be used for different kind of applications, mainly for event detections : detection of hand free
connection, detection of hood opening, detection of battery charger connection.
In SL300V, The External interrupts are used for Headset detection, Charger Detection and Blue Tooth
Detection.
3.6 Internal Memory Interface
System Ram
MT6227 provides one 284Kbyte size of on-chip memory modules acting as System Ram for data access with
low latency. Such a Module is composed of three high speed synchronous SRAMs with AHB Slave interface
connected to the system backbone AHB Bus. Bank 0 and bank 1 SRAMs are 128Kbyte and Bank 2 SRAM is
28Kbyte. The synchronous SRAM operates on the same clock as the AHB Bus and is organized as 32bits wide
with 4 byte-write signals capable for byte operations. Band 0 and Band 1 SRAM macros have limited repair
capability. The yield of SRAM is improbed if the defects inside it can be repaired ur ing testing.
System ROM
The 27Kbyte System ROM is primarily used to store software program for Factory programming.. However, due
to its advantageous low latency performance, some of the timing critical codes are also placed in System ROM.
This module is composed of high-speed VIA ROM with an AHB Slave Interface connected to a system
backbone.
3.7 External Memory Interface
MT6227 incorporates a powerful and flexible memory controller, External Memory Interface, to connect with a
variety of memory components. This controller provides one generic access scheme for FLASH memory, SRAM
and PSRAM. Up to 8 memory banks can be supported simultaneously, ban 0 ~ Bank 7, with a maximum size of
64MB each.
Since mose of the Flash Memory, SRAM and PSRAm have similar ac requirements, a generic configuration
scheme to interface them is desired. This way, the software program can treat different components by simply
specifying certain predefined parameters. All these parameters are based on cycle time of system clock.
External Memory Interface of MT6227 for Asynchronous/Synchronous components.
In SL300V, ECS0# is used for External Flash Memory and ECS1# is used for External PSRAM.
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4. Microcontroller Peripherals
Microcontroller(MCU) Peripherals are devices that are under direct control of the Microcontroller. Most of the
devices are attached to the Advanced Peripheral Bus(APB) of the MCU subsystem, and serve as APB slaves.
Each MCU peripheral must be accessed as a memory-mapped I/O device: that is, the MCU or the DMA bus
master reads from or writes to the specific peripheral by issuing memory-addressed transactions.
Pulse-Width Modulation Outputs.
Two generic Pulse-Width Modulators are implemented to generate pulse sequences with programmable
frequency and duty cycle for LCD backlight or charging purpose. The duration of the PWM output signal is low
as long as the internal counter value is greater than or equal to the threshold value.
In SL300V, PWM1 is used for LCD Module Backlight Enable and PWM2 is used for Flash LED Enable.
SIM Interface
The MT6227 contains a dedicated smart card interface to allow the MCU access to the SIM Card. It can operate
via 5 terminals, using SIMVCC, SIMSEL, SIM RST, SIMCLK and SIMDATA.
The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines the
regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and
SIMCLK are used for data exchange purpose. Basically, the SIM interface acts as a half duplex asynchronous
communication port and its data format is composed of ten consecutive bits: a start bit in state Low, eight
information bits and a tenth bit used for parity checking.
In SL300V, Only 3V SIM interface is used.
Figure 11. SIM interface
Keypad Scanner
The keypad can be divided into two parts : One is the keypad interface including 7 columns and 6 rows The
other is the key detection block which provides key pressed, key released and de-bounce mechanism. Each time
the key is pressed or released, i.e. something different in the 7x6 matrix, the key detection block will sense it,
and it will start to recognize if it is a key pressed or key released event. Whenever the key status changes and is
stable, a KEYPAD IRQ will be issued. The MCU can then read the key pressed directly in KP_HI_KEY,
KP_MID_KEY and KP_LOW_KEY register.
In SL300V, The 6 Rows are used (Row0 ~Row5) and The 5 Columns are used (Col 0~3 and Col 6)
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Figure 12. Key pressed with de-bounce mechanism
General Purpose Inputs/Outputs
MT6227 offers 57 general purpose I/O pins and 5 general-purpose output pins. By setting the control registers,
MCU software can control the direction, the output value and read the input values on these pins. These GPIOs
and GPOs are multiplexed with other functionalities to reduce the pin count.
Upon hardware Reset(/SYSRST), GPIOs are all configured as inputs.
Figure 13. GPIO Block diagram.
General Purpose Timer
Three general-purpose timers are provided. The Timers are 16 bits long and run independently of each other,
although they share the same clock source. Two timers can operate in one of two modes: one-shot mode and
auto-repeat mode; the other is a free running timer. In one-shot mode, When the timer counts down and reaches
zero, it is halted. In auto-repeat mode, when the timer reaches zero, it simply resets to countdown initial value
and repeats the countdown to zero; this loop repeats until the disable signal is set to 1.
UART
The baseband chipset houses three UARTs. The UARTs provide full duplex serial communication channels
between baseband chipset and external devices.
In SL300V, UART1(URXD1, UTXD1) is used for Factory Programming and UART3(URXD3, UTXD3) is
used for Blue Tooth Programming.
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Figure 14. UART block diagram.
RX data Timeout Interrupt :
When virtual FIFO mode is disabled, RX data Timeout Interrupt is generated if all of the following apply :
1. FIFO contains at least on character.
2. The most recent character was received longer than four character periods ago(including all start, parity
and stop bit)
3. The most recent CPU read of the FIFO was longer than four character periods ago.
When virtual FIFO mode is enabled, RX Data timeout Interrupt is generated if all of the following apply:
1. FIFO is empty.
2. The most recent character was received longer than four character periods ago(including all start, parity
and stop bit)
3. The most recent CPU read of the FIFO was longer than four character periods ago
IrDA framer
IrDA framer, which is depicted in Figure 15, is implemented to reduce the CPU loading for IrDA transmission.
IrDA framer functional block can be divided into two parts : the transmitting part and the receiving part. In the
transmitter, it will perform BOFs addition, byte stuffing, the addition of 16bits FCS and EOF appendence. In the
receiving part, it will execute BOFs removal, ESC character removal, CRC checking and EOF detection. In
addition, the framer will perform 3/16 modulation and demodulation to connect to the IR transceiver. The
transmitter and receiver all need DMA channel.
Figure 15. IrDA Block Diagram.
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Read Time Clock
The Real Time Clock(RTC) module provides time and data information. The clock is based on a 32.768Khz
oscillator with an independent power supply. When the mobile handset is powered off, a dedicated regulator
supplies the RTC block. If the main battery is not present, a backup supply such as a small mercury cell battery
or a large capacitor is used. In addition to providing timing data, an alarm interrupt is generated and can be used
to power up the baseband core via the BBWAKEUP pin. Regulator interrupts corresponding to seconds, minutes,
hours and days can be generated whenever the time counter value reaches a maximum value. The Maximum
day-of-month values, which depend on the leap year condition, are stored in the RTC block.
In SL300V, Big Capacitor Battery(BAT100) is used for Backup Battery. The Charging Voltage is about 1.5V
by VRTC.
Auxiliary ADC Unit
The auxiliary ADC unit is used to monitor the status of battery and charger, identify the plugged peripheral and
perform temperature measurement. There provides 7 input channels for diversified application in this unit. There
provides 2 modes of operation : immediate mode and timer-triggered mode.
5. Microcontroller Coprocessors
Microcontroller Coprocessors are designed to run computing-intensive processes in place of the
Microcontroller(MCU). These coprocessors especially target timing critical GSM/GPRS Model processes
that require fast response and large data movement. Controls to the coprocessors are all through memory
access via the APB.
6. Multi-Media Subsystem
MT6227 is specially designed to support multi-media terminals. It integrates several hardware based
accelerators such as advanced LCD display controller, hardware JPEG encoder/decoder, hardware Image
Resizer, and MPEG4 video Codec.
In addition, MT6227 also incorporates Nand Flash, USB 1.1 Device and SD/MMC/MS/MS Pro Controllers
for mass data transfers and storages. This chapter describes those functional bocks in more details.
6.1 LCD Interface
MT6227 contains a versatile LCD controller which is optimized for multimedia applications. This
controller supports many types of LCD modules and contains a rich feature set to enhance the
functionality. These features are :
- Up to 320x240 resolution
- The internal frame buffer supports 8bpp indexed color and RGB 565 format
- Supports 8bpp(RGB332), 12bpp(RGB444), 16bpp(RGB5650, 18bit(RGB666) and 24bit(RGB888) LCD
modules
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- 4 Layers overlay with individual color depth, window size, vertical and horizontal offset, source key, alpha
value and
o
Display rotation control(90
- One Color Loop-up Tables.
For Parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 8/9/16/18
bit parallel interface to access them and 8080 type interface is supported. It can transfer the display data from
the internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
,180o,270o, mirror and mirror then 90o, 180o and 270o)
Figure 16. LCD interface block diagram.
In SL300V, The 262K color TFT LCD Module is used with Samsung Driver IC – S6D0133.
The Resolution is 176x220 dots and 1.66inch Panel from Han Star.
6.2 JPEG Decoder
To boost JPGE image processing performance, a hardware block is preferred to aid software and deal with
jpeg file as much as possible. As a result, JPEG Decoder is designed to decode all baseline and progressive
JPEG images with all YUV sampling frequencies combinations. To gain the best speed performance, JPEG
decoder will handle all portions of JPEG files except the 17 byte SOF marker. The software prog ram only needs
to program related control registers based on the SOF maker and wait for an interrupt coming from hardware.
Taking into consideration the limited size of memories, hardware also supports multiple runs of JPEG
progressive images and breakpoints insertion in huge JPGE files.
6.3 Image Resizer
This Block provides image resizing capability. It receives image data from a block-based image source such
as JPEG decoder in format of YUV color space, or a pixel-based image source such as camera in format of RGB
or YUV and performs image resizing. The first pass is coarse resizing pass and it can shrink the image by a
factor of 1, 1/4, 1/16, 1/64. The second pass is fine resizing pass and it can shrink and enlarge the image in
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fractional ratio. Refer to the Figrue9 Image resizer block diagram. The maximum size of a pixel based source
image is only 2047x2047.
Figure 17. Overview of Image Resizer.
6.4 NAND Flash interface
MT6227 provides NAND flash interface. The NAND Flash interface support features as follows.
- ECC(Hamming Code) acceleration capable of one-bit error correction or two bits error detection.
- Programmable ECC block size. Support 1.2 or 4ECC block with in a page
- Word/byte access through APB bus.
- Direct memory Access for massive data transfer..
- Latch sensitive interrupt to indicate ready state for read, program, erase operation and error report.
- Support Page size : 512(528) bytes and 2048(2112) bytes.
- Support 2 chip select for NAND flash parts.
- Support 8/16bits I/O Interface.
- Support LCD Data interface together.
- Used 7 control Signal : NRE#, NEW#,NCE#,NALE, WATCHDOG#,NCLE, NRNB.
6.5 USB Device controller
MT6219 provides a USB function interface that is in compliance with Universal Serial Bus Specification Rev
1.1. The USB device controller supports only full-speed(12Mbps) operation. The cellular phone can make use of
this widely available USB interfaces to transmit/receive data with USB host, typically PC.
The USB device uses cable-powered feature for the transceiver but only drains little curren t. An external
resistor(nominally 1.5kohm) is required to be placed across Vusb and DP Signal. Two additional external serial
resistors might be needed to be placed on the output of DP and DM signals to make the output impedance
equivalent to 28~44ohm. Also, USB cable can be used to Charger for 5V input.
The ADC4_USB is to monitor whether USB cable is inserted or not.
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Figure 20. USB Interface Circuit
6.6 Memory Stick and SD Memory Card Controller
The controller fully supports the SD Memory Card bus protocol as defined in SD Memory Card Specification
Part1 Physical Layer Specification version1.0. But SL300V is not interfaced Mini SD card but T-Flash Memory
Card. Interface Signals are same. Normally, the Detection is controlled by INS pin status. When Card is nothing,
The INS is high logically. And When Card inserted, The INS is low.
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Card Detection
Figure 21. Card Detection.
In SL300V, The INS pin is always VSS. Because T-Flash Connector does not have a Detection Pin. So, The
Detection is done by Software programming.
6.7 Camera Interface
Figure 22. Rich Image Processor
MT6227 incorporates a feature rich image signal processor to connect with a variety of image sensor
components. This processor consists of timing generated unit(TG) and Lens/Sensor compensation unit and
image process unit.
So, The Camera sensor doesn’t need the ISP block.
In SL300V, Camera Sensors can be selected by BB processor. If MT6227 is used, The Camera Module will be
used 2.0Mpixels sensor from silicon file(Noon200pc20). If MT6226M is used, The Camera Module will be
used 1.3M Sensor from Samsung(S5K4AAFA). If 2.0M sensor is used, The 2 Power supplies are used(2.8V,
1.8.V). But If 1.3M sensor is used, Dual power supply(2.8V, 1.5V) is need.
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Figure 23. Camera Sensor Interface circuit.
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7. Audio Front-End
The audio front-end essentially comprises voice and audio data paths. The whole voice band data paths are
complied with GSM03.50 specification. Furthermore, Mono hands-free audio or external FM radio playback
path are provided. The stereo audio path facilitates audio quality playback, external FM radio, and voice
playback through headset.
Figure 24. Audio Front-End Block Diagram
Figure 25 shows the block diagram of digital circuits of the audio front-end. The APB register block is an APB
peripheral to get settings from the MCU. The DSP audio port block interfaces with the DSP for control and data
communications. Besides, there is a Digital Audio Interface(DAI) block to communicate with the System
Simulator for FTA or external Bluetooth module for particular applications. The digital filter block performs
filter operations for voice band and audio band signal processing.
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Figure 25. The block diagram of the digital circuits for Audio Front-End
Stereo sound are implemented by TS4990 IC(Audio amplifier).
SL300V used single speaker. The AU_Out0_N/_P lines are for Voice Audio and AU_MOUTL/R are for Ring
Tone and Melody(Midi and MP3).
8. Radio Interface Control
This chapter details the MT6227 interface control with the radio part of a GSM terminal. Providing a
comprehensive control scheme, the MT6227 radio interface consists of Baseband Serial Interface(BSI),
Baseband Parallel Interface(BPI), Automatic Power Control(APC) and Automatic Frequency Control(AFC),
together with APC-DAC and AFC-DAC.
Baseband Serial Interface
The Baseband Serial Interface controls external radio components. A 3-wire serial bus transfers data to RF
circuitry for PLL frequency change, reception gain setting and other radio control purposes. In this unit,
BSI data registers are double-buffered in the same way as the TDMA event registers. The user writes data
into the write buffer and the data is transferred from the write buffer to the active buffer when a
TDMA_EVTVAL signal(from the TDMA timer) is pulsed.
The unit has four output pins : BSI_CLK is the output clock, BSI_DATA is the serial data port and
BSI_CS0,BSI_CS1 are the select pins for 2 external components. These outputs are connected to MT6120
Transceiver.
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Figure 26. BSI Unit block diagram and Timing Characteristic.
Baseband Parallel Interface
The Baseband Parallel Interface features a 10-pin output bus used for timing-critical control of the external
circuits. These pins are typically used to control front-end components at the specified time along the GSM timebase, such as transmit-enable(PA_EN), band switching(BANDSW_DCS), TR-switch(LB_TX, HB_TX), etc.
Figure 27. Baseband Parallel Interface Block Diagram.
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The following table is shown the used pin for RF part.
Pin Name Pin Description Description Component
BPI_BUS 0 HB_TX Switch Module DCS/PCS TX Switch Module(LMSP54HA)
BPI_BUS 1 LB_TX Switch Module GSM TX Switch Module(LMSP54HA)
BPI_BUS 2 PCS Switch Module PCS RX Switch Module(LMSP54HA)
BPI_BUS 4 PA_EN PAM Enable PAM (RF3146)
BPI_BUS 5 BANDSW_DCS Band switch for DCS PAM (RF3146)
BPI_BUS 8 BT_LDO_EN Blue Tooth Power Supply Enable BTM(CR222)
BPI_BUS 9 RFVCOEN RF VCO Enable Transceiver(MT6120)
Automatic Power Control Unit
Automatic Power Control unit is used to control the Power Amplifier module. Through APC unit, we can set the
proper transmit power level of the handset and to ensure that the burst power ramping requirements are met. In
one TDMA frame, up to 7 TDMA events can be enabled to support multi-slot transmission. In practice, 5 banks
of ramp profiles are used in one frame to make up 4 consecutive transmission slots.
The shape and magnitude of the ramp profiles are configurable to fit ramp-up, intermediate ramp, and rampdown profiles. Each bank of the ramp profile consists of 16 8-bit unsigned values, which is adjustable for
different conditions.
The entries from one bank of the ramp profile are partitioned into two parts, with 8 values in each part. In
normal operation, the entries in the left half part are multiplied by a 10-bit left scaling factor, and the entries in
the right half part are multiplied by a 10-bit right scaling factor. Those values are then truncated to form 16 10bit intermediate values. Finally the intermediate ramp profile are linearly interpolated into 32 10- bit values and
sequentially used to update to the D/A converter. The block diagram of the APC unit is shown in Figure 28.
Figure 28. Block diagram of APC unit
In SL300V, The APC Analog Signal is inputted to Power Amplifier Module through Low Pass filter
(R400,C406)
The APC Analog Signal has 32 Ramp profiles for Up Ramp and Down Ramp each 16 profiles.
The Figure 29 shown the Timing Mask for Normal VAPC.
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Figure 29. Timing Mask for normal VAPC.
Automatic Frequency Control Unit
Automatic Frequency Control unit provides the direct control of the oscillator for frequency offset and Doppler
shift compensation. The Block diagram is depicted in Figure 30. It utilizes a 13-bit D/A converter to achieve
high-resolution control. The AFC is always inputted to VCTCXO to generate 26Mhz. The Aanlog voltage is
about 1.5V and AFC_DAC is about 4200 decimally.
Figure 30. Block diagram of the AFC Controller
9. Baseband Front End
Baseband Front End is a modem interface between Tx/Rx mixed-signal modules and digital signal processor.
We can divide this block into two parts. The first is the uplink(transmitting) path, which converts bit-stream
from DSP into digital in-phase and quadrature signals for TX mixed-signal module. The second part is the
downlink(receiving) path, which receives digital in-phase and quadrature signals from RX mixed-signal module,
performs FIR filtering and then sends results to DSP. The uplink path is mainly composed of GMSK Modulator
and uplink parts of Baseband Serial Ports, and the dow nlink path is mainly composed of RX digital FIR filter
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and downlink parts of Baseband Serial Ports. Baseband Serial Ports is a serial interface used to communicate
with DSP. In addition, there is a set of control registers in Baseband Front End that is intended for control of
Tx/Rx mixed-signal modules, inclusive of calibration of DC offset and gain mismatch of downlink Analog-todigital conve
rters as well as uplink.
Figure 31. Block Diagram of Baseband Front-End
9.1 Baseband Serial Ports
Baseband Front End communicates with DSP through the sub block of Baseband Serial Ports. Baseband Serial
Ports interfaces with DSP in serial manner. It implies that DSP must be configured carefully in order to have
Baseband Serial Ports cooperate with DSP core correctly.
9.2 Downlink Path(RX Path)
On downlink path, the sub-block between RX mixed-signal module and Baseband Serial Ports is RX Path. It
mainly consists of a digital FIR filter, two sets of multiplexing paths for loopback modes, interface for RX
mixed-signal module and interface for Baseband Serial Ports.
Figure 32. Block Diagram of RX Path
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9.3 Uplink Path (TX Path)
The purpose of the uplink path inside Baseband Front End is to sink TX symbols, one bit for each symbol,
from DSP, then perform GMSK modulation on them, then perform offset cancellation on I/Q digital signals out
of GMSK modulator, and finally control TX mixed-signal module to make D/A conversion on I/Q signals out of
GMSK Modulator with offset cancellation. Accordingly, the uplink path is composed of uplink parts of
Baseband Serial Ports, GSM Encryptor, GMSK Modulator and Offset Cancellation.
Figure 33. Block Diagram of TX Path
10. Timing Generator
Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple interface for
the MCU to program all the timing-related events for receive event control, transmit event control and the timing
adjustment.
In pause mode, the 13MHz reference clock may be switched off temporarily for the purpose of power saving
and the synchronization to the base-station is maintained by using a low power 32.768KHz crystal oscillator.
The 32.768KHz oscillator is not accurate and therefore it should be calibrated prior to entering pause mode.
Figure 34. The Block Diagram of TDMA Timer.
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The Slow clocking unit is provided to maintain the synchronization to the base-station timing using a 32Khz
crystal oscillator while the 13Mhz reference clock is switched off. As shown in Figu re 35, this unit is composed
of frequency measurement unit, pause unit and clock management unit. Because of the inaccuracy of the 32Khz
oscillator, a frequency measurement unit is provided to calibrate the 32Khz crystal taking the accurate 13Mhz
source as the reference.
Figure 21. Figure 35. The Block Diagram of Slow Clocking unit.
11. Power, Clocks and Reset
This Chapter describes about the power, clock and reset management functions provided by MT6227.
Together with Power Management IC, MT6227 offers both fine and coarse resolutions of power control by
way of software programming. With this efficient method, the developer can turn on selective resources
accordingly in order to achieve optimized power consumption. The Operating modes of MT6227 as well as
main power states provided by the PMIC are shown in Figure 36.
Figure 36. Major Phone Power States and Operation Modes for MT6219 based terminal
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B2PSI
MT6227 use 3 wires B2PSI interface connected to PMIC, this bi-directional serial bus interface allows
baseband to write command to and read from PMIC. The bus protocol utilizes a 16bits proprietary format.
B2PSICK is the serial bus clock and is driven by the master. B2PSIDAT is the serial data; master or slave can
drive it. B2PSICS is the bus selection signal. Once the B2PSICS goes low, Baseband starts to transfer the 4
register bits followed by a read/write bit, then wait for 3 clocks for PMIC B2PSI state machine to decode the
Operation for the next succeeding 8 data bits. The State machine should count for 16 clocks to complete the data
transfer.
11.1 Clocks
There are two major time bases in the MT6227. For the faster one is the 13MHz clock origination from an offchip temperature-compensated voltage controlled oscillator that can be 26MHz. This signal is the input from the
SYSCLK pad then is converted to the square-wave signal. The other time base is the 32.768KHz clock
generated by an on-chip oscillator connected to an external crystal.
Figure 37. Clock distributions in the MT6227
- 32.768Khz Time Base
The 32.768Khz clock is always running. It’s mainly used as the time base of the Real Time
Clock(RTC) module, which maintains time and date with counters. In low power mode, the 13Mhz
time base is turned off, so the 32.768Khz clock shall be employed to update the critical TDMA timer
and Watchdog timer. This Time base is also used to clock the keypad Scanner logic. The C101,C102
must be tuned with Oscillator.
- 13Mhz Time Base
Two 1/2-dividers, one for MCU Clock and the other for DSP Clock, exist to allow usage of 26 or
13Mhz TXVCXO as clock input. There phase-locked loops(MPLL, DPLL and UPLL) are used to
generate three primary clocks.
MPLL : Provides the MCU System Clock.
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DPLL : Provides the DSP System Clock. DPLL can be programmed to provide 1x to 6x
output of the 13Mhz reference.
UPLL : Provides the USB System Clock.
11.2 Reset Generation Unit
Figure 38 shows reset scheme used in MT6227. There are three kinds of resets in the MT6227, i.e., hardware
reset, watchdog reset, and software resets.
Figure 38. Reset Scheme used in MT6227
- Hardware Reset
This Reset is inputted through the SYSRST# pin from PMIC(MT6305 Pin 24). The SYSRST# shall be
driven to low during power-on. The Hardware reset has a global effect on the chip. It initializes all
digital and Analog circuits except the RTC. Refer to the listed below.
- All Analog Circuits are turned off
- All PLLs are turned off and bypassed. The 13Mhz system clock is the default time base.
- Special Trap statue in GPIO.
- Watchdog Reset
A Watchdog reset is generated when the Watchdog timer expires as the MCU software failed to re-
program the timer counter in time. Hardware blocks that are affected by the watchdog reset are :
- MCU Subsystem
- DSP Subsystem
- External Component (By software program)
- Software Reset
These are local reset signals that initialize specific hardware. For example, The MCU or DSP software
may write to software reset trigger registers to reset hardware modules to their initial states, when
hardware failures are detected. The following Modules has software resets
- DSP Core
- DSP Coprocessors.
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12. Analog Front-End & Analog Blocks
To communicate with Analog blocks, a common control interface for all Analog blocks is implemented. In
addition, there are some dedicated interfaces for data transfer. The common control interface translates APB
bus write and read cycle for specific addresses related to Analog front-end control. Dedicated data interface
of each Analog block is implemented in the corresponding digital block. The Analog blocks includes the
following Analog function for complete GSM/GPRS base-band signal processing :
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II. MT6318 (GSM Power Management System)
The MT6318 is a power management system chip optimized for GSM/GPRS handsets, especially those based on
the MediaTek
MT621x/MT622x system solution. MT6318 contains 11 LDOs, one to power each of the critical GSM/GPRS
sub-blocks
Sophisticated controls are available for power-up during battery charging, for the keypad interface, and for the
RTC alarm.
The MT6318 is optimized for maximum battery life.
The 2-step RTC LDO design allows the RTC circuit to stay alive without a battery for several hours.
The MT6318 battery charger can be used with a lithium-ion (Li+) battery.
The SIM interface provides the level shift between SIM card and microprocessor.
The MT6318 is available in a 96-pin TFBGA package.
The operating temperature range is -25°C to +85°C.
The interface Features are listed below.
- Handles all GSM/GPRS Baseband Power Management
- Input range: 2.8 V ~ 5.0 V
- Charger input of up to 15 V
- 11 LDOs optimized for specific GSM/GPRS subsystems
- 2-step RTC LDO
- 600 mW Class AB audio amplifier
- Booster for series backlight LED driver
- Charge pump for parallel backlight LED driver
- SPI interface
- Pre-charge indication
- Li-ion battery charge function
- SIM card interface
- RGB LED driver
- Vcore for power-saver mode
- Over-current and thermal overload protection
- Programmable under voltage lockout protection
- Power-on reset and start-up timer
- 96-pin TFBGA package
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Figure 40. MT6318 Pin configuration.
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Figure 41. Functional Block Diagram of MT6318
1. Charger Circuit
The charger circuit in PMIC is mainly comprised of 3 sub-functions.
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Figure 42. PMIC Charger Block Diagrams
Charger Detector
The charger detector senses the charging voltage from either a standard AC-DC adaptor or a USB
connection.
When the charging input voltage is greater than the pre-determined threshold, the charging process is
triggered.
The detector resists higher input voltages than other parts of the PMIC.
Charger Control
When the charger is on, this block controls the charging phase and turns on the appropriate LDOs
according to the
battery status. The battery voltage is constantly monitored: if the voltage is greater than 4.3 V,
charging is stopped
immediately to prevent permanent damage to the battery.
Control for Pre-Charge Indication
The PMIC provides 2 control signals SEL1 and SEL2 for the application that shows pre-charge status
on the LCD. In normal cases, VBAT is selected (SEL2 turned on) as the power input to the PMIC.
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Figure 43. Charger and Voltage Detection
Figure 44. Li-Ion Battery Charging Profile
2. Low Dropout Regulator (LDOs) and Reference
The MT6318 integrates eleven LDOs that are optimized for their given functions by balancing
quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise.
1) Digital Core LDO (VD)
The digital core LDO is a regulator that sources 200 mA (max) with a 1.8 V or 1.2 V output voltage
selection
based on the supply voltage requirement of the BB chipset. The LDO also provides 1.5 V/0.9 V
power-down modes that can be controlled either by the SRCLKEN pin or by the PWR_SAVE_SPI
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MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 45/57
software register. The digital core LDO supplies the BB circuitry in the handset, and is optimized for a
very low quiescent current.
2) Digital IO LDO (VIO)
The digital IO LDO is a regulator that sources 100 mA (max) with a 2.8 V output voltage. The LDO
supplies the BB circuitry in the handset, and is optimized for a very low quiescent current. This LDO
powers up at the same time as the digital core LDO.
3) Analog LDO (VA)
The analog LDO is a regulator that sources 150 mA (max) with a 2.8 V output voltage. The LDO
supplies the analog sections of the BB chipsets and is optimized for low frequency ripple rejection in
order to reject the ripple coming from the RF power amplifier burst frequency at 217 Hz.
4) TCXO LDO (VTCXO)
The TCXO LDO is a regulator that sources 20 mA (max) with a 2.8 V output voltage. The LDO
supplies the temperature compensated crystal oscillator, which needs its own ultra low noise supply
and very good ripple rejection ratio.
5) RTC LDO (VRTC)
PMIC features a 2-step RTC that keeps RTC alive for a long time after the battery has been removed.
The 1st LDO charges a backup battery on the BAT_BACKUP pin to ~2.6 V. Also, when the battery is
removed, the first stage prevents the backup battery from leaking back to VBAT. The 2nd LDO
regulates the 2.6 V supply to a 1.5 V/1.2 V optional RTC voltage. The RTC voltage can be set by the
RTC_SEL pin while the BB is alive.
6) Memory LDO (VM)
The memory LDO is a regulator that sources 150 mA (max) with a 1.8 V or 2.8 V output voltage
selection based on the supply specs of the memory chips. The LDO supplies the memory circuitry in
the handset, and is optimized for a very low quiescent current. This LDO powers up at the same time
as the digital core LDO.
7) SIM LDO (VSIM)
The SIM LDO is a regulator that sources 20 mA (max) with a 1.8 V or 3.0 V output voltage selection
based on the
supply specs of subscriber identity module (SIM) card. The LDO supplies the SIMs in the handset, and
is controlled independently of the other LDOs.
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 46/57
8) Memory Card LDO (VMC)
The memory card LDO is a regulator that sources 250 mA (max) with a 2.8 V or 3.0 V output voltage
selection. The LDO supplies the memory card (MS, SD, MMC) in the handset, and is controlled
independently of the other LDOs.
9) Auxiliary Analog Circuit LDO (VA_SW)
The auxiliary analog circuit LDO is a regulator that sources 50 mA (max) with 2.8 V or 3.3 V output
voltage
selection based on the VA_SW_SEL register setting (Register F [7]). It can be switched on/off by
register control.
10) USB IO LDO (VUSB)
The USB IO LDO is a regulator that sources 20 mA (max) with a 3.3 V output voltage. The LDO
output on/off
follows the control bit USB_PWR (Register 1 [3]). When the USB_PWR control bit is set to off, the
VUSB output
voltage drops below 0.3 V within 1 ms. (VUSB output is shunt with a 1 μF capacitor.)
11) Vibrator LDO (VIBR)
The vibrator LDO is a regulator that sources 200 mA (max) with a 1.8 V or 3.2 V output voltage
selection based on the VIBSEL register setting (Register E [1]). This LDO can be powered on/off by
register.
12) Reference Voltage Output (VREF)
The reference voltage output is a low noise, high PSRR and high precision reference with a guaranteed
accuracy of
1.5% over temperature. The output is used as a system reference in MT6318 internally. However for
accurate specs of every LDO output voltage, avoid loading the reference voltage; only bypass it to
GND with a minimum 100 Nf capacitance.
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 47/57
Figure 45. Status of Mobile Handset and LDOs.
3. LED Drivers
PMIC provides 4 independent drivers. Three of them use an identical structure to drive 3 different
LEDs (R, G, B). The fourth is dedicated to driving the keypad LEDs. The reason for separating the
LED drivers into 2 groups is phone feature oriented.
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 48/57
Figure 46. MT6318 Circuit diagram
To Power on the handset, The Power_On_Off Signal must be Low. The external sense resistor R307 0.2ohm
can determine the charging current. The function equation is : Iconstant = 0.16/R307 = about 800mA. Iprecharging = 10/R307 = about 50mA. The LDO Bypass capacitors are recommended to use Min X5R grade.
Specially The DVDD, AVDD,VMEM and VCORE must be used 4.7uF, 2012 type.
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 49/57
III. SL300V-2.0M
( CMOS Camera Module )
SL300V-2.0M is a CMOS Camera Module which supports 2.0Mega Pixel CMOS sensor in SL300V.
CCM used the Sharp sensor which supports 1600 X 1200 UXGA format and 1/4 inch optical format.
Figure 29. Reference Circuit.
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 50/57
IV. LRS18C8A (Smart combo RAM + Nor Flash
Memory) and K9K1208U0C Nand EEPROM)
1. LRS18C8A
The LRS18C8A is a mixed multi-chip package containing a 32Mbit smart combo RAM and a 128Mbit
Flash memory. The /BYTE inputs can be used to select the optimal memory configuration. The power
supply for the LRS18C8A can range from 1.7V to 1.95V. The LRS18C8A can perform simultaneous
read/write operations on its flash memory and is available in a 107-pin BGA package making it
suitable for a variety of applications. The Boot block architecture for flash memory is a bottom boot
block. The MCP has two CE# signal for Flash.
These CE# are controlled EA23 address Pin.
Figure 30. MCP Block diagram
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 51/57
Ⅴ. HY27US08121A (Nand Flash EEPROM)
The HY27US08121A offered in 64Mx8Bit or 32Mx16bit with spare 16MBit capacity. The device is
offered 2.7 ~ 3.3v VCC. Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. A program operation allows to write the 512-byte page in typical 200us and an
eraser operation can be performed in typical 2ms on a 16kbyte or 8K word block. Data in the page can
be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input.
Figure 31. Block Diagram
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 52/57
RF section
I. MT6120 (RF Transceiver IC)
MT6120 includes LNAs, two RF quadrature mixers, an integrated channel filter, programmable gain
amplifiers(PGA), an IQ demodulator for the receiver, a precision IQ modulator with offset PLL for the
transmitter, two internal TX VCOs, a VCXO, on-chip regulators, and a fully programmable sigmadelta fractional-N synthesizer with an on-chip RF VCO.
Figure 34. MT6120 Functional block diagram
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 53/57
- Recommended Operating Range
Item Symbol Min Typ Max Unit
Power Supply Voltage(VBAT) VBAT 3.1 3.6 3.6 V
Power Supply Voltage(VCCD) VCCD 2.5 2.8 3.1 V
Operating Ambient Temperature Topr -20 25 75 C
1. Receiver
The receiver section of MT6120 includes Quad-band low noise amplifiers(LNAs), RF quadrature
mixers, an on-chip channel filter, Programmable Gain Amplifiers(PGAs), quadrature second mixers,
and a final low-pass filter. The very low-IF MT6120 uses image-rejection mixers and filters to
eliminate interference. With accurate RF quadrature signal generation and mixer matching techniques,
the image rejection of the MT6120 can reach 35dB for all bands. Compared to a direct conversion
receiver(DCR), MT6120’s very low-IF architecture improves the blocking rejection, AM suppression,
as well as the adjacent channel interference performance.
The SL300V was designed for Tri-Band(GSM900, DCS1800, PCS1900)
- Receiver Input Frequency
Mode Min Max Unit
GSM900 925 960 Mhz
DCS 1805 1880 Mhz
PCS 1930 1990 Mhz
2. Transmitter
The MT6120 transmitter section consists of two on-chip TX VCOs, buffer amplifiers, a downconverting mixer, a quadrature modulator, an Analog phase detector and a digital phase frequency
detector, each with a charge pump output and on chip loop filter. The dividers and loop filters are used
to achieve the desired IF frequency from the down-conversion mixer and quadrature modulator. For a
given transmission channel, the transmitter will select one of the two different TX reference dividing
numbers. These built-in components, along with an internal voltage controlled oscillator and a loop
filter, implement a translation loop modulator. The TX VCO output is fed to the power amplifier. A
control loop, implemented externally, is used to control the PA’s output power level.
- Transceiver Output Frequency
Mode Min Max Unit
GSM850 824 849 Mhz
GSM900 880 915 Mhz
DCS 1710 1785 Mhz
PCS 1850 1910 Mhz
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 54/57
3. TX VCO
Two power VCOs are integrated with OPLL to form a complete transmitter circuit. The TX VCO
output power is typically 9dBm with +/-2.5dB variation in EGSM bands and +8dBm output power
with +/-2dB variation in DCS1800/PCS1900 bands over extreme Temperature conditions.
The PAM(RF3146) Input range is Typically 3dBm. So 5dB Attenuator is added Between MT6120 and
RF3146. Tx VCO Frequency Range is same with Tranceiver Frequency Range.
4. Frequency Synthesizer
The MT6120 includes a frequency synthesizer with a fully integrated RF VCO to generate RX and TX
local oscillator frequencies. The PLL locks the RF VCO to a precision reference frequency at 26MHz.
To reduce the acquisition time or to enable fast settling time for multi-slot data services such as GPRS,
a digital loop along with a fast-acquisition system are implemented in the synthesizer. After the
calibration, a fast-acquisition system is utilized for a period of time to facilitate fast locking.
The frequency ranges of the synthesizer for RX mode are
RX mode GSM850 1737Mhz ~ 1788Mhz
E-GSM900 1850Mhz ~ 1920Mhz
DCS1800 1805Mhz ~ 1880Mhz
PCS1900 1930Mhz ~1990Mhz
The Calculate LO Freqnecy Fvco from RX Channel Frequency Fch is following.
Fvco = 2*Fch-200K for GSM850 and E-GSM900
Fvco = Fch-100K for DCS1800 and PCS1900.
The frequency ranges of the synthesizer for TX mode are
TX mode GSM850 1813Mhz ~ 1868Mhz
E-GSM900 1936Mhz ~ 2059Mhz
DCS1800 1881Mhz ~ 2008Mhz
PCS1900 2035Mhz ~2149Mhz
The Calculate LO Freqnecy Fvco from TX Channel Frequency Fch is following.
(set the divider ratio D1 of TX reference divider = 11)
Fvco = 2*D1*Fch/(D1-1) for GSM850 and E-GSM900
Fvco = D1*Fch/(D1-1) for DCS1800 and PCS1900.
The MT6120 uses a digital calibration technique to reduce the PLL settling time Once the RF
synthesizer is programmed through a 3-wire serial interface, the calibration loop is activated. The main
function of the calibration loop is to preset the RF VCO to the vicinity of the desired frequency
quickly and correctly, thus aiding the PLL to settle faster. On the other hand, since a large portion of
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 55/57
initial frequency error is dealt with by the integrated calibration loop, the overall locking time can be
drastically reduced, irrespective of the desired frequency.
5. Voltage Control Crystal Oscillator(VCXO)
VCXO consists of an amplifier, a buffer, and a programmable capacitor array. The VCXO provides the
MT6120 with a selectable reference frequency of either 13MHz or 26MHz. When VCXOFRQ pin is
high, Output Frequency is 26Mhz. When VCXOFRQ pin is low, Output Frequency is 13Mhz.
VCXOFRQ is High in SL300V. The Amplifier is designed to be in series resonance with a standard
26Mhz crystal. The Crystal is connected from the Input pin XAL of Amplifier to ground through a
series load capacitance. The buffer provides a typical 600mVpp voltage swing. As an alternative, the
reference frequency can be provided by an external 26Mhz VCTCXO module. When Pin VCXOCXR
is tied to the VCCVCXO supply, the XTAL pin will accept an external signal. Furthermore, the
VCXO control pin can be tied to VCCVCXO to prevent the current leakage during the sleep mode
operation.
6. Regulator
The MT6120 internal regulators provide low noise, stable, temperature and process independent
supply voltages to critical blocks in the transceiver. An internal P-channel MOSFET pass transistor is
used to achieve a low dropout voltage of less than 150mV in all regulators.
II. RF3146 ( GSM850,EGSM,DCS and PCS Power
Amplifier Module)
Figure 35. RF3146 Block Diagram
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 56/57
The RF3146 is a high-power, high-efficiency power amplifier module with integrated power control of
RFMD. The device is a self-contained 7mm*7mm*0.9mm lead frame module with 50ohm input and
output terminals. The power control function is also incorporated, eliminating the need for directional
couplers, detector diodes, power control ASICs and other power control circuitry(See figure 34) ; this
allows the module to be driven directly from the DAC output. The device is designed for use as the
final RF amplifier in EGSM900 and DCS handsets. On-board power control provides over 50dB of
control range with an Analog voltage input. The RF3146 has Max +35dBm GSM output power and
Max +33dBm DCS output power at 3.5V.
Figure 36. The Shaded area are eliminated on RF3146.
Figure 37. Diagram of the power control
Figure 38. Diagram of the Power control
SL300V TECHNICAL MANUAL
MODEL SL300V VERSION V_1.0
PREPARED BY H/W DATE 2008.05.23
SUBJECT TECHNICAL MANUAL PAGE 57/57
Most power control systems in GSM sense either forward power or collector/drain current. The
RF3146 does not use a power detector A high-speed control loop is incorporated to regulated the
collector voltage of the amplifier while the stage are held at a constant bias. The Vramp signal is
multiplied by a factor of 2.65 and the collector voltage for the second and third stages are regulated to
the multiplied Vramp voltage. The basic circuit is shown as above.
III. LMSP54HA-348TEMP
(Antenna Switch Module for Tri- Band with SAW Filter)
LMSP54HA-348TEMP is an Antenna Switch Module for GSM900, DCS1800 and PCS1900 of
Murata with Three SAW Modules.
Control Pins (VC1, VC2, VC3) are connected to LB_TX, HB_TX,PCB (signals from baseband
processor). The Control Pins Operating range is 2.4V 2.8V.
Figure 39. The Evaluation board and control logic of LMSP54HA-348TEMP
The GSM900 and DCS1800/PCS1900 input port matching impedances are 50 ohm.
The GSM900, DCS1800 and PCS1900(Balance) output port matching impedance are 150ohm.
SL300V TECHNICAL MANUAL
Model SL300V Version V_1.0
Prepared by H/W Date 2008.05.23
Subject Technical Manual Page 1/41
Pin out for U204 (LMSP54HA-348TEMP)
PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GSM900 RX1
GSM900 RX2
DCS1800 RX1
DCS1800 RX2
PCS1900 RX1
PCS1900 RX2
GND
DCS/PCS TX
VC2
GSM TX
VC1
VC3
ANT
GND
GSM900 RX1
GSM900 RX2
DCS1800 RX1
DCS1800 RX2
PCS1900 RX1
PCS1900 RX2
GND
DCS/PCS TX
VC2
GSM TX
VC1
VC3
ANT
GND
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Pin out for U203 (CSX-325T26BADT-J2E)
SL300V Technical Manual Page 2
Model SL300V Version V_1.0
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Pin out for BAT100 (SF-3R3-S104Z)
① ②
PIN NO FUNCTION NAME
1
2
VCC
Ground
VCC
GND
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Model SL300V Version V_1.0
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Pin out for U150 (DF30FC-40DS-0.4V)
SL300V Technical Manual Page 4
Model SL300V Version V_1.0
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Pin out for CN20 (SCHB1A0101)
PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
SL300V Technical Manual Page 5
MCDA2
MCDA3
MCCMO
VCC
MCCK
GROUND
MCDA0
MCDA1
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
Model SL300V Version V_1.0
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Pin out for U601 (A3212EEHLT)
PIN NO FUNCTION NAME
1
2
3
4
5
6
Output
No connection
GND
GND
No connection
Power supply
OUTPUT
NO CONNECTION
GROUND
GROUND
NO CONNECTION
SUPPLY
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Pin out for U600 (TS4990IJT)
PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
9
-IN
GROUND
BYPASS
V02
SHUTDOWN
VDD
+IN
V01
GROUND
A1
B1
C1
C2
C3
B3
A3
A2
B2
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Model SL300V Version V_1.0
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Pin out for U50 (XC6401EE20MR)
PIN NO FUNCTION NAME
1
2
3
4
5
6
ON/OFF Control 1
Power Input
ON/OFF Control 2
Output 2
Ground
Output 1
EN1
VIN
EN2
VOUT2
VSS
VOUT1
SL300V Technical Manual Page 8
Model SL300V Version V_1.0
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Pin out for U201 (RF3146)
SL300V Technical Manual Page 9
Model SL300V Version V_1.0
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PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pkg Base
Internal circuit node. Do not externally connect.
Controlled voltage input to the GSM driver stage.
Internal circuit node. Do not externally connect.
Ground (Internal)
Ground (Internal)
GSM RF Output
Ground (Internal)
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
No Internal or external connection.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Controlled voltage input to the GSM output stage.
Controlled voltage output to feed VCC2 and VCC3.
Controlled voltage output to feed VCC2 and VCC3.
Controlled voltage input to the DCS/PCS output stage.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
No Internal or external connection.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Ground (Internal)
DCS / PCS RF Output
Ground (Internal)
Internal circuit node. Do not externally connect.
Ground (Internal)
Controlled voltage input to the DCS/PCS driver stage.
No internal connection. Connect to ground.
DCS/PCS RF Input
No internal connection. Connect to ground.
Controlled voltage on the GSM and DCS/PCS preamplifier
Control to select the GSM or DCS/PCS bands.
Enable PA module
Power
Power
Internal circuit node. Do not externally connect.
Ramping signal from DAC.
Controlled voltage on the GSM preamplifier stage.
Ground for the GSM preamplifier stage.
GSM RF input
Ground
GSM 850 / 900 OUT
VCC3 DCS / PCS
DCS / PCS OUT
VCC2 DCS / PCS
VCC1 DCS / PCS
GSM 850 / 900 IN
NC
VCC2 GSM
NC
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC3 GSM
VCC OUT
VCC OUT
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
NC
GND
NC
DCS / PCS IN
NC
BAND SEL
TX ENABLE
VBATT
VBATT
NC
VRAMP
VCC1 GSM
GND1 GSM
GND
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Pin out for F100 (0467 001.NR)
SL300V Technical Manual Page 11
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Pin out for U300 (MT6318)
SL300V Technical Manual Page 12
Model SL300V Version V_1.0
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PIN NAME FUNCTION
K7
A9
G9
H9
B10
B4
K4
H3
C9
E9
E1
D1
C1
B9
D2
E2
F2
H2
G2
J7
H10
K9
H8
J9
K10
B7
F9
F1
J1, J2, J3,
D9, D10,
A8,
B8, C8, A5,
B5, C5, D5
J4
H5
K2
D3, E3, E4,
F3, F4, G3,
G4, G5, G6,
G7, H4, H6,
H7, D7, D8,
E7, E8, F7,
C3, C4, C6,
C7, D4, D6
J10
C10
K1
PWRKEY
PWRBB
SRCLKEN
SIMVCC
BAT_ON
DC_OV
VM_SEL
SEL1_EN
RTC_SEL
VD_SEL
AC
USB
V_USB
INT
GDRVUSB
GDRVAC
ISENSE
SEL1
SEL2
SIMIO
SIMRST
SIMCLK
SIO
SRST
SCLK
RSTCAP
RESET
VBAT
PWRIN
VB_OUT
ISENSE_OUT
BP/VREF
GND
VD
VIO
VA
Power on button input. Active low
Power on/off from microprocessor. Active high
VTCXO and VA enable. High = enable. Low = disable
VSIM enable. High = enable. Low = disable.
Indication that Li-ion battery is inserted
DC/DC protection input. OV threshold voltage is 1V.
External memory supply selection. 1 = 2.8V, 0 = 1.8V
Enable the “pre-charge indication” function. 1 = enable, 0 = disable.
VRTC output voltage selection. 1 = 1.5V, 0 = 1.2V
VD output voltage selection. 1 = 1.8V/1.5V, 0 = 1.2V/0.9V
AC-DC adaptor input
USB power input
3.3V USB power output
Interrupt PIN. Active low
Control output to the gate of the external p-channel FET for the USB charger.
Control output to the gate of the external p-channel FET for the AC charger.
Charger current sensing input
Control output to the gate of the external PMOS for the AC charger input
Control output to the gate of the external PMOS for the VBAT input
Non level-shifted SIM data (3V)
Non level-shifted SIM reset input (3V)
Non level-shifted SIM clock input (3V)
Level-shifted SIM data (1.8/3V)
Level-shifted SIM reset output (1.8/3V)
Level-shifted SIM clock output (1.8/3V)
Reset delay time capacitance
System reset. Low active.
Battery input voltage
Power input
Battery output voltage. Switchable.
ISENSE output voltage. Switchable.
Bandgap reference and bypass capacitance
Ground
Digital core supply
Digital IO supply
Analog supply
Auxiliary analog supply. Switchable.
SL300V Technical Manual Page 13
E10
H1
G1
K8
G10
K3
F10
A3
A4
A2
A10
J5
J6
K5
K6
B2
B1
C2
A1
B3
A7
B6
A6
F8
G8
J8
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BAT_BACKUP
Model SL300V Version V_1.0
VA_SW
VTCXO
VM
VSIM
VRTC
VMC
VIBR
C1+
C1-
C2+
AUDP
AUDN
SPK+
SPKVO_R
VO_G
VO_B
LED_KP
CS_KP
BLDRV
CS_BL
FB_BL
SPICS
SPICK
SPIDAT
TCXO supply
Memory supply
SIM supply
RTC supply
Memory card supply
Vibrator driver
Charge pump capacitor. Positive terminal.
Charge pump capacitor. Negative terminal.
DC/DC output back-up capacitor. Positive terminal.
Backup battery pin for 2-step RTC
Audio positive input
Audio negative input
Speaker positive output
Speaker negative output
R LED current driver
G LED current driver
B LED current driver
KP LED driver
KP LED current sensor
Control output to the gate of the external.
Voltage sensor input for external BL FET current
Voltage sensor input from white LED ballast resistor
Serial port select input
Serial port clock input
Serial port I/O
SL300V Technical Manual Page 14
Model SL300V Version V_1.0
Prepared by H/W Date 2008.05.23
Subject Technical Manual Page 15/41
Pin out for U302 (SI7911DN)
PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
Source 1
Gate 1
Source 2
Gate 2
Drain 2
Drain 2
Drain 1
Drain 1
S1
G1
S2
G2
D2
D2
D1
D1
SL300V Technical Manual Page 15
Model SL300V Version V_1.0
Prepared by H/W Date 2008.05.23
Subject Technical Manual Page 16/41
Pin out for U103 (SI7703EDN)
PIN NO FUNCTION NAME
1
2
3
4
5
6
7
8
Anode
Anode
Source
Gate
Drain
Drain
Cathode
Cathode
A
A
S
G
D
D
K
K
SL300V Technical Manual Page 16
Model SL300V Version V_1.0
Prepared by H/W Date 2008.05.23
Subject Technical Manual Page 17/41
Pin out for U800 (LRS18C8A)
Pin Description Type
A0 to A20 Address Inputs (Common) Input
A21, A22 Address Inputs (Flash) Input
SL300V Technical Manual Page 17
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