FLY SL300m Service Manual Circuit Description

Slide M odule

External
Memory

Interface

Key
Pad

Camera

Module

Nand Flash

Interface

Camera

Interface

(Baseb and Processor)

receiver

32.768Khz
OSC

VAFC

SYSCLK

TX I/Q
RX I/Q

VAPC

B2PSI

AuxADC

Suppl y Vol tages

Cristal

32.768
KHz

26MHz

TX

RX

MT6129

(RF Transceiver)

AMPS/GSM

DCS/PCS

VAPC

(PAM)

GSM RX

DCS RX

PCS RX

GSM TX

DCS TX

ESHS-

M090SF

Main

Mic

Bottom

Connector

HeadSet
Receiver

HeadSet

Mic

USB

UART

Charger

KEYPAD

SIM

(Power Management IC)

HB_TX
(DCS/PCS
TX Enable)

LB_TX

(GSM TX

Enable)

MODEL ESL808 VERSION V_0.01

PREPARED BY H/W DATE 20/09/2005

SUBJECT TECHNICAL MANUAL PAGE 1/32

Baseband section

This document provides a description of the baseband section of the ESL808. Most design decisions
are explained, but no detailed calculations are included. Total chip solutions(MT6219, MT6305,
MT6129) except for RF Power Amplifier(RF3146) are from Media Tek, Taiwan.

I. MT6219 ( GSM/GPRS Baseband Processor )

Figure 1. Block Diagram of MT6219

Figure 1 details the block diagram of MT6219. Based on dual-processor architecture, the major
processor of MT6219 is ARM7EJ-S, which mainly runs high-level GSM/GPRS protocol software as

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well as multi-media applications. With the other one is a digital signal processor corresponding for
handling the low-level MODEM as well as advanced audio functions. Except for some mixed-signal
circuitries, the other building blocks in MT6219 are connected to either the microcontroller or the
digital signal processor.

Figure 2. Typical Application of MT6219

1. Micro-Controller Unit Subsystem

ARM7EJ-S, plays the role of the major bus master controlling the whole subsystem. Essentially, it
communicates with all the other on-chip modules by way of system buses : AHB Bus and APB Bus.
All bus transactions originate from bus masters, while slaves can only respond requests from bus
masters. Prior to a data transfer can be established, bus master must ask for bus ownership. This is
accomplished by request-grant handshaking protocol between masters and arbiters.
Two levels of bus hierarchy are designed to provide alternatives for different performance
requirements, i.e. AHB Bus and APB Bus for system back bone and peripheral buses, respectively. To
have high performance and proper efficiency, the AHB Bus provides 32-bit data path with multiplex
scheme for bus interconnections.

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Only memory addressing method is used in MT6219 based system. All components are mapped onto
MCU 32-bit address space. A Memory Management Unit is employed to have a central decode scheme.
It generates certain selection signals for each memory-addressed modules on AHB Bus.
In order to off-load the processor core, a DMA Controller is designated to act as a master and share the
bus resources on AHB Bus to do fast data movement between modules. This controller comprises
thirteen DMA channels.
A 512KByte SRAM is provided for acting as system memory for high-speed data access. For factory
programming purpose, a Boot ROM module is used. These two modules use the same Internal
Memory Controller to connect to AHB Bus.
External Memory Interface supports both 8-bit and 16-bit devices. Since AHB Bus is 32-bit wide, all
the data transfer will be converted into several 8-bit or 16-bit cycles depending on the data width of
target device. This interface is specific to both synchronous and asynchronous components, like Flash,
SRAM and parallel LCD. This interface supports also page and burst mode type of Flash.

1.1 Processor Core

The Micro-Controller Unit Subsystem in MT6219 is built up with a 32-bit RISC core, ARM7EJ-S.
The memory interface of ARM7EJ-S is totally compliant to AMBA based bus system. Basically, it can
be connected to AHB Bus directly.

1.2 Memory Management

The processor core of MT6219 supports only memory addressing method for instruction fetch and data
access. It manages a 32-bit address space that has addressing capability up to 4GB. System RAM,
System ROM, Registers, MCU Peripherals and external components are all mapped onto such 32-bit
address space.

1.3 Bus System

Two levels of bus hierarchy are employed in constructing the Micro-Controller Unit Subsystem of
MT6219. AHB Bus and APB Bus serve for system backbone and peripheral buses, while an APB
bridge connects these two buses. Both AHB and APB Buses operate at the same clock rate as
processor core.

1.4 Direct Memory Access

A generic DMA Controller is placed on Layer2 AHB Bus to support fast data transfers, and also to
off-load the processor. With this controller, specific devices on AHB or APB buses can benefit greatly
from quickly completing data movement from or to memory module, i.e. Internal System RAM or

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External SRAM. Such Generic DMA Controller can also be used to connect any two devices other
than memory module as long as they can be addressed in memory space.

1.5 Interrupt Controller

Figure 2 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller
processes all interrupt sources coming from external lines and internal MCU peripherals. Since
ARM7EJ-S core supports two levels of interrupt latency, this controller will generate two request
signals : FIQ for fast, low latency interrupt request and IRQ for more general interrupts with lower
priority.
One and only one of the interrupt sources can be assigned to FIQ Controller and have the highest
priority in requesting timing critical service. All the others should share the same IRQ signal by
connecting them to IRQ Controller. The IRQ Controller manages up 32 interrupt lines of IRQ0 to
IRQ31 with fixed priority in descending order.

Figure 3. Block Diagram of the Interrupt Controller

1.6 Internal Memory Controller

System RAM

MT6219 provides four 64KByte size of on-chip memory modules acting as System RAM for data
access with zero latency. Such module is composed of four high speed synchronous SRAMs with
AHB Slave Interface connected to system backbone AHB Bus. The synchronous SRAM operates at
the same clock as AHB Bus and is organized as 32-bit wide with 4 byte-write signals capable for byte
operations.

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System ROM

The System ROM is primarily used to store software program for Factory Programming. However,
due to it’s advantageous zero latency performance, some of timing critical codes are also placed in this
area. This module is composed of high-speed diffusion ROM with AHB Slave Interface connected to
system backbone AHB Bus.

1.7 External Memory Interface

MT6219 incorporates a powerful and flexible memory controller, External Memory Interface, to
connect with a variety of memory components. This controller provides generic access schemes to
asynchronous/synchronous type of memory devices, such as Flash Memory and SRAM. It can
simultaneously support up to 8 memory banks with max size of 64MB each.
Refer to Figure 2. Typical Application of MT6219.

2. Microcontroller Peripherals

MCU Peripherals are devices that are under control of the Microcontroller. Most of them are attached
to the APB of the MCU subsystem, thus shall serve as APB slaves. Each MCU peripheral has to be
accessed as a memory-mapped I/O device, i.e., the MCU or the DMA bus master read or write specific
peripheral by issuing memory-addressed transactions. Refer to Figure2. Typical Application of
MT6219.

2.1 Pulse-Width Modulation Outputs

Two generic pulse-width modulators are implemented to generate pulse sequences with programmable
frequency and duty cycle for LCD backlight. The duration of the PWM output signal is Low as long as
the internal counter value is greater than or equals to the threshold value and the waveform is shown in
Figure3.

Figure 4. PWM waveform

PWM1 and PWM2 are devoted to LCM Backlight dimming function and enabling camera flash.

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2.2 Alerter

The output of Alerter has two sources : one is the enhanced pwm output signal, which is implemented
embedded in Alerter module; the other is PDM signal from DSP domain directly. The enhanced pwm
with three operation modes is implemented to generate a signal with programmable frequency and tone
volume. However the output of Alerter in ESL808 is dedicated to the enabling signal of vibrator.

2.3 SIM Interface

The MT6219 contains a dedicated smart card interface to allow the MCU access to the SIM card. It
can operate via 5 terminals, using SIMVCC, SIMSEL, SIMRST, SIMCLK and SIMDATA.

Figure 5. SIM Interface Block Diagram

The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines
the regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides,
SIMDATA and SIMCLK are used for data exchange purpose.

2.4 Keypad Scanner

The keypad can be divided into two parts : one is the keypad interface including 7columns and 6
rows ; the other is the key detection block which provides key pressed, key released and de-bounce
mechanism. Each time key pressed or key released, i.e. something different in the 7*6 matrix, the key
detection block will sense it, and it will start to recognize if it’s a key pressed or key released event.
Whenever the key status changes and is stable, a KEYPAD IRQ will be issued. The MCU can then
read the key pressed directly in registers. And this keypad can detect one or two key-pressed
simultaneously with any combination.

2.5 General Purpose Inputs/Outputs

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Figure 6. GPIO Block Diagram

MT-6219 offers 48 general-purpose I/O pins and 3 general-purpose output pins. By setting the control
registers, MCU software can control the direction, the output value and read the input values on these
pins. Besides, these GPIOs and GPOs are multiplexed with other functionalities to reduce the pin
count.

2.6 UART

The MT6219 houses three UARTs. The UARTs provide full duplex serial communication channels
between the MT6219 and external devices. However, 1st UART ports (URXD1, UTXD1) are only
available in ESL808.

2.7 Real Time Clock

The Real Time Clock module provides time and data information. It works on the 32.768KHz
oscillator (OSC60) with independent power supply. When the MS is powered off, a dedicated
regulator is used to supply the RTC block. If the main battery is not present, the backup supply such as
a small mercury cell battery or a large capacitor is used. In addition to provide timing data, alarm
interrupt is generated and it can be used to power up the baseband core through the BBWAKEUP pin.
Also, regulator interrupts corresponding to the seconds, minutes, hours and days can be generated
whenever the time counter value reaches a maximum.

2.8 Auxiliary ADC Unit

The auxiliary ADC unit is used to monitor the status of battery and charger, identify the plugged
peripheral, and perform temperature measurement.
ADC0 and ADC1 : current sensing
ADC2 : battery temperature
ADC3 : charging voltage
ADC5 : detecting ear microphone.

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2.9 Irda Framer

Irda Framer functional block can be divided into twp parts : The transmitting part and the receiving
part. In the transmitter, It will perform BOFs addition, byte stuffing, the addition of 16-bits FCS and
EOF appendence. In the receiving part, it will execute BOFs removal, ESC character removal, CRC
checking and EOF detection. In addition, the framer will pwerform 3/16 modulation and
demodulation to connect to the IR transceiver. The transmitter and receiver all need DMA channel.

Figure 7. Irda Framer Functional Block

3. Microcontroller Coprocessors

Microcontroller Coprocessors are designed to run computing-intensive processes in place of MCU.
Those coprocessors intend to offer a solution special for timing critical GSM/GPRS Modem processes
that require fast response and massive data movement. Controls to the coprocessors are all through
memory access by way of APB Bus.

4. Multi-Media Subsystem

MT6219 is specially designed to support multi-media terminals. It integrates several hardware
based accelerators such as advanced LCD display controller, hardware JPEG encoder/decoder,
hardware Image Resizer and MPEG4 video CODEC. In addition, MT6219 also incorporates
NAND Flash, USB 1.1 Device and SD/MMC/MS pro controllers for Mass data transfers and
storages.

4.1 LCD Interface

A specific LCD controller is implemented to allow MCU to access external LCD module by dedicated
Parallel Interface(NLD00:NLD07) and to improve data throughput for color LCD applications. LCM
is 1.8 inch, 260K colors TFT and 176x220 resolutions.

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Figure 8. LCD Interface Block Diagram

4.2 JPEG Decoder

To boost JPEG image processing performance, a hardware block is preferred to aid software and deal
with JPEG file as much as possible. As a result, JPEG Decoder is designed to decode all baseline and
progressive JPEG images with all YUV sampling frequencies combinations.

4.3 JPEG Encoder

The Hardware JPEG Encoder implements the baseline mode of Standard ISO/IEC 10918-1. It
supports YUV422 format for color pictures and greyscale format. For hardware reduction, it uses
stardard DC and AC Juffman tables for both the luminance and chrominance components. To adjust
the picure compression ratio and picture quality, there are 4 levels of quantization that can be
programmed. After initialization by software, the hardware JPEG encoder can generate the entire
compressed file.

4.4 Image Resizer

This Block provides image resizing capability. It receives image data from a block-based image
source such as JPEG decoder in format of YUV color space, or a pixel-based image source such as
camera in format of RGB or YUV and performs image resizing. The first pass is coarse resizing pass
and it can shrink the image by a factor of 1, 1/4, 1/16, 1/64. The second pass is fine resizing pass and it
can shrink and enlarge the image in fractional ratio. Refer to the Figrue9 Image resizer block diagram.
The maximum isze of a pixel based source image is only 2047x2047.

ESL808 TECHNICAL MANUAL