FLY S1160, S1190 Schematics 2
S1160 Service Manual
Summary: My windows, My world S1160—Lucid new window, good view of world. Lucid
new window shows incoming calls and messages with flap folded. To answer the call or not is
up to you; Advanced RF technology, power signal; Adopt military RF technology from
European jets. Unique powerful ability of communication without dead angle; Wonderful DIY
rings can bring you stage of personalities and the compile fair-sounding music through the
keyboard shows your initiative and talent; Unique hands free function, giving owner more
freedom, when engaging in work, Bird S1160 is the best choice to free your hands from holding
mobile phone. Just slight push on button; Fun game, more choices in leisure time, internal fun
game makes you more relax in your spare time.
Keywords: Streamlined, delicate and round, slim and lovely; transparent, advance, meticulous
1. Performance
1.1 H/W Features
Item Feature Comment
Dimensions 86*46*20.5mm
Weight 85g(including battery)
Battery Type 550mAh Li-Ion
Ring MINI rings 25 Embedded Tones
Type of LCD TN B&W(112*64)
Call time 1.5-2h
Recharge time 1.5-2h
Stand-by time 50—120h
SIM card type Plug-In SIM 3V
LCD Indicator Green
Keypad Indicator Green
Number key: 10 Shortcut key: 3
Keypad
Internal Phone Book 200
Internal SMS Memory 10
Redial List / Notebook 10
Answer Auto/any Key Answer
Games Embedded Yes 2
Free hands Yes
Navigation Key: 3 Side key:0
Confirm Key: 2 #/* Key
Depends on the
network conditions
Table 1-1 H/W Features of S288
1.2 Technical Specification
Item Description Specification
GSM TX：（890~915Mhz）
RX：（935~960Mhz）
1
2
Frequency Band
Phase Error
3 Frequency Error < 0.1 ppm
4
Level Power Toler. Level Power Toler
10 23dBm
11 21dBm
Power Level
12 19dBm
Level Power Toler. Level Power Toler
Output RF Spectrum
(due to modulation)
Offset from Carrier (kHz). Max. dBc
EGSM TX：（880~890Mhz）
RX：（925~935Mhz）
DCS TX：（1710~1785Mhz）
RX：（1805~1880Mhz）
RMS < 5 degrees
Peak < 20 degrees
GSM, EGSM
5 33dBm
6 31dBm
7 29dBm
8 27dBm
9 25dBm
±2dBm
±3dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
13 17dBm
14 15 dBm
15 13 dBm
16 11 dBm
17 9 dBm
18 7 dBm
19 5 dBm
DCS1800
0 30dBm
1 28dBm
2 26dBm
3 24dBm
4 22dBm
5 20dBm
6 18dBm
7 16dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
±2dBm
8 14dBm
9 12dBm
10 10dBm
11 8dBm
12 6dBm
13 4dBm
14 2dBm
GSM, EGSM
100
200
250
400
＋0.5
－30
－33
－60
600～1200 －60
1200～1800
-60
±2dBm
±3dBm
±3dBm
±5dBm
±5dBm
±5dBm
±5dBm
±2dBm
±3dBm
±3dBm
±5dBm
±5dBm
±5dBm
±5dBm
Output RF Spectrum
5
(due to switching transient)
6 Bit Error Ratio
7 RX Level Report Accuracy
8 SLR
9 Sending Response
10 RLR
11 Receiving Response
1800～3000 －63
3000～6000 －65
>=6000 -71
DCS
Offset from Carrier (kHz). Max. dBc
100
200
250
400
＋0.5
－30
－33
－60
600～1200 －60
1200～1800
-60
1800～3000 －65
3000～6000 －65
>=6000 -73
Offset from Carrier (kHz). Max. ( dBm )
400
600
1200
1800
－23
－26
－32
－36
GSM，EGSM，DCS
BER (Class II) < 2.439% @-102 dBm
±3dB
8±3dB
Frequency (Hz) Max.(dB) Min.(dB)
100
－12
/
200 0 /
300 0
1000 0
2000 4
3000 4
3400 4
－12
－6
－6
－6
－9
4000 0 /
2±3dB
Frequency (Hz) Max.(dB) Min.(dB)
100
－12
/
200 0 /
300 2
1000 *
2000 0
3000 2
－7
－5
－5
－5
3400 2
4000 2
Mean that Adopt a straight line in between 300 Hz
and 1,000 Hz to be Max. level in the range.
2. BB Brief and Trouble Shooting
2.1 Power On Signal Flow Chart
ULYSEE
MN301
－10
OMEGA
MN201
MANAGE
MN401
32.768KHZ
FLASH
MN303
MIC
PC201
SIM READER
J102
CHARGE IC
Q401
JACK
J103
Figure 2-1 Distribution of Baseband Hardware
2.2 Technical Brief
2.2.1 ULYSEE (MN301)
HERCROM 200G2C035 is a chip implementing
the digital base-band processes of a GSM/GPRS
mobile phone. This chip combines a DSP
sub-chip (LEAD2 CPU) with its program and
data memories, a Micro-Controller core with
emulation facilities (ARM7TDMIE), internal
8Kb of Boot ROM memory, 4M bit SRAM
memory, a clock squarer cell, several compiled
single-port or 2-ports RAM and CMOS gates.
The application of this circuit is the management
of the GSM/GPRS base-band processes through
the GSM layer 1, 2 and 3 protocols as described
in the ETSI standard with a specific attention to
the power consumption in both GSM dedicated
and idle modes, and GPRS (class 12) capability. HERCROM200G1 architecture is based on
two processor cores ARM7 and LEAD2 using the generic TI RHEA bus standard as interface
with their associated application peripherals. ULYSEE block diagram is shown in Fig 2-3.
Figure 2-3 ULYSEE Internal Architecture
A14
A1 P1
Figure 2-2
ULYSEE device pin configuration is shown in Table 2-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A GND D14 VRMEM
B GND RWL D15 D11 D8 VRMEM D0
C FLASH1 D12 D7 D5
D VRMEM D13 D9 D3 D1
VDD
E
HERC
F GND A1 FDPL BHE ONOFFL VDDPLL
G VRMEM A4 A5 A3 A2
H A6 A8 A7 A9 A10 TSPDI DA ENIOTA EN
OEL BLE D10 D6 D2
VDD
HERC
D4 GND
RXIR
_IRDA
TX_
IRDA
RX_
IRDA
RTS_
MODEM
RX_
MODEM
TX_
MODEM
CTS_
MODEM
DSR_
MODEM
TMS NEMU1 VDDANG GND CLKTCXO GND
GND VRIO VCXOEN VSSO
TCLK EMU0*
TDO CLK32K
TDI BSCAN*
SIM
RST3
VDDHERC OSC32K
PWRON
VRIO
HORUS
NRES
CLK
IOTA
CS
OSC32K
VDDRTC VDDRTC
SIMCLK3 VSDIO3
SIMIO3 GND
_OUT
_IN
IT
WAKEUP
GND
J A11 A12 A13 A14 A18
K GND A16 A15 A17 C2 R1 DOMIW DAIRST BDX
L A19 A20 IRQ4 C3 DAIOUT BFSX PUPLO2 RXON VRIO
VDD
M
HERC
N IBOOT* RSLCD C1 VRIO R4 UDX GND CSLCD DAICLK VCK VDX
P FIQL GND
GND EXTIT
RESET
LCD
SIM
_RNW
GND C4 R3
C5 R2 UDR MCUEN0 DIUW DAIIN BDR TXON VFS VREG
VDD
HERC
CKMIW GND ARMCLK BFSR GND VDR
MCLK CLK
CLKX
_SPI
TX
VDD
HERC
Table 2-1 ULYSEE DEVICE Pin Configuration (TOP VIEW)
ULYSEE device pin description is shown in Table 2-2.
Pin nb Pin name Description I/O
MICRO_WIRE INTERFACE: 5 pins.
M9 DIUM Data In IN
K8 DOMIW Data Out OUT
P9 CRMIW Serial Clock OUT
L9 SCS0 Not Connect
N9 CSLCD LCD Select OUT
UART 16C750 INTERFACE (UART_IRDA): 5 pins
D8 RX_IRDA Receive Data IN
C8 TX_IRDA Transmit Data OUT
A8 RXIR_IRDA Not Application
C7 TXIR_IRDA Not Connect
B8 SD_IRDA Not Connect
UART 16C750 INTERFACE (UART_MODEM): 5 pins
A9 RXDI Receive Data IN
B9 TXDI Transmit Data OUT
D9 DSR_MODEM Not Application
E8 RTS_MODEM Request To Send OUT
C9 CTS_MODEM Data Set Ready IN
ARM MEMORY INTERFACE: 4 9 pins.
A (20:1) FLASH Address Bus Out OUT
D (15:0) FLASH Data Bus IN/OUT
CS (4:1) Not Connect
C2 FLASH 1 FLASH Select OUT
B2 RW FLASH Memory Read (no write) signal. OUT
F5 BHE OUT
E4 BLE
Ext RAM1/RAM2 Chip Select.
OUT
E2 OEL Flash Output Enable For Standby Mode.. OUT
F4 FDP Flash Deep Low-power OUT
E3 FWE Not Connect
TPU PARALLEL PORT: 12 pins.
TSPACT (11:0)
Synchronous Activation Signal (GSM bit accuracy)
OUT
TPU SERIAL PORT: 7 pins.
G12 TSPEN (3:0) Configurable Enable Triggers
OUT
(Edge/level, pos/neg)
H11 TSPDO Output Serial Data. OUT
J14 CLK Transfer Serial Clock OUT
H10 TSPDI Not Application
ARM SERIAL PORT: 5 pins.
N7 UDX Input Serial Data. IN
M7 UDR Output Serial Data. OUT
L8 MCUEN (2) Not Connect
P8 MCUEN (1) Not Connect
M8 MCUEN0 Configurable Enable Triggers
OUT
(edge/level, positive/negative)
JTAG PORT: 7 pins.
B10 TCLK Test Clock. IN
E9 TMS Test Mode Select. IN
C10 TDO Test Data Output. OUT
D10 TDI Test Data Input. IN
D11 NBSCAN Boundary-scan Selection IN
E10 NEMU1 Test Emulation pin 1. IN/OUT
B11 NEMU0 Test Emulation pin 0. IN/OUT
MISCELLANEOUS: 11 pins.
D12 NRESPWRON Chip Power-On Reset IN
N (2) NRESET_OUT Not Connect
M2 IDDQ Not Application
E13 CLKTCXO VCTXO Input Clock (=13MHz). IN
F12 CLKIOTA CLKM Output Clock (=13MHz). OUT
C13 OSC32K_IN Input Component Signal of 32KHz Quartz. IN
B13 OSC32K_OUT Output Component Signal of 32KHz Quartz. OUT
C12 CLK32K 32KHz Oscillator Square Waveform Output OUT
M3 EXT_IT External Interrupt For ARM IN
P1 FIQL Fast External Interrupt For ARM IN
P11 ARMCLK Not Application
POWER MANAGEMENT: 4 pins.
B14 ITWAKEUP Wake-up Interrupt of Real Time Clock. OUT
A12 VCXOEN External TCXO Enable OUT
A13 PFEN Not Connect
F10 ONOFF Regulators Activity IN
VOICE BAND INTERFACE: 4 pins.
M13 VFS Transmit/Receive Synchrony. IN
N13 VDX Receive Data. IN
P14 VDR Transmit Data. OUT
N12 VCK Transmit/Receive Clock. IN
MCSI INTERFACE: 4 pins.
L10 DAIOUT Not Application
M10 DAIIN Not Application
N10 DAICLK Not Application
K9 DAIRST Not Application
BASE BAND INTERFACE: 6 pins.
L11 BFSX Receive Synchrony. IN
P11 BCLKR Not Application
K10 BDX Receive Data. IN
M11 BDR Transmit Data. OUT
N11 BCLKX Not Connect
P12 BFSR Transmit Synchrony. OUT
SIM INTERFACE: 5 pins.
G10 SIMRST3 SIM Reset. OUT
F13 SIMCLK3 Output Clock. OUT
G13 SIMIO3 Input Output Signal. IN/OUT
F14 VSDIO3 Power Control. OUT
G11 VRIO Card Presence Detection IN
Table 2-2 ULYSEE DEVICE Pin Description
2.2.2 OMEGA (MN201)
The TWL3014 device includes a complete set of
baseband functions that perform the interface and
A10
processing of the following voice signals, the
baseband in-phase (I) and quadrature (Q) signals,
which support both the single-slot and multi-slot
mode, associated auxiliary RF control features,
supply voltage regulation, battery charging control
and switch ON/OFF system analysis. The TWL3014
device interfaces with the DBB device through a
A1
K1
digital baseband serial port (BSP) and a voice band
serial port (VSP). The signal ports communicate
with a DSP core (LEAD). A microcontroller serial
Figure 2-4
port (USP) communicates with the microcontroller
core and a time serial port (TSP) communicates with the time processing unit (TPU) for
real-time control. OMEGA BLOCK DIAGRAM is shown as in Fig 2-5.
Figure 2–5 TWL3014 Functional Block Diagram
This section provides the terminal descriptions for the TWL3014 device. Fig 2–6 shows the
signal assigned to each terminal in the package. Table 2–3 shows the terminal functions for the
TWL3014 device.
Figure 2-5. TWL3014 Device Pin Figuration (TOP VIEW)
Figure2-6 signal assigned of OMEGA
PIN nb PIN name Description I/O
B6 CTN Monitoring ADC Input 1 and Battery Temperature
I/O
Current Source
A6 NC Not Connect
C7 NC Not Connect
C6 VMES Monitoring ADC Input I
J4 AFC Automatic Frequency Control DAC Output O
K4 APC Automatic Power Control DAC Output O
G7 AUXIN Auxiliary Speech Signal Input I
K10 AUXON Auxiliary Speech Signal Output (–) O
K9 AUXOP Auxiliary Speech Signal Output (+) O
F10 IRX In-phase Input (I–) Baseband Codec Downlink I
F9 IR In-phase Input (I+) Baseband Codec Downlink I
E9 QRX Quadrature Input (Q–) Baseband Codec Downlink I
E10 QR Quadrature Input (Q+) Baseband Codec Downlink I
J3 BDR Baseband Serial Port Receive Data I
J2 BDX Baseband Serial Port Transmit Data O
H3 BFSR Baseband Serial Port Receive Frame Synchronization I
K2 BFSX Baseband Serial Port Transmit Frame Synchronization O
D10 ITX In-phase Output (I–) Baseband Codec Uplink O
D9 IT In-phase Output (I+) Baseband Codec Uplink O
C9 QTX Quadrature Output (Q–) Baseband Codec Uplink O
C10 QT Quadrature Output (Q+) Baseband Codec Uplink O
E4 CLKIOTA 13-MHz Master Clock Input and BSP/TSP/USP Clock I
E2 CLK32K 32-kHz Clock Input I
H4 NC Not Connect
F4 SIMCLK3 SIM Card Shifters Clock Input I
E5 SIMIO3 SIM Card Shifters Data I/O
G4 SIMRST3 SIM Card Shifters Reset Input I
J10 EARN Earphone Amplifier Output (–) O
J9 EARP Earphone Amplifier Output (+) O
G10 GND Ground
G6 GND Ground
A3 GND Ground
B9 GND Ground
A9 GND Ground
K8 NC Not Connect
K7 NC Not Connect
H9 NC Not Connect
B7 IBIAS Bias Current Reference Resistor (100 kΩ) I/O
D6 NC Not Connect
H6 FIQL Fast Interrupt / Test Pad 1 (Default is INT1) I/O
E6 ITIOTA Microcontroller Interrupt / Test Pad 2 (Default is INT2) I/O
D2 ITWAKEUP Real-time Wake-up Input I
B8 NC Not Connect
B10 LEDB1 Connected to LEDB2
A10 LEDB2 Connected to LEDB1
C8 NC Not Connect
J8 NC Not Connect
H7 MICPIOTA Microphone Amplifier Input (–) I
J7 MICNIO Microphone Amplifier Input (+) I
E3 ONOFFL Digital Baseband Reset (@ each switch on) O
B5 NC No Connect
F8 OUIL On Button Input I
A7 REFGND Reference Voltage Ground I/O
D3 NRESPWON Digital Baseband Power-on Reset (First Battery Plug) O
F7 RPWRC Remote Power-on (other than button) I
C4 SIMCLK SIM Card Shifters Clock Output (1.8 V/3 V) O
B3 SIMIO SIM Card Shifters Data I/O
D4 SIMRST SIM Card Shifters Reset Output O
D8 TCLK Scan Test Clock I
D7 TDIIOTA Scan Path Input I
E7 TDOIOTA Scan Path Output O
G3 DA Time Serial Port Input I
H1 ENIOTA Time Serial Port Enable I
J6 TEST3 Special Test I/O Terminals I/O
F6 TEST4 Special Test I/O Terminals I/O
H8 NC Not Connect
G8 NC Not Connect
E8 TMS JTAG Test Mode Select I
K5 UDR Microcontroller Serial Port Receive Data I
J5 UDX Microcontroller Serial Port Transmit Data O
K6 MCUENO Microcontroller Serial Port Enable I
C2 UPR Uninterrupted Power Rail Output O
E1 VBACKUP Backup Battery Input I/O
A4 VBAT Battery Voltage Sense Input I/O
C5 VBAT Battery Voltage Sense
G9 VBAT Input of Voltage Regulator VRABB I/O
D5 NC Not Connect I
K1 VBAT Input of Voltage Regulator VRDBB I/O
A5 GND Ground
A2 VBAT Input 1 of Voltage Regulators VRIO and VRSIM I/O
A1 VBAT Input 2 of Voltage Regulators VRIO and VRSIM I/O
K3 VCK Voiceband Serial Port Clock O
G2 VBAT Input of Voltage Regulator VRMEM I/O
F2 VBAT Input of Voltage Regulator VRRAM I/O
F5 VDR Voiceband Serial Port Receive Data I
H5 VDX Voiceband Serial Port Transmit Data O
G5 VFS Voiceband Serial Port Frame Synchronization O
F3 VLMEM Select Output Voltage of VRMEM I
C3 VLRTC Select Output Voltage of VRRTC and VRDBB I
H10 VRABB Voltage Regulator VRABB Output O
J1 VRDBBIOTA Voltage Regulator VRDBB Output O
A8 NC Not Connect I/O
B2 VRIOIOTA Voltage Regulator VRIO Output O
B1 VRIOIOTA Voltage Regulator VRIO Output O
G1 VRMEM Voltage Regulator VRMEM Output O
F1 VRRAM Not Application O
D1 VDDRTC Voltage Regulator VRRTC Output O
B4 SIMVCC Voltage Regulator VRSIM Output O
H2 VRDBBIOTA Voltage Regulator VRDBB Input Feedback I
C1 NC Not Connect
Table 2-3 TWL3014 Pin Descriptions
The TWL3014 voltage regulation block consists of seven sub blocks. Several low-dropout (LDO)
regulators perform linear voltage regulation. These regulators supply power to internal analog and
digital circuits, to the DBB processor, and to external memory. TABLE 2-4 shown OMEGA volt
supply and descriptions. Fig 2-7 shown the test points of OMEGA supply.
Power supply Test point Supply to TEST POINT
VRDBBIOTA C208
VDDHERC C307
VDDPLLHERC C303
VDDRTC C217, C305
VDDRTC Q402, 2#
VDDRTC C305
VRMEM C215
VDDANGHERC C312
VRIOIOTA C220
VRIO
R315
R302
VRRAM
No Application
VRABB
Table 2-4 OMEGA voltage supply and descriptions
The first LDO (VRDBBIOTA) is a programmable regulator that generates the supply voltage
(1.5V) for the core of the DBB processor and inside PLL circuit
The second LDO (VDDRTC) is a programmable regulator that generates the supply voltage (1.6V)
for the 32-kHz oscillator located in the DBB device. Meanwhile supply to Q402, 2# logic high for
OMEGA transmit digital baseband power-on reset to Power IC. The main or backup battery
supplies VDDRTC.
The third LDO (VRMEM) is a programmable regulator that generates the supply voltages (2.8V)
for external memories (typically flash memories) and DBB memory interface I/Os.
(
)
(
)
The fourth LDO (VRIOIOTA) generates the supply voltage (2.8V) for the digital core, analog
functions and I/Os of the TWL3014 device.
The fifth LDO (VRSIM) is programmable regulator that generates the supply voltages (2.9V) for
SIM card and SIM card drivers.
The sixth LDO (VRRAM) and the seventh LDO (VRABB) is not application in S1160.
VDDRTC
(Q402,2#)
VRIOIOTA
(C220)
VDDRTC
(C217)
VDDRTC
(C305)
VDDANGHERC
C312
VRDBBIOTA
(C208)
VRMEM
C215
VDDHERC
(C307)
VRIO
VDDPLLHERC
(C303)
Figure 2-7 Test point of OMEGA supply
2.2.3 Manager IC (MN401)
HORUS is a chip implementing the analog base-band processes
of a GSM/GPRS mobile phone peripheral circuit. HORUS
A1
A10
integrates power management (battery and charger) functions,
audio functions, power I/Os, radio interface I/Os and others
facilities tailored and adapted to SAGEM mobile phones
specific architecture. Fig 2–9 shows the signal assigned to
each terminal in the package. Table 2-5 shown the device
pins description.
K1
Figure 2-8
Figure 2-7.
.
Figure 2-9 HORUS Terminal Assignments
PIN nb PIN name Description I/0
POWER MANAGEMENT
VBAT Power supply source I
GND
Power supply ground
A5 VMHV VBACKUP and ALIMLCD control O
B5 VBACKUP Backup area supply I/O
C4 ALIMLCD LCD interface supply O
D1 VCAPP Filter Output O
E1 VCAPN Filter Input I
E3 P5V6 Voltage doubler output O
J5 P5V6 Interior RADIO LDO supply O
F1 CHARGEUR Charger measurement bridge I
G8 VB Charge control device base current control O
G9 PCHAR Charge control shunt regulator supply I
H8 RESETHORUS Reset input/output I/O
H10 VSAUV Power management and low power modes supply O
J5 P5V6 Interior RADIO LDO input I
K5 P4V5 MIC Bias voltage O
K7 VCRADIO RF supply O
K9 VPLL Radio VCO supply O
RADIO INTERFACE
B6 TX TX radio control input I
D6 BSW Band radio control input I
H6 SWANT3 Radio switch control O
J6 SWANT4 Radio switch control O
REFERENCES
J10 CREF Integrated reference output (external filtering) O
K2 VBIAS Reference current resistor pin Current
output
K10 Vfuse/Tes Fuse prog. I/O I/O
AUDIO
C9 GMICP Audio converter negative input I
D8 AAUX2 Auxiliary audio path negative input to power amplifier I
D9 AAUX1 Auxiliary audio path positive input to power amplifier I
E6 ARX2 Main power audio path negative input to power
I
amplifier
E7 ARX1 Main power audio path positive input to power
I
amplifier
E8 AUXIN Audio converter positive output O
E10 EARP Power Audio amp. high/mean power positive output O
F10 HPN Power Audio amp. high power negative output O
F7 Cbp Power audio amp. bypass capacitor O
G10 LPHPN Power Audio amp. mean power amp. Negative output O
POWER I/O
F3 BACKLCD LCD Backlight current source output Open-drain O
G1 BACKKEY KEY Backlight current source output Open-drain O
G3 Cmdvib Vibrator current source output Open-drain O
H2 VCRADIO RF supply Open-drain O
H4 CTN CTN current source detect O
SERIAL INTERFACE
A7 CKMIW Serial interface clock input I
B8 DIUM Serial interface data output (ULYSEE) O
C7 VCBB General purpose I/O I/O
C8 DOMIW Serial interface data input I
D7 CSHORUS Serial interface chip-select I
NC N
d
F2 ITHORUS CPU interrupt O
ECO MODE (CLOCKS)
A6 OSCBF 32k digital square wave output O
A8 VCXOEN Radio VCO supply control digital input I
A9 CLK13MHOR
US
K8 CLKVCXO 13MHz analog clock input from VCO to low swing
MEASURMENT
A10 VMES Measurement bridges output O
2.2.4 FLASH (MN303)
The Am29DL161D is 16megabit, 2.8 volt flash memory
devices. The device is designed to be programmed in-system
with the 2.8 volt Vcc supply by OMEGA (MN201)
Table 2-5 Manager IC Terminal Functions
13MHz square wave output O
I
trigger
H1 A1
A6
Figure 2-10
A1–A20 20 Addresses
D0–D14 15 Data Inputs/Outputs
D15 Data Input/Output, word mode
FLASH1 Chip Enable
OE* Output Enable
RWL Write Enable
WP# Hardware Write Protect
FDPL Hardware Reset Pin, Active Low
VRMEN 3.0 volt-only single power supply
GND Device Ground
ot Connecte
Table 2-6 FLASH Device Pins Description
Figure 2-11 FLASH Terminal Assignments
2.3 ULYSEE to OMEGA connections
ULYSEE OMEGA
Pin name Pin nb Pin name Pin nb
TSP Serial Interface
DA H11 DA G3
ENIOTA H13 ENIOTA H1
RIF/BSP Serial Interface
BFSX L11 BFSX K2
BDX K10 BDX J2
BFSR P12 BFSR H3
BDR M11 BDR J3
ARM SPI/USP Serial Interface
UDX N7 UDX J5
UDR M7 UDR K5
MCUENO M8 MCUENO K6
LEAD SPI/VSP
VCK N12 VCK K3
VDR P14 VDR F5
VDX N13 VDX H5
VFS M13 VFS G5
SIM Interface
SIMCLK3 F13 SIMCLK3 F4
SIMIO3 G13 SIMIO3 E5
SIMRST3 G10 SIMRST3 G4
JTAG Interface
TDOCALYPSO C10 TDIIOTA D7
TMS E9 TMS E8
TCLK B10 TCLK D8
TDICALYPSO D10
TDOIOTA E7
CLOCKS
CLK32K C12 CLK32K E2
CLKIOTA F12 CLKIOTA E4
INTERRUPTS
EXTIT M3 ITIOTA E6
FIQL P1 FIQL H6
POWER MGMT
ITWAKEUP B14 ITWAKEUP D2
ONOFFL F10 ONOFFL E3
NRESPWRON D12 NRESPWRON D3
POWER SUPPLIES
VDDHERC
E1 J1
VRDBBIOTA
M1
P7
N14 H2
B12
A5
VDD-RTC D14 VRRTC D1
VDD-RTC D13 VRRTC D1
VRMEN
D1 G1
VRMEM
G1
B6
A4
N5 VRIO
VRIOIOTA
B1
L14
VDDS2 A11
B2
VDDPLL F11 VRDBBIOTA J1
VDDANG E11 VRIOIOTA B1
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