Fly FS404 Schematic
[1,2,3,4,5,8]
VIO18_PMU
1uF
C126
If double-sided SMT, put C405 & C406 below BB.
If single-sided SMT, put C405 & C406 around memory.
[4]
VIO_EMI
1.8V IO for DDR1
1.2V IO for DDR2
C131
100nF
C130
100nF
C124
100nF
VMC_PMU
[3]
Based on your system level
design , if better FM performance
is needed on your system ,
please refer to FM desense
performance enhance proposal
C121
100nF
VIO28_PMU
[3,5,7,8]
Close to BB IC, recommand < 150mil
1uF
C117
[1,3]
VPROC_PMU
120mil
TO:MT6323_B12
TO:MT6323_C12
GND
VPROC_PMU
Vproc remote sense :
differential 4mil with good shielding, from the BB to PMIC
[1,3]
[2,3,4,5,6,7,8]
C10310uF
C10210uF
C10610uF
C111
4.7uF
2.2uF(0402)
C137
2.2uF(0402)
C136
1uF
C119
1uF
C134
4mil - defferential - GND shielding
1uF
C120
1uF
C135
RLC0201
100NF
C116
RLC0201
100NF
C118
RLC0201
100NF
C115
RLC0201
100NF
C114
W9
W12
W14
VCCIO_EMI
VCCIO_EMI
VCC
U100-B
100nF
W16
W19
VCCIO_EMI
VCCIO_EMI
Memory
GND
AC21
AB11
C108
VCCIO_EMI
GND
GND
AF13
[3,5]
VTCXO_PMU
GND
AD11
GND
AC8
AB5
AA1
DVDD18_MC0
Peripheral
DVDD
GND
GND
GND
W26
AB14
[1,2,3,4,5,8]
VIO18_PMU
L3
K20
DVDD18_CAM
DVDD18_VIO_1
GND
GND
T15
W23
H13
AB24
J19
DVDD18_LCD
DVDD18_VIO_3
DVDD18_VIO_2
GND
GNDG3GND
GND
T14
K21
AF26
[1,2,3,4,5,8]
VIO18_PMU
100nF
K24
P6
W24
P7
C10
T7
VCCK_CPU
VCCK_CPUP8VCCK_CPUP9VCCK_CPUR6VCCK_CPUR7VCCK_CPUR8VCCK_CPUR9VCCK_CPUT6VCCK_CPU
GND
L15
DVDD3_LCD
GNDM5GND
L16
DVDD28_BPI
GND
GND
M11
M12
VCCK_CPU
CPU
VCC
GND
GND
GND
GND
GNDN8GNDN9GND
GND
GND
GND
M13
GND
M14
M15
M16
N10
N11
N12
N13
N14
Based on your system level design
GND
N15
1. use RTP
DVDD3_MC1
GND
GND
GND
L11
L12
L14
C128
J9
J15
K11
K14
K15
M9
T8
VCCK
VCCKK6VCCKK7VCCKK8VCCKK9VCCK
VCCK
VCCK
VCCK
VCCK
VCCK_CPUT9VCCK_CPUU6VCCK_CPUU7VCCK_CPU
Core
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N16
N22
P10
P11
P12
P13
P14
P15
P16
R10
AVDD18_AP = ext. 1.8V LDO
cap = 0.1uF
2. use AUXADC, no RTP
AVDD18_AP = VIO18
cap = 0.1uF (NC)
3. no use AUXADC, no RTP
GND
R11
R12
R13
R14
R15
R16
T10
T11
T12
T13
AVDD18_AP = VIO18
cap = none (share with C112)
K16
K17
M10
VCCK
VCCK
VCCKJ8VCCK
GND
GND
AF1
U10
K12
GND
L17
VCCKM6VCCKM7VCCKM8VCCK
L6
J10
J11
J14
T16
T17
J16
J17
U12
U13
U14
U15
U16
M17
R17
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
VCCK
DUMMY
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
A26
L7
U17
VCCKL8VCCKL9VCCK
VCCK
GND
GND
GND
U11
V13
W11
Y21
cap Close to BB IC
E5
F1
AVDD28_DAC
U100-H
DVDD18_MIPIRX
DVSS18_MIPIRX
T25
U25
cap Close to BB IC
VIO18_PMU
[1,2,3,4,5,8]
U9
AVDD18_AP
R25
DVDD18_PLLGP
DVDD18_MIPITX
DVSS18_MIPITX
P25
100nF
A1
D3
AVSS18_MDA4AVSS18_MDC3AVSS18_MDE2AVSS18_MD
AVDD18_MD
AVDD18_USB
AVDD33_USB
H23
G24
G23
VUSB_PMU
VIO18_PMU
[3]
[1,2,3,4,5,8]
C112
AVSS33_USB
1uF
BG
REFPG6REFN
F6
0.1uF
C113
C104
100nF
C101
100nF
C107
100nF
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
C109
dedicate VSS ball, must return to cap then to main GND:
1. REFN(G6) => C109
2. DVSS18_MIPIRX(U25) => C107
3. DVSS18_MIPITX(P25) => C101
6572M
6572A/X
WCDMA: 6572A/W
6572A/F
GSM: 6572A/E
~
~
TPLED5
TPLED1
TPLED2
TPLED3
VIO18_PMU
[1,2,3,4,5,8]
R213 NC
reserve for JTAG debug
U100-D
AUD_DAT_MISOK5AUD_CLK_MOSIK1AUD_DAT_MOSIH4SRCLKENA
J1
AUD_MISO
[3]
SIM1_SCLK
[2,3]
PMIC_SPI_CSN
PMIC_SPI_MOSIL5PMIC_SPI_MISOL4PMIC_SPI_SCKG2WATCHDOGJ2EINTXH5SIM1_SCLKM3SIM1_SIOJ5SIM2_SCLKM1SIM2_SIO
K2
L2
SRCLKENA
WATCHDOG
PMIC_SPI_CS
PMIC_SPI_SCK
PMIC_SPI_MISO
[3]
[3]
[3] PMIC_SPI_MOSI
[3,4]
[3,4]
EINT_PMIC
[3,5]
[3]
AUD_MOSI
[3]
[3] AUD_CLK
JTAG : 20K
Normal : NC
Reserve R footprint
SIM1_SIO
SIM2_SIO
SIM2_SCLK
[3]
[2,3]SIM1_SCLK
[3]
[3]
for JTAG debugging
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
U100-E
D12
E12
PWM_A
PWM_B
PWM
SYSTEM
CLK32K_ING4TESTMODE
CLK26M
H2
E1
CLK1_BB
CLK32K_BB
[3]
[5]
N2
N3
LPD16N1LPD17
LPD15P2LPD14N4LPD13R2LPD12N5LPD11R1LPD10
Parallel
LCD
SYSRSTB
M2
RESETB
[3]
FSOURCE
AC24
BC 1.1
CHD_DP
J26
CHD_DP
[3]
P5
T2
LPD6T5LPD5U2LPD4T3LPD3U5LPD2T4LPD1V2LPD0
LPD9T1LPD8R5LPD7
i2C
USB 2.0
USB_DM
USB_DP
CHD_DM
USB_VRT
G26
G25
J25
H25
USB_VRT
5.1K 1%
R2
CHD_DM
[3]
90-ohm differential
USB_DP
USB_DM
close to BB
[7]
[7]
KCOL2
MT6572 support JTAG from below :
1. KP (recommand)
2. MC1
3. CAM
[8]
[8]
[8]GPIO59_LRSTB
LPTE
G_SENSOR_INT
AC26
AB26
AD25
AA22
LPTE
LRSTB
LPCE0B
SPI
SCL_0
SDA_0
SCL_1
SDA_1
SPI_MOSI
SPI_MISO
C25
C26
B24
B23
F25
F23
F24
SDA_0
SCL_1
SCL_0
SDA_1
[2,8]
[2,8]
[2,8]
[2,8]
[2]
for JTAG pin out from MC1/CAM, refer
to HW design notice
[7,8]
[2]
[8]
[8]
KCOL0
KROW0
KCOL2
KROW1
[8]
[8]
R77
R79
R75
GPIO57_CTP_RSTB
GPIO58_FLASH_SEL
LPRDB
SPI_SCK
AB23
E23
LPA0
SPI_CS
1K
1K
1K
AC25
B25
A24
B26
A25
D24
C24
E25
LPWRB
KROW0
KROW1
KROW2
KCOL2
KCOL1
KCOL0
UTXD1
KP
UART
ADC
T-flash
AUX_IN0B6AUX_IN1B5AUX_IN3_YPC4AUX_IN4_XMA5AUX_IN5_YM
MC1_CMD
MC1_CK
MC1_DAT0
MC1_DAT3
MC1_DAT2
MC1_DAT1
B7
K23
L21
K22
L26
M25
M22
MC1CK
MC1CMD
MC1DAT0
MC1DAT1
MC1DAT3
MC1DAT2
[7]
[7]
[7]
[7]
[7]
[7]
E26
D25
URXD1
C5
F26
UTXD2
URXD2
AUX_IN2_XP
VIO18_PMU
[1,2,3,4,5,8]
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
VCAMD_IO_PMU
[3,8]
Power by CTP, MEMS sensor
R207 2.2K
R206 2.2K
SDA_1
SCL_1
[2,8]
[2,8]
Power by CAM_IO
R205 2.2K
R204 2.2K
SDA_0
SCL_0
[2,8]
[2,8]
2.8V
[5]
[5]
[5]
[5]
[5]
[5]
[8]
[5]
[7]
EINT0_HP
WG_GGE_PA_ENABLE
W_HB_V2
W_PA_H_EN
W_PA_L_EN
ASM_VCTRL_B
ASM_VCTRL_A
ASM_VCTRL_C
11 are 2G+3G mode both
GPIO134
4 and 10
BPI0
BPI5~9 and 12~14 are 3G mode only
(suggest BPI5~9 = 1.8V)
B12
B11
C12
A11
D11
C11
A13
A10
B10
D10
BPI_BUS0
BPI_BUS1
BPI_BUS2
BPI_BUS3
BPI_BUS4
BPI_BUS5
BPI_BUS6
BPI_BUS7
BPI_BUS8
4
U100-A
DL_I_NC1DL_Q_NB1DL_Q_PD2DL_I_PA2UL_I_PB2UL_I_NB3UL_Q_NB4UL_Q_P
C2
1.8V
[8]GPIO144_FLASH_EN
[8]
[8]
[5]
[5]
[5]
BSI-A_DAT2
BSI-A_DAT1
EINT8_CTP
EINT4_ALPXS
W_HB_V1
D7
E9
D6
E7
E8
BPI_BUS9
BPI_BUS15
BPI_BUS10C7BSI_DATA1
BSI_DATA2
BPI_BUS14
BPI_BUS11B9BPI_BUS12B8BPI_BUS13
VM0A7VM1D5TXBPIF2APCF3VBIAS
A8
[5]
[5]
[5]
BSI-A_EN
BSI-A_CK
BSI-A_DAT0
Must be sure BPI_BUS4 & 5 is under
0.2*VDD28_BPI during booting
(please refer to HW design notice V0.4)
F11
F9
G11
BSI_EN
BSI_CLK
BSI_DATA0
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
[8]
[8]
[8]
[8]
[8]
[8]
CMHSYNC
CMDAT6
CMDAT7
CMVSYNC
CMPCLK
CMMCLK
V23
V24
W25
V25
Y22
Y23
RCP_A
RCN_A
RDP1_A
RDN1_A
CMMCLK
CMPCLK
Parallel 8-bit
U100-G
MIPI_2nd_CAM
CMPDN2
CMRST2
CMPDN
L25
K25
H22
CMRST2
CMPDN2
GPIO_CMPDN
[8]
[8]
[8]
CMRST
J22
GPIO_CMRST
[8]
MIPI_CAM
RDN0
R24
R23
MIPI_RDN0
MIPI_RDP0
[8]
RDN1
RDP0
R22
MIPI_RDN1
[8]
[8]
RCN
RDP1
R26
R21
MIPI_RCN
MIPI_RDP1
[8]
[8]
RCP
T26
MIPI_RCP
[8]
Based on your system level design , if better
desense performance is needed on your
system , please refer to desense
performance enhance proposal
[8]
[8]
[8]
[8]
[8]
[8]CMDAT1
CMDAT4
CMDAT5
CMDAT0
CMDAT2
CMDAT3
U21
U22
Y26
Y25
AA25
AB25
RDP0_A
RDN0_A
CMDAT3
CMDAT2
CMDAT1
CMDAT0
MIPI_LCD
TDP0
TDN1
TDN0
TDP1
TCN
TCP
TDP2
TDN2
P20
N25
P19
N26
N20
N19
P24
P23
MIPI_TDP0
MIPI_TDN0
MIPI_TCN
MIPI_TCP
MIPI_TDN1
MIPI_TDP1
[8]
[8]
[8]
[8]
[8]
[8]
100-ohm differential
VRT
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
P26
R202 1.5K 1%
close to BB
100-ohm differential
1. All MIPI port can NOT as Output function
2. MIPI group function is mutually exclusive with Input function
(please refer to HW design notice V0.5)
VM1
VM0
TXBPI
[5]
[5]
RX_I_P
[5]
RX_I_N
[5]
RX_Q_P
[5]
RX_Q_N
[5]
TX_I_P
[5]
TX_I_N
[5]
TX_Q_P
[5]
TX_Q_N
[5]
[5]
WG_GGE_PA_VRAMP
[5]
[7]
[7]
[7]
[7]
AU_HSN
AU_SPKN
AU_SPKP
AU_HSP
H1
K1
G1
SPK_PL1SPK_N
AU_HSP
AU_HSNH4AU_HPLJ4AU_HPR
U301
MT6323/VFBGA145/P0.4/B0.25/5.8X5.8
VBAT_SPKE4AU_VIN0_PF4AU_VIN0_NG3AU_VIN1_PG4AU_VIN1_ND2AU_VIN2_PD1AU_VIN2_N
GND_SPK
P1
L2
C313
2.2uF(0402)
VBAT
[3,5,8]
if you use digital MIC,
please change cap (C312)
to 1.0uF
[7]
[7]
AU_HPR
AU_HPL
AU_MICBIAS0G2AU_MICBIAS1
F2
[7]
MICBIAS1
MICBIAS0
[7]
[8]
Please use inductor recommand by MTK
Refer to MT6323 design notice
LED-
E9
E10
C10
ISINK0C9ISINK1
ISINK2
ISINK3
DRIVER
AUDIO
AVDD28_ABB
J2
[7]
[7]
[7]
[7]
AU_VIN1_N
AU_VIN0_P
AU_VIN1_P
AU_VIN0_N
C312
100nF
1uF
VA_PMU
[3]
AVDD28_AUXADCH2GND_ABB
D3
C314
L301 0.68uH
C14
BUCK OUTPUT
ACCDET
E2
ACCDET
[7]
VPROC_PMU
D14
VPROC
VPROC
CLK26M
E1
[1,3]
E14
CLK4_AUDIO
[5]
VPROC
ISENSE/BSTSNS 4mil
TO:C114-
TO:C114+
[1,3]
VPROC_PMU
[1,2,4,5,6,7,8]
GND
B14
B12
A14
D12
C12
VPA
VPA
VPA_FB
VPROC_FB
GND_VPROC_FB
CHARGER
VCDT
VDRV
ISENSE
BATSNSK3BATON
A12
M13
P12
P13
VBAT
VCDT
ISENSE
BAT_ON
VDRV
1uF
C302
VCDT
ISENSE
VBAT
BAT_ON
[3]
[3]
[3]
[3] VDRV
[3,5,8]
differential to Rsense
CHRLDO
N13
CHR_LDO
CHR_LDO
[3]
[3]
VSYS_PMU
L303 0.68uH
H14
VSYS
1uF
[3]
VA_PMU
6mil
8mil
M3
VA
ALDO OUTPUT
CONTROL SIGNAL
RESETBM2PWRKEYN2PMU_TESTMODEB6AUD_MISO
FSOURCEE7AUD_MOSIE8AUD_CLK
INT
SYSRSTB
K4
A9
A7
A1
1K
R316
RESETB
PWRKEY
WATCHDOG
EINT_PMIC
[8]
[2]
[2]
[2,4]
C316
[6]
[1,5]
VTCXO_PMU
VCN_2V8_PMU
6mil
L4
N3
VTCXO
VCN28
EXT_PMIC_EN
N12
10nF
C351
[8]
[6]
VCAMA_PMU
VCN_3V3_PMU
12mil
P3
VCAMAM6VCN33
AUD_MOSI
[2]
[3]
VRTC
6mil
12mil
C3
AVDD33_RTC
AUD_CLK
[2]
AUD_MISO
[2]
[4]
C355
1uF
J13VMH11
DLDO OUTPUT
SRCLKEN
FCHR_ENBD9SPI_CLK
A2
M1
SRCLKENA
[2,5]
[5]
VM_PMU
VRF18_PMU
15mil
35mil
L12
VRF18
B7
PMIC_SPI_SCK
PMIC_SPI_CS
[2]
[1,5,7,8]
[1,2,3,4,5,8]
VIO18_PMU
VIO28_PMU
[8]
[6]
VCN_1V8_PMU
VCAMD_PMU
8mil
15mil
12mil
12mil
M4
K14
J12
VIO18
VIO28
VCAMD
VCN18
SPI_CSND8SPI_MOSIB8SPI_MISO
PMIC_SPI_MOSI
PMIC_SPI_MISO
[2]
[2]
[2,4]
VEMC_3V3_PMU
[3,4]
[2,8]
[3,4]
[7]
[1]
VCAMD_IO_PMU
VEMC_3V3_PMU
VMC_PMU
VMCH_PMU
12mil
15mil
6mil
8mil
L6
P4
L13
P7
VMC
VMCHL8VGP1N6VUSB
VCAM_IO
VEMC_3V3
VBAT INPUT
VBAT_VPROC
VBAT_VPAP5VBAT_LDOS2
VBAT_VPROCP2VBAT_LDOS1
VBAT_VPROC
F14
A13
G13
F13
30mil
30mil
15mil
100nF
C354
[8]
[8]
[7]
[1]
[7]
VIBR_PMU
VSIM2_PMU
VGP1_TP_2.8
VSIM1_PMU
VUSB_PMU
6mil
8mil
6mil
8mil
N8
L14
P9
M7
VGP2
VGP3
VIBR
VSIM1N9VSIM2
VBAT_VSYS
AVDD22_BUCK
VBAT_LDOS3A5DVDD18_IOA8DVDD18_DIG
VBAT_LDOS3
AVDD22_BUCK
VBAT
P6
P8
H13
J14
M14
20mil
20mil
20mil
20mil
RTC
RTC 32K : X301+C324+C319=> mount, R333=> NC
[8]
VCAM_AF_PMU
8mil
N7
VCAM_AF
C323
有问题
100nF
C323 must to be close to PMIC
32K-less: X301+C324=> remove, C319+R333=> 0R
dedicate VSS ball, must return to cap then to main GND:
1. GND_VREF(N14) => C320
[2]
CLK32K_BB
C320
100nF
VREF
P14
VREF
AUXADC
AUXADC_VREF18B1AUXADC_AUXIN_GPSB2AVSS28_AUXADC
C2
R350 0
GND_AUXADC
AUXADC_REF
AUXADC_TSX
[5]
[5]
[3,5]
DCXO_32K
B10
A3
A4
D5
C4
N14
XIN
XOUT
GND_VREF
RTC_32K1V8
RTC_32K2V8
RTC
SIM LVS
BC 1.1
CHG_DP
CHG_DM
SIM1_AP_SCLK
SIMLS1_AP_SIOE6SIM1_AP_SRSTC5SIM2_AP_SCLK
B5
A11
A10
M11
CHD_DM
CHD_DP
SIM1_SIO
SIM1_SCLK
[2]
[2]
[2] SIM2_SCLK
[2]
[2]
C322 100nF
Connect TSX/XTAL GND
to AUXADC_GND first
than connect to main GND
C322 must to be close
to PMIC AUXADC_AUXIN_GPS pin
1uF
C308
1uF
C307
10uF
C309
10uF
C306
1uF
C304
C303
10uF
C301
Refer to GPS co-clock layout rule
10uF
G11
GND_VSYS
GND_ISINK
SIMLS2_AP_SIOD6SIM2_AP_SRSTM9SIMLS1_SCLK
K11
SIM2_SIO
[2]
E13
E11
GND_VPA
F11
GND_VPROC
GND_VPROC
SCLK
[7]
F10
GND_VPROC
SIMLS1_SIO
M10
N11
SIO
SRST
[7]
[7]
SIMLS1_SRST
K6
GND_LDOK8GND_LDO
L11
SCLK2
[7]
F5
GND_LDOG5GND_LDO
SIMLS2_SRST
SIMLS2_SIOK9SIMLS2_SCLK
K10
SIO2
SRST2
[7]
[7]
DCXO_32K
[5]
Close to chip
F6
F7
G6
GND_LDO
GND_LDOF8GND_LDOF9GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
C318
100nF
R312
1K
10uF
VRTC
C325
[3]
please refer to RTC design notice
==> for longer RTC time sustain after battery remove,
G7
G8
G9
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
J10
MT6323
[3,5]
AUXADC_REF
BATTERY
CONNECTOR
靠近PMU
R334 16.9K 1%
[3]
BAT_ON
R3171K
R334,R335 must to be close to
PMIC AUXADC_REF pin
R335 27K 1%
[3,5,8]
VBAT
if battery NTC is 10kohm, R334=39K, R335=90K
if battery NTC is 47kohm, R334=190K, R335=390K
Refer to MT6323 HW design notice
10uF
C382
C377
33pF
T300
40mils
T301
TPLED4
2ID3
TPLED6
GND
J1
WKBAH009-A31
1
VBAT
VIO18_PMU
VSYS_PMU
[3]
[1,2,3,4,5,8]
10uF
C310
D302
5V1 SOD123
80mil
VBAT
[3,5,8]
TPLED7
Refer to MT6323 design notice
for Buck GND layout rule
39K
R324
VBUS
[7]
Pulse Charger
VCDT
CHR_LDO
[3]
[3]
3.3K
R331
330K
R329
40mils
C329
1uF
瑻溃+16V
CHRIN max. 8.0V when U290 NC
[3]
VDRV
Q301
NTA4153NT1G
R301
1
10K
32
BC
E
34
C
52
16
C
C
U303
STT818B
40mils
R328
and others are 40mils
connector, and SNS trace should be 4mil~6mil,
Place this resister close to battery
VBAT
[3,5,8]
0.2R
ISENSE
[3]
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