FLY DS500 Service Manual Contents
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Baseband section
This document provides a description of the baseband section of the DS1. Most design decisions
are explained, but no detailed calculations are included. Total chip solutions(MT6227, MT6223,
MT6318, MT6120) except for RF Power Amplifier(RF3166) are from Media Tek, Taiwan.
I. MT6227 ( GSM/GPRS Baseband Processor )
1. System Over View
The Revolutionary MT6227 is a leading edge single-Chip solution for GSM/GPRS mobile phones
TM
targeting the emerging applications in digital audio and video. Based on 32bit ARM7EJ-S
processor, MT6227 not only features high performance GPRS Class 12 MODEM, but also provides
comprehensive and advanced solutions for handheld multi-media.
RISC
The Figure 1 is shown Typical Application for MT6227.
Figure 1 : Typical Application for MT6227
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Figure 2 is shown the Block Diagram of MT6227 in detail.
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Figure 2 : Block Diagram of MT6227
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2. Product Description
2.1 Pin Outs
One type of Package for this product, TFBGA 13x13mm, 296balls, 0.65mm pitch package, is offered.
Pin outs and the top view are illustrated in Figure 3,4.
-. Pin Out
Figure 3 . MT6227 Pin Out.
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-. Top and Bottom View
2.2 Top Masking Definition
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Figure 5. Top masking definition
2.3 Pin Description
-. JTAG Port
-. RF Parallel Control Unit
-. RF Serial Control Unit
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-. PWM Interface
-. Serial LCD/PM IC Interface
-. Parallel LCD/Nand_Flash Interface
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-. SIM Card Interface
-. Dedicated GPIO Interface
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-. Miscellaneous
-. Key Pad Interface
-. External Interrupt Interface
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-. External Memory Interface
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-. USB Interface
-. Memory Card Interface
-. UART Interface
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-. Digital Audio Interface
-. Image Sensor Interface
-. Analog Interface
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-. VCXO Interface
-. RTC Interface
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-. Supply Voltages
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3. Micro-Controller Unit Subsystem
Figure 6 illustrates the block diagram of the Micro-Controller Unit Subsystem in MT6227. The
Subsystem utilizes a main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus
master controlling the whole subsystem. The processor communicates with all the other on-chip
modules via the two-level system buses: AHB Bus and APB Bus. All bus transactions originate from
bus masters, while salves can only respond to requests from bus masters. Before data transfer can be
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established, bus master must ask for bus ownership. This is accomplished by request-grant
handshaking protocol between masters and arbiters.
Figure 6. Block Diagram of MCU in MT6227
3.1 Processor Core
The Micro-Controller Unit subsystem in MT6227 uses the 32-bit Arm7EJ-S RISC processor that is
based on the Von Neumann architecture with a single 32-bit data bus carrying both instructions and
data. The memory interface of ARM7EJ-S is totally compliant to AMBA based bus system, which allows
direct connection to the AHB Bus.
3.2 Memory Management
The processor core of MT6227 supports only memory addressing method for instruction fetch and data
access. It manages a 32bit address space that has addressing capability up to 4GB. System RAM,
System ROM , Registers, MCU Peripherals and external components are all mapped onto such 32-bit
address space, as depicted in Figure 7.
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Figure 7. Memory Layout of MT6227
External Memory Access
To allow external access, The MT6227 outputs 26bits(A25~A0) of address line along with 8 selection
signals that correspond to associated memory blocks. This is, MT6227 can support up to 8 MCU
addressable external components. The data width of internal system bus is fixed at 32bit wide, while
the data width of the external components can be either 8 or 16 bits.
Factory Programming
The configuration for factory programming is shown in Figure 8. Usually the factory programming host
connects with MT6227 via the UART interface. In order to have it work properly, the system should
boot up from Boot Code. That is, IBOOT should be tied to GND. The download speed can be up to
921K bps while MCU is running at 26Mhz. After the system has reset, the Boot Code will guide the
processor to run the Factory Programming software placed in System ROM. Then, MT6227 will start
and continue to poll the UART1 port until valid information is detected. The first information received
on the UART1 will be used to configure the chip for factory programming. The Flash downloader
program is then transferred in to System RAM or external SRAM.
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Figure 8. Factory Programming
3.3 Bus System
Two levels of bus hierarchy are employed in the Micro-Controller Unit Subsystem of MT6227. As depicted
in Figure5, AHB Bus and APB Bus serve as system backbone and peripheral buses, while an APB bridge
connects these two buses. Both AHB and APB Buses operate at the same clock rate as processor core.
The APB Bridge is the only bus master residing on the APB Bus. All APB slaves are mapped onto memory
block MB8 in MCU 32bit addressing space. A central address decoder is implemented inside the bridge to
generate select signals for individual peripherals. In addition, since the base address of each APB slave has
been associated with select signals, the address bus on APB will contain only the value of offset address.
The base address and data width of each peripheral are listed in below table.
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3.4 Direct Memory Access
A generic DMA controller is placed on Layer2 AHB Bus to support fast data transfer snd to off-load the
processor. With this controller, specific devices on AHB or APB buses can benefit greatly from quick
completion of data movement from or to memory modules such as Internal System Ram or External
SRam. Such generic DMA Controller can also be used to connect any two devices other than memory
module as long as they can be addressed in memory space.
Figure 9. Variety data paths of DMA transfer.
3.5 Interrupt Controller
Figure 10 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller
processes all interrupt sources coming from external lines and internal MCU peripherals. Since
ARM7EJ-S core supports two levels of interrupt latency. This controller generates two request signals :
FIQ for fast, low latency interrupt request and IRQ for more general interrupts with lower priority.
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Figure 10. Block Diagram of Interrupt controller.
External Interrupt
This interrupt controller also integrates an External Interrupt controller that can support up to 4 interrupt
requests coming from external sources, the EINT0~3 and 4 wake up interrupt requests. The four
external interrupts can be used for different kind of applications, mainly for event detections : detection
of hand free connection, detection of hood opening, detection of battery charger connection.
In DS1, external interrupts are used for Headset detection, Charger Detection and Blue Tooth Detection.
3.6 Internal Memory Interface
System Ram
MT6227 provides one 284Kbyte size of on-chip memory modules acting as System Ram for data access
with low latency. Such a Module is composed of three high speed synchronous SRAMs with AHB Slave
interface connected to the system backbone AHB Bus. Bank 0 and bank 1 SRAMs are 128Kbyte and Bank 2
SRAM is 28Kbyte. The synchronous SRAM operates on the same clock as the AHB Bus and is organized as
32bits wide with 4 byte-write signals capable for byte operations. Band 0 and Band 1 SRAM macros have
limited repair capability. The yield of SRAM is improved if the defects inside it can be repaired urging testing.
System ROM
The 27Kbyte System ROM is primarily used to store software program for Factory programming.. However,
due to its advantageous low latency performance, some of the timing critical codes are also placed in
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System ROM. This module is composed of high-speed VIA ROM with an AHB Slave Interface connected to
a system backbone.
3.7 External Memory Interface
MT6227 incorporates a powerful and flexible memory controller, External Memory Interface, to connect with
a variety of memory components. This controller provides one generic access scheme for FLASH memory,
SRAM and PSRAM. Up to 8 memory banks can be supported simultaneously, ban 0 ~ Bank 7, with a
maximum size of 64MB each.
Since more of the Flash Memory, SRAM and PSRAM have similar ac requirements, a generic configuration
scheme to interface them is desired. This way, the software program can treat different components by
simply specifying certain predefined parameters. All these parameters are based on cycle time of system
clock.
External Memory Interface of MT6227 for Asynchronous/Synchronous components.
In DS1, ECS0# is used for External Flash Memory and ECS1# is used for External PSRAM.
4. Microcontroller Peripherals
Microcontroller(MCU) Peripherals are devices that are under direct control of the Microcontroller. Most of
the devices are attached to the Advanced Peripheral Bus(APB) of the MCU subsystem, and serve as APB
slaves. Each MCU peripheral must be accessed as a memory-mapped I/O device: that is, the MCU or the
DMA bus master reads from or writes to the specific peripheral by issuing memory-addressed transactions.
4.1 Pulse-Width Modulation Outputs.
Two generic Pulse-Width Modulators are implemented to generate pulse sequences with programmable
frequency and duty cycle for LCD backlight or charging purpose. The duration of the PWM output signal is
low as long as the internal counter value is greater than or equal to the threshold value.
In DS1, PWM1 is used for LCD Module Backlight Enable and PWM2 is used for Flash LED Enable.
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4.2 SIM Interface
The MT6227 contains a dedicated smart card interface to allow the MCU access to the SIM Card. It can
operate via 5 terminals, using SIMVCC, SIMSEL, SIM RST, SIMCLK and SIMDATA.
The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines the
regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and
SIMCLK are used for data exchange purpose. Basically, the SIM interface acts as a half duplex
asynchronous communication port and its data format is composed of ten consecutive bits: a start bit in
state Low, eight information bits and a tenth bit used for parity checking.
In DS1, Only 3V SIM interface is used.
Figure 11. SIM interface
4.3 Keypad Scanner
The keypad can be divided into two parts : One is the keypad interface including 7 columns and 6 rows
The other is the key detection block which provides key pressed, key released and de-bounce mechanism.
Each time the key is pressed or released, i.e. something different in the 7x6 matrix, the key detection block
will sense it, and it will start to recognize if it is a key pressed or key released event. Whenever the key
status changes and is stable, a KEYPAD IRQ will be issued. The MCU can then read the key pressed
directly in KP_HI_KEY, KP_MID_KEY and KP_LOW_KEY register.
In DS1, The 6 Rows are used (Row0 ~Row5) and The 6 Columns are used (Col 0~4 and Col 6)
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Figure 12. Key pressed with de-bounce mechanism
4.4 General Purpose Inputs/Outputs
MT6227 offers 57 general purpose I/O pins and 5 general-purpose output pins. By setting the control
registers, MCU software can control the direction, the output value and read the input values on these pins.
These GPIOs and GPOs are multiplexed with other functionalities to recude the pin count.
Upon hardware reset(/SYSRST), GPIOs are all configured as inputs.
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Figure 13. GPIO Block diagram.
4.5 General Purpose Timer
Three general-purpose timers are provided. The Timers are 16 bits long and run independently of each
other, although they share the same clock source. Two timers can operate in one of two modes: one-shot
mode and auto-repeat mode; the other is a free running timer. In one-shot mode, When the timer counts
down and reaches zero, it is halted. In auto-repeat mode, when the timer reaches zero, it simply resets to
countdown initial value and repeats the countdown to zero; this loop repeats until the disable signal is set to
1.
4.6 UART
The baseband chipset houses three UARTs. The UARTs provide full duplex serial communication channels
between baseband chipset and external devices.
In DS1, UART1(URXD1, UTXD1) is used for Factory Programming and UART3(URXD3, UTXD3) is used for
Blue Tooth Programming.
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Figure 14. UART block diagram.
RX data Timeout Interrupt :
When virtual FIFO mode is disabled, RX data Timeout Interrupt is generated if all of the following apply :
1. FIFO contains at least on character.
2. The most recent character was received longer than four character periods ago(including all start,
parity and stop bit)
3. The most recent CPU read of the FIFO was longer than four character periods ago.
When virtual FIFO mode is enabled, RX Data timeout Interrupt is generated if all of the following apply:
1. FIFO is empty.
2. The most recent character was received longer than four character periods ago(including all start,
parity and stop bit)
3. The most recent CPU read of the FIFO was longer than four character periods ago
4.7 IrDA framer
IrDA framer, which is depicted in Figure 15, is implemented to reduce the CPU loading for IrDA
transmission. IrDA framer functional block can be divided into two parts : the transmitting part and the
receiving part. In the transmitter, it will perform BOFs addition, byte stuffing, the addition of 16bits FCS and
EOF appendence. In the receiving part, it will execute BOFs removal, ESC character removal, CRC checking
and EOF detection. In addition, the framer will perform 3/16 modulation and demodulation to connect to the
IR transceiver. The transmitter and receiver all need DMA channel.
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Figure 15. IrDA Block Diagram.
4.8 Read Time Clock
The Real Time Clock(RTC) module provides time and data information. The clock is based on a 32.768Khz
oscillator with an independent power supply. When the mobile handset is powered off, a dedicated
regulator supplies the RTC block. If the main battery is not present, a backup supply such as a small
mercury cell battery or a large capacitor is used. In addition to providing timing data, an alarm interrupt is
generated and can be used to power up the baseband core via the BBWAKEUP pin. Regulator interrupts
corresponding to seconds, minutes, hours and days can be generated whenever the time counter value
reaches a maximum value. The Maximum day-of-month values, which depend on the leap year condition,
are stored in the RTC block.
In DS1, Big Capacitor Battery(BAT100) is used for Backup Battery. The Charging Voltage is about 1.5V by
VRTC.
4.9 Auxiliary ADC Unit
The auxiliary ADC unit is used to monitor the status of battery and charger, identify the plugged peripheral
and perform temperature measurement. There provides 7 input channels for diversified application in this
unit. There provides 2 modes of operation : immediate mode and timer-triggered mode.
5. Microcontroller Coprocessors
Microcontroller Coprocessors are designed to run computing-intensive processes in place of the
Microcontroller(MCU). These coprocessors especially target timing critical GSM/GPRS Model processes
that require fast response and large data movement. Controls to the coprocessors are all through
memory access via the APB.
6. Multi-Me dia Subsystem
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MT6227 is specially designed to support multi-media terminals. It integrates several hardware based
accelerators such as advanced LCD display controller, hardware JPEG encoder/decoder, hardware
Image Resizer, and MPEG4 video Codec.
In addition, MT6227 also incorporates nand Flash, USB 1.1 Device and SD/MMC/MS/MS Pro Controllers
for mass data transfers and storages. This chapter describes those functional bocks in more details.
6.1 LCD Interface
MT6227 contains a versatile LCD controller which is optimized for multimedia applications. This
controller supports many types of LCD modules and contains a rich feature set to enhance the functionality.
These features are :
- Up to 320x240 resolution
- The internal frame buffer supports 8bpp indexed color and RGB 565 format
- Supports 8bpp(RGB332), 12bpp(RGB444), 16bpp(RGB5650, 18bit(RGB666) and 24bit(RGB888) LCD
modules
- 4 Layers overlay with individual color depth, window size, vert ical and horizontal offset, source key,
alpha value and
o
Display rotation control(90
,180o,270o, mirror and mirror then 90o, 180o and 270o)
- One Color Loop-up Tables.
For Parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated
8/9/16/18 bit parallel interface to access them and 8080 type interface is supported. It can transfer the
display data from the internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
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Figure 16. LCD interface block diagram.
In DS1, The 262K color TFT LCD Module is used with Samsung Driver IC – LGDP4524.
The Resolution is 176x220 dots and 2.0inch Panel from LG Philips.
6.2 JPEG Decoder
To boost JPGE image processing performance, a hardware block is preferred to aid software and deal
with jpeg file as much as possible. As a result, JPEG Decoder is designed to decode all baseline and
progressive JPEG images with all YUV sampling frequencies combinations. To gain the best speed
performance, JPEG decoder will handle all portions of JPEG files except the 17 byte SOF marker. The
software program only needs to program related control registers based on the SOF maker and wait for an
interrupt coming from hardware. Taking into consideration the limited size of memories, hardware also
supports multiple runs of JPEG progressive images and breakpoints insertion in huge JPGE files.
6.3 Image Resizer
This Block provides image resizing capability. It receives image data from a block-based image source
such as JPEG decoder in format of YUV color space, or a pixel-based image source such as camera in
format of RGB or YUV and performs image resizing. The first pass is coarse resizing pass and it can shrink
the image by a factor of 1, 1/4, 1/16, 1/64. The second pass is fine resizing pass and it can shrink and
enlarge the image in fractional ratio. Refer to the Figrue9 Image resizer block diagram. The maximum size of
a pixel based source image is only 2047x2047.
Figure 17. Overview of Image Resizer.
.
6.4 USB Device controller
MT6227 provides a USB function interface that is in compliance with Universal Serial Bus Specification Rev
1.1. The USB device controller supports only full-speed(12Mbps) operation. The cellular phone can make
use of this widely available USB interfaces to transmit/receive data with USB host, typically PC.
The USB device uses cable-powered feature for the transceiver but only drains little current. An external
resistor(nominally 1kohm) is required to be placed across Vusb and DP Signal. Two additional external serial
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