SERVICE MANUAL
----DS115
Date Version Maintenance Level Author
December 15, 2012
V1.0 L1~L4 Cheney Chen
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TABLE OF CONTENTS
CAUTIONS……………………………………………….…………………………..….……….4
GENERAL REPAIR INFORMATION……………………..……………………..……….…….5
Chapter 1
SERVICE TOOLS
…………………………………………………………………….………….…….....7
Chapter 2 Baseband Circuit Analysis
Mobile solution diagram ….……..……………………………………….……………………9
Baseband Block Diagram
Baseband Chip Pin Description
.……..…………………………………………………………9
……………………………………………….………………12
2.2.1 MCU subsystem ……………….....…………………..................……….………………12
2.2.2 extra memory description ……………………........………………………..……….………15
2.2.3 camera subsystem ……………….................…........………………………..……….………18
2.2.4 Audio process subsystem………………...................………………………..……….………19
2.2.5 Power Manager subsystem….......……...................………………………..……….………23
2.2.6 I/O interface circuit……………….......................................……………………….…….…..32
Chapter 3 RF Circuit Analysis
Mobile solution diagram…………………………………………………………………………33
RF receiver circuit description …………………………………………………………………….35
RF transit circuit description
……………………………………………………..……………….36
Chapter 4 Trouble shooting
Turning on failure ------L1~L2
………………………………………………..………………..37
Turning on failure ------no current………………………………………………………………….38
Turning on failure ------10~30mA………………………………………………………………….39
Turning on failure ------large current……………………………………………………..……….40
Ringtone failure------L1~L2 ……………. ……………….………………………………………..41
Ringtone failure------L3~L4 ……………. …….…………………………………………………..42
No display------L1~L2 …………….……………………………………………………………....43
No display------L3~L4……………….……………………………………………………………....44
Download circuit failure------L1~L2……………….……………………………………………...45
Download circuit failure------L3~L4……………….……………………………………………...46
Keypat circuit failure-……………….……....................……...........................…………………...47
T-flash reader circuit failure------L3~L4…………………………………………………………...48
Dual SIM failure------L1~L2.……..……………………………………………………..…………..49
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Camera circuit failure-……………….……………...........................…………………...50
Call in failure------L1~L2.……..……………………………………………………........51
Call in failure------L3~L4……..………………………………………………………..…………..52
Call out failure------L1~L2.……..…………………………………………………………………..53
Call out failure------L3~L4……..…………………………………………………………………..54
Chapter 6 Appendix……………..…………………………………………………....................55
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CAUTIONS
Please refer to the phone’s user’s guide for instructions relating to operation, care,
and maintenance, which include important safety information.
1. Servicing and alignment must be undertaken by qualified personnel only.
2. Ensure all work is carried out at an anti-static workstation and that an anti-static
wrist strap is worn.
3. Use only approved components as specified in the parts list.
4. Ensure all components, modules, screws, and insulators are correctly re-fitted
after servicing and alignment
5. Ensure all cables and wires are repositioned correctly
Electrostatic discharge can easily damage the sensitive components of electronic
products. Therefore, every service supplier must observe the precautions which
mentioned above.
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GENERAL REPAIR INFORMATION
1. Make sure your testing equipment is functioning properly before beginning repair
work.
2. Before starting repairs you must observe ESD precautions such as being in your
ESD protected area and connecting your wristband.
3. Use gloves to avoid corrosion and fingerprints.
4. Cover windows and displays with a protective film to avoid dust and scratches.
5. Use a lint-free cloth to clean the LCD.
6. When cleaning the pads use a soft cloth\ESD brush and isopropanol .
7. Non-faulty mechanical parts (except shielding lids and bent parts or soldered
components). May be reused if they are not soldered.
8. When removing the shielding lids make sure to cover it back or replace them with
new ones, otherwise the high-frequency leakage can affect the device.
9. Always use the original spare parts.
10. Check the soldering joints of the parts concerned with regard to the fault
symptom. And re-solder them if necessary.
11. Remove excess soldering flux after repair.
12. Observe the torque requirements when assembling the unit.
13. please aware that some malfunctions may be software related and solved by an
update
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Chapter 1
Service tools
850 Rework station & Solder Iron
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DC Power supply
Multimeter
Digital Oscillograph
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Screw driver and tweezer
Solder wire
Flux paste
Wrist grounding strap, Antistatic gloves
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Serial flash chipset
BB chipset
26MHz crystal
Filter
PA
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Chapter 2
Baseband Circuit Analysis
2.1 Mobile solution diagram
MT6250 is a monolithic chip integrating leading edge power management unit, analog
baseband and radio circuitry based on the low-power CMOS process.
MT6250 is a feature-rich and extremely powerful single-chip solution for high-end SM/GPRS
and EDGE-Rx capability. Based on the 32-bit ARM7EJ-STM RISC processor, MT6250’s
superb processing power, along with high bandwidth architecture and dedicated hardware
support, provides a platform for high-performance GPRS/EDGE-Rx Class 12 MODEM
application and leading-edge multimedia applications.
Figure 2-1: Solution Diagram
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MT6250 is capable of running the ARM7EJ-STM RISC processor at up to 260MHz,
which provides the best trade-off between system performance and power consumption.
For large amounts of data transfer, high-performance DMA (Direct Memory Access) with
hardware flow control is implemented, which greatly enhances the data movement speed while
reducing the MCU processing load.
Targeted as a media-rich platform for mobile applications, MT6250 also provides
hardware security digital rights management for copyright protection. For further safeguard
and to protect the manufacturer’s development investment, hardware flash content protection
is provided to prevent unauthorized porting of the software load.
Specifically, MT6250 consist of the following subsystems:
General
Integrated voice -band, audio-band and base-band analog front-end
Integrated full -featured power management unit
MCU subsystem
ARM7EJ -STM 32-bit RISC processor
Java hardware acceleration for fast Java -based games and applets
Operating fr equency: Max. 260MHz with dynamic clock gating
High -performance multi-layer AHB bus
Dedicated DMA bus with 17 DMA channels
On -chip boot ROM for factory flash programming
Watchdog timer for system crash recovery
4 sets of general -purpose timers
Circuit switch data coprocessor
Division coprocessor
Serial flash interfaces
Supports various operating frequency combinations for serial flash
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Supports QPI and SPI serial flash
User interfaces
8 -row × 8-column and 5-row x 5-column keypad controller with hardware scanner
Supports multiple key presses for gaming
Dual SIM/USIM controller with hardware T = 0/T = 1 protocol control
Real -time clock (RTC) operating with a low-quiescent-current power supply
General -purpose I/Os (GPIOs) available for auxiliary applications
1 sets of Pulse Width Modulation (PWM) output
13 external interrupt lines
1 external channel auxiliary 10 -bit A/D converter
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p
MIC input
Earphone MIC input
Receiver out
Earphone audio output
Speaker output
USB communicate bus
Keypad scan bus
TORCH enable
UART download channel
ut
2.2 Baseband Chip Pin Descriptions
2.2.1 MCU Subsystem
I2C communicate bus
T-Flash memory channel
Figure 2-2: CPU U100F MCU part
* UART----Universal Asynchronous
receiver or transmitter
Camera control
and data channel
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MCU Subsystem
ARM7EJ -STM 32-bit RISC processor
Java hardware acceleration for fast Java -based games and applets
Operating frequency : Max. 260MHz with dynamic clock gating
High -performance multi-layer AHB bus
Dedicated DMA bus with 17 DMA channels
On -chip boot ROM for factory flash programming
Watchdog timer for system crash recovery
4 sets of general -purpose timers
C ircuit switch data coprocessor
Division coprocessor
A main 32-bit ARM7EJ-S RISC processor, which plays the role of the main bus master
controlling the whole subsystem. All processor transactions go to code cache first. The code
cache controller accesses TCM (memory dedicated to ARM7EJS core), cache memory, or bus
according to the processor’s request address. If the requested content is found in TCM or in
cache, no bus transaction is required. If the code cache hit rate is high enough, bus traffic
can be effectively reduced and processor core performance maximized. The bus comprises
of two-level system buses: Advanced High-Performance Bus (AHB) and Advanced Peripheral
Bus (APB). All bus transactions originate from bus masters, while slaves can only respond to
requests from bus masters. Before data transfer can be established, the bus master must ask
for bus ownership, accomplished by request-grant handshaking protocol between masters and
arbiters. Two levels of bus hierarchy are designed to provide optimum usage for different
performance requirements. Specifically, AHB Bus, the main system bus, is tailored toward
high-speed requirements and provides 32-bit data path with multiplex scheme for bus
interconnections. The APB Bus, on the other hand, is designed to reduce interface complexity
for lower data transfer rate, and so it is isolated from high bandwidth AHB Bus by APB
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Bridge. APB Bus supports 16-bit addressing and both 16-bit and 32-bit data paths. APB
Bus is also optimized for minimal power consumption by turning off the clock when there is no
APB bus activity. During operation, if the target slave is located on AHB Bus, the transaction
is conducted directly on AHB Bus. However, if the target slave is a peripheral and is attached
to the APB bus, then the transaction is conducted between AHB and APB bus through the use
of APB Bridge. In order to off-load the processor core, a DMA Controller is designated to act
as a master and share the bus resources on AHB Bus to do fast data movement between
modules. This controller comprises thirteen DMA channels. The Interrupt Controller provides
a software interface to manipulate interrupt events. It can handle up to 32 interrupt sources
asserted at the same time. In general, it generates 2 levels of interrupt requests, FIQ and IRQ,
to the processor. A SRAM is provided for acting as system memory for high-speed data access.
For factory programming purpose, a Boot ROM module is used. These two modules use the
same Internal Memory Controller to connect to AHB Bus.
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