first international computer VY240D Schematics
5
4
3
2
1
First International Computer,Inc
D D
Protable Computer Group HW Department
Board name : Mother Board Schematic
Project : VY240D
C C
Version : 0.1
1. Schematic Page Description :
2. PCI & IRQ & DMA Description :
3. Block Diagram :
4. Nat name Description :
Initial Date : January. 3 , 2008
5. Board Stack up Description :
6. Schematic modify Item and History :
7. power on & off & S3 Sequence :
8. Layout Guideline :
9. switch setting
B B
Manager Sign by: AVERY
Drawing by : JASON
Total confirm by: ADAM
A A
LAN Circuit check by:
2006/09/08
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Audio Circuit check by:
5
4
Title
Size Document Number Rev
C
3
2
Date: Sheet
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Title
1
1 49Saturday, January 19, 2008
0.1
of
8
7
6
5
4
3
2
1
1. Schematic Page Description :
VY240 Schematic Ver : 0.1
D D
1. Title
2. Schematic Page Description
21. CRT Connector
22. TV-Out VT1623M ( no use )
23. VT8237A PCI/USB (1/3)3. Block Diagram
4. ANNOTATIONS
5. Schematic Modify
6. Timing Diagram
7. DDR Layout Guideline
8. Merom processor (1/2)
9. Merom processor (2/2)
10. CPU Thermal
24. VT8237A IDE/AC-LINK (2/3)
25. VT8237A V-LINK/MII/LPC (3/3)
26. Power Good
27. Reset Circuit
28. VT6103L LAN PHY (10/100Ms) 48. DCIN
29. USB CNN
30. MINI / MDC / BT / CCD
31. Blank
C C
12. Clock Buffer
13. VN896 Host (1 OF 4)
14. VN896 DDR2 (2 OF 4)
15. VN896 Video (3 OF 4)
16. VN896 Power (4 OF 4)
17. DDR2 SO-DIMM0
18. DDR2 SO-DIMM1
19. VT1637 LVDS Transmitter
20. LCD Connector
32. AU6371 (Card Reader)
33. Express Card
34. Blank
35. Firm Ware Hub
36. INT K/B /LID/GP
37. S-ATA HDD / ODD CONN
38. Azalia ALC268 Codec
39. AMP MAXIM9789AETJ
40. HP / MIC IN/ Int. MIC/Line-in
41. LED / DIP SW
42. Screw Hole
43. EC_PMX
44. Power Block
45. POWER (CPU CORE)
46. ACIN, BATIN and ADPOUT1
47. Charger
49. 5VDDA/S/M, 3VDDA/S/M
50. 1.05VDDM/1.5VDDM
51. 2.5VDDA/M, 1.5VA/1.8VM11. Clock Generator
52. DDR 1.8VDDS/0.9VDDM
53. Daughter Board
54. (U) USB Board
55. (F) Finger Printer Board
2. PCI & IRQ & DMA Description :
B B
IDSEL
AD17
AD23 CardBus
IRQA
IRQB
IRQC
IRQD
BUSMASTER
A A
REQ
REQ0 / GNT0
REQ1 / GNT1
REQ2 / GNT2
REQ3 / GNT3
REQ4 / GNT4
CHIP
Mini PCI(Wireless LAN)
CHIPPCIINT
MiniPCI/NB
MiniPCI/CardBus
MiniPCI
8
CHIP
MiniPCI
CardBus
Mini PCI(Wireless LAN)
7
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
6
System timer
Keyboard
(Casacde)
LAN / MODEM
Serial Port
AUDIO / VGA / USB
FLOPPY DISK
LPT
RTC
ACPI
(Disable by default)
FIR
Cardbus
PS/2 mouse
FPU
HDD
CDROM
5
(MODEM/LAN)
4
DMA Channel
DMA0 FIR
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
3
DeviceIRQ Channel Desciption
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused
(disable by default)
(MODEM / LAN)
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
2
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Schematic Page DESCR
2 49Saturday, January 19, 2008
of
1
0.1
8
7
6
3. Block Diagram :
5
4
3
2
1
D D
Thermal
Sensor
P10
Intel
Merom CPU
Processor
P8,9
Host Bus
VN896
CRT
C C
LCD
RJ-45
ACIN
P42,P44
3VDDA/5VDDA
P45
B B
PMU3V/5V
3VDDM/5VDDM
VCCP/1.5VDDM
1.8VDDS/DDM
DDR 0.9VDDM
Over Voltage
Protect
Battery
charger
Battery Select
P21
P20
P26
P45
P45
P46
P47,P48
P48
P43
LVDS Tx
VT1637
LAN Phy
VT6103L
USB0~2
USB3
(USB/B)
P27,P49
W-LAN
(Mini card)
Card
Reader
AU6371
CAMERA
P27
P28
P29
Option
P28
P26
#0,#2,#3
P19
MII BUS
USB 2.0
#1
#5
#7
#6
952 HSBGA
P13~P16
Hub Interface
V-Link Bus
VT8237A
539 BGA
P22~P24
Mem Bus
PCI-E BUS
USB BUS
IDE BUS
S-ATA
CDROM
HDD
HDC-Link
LPC BUS
PMX (PMU+KBC)
Fujitsu
MB90F372
INT K/B GP
P32
CPU CORE
ISL6262CRZ-T
VCCP
CPU
DDR2 533/667
INTERFACE
Express Card
P33
P33
P39
P32
P41GMT G780P81U
P50
P17,P18
P30
Azalia
CODEC
ALC268
P34
MDC CNN
P28
FLASH ROM
(F/W Hub)
4M
Audio AMP
MAXIM9789
P31
CLK-G ICS953009AFLF-T
CLK Buffer ICS9P936AFLF-T
FAN CNN
RTC
P10
P24
RESET
P25,P39
SPEAKER
P35
HEADPHONE
Mic IN
P36
LINE IN
P36
P11
P12
P35
P36
A A
8
BAT CON
Battery Voltage
sense
P42
P43
7
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
6
5
4
3
Date: Sheet
2
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Block Diagram
of
3 49Saturday, January 19, 2008
1
0.1
8
7
6
5
4
3
2
1
4. Nat name Description :
Voltage Rails
DCIN
PMU5V 5.0V always on power rail by LATCH or ACIN
D D
PMU3V 3.3V always on power rail by LATCH or ACIN
3VDDA 3.3V always on power rail by DCON or PSUSC0
3VDDS 3.3V power rail
5VDDS 5.0V power rail
3VDDM
Vcore_CPU
VCCP 1.05V for AGTL+ Termination Voltage
DDR_0.9VDDM 0.9V DDR Termination Voltage
1.5VDDM 1.5V switched power rail
1.5VDDS 1.5V power rail
1.5VDDA 1.5V always on power rail
2.5VDDS 2.5V power rail for DDR
C C
Primary DC system power supply
5.0V always on power rail by DCON or PSUSC05VDDA
3.3V switched power rail
5.0V switched power rail5VDDM
Core Voltage for CPU
1.8V for CPU PLL Voltage1.8VDDM
5.Board Stack up Description
PCB Layers
Layer 1
Layer 2 Power Plane
Layer 3
Layer 4
Layer 5
Layer 6
Component Side, Microstrip signal Layer
Stripline Layer
Stripline Layer
Ground Plane
Component Side,Microstrip signal Layer
Part Naming Conventions
C
CN
D
F
L
Q
R
B B
RP
U
Y
Capacitor
=
=
Connector
=
Diode
=
Fuse
=
Inductor
=
Transistor
=
Resistor
=
Resistor Pack
=
Arbitrary Logic Device
=
Crystal and Osc
Net Name Suffix
0 =
Active Low signal
Signal Conditioning
_D_
_Q_
_L_
A A
Damped (by a resistor)
=
Isolated (by a Q-switch)
=
Filtered (by an inductor or bead)
=
8
7
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
6
5
4
3
Date: Sheet
2
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Anntotations
4 49Saturday, January 19, 2008
of
1
0.1
5
4
3
2
1
6.Schematic modify Item and History :
D D
C C
B B
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
(886-2)875 1-8751
VY240D (Merom + VIA VN896 + VT8237A)
Schenatic Modify
1
5 49Saturday, January 19, 2008
of
0.1
5
4
3
7. power on & off & S3 Sequence :
2
1
D D
Power On Sequencing Timing Diagram
VID
VR_ON
Vcc-core
CPU_UP
Tboot
Tsft_star_vcc
Tcpu_up
Vboot
Tboot-vid-tr
Vid
Vccp
Vccp_UP
Tvccp_up
Vccgmch
GMCHPWRGD
Tgmch_pwrgd
CLK_ENABLE#
IMVP4_PWRGD
C C
BATTERY ONLY POWER ON TIMING
POWSW0
PMU5V/PMU3V
DCON
VDDA
MAINSW0_ICH
PM_RSTRST0
PM_SLP_S30/S40/S50
PSUSC0
B B
A A
SUSTAT_B0
VDDM,VDDS
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP/1.2VDDM
VCORE_ON
VR_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGD
PCI_RST0
AGTL+_CPURST0
Tcpu_pwrgd
To ICH4
To ICH4
From ICH4
From ASIC_B0
From ASIC_B0
To clock generator
To ODEM and ICH4
From ICH4 to CPU
To ODEM/other PCI device
From ODEM to CPU
S3 SUSPEND AND RESUME TIMING
POWSW0
PMU5V/PMU3V
PM_RSMRST0
PM_SLP_S30
PM_SLP_S40/S50
PSUSC0
SUSTAT_B0
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP,1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGOOD
PCI_RST0
AGTL+_CPURST0
DCON
VDDA
VDDS
VDDM
VR_ON
H
H
H
H
H
H
H
To ICH4_M
From ICH4_M
From ICH4_M
From ASIC_B0
From ASIC_B0
1.5VDDS AND
DDR_PWRGD
Generator
To clock
ToICH4 and ODEM
From ICH4 to CPU
To ODEM/other
PCI device
From ODEM to CPU
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Timing Diagram
1
6 49Saturday, January 19, 2008
of
0.1
5
4
3
2
1
8. Layout Guideline :
Montara-GM DDR Layout Guidelines
Note that all length matching formulas are based on GMCH die-pad to SO-DIMM pin total length
D D
DDR Signal Groups
Group Signal Name
Clocks
Data
Control
Command
CPC
Feedback
SCK[5:0]
SCK#[5:0]
SDQ[71:0]
SDQS[8:0]
SDM[8:0]
SCKE[3:0]
SCS#[3:0]
SMA[12:6,3:0]
SBA[1:0]
SRAS#
SCAS#
SWE#
SMA[5,4,2,1]
SMAB[5,4,2,1]
RCVENOUT#
RCVENIN#
Length Matching Formulas
Signal Group Minimum Length Maximum Length
Control to Clock
Command to Clock
CPC to Clock
Strobe to Clock
Data to Strobe
Clock - 1.0"
Clock - 1.0"
Clock - 1.0"
Clock - 1.0"
Strobe - 25 mils Strobe + 25 mils
Clock + 0.5"
Clock + 2.0"
Clock + 0.5"
Clock + 0.5"
Clock Signals Topologies and Routing Guidelines
SO-DIMM PADS
C C
GMCH
Pin
P1 L1
Package Length
Range
Min:0.5"
Max:5.0"
7 mil trace, 4 mil pair space
Clock length tolerenve within the pair : +/- 10 mil
Clock to Clock Length Matching : +/- 25 mils
Minimum Pair to Pair Spacing : 20 mils
Minimum Spacing to other Signals : 20 mils
CLOCKS LENGTH
HCLKCPU[1..0]
HCLKNB[1..0]
HCLKITP[1..0]
66MCLK_ICH
66MCLK_GMCH
AGPCLK_ATI
PCLKICH
PCLKCB
PCLK1394
PCLKUSB20
PCLKOP
PCLKFWH
PCLKSIO
PCLKLAN
14MCLK_SIO
14MCLK_ICH
14MCLK_AC97
48MCLK_ICH
48MCLK_CB
2" ~ 8 "
4.5" ~ 9.0 "
MAX : 8.5"
4.5"~9.0"
4.5"~9.0"
3.5" ~ 12.5"
TRACE / SPACE NOTES
5 / 20 mils
(5 mil space
between + & - )
5 / 20 mils
Differentials pairs with1.
the same length
(within 10 mil)
2.CPU & NB trace
mismatch within
450 mil
* 66MCLK_ICH &
AGPCLK_GMCH
AGPCLK_ATI
Length mismatch
within 100 mils
1.Making PCI length with
minimum various
2.Max skew = 1ns
5 / 20 mils
5 / 10 mils
5 / 20 mils
Data Signals Topologies and Routing Guidelines
GMCH
Pin
Package Length
Range
B B
Control Signals Topologies and Routing Guidelines
GMCH
Pin
Package Length
Range
L1
P1
L1
P1
L2 L3 L4
SO-DIMM0
PADS
SO-DIMM1
PADS
L2
56 ohm 5%
56 ohm 5%
Minimun Spacing to Trace Width Ratio, SDQ/SDM : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 3.75"
Length Matching : SDQS to SCK/SCK#
Trace spacing to trace width ratio : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 5.5"
Length Matching : CTRL(P1+L1) to SCK/SCK#
L2 : Max 0.75"
L3 : Min 0.25" , Max 1.0"
L4 : Max 1.0 "
SDQS , SODIMM0 P1+L1+L2
SDQS , SODIMM1 P1+L1+L2+L3
Min : Clock - 1.0" , Max : Clock + 0.5"
SDQ/SDM to SDQS : +/- 25 mils
L2 : Max 2.0"
Min : Clock - 1.0" , Max : Clock + 0.5"
SO-DIMM0,1 PADS
Command Signals Topologies and Routing Guidelines
GMCH
Pin
A A
Package Length
Range
L1
P1
SO-DIMM0
PADS
5
10 ohm 5%
L2
L3 L4
SO-DIMM1
PADS
56 ohm 5%
Trace spacing to trace width ratio : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 4.0"
Length Matching : CMD to SCK/SCK#
L2 : Max 1.0"
L3 : Max 2.0"
L2+L3 : Max 3.0"
L4 : Max 1.0"
4
CMD , SODIMM0 P1+L1+L2
CMD , SODIMM1 P1+L1+L3
Min : Clock - 1.0" , Max : Clock + 2.0"
SDQS : 3 to1
CPC Signals Topologies and Routing Guidelines
GMCH
Pin
Package Length
Range
3
P1
L1
SO-DIMM0,1 PADS
SDQ/SDM to SDQS Mapping
Signal Mask
SDQ[7..0]
SDQ[15..8]
SDQ[23..16]
SDQ[31..24]
SDQ[39..32]
SDQ[56..40]
SDQ[55..48]
SDQ[63..56]
SDQ[71..64]
SDM[0]
SDM[1]
SDM[2]
SDM[3]
SDM[4]
SDM[5]
SDM[6]
SDM[7]
SDM[8]
L2
56 ohm 5%
2
Relative To
SDQS[0]
SDQS[1]
SDQS[2]
SDQS[3]
SDQS[4]
SDQS[5]
SDQS[6]
SDQS[7]
SDQS[8]
Mismatching
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
+/- 25 mil
Trace spacing to trace width ratio : 2 to 1
Minimum Spacing to other Signals : 20 mils
Trace Length L1 : Min 0.5" , Max 5.5"
Length Matching : CPC(P1+L1) to SCK/SCK#
L2 : Max 2.0"
Min : Clock - 1.0" , Max : Clock + 0.5"
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
DDR layout Gideline
1
0.1
of
7 49Saturday, January 19, 2008
A
For Merom
1.05VDDM
H_A20M#
R543 150Ω 1% 1/10W SMT0603 LR
H_DPSLP#
R164 150Ω 1% 1/10W SMT0603 LR
H_IGNNE#
R163 150Ω 1% 1/10W SMT0603 LR
H_INIT#
R165 150Ω 1% 1/10W SMT0603 LR
H_INTR
R168 150Ω 1% 1/10W SMT0603 LR
H_STPCLK#
R159 150Ω 1% 1/10W SMT0603 LR
H_NMI
R167 150Ω 1% 1/10W SMT0603 LR
H_CPUSLP#
R161 150Ω 1% 1/10W SMT0603 LR
H_SMI#
4 4
3 3
R166 150Ω 1% 1/10W SMT0603 LR
PSI#
R173 150Ω 1% 1/10W SMT0603 LR
H_FERR#
R548 51Ω 1% 1/10W SMT0603 LR
H_BREQ#
R156 220Ω 5% 1/10W SMT0603 LR
H_CPURST#
R162 51Ω 1% 1/10W SMT0603 LR
H_PWRGD
R160 470Ω 5% 1/10W SMT0603 LR
2/5
C762 150pF 50V 5% SMT0402 NPO LR(NU)
H_A20M#
H_DPSLP#
C763 150pF 50V 5% SMT0402 NPO LR(NU)
H_IGNNE#
C764 150pF 50V 5% SMT0402 NPO LR(NU)
H_INIT#
C765 150pF 50V 5% SMT0402 NPO LR(NU)
H_INTR
C766 150pF 50V 5% SMT0402 NPO LR(NU)
H_STPCLK#
C767 150pF 50V 5% SMT0402 NPO LR(NU)
H_NMI
C768 150pF 50V 5% SMT0402 NPO LR(NU)
H_CPUSLP#
C769 150pF 50V 5% SMT0402 NPO LR(NU)
H_SMI#
C770 150pF 50V 5% SMT0402 NPO LR(NU)
PSI#
C771 150pF 50V 5% SMT0402 NPO LR(NU)
H_FERR#
C772 150pF 50V 5% SMT0402 NPO LR(NU)
H_BREQ#
C773 150pF 50V 5% SMT0402 NPO LR(NU)
H_CPURST#
C774 150pF 50V 5% SMT0402 NPO LR(NU)
H_PWRGD
C775 150pF 50V 5% SMT0402 NPO LR(NU)
H_A#[31..3](13)
H_ADSTB#0(13)
H_REQ#[4..0](13)
H_A#[31..3](13)
H_ADSTB#1(13)
H_STPCLK#(24)
A#[32-39], APM#[0-1]:Leave escape routing on for future functionality
H_D#[63..0](13)
2 2
H_DSTBN#0(13 )
H_DSTBP#0(13)
H_DINV#0(13)
H_D#[63..0](13)
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
R117
1.05VDDM
1KΩ 1% 1/10W SMT0603 LR
1 1
2KΩ 1% 1/10W SMT0603 LR
R116
A
C163
0.1uF 10V 10% SMT0402 X5R LR
H_DSTBN#1(13 )
H_DSTBP#1(13)
H_DINV#1(13)
R527 1KΩ 5% 1/16W SMT0402 LR(NU)
R528 1KΩ 5% 1/16W SMT0402 LR(NU)
C166
1uF 6.3V 10% SMT0402 X5R LR
C778
0.1uF 10V 10% SMT0402 X5R LR(N U)
Place C? close to the CPU_TE ST4 pin.
Make sure CPU_TEST4 routing is reference to GND
and away from other nossy signale.
H_A20M#(24)
H_IGNNE#(24)
H_INTR(24)
H_NMI(24)
H_SMI#(24)
H_D#[63..0]
H_D#[63..0]
H_GTLREF
CPU_TEST4
H_BSEL0(11)
H_BSEL1(11)
H_A#[31..3]
H_REQ#[4..0]
H_A#[31..3]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
NU for Merom CPU
with VN896
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
U36A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
ADDR GROUP
0
ADDR GROUP
1
THERMAL
PROCHOT#
ICH
THERMTRIP#
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SIGNALS
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
H1
E2
G5
H5
F21
E1
H_BREQ#
F1
D20
H_INIT#
B3
H4
H_CPURST#
C1
F3
F4
G3
G2
G6
HIT#
E4
AD4
AD3
AD1
AC4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
TCK
XDP_TDI
AA6
TDI
XDP_TDO
AB3
TDO
XDP_TMS
AB5
TMS
XDP_TRST#
AB6
C20
D21
A24
B25
R140 510Ω 5% 1/16W SMT040 2 LR
C7
A22
A21
Rout to TP via and place gnd via w/in 100mils
U36B
D[0]#
D[1]#
D[2]#
DATA GRP 0
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
DATA GRP 1
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
MISC
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
Merom Ball-out Rev 1a
B
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
DATA GRP 2DATA GRP 3
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
H_DPRSTP#
E5
H_DPSLP#
B5
D24
H_PWRGD
D6
H_CPUSLP#
D7
PSI#
AE6
PSI#
H_D#[63..0]
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#[63..0]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
R119 27.4Ω 1% 1/10W SMT0603 LR
COMP1
R118 54.9Ω 1% 1/16W SMT0402 LR Sn
COMP2
R150 27.4Ω 1% 1/10W SMT0603 LR
COMP3
R142 54.9Ω 1% 1/16W SMT0402 LR Sn
H_DPRSTP# (41)
H_DPSLP# (24)
H_DPWR# (13)
PSI# (41)H_BSEL2(11)
H_PWRGD rise time :
Max : 15ns
C
Topology : FERR#
H_ADS# (13)
H_BNR# (13)
H_BPRI# (13)
H_DEFER# (13)
H_DRDY# (13)
H_DBSY# (13)
R124 51Ω 5% 1/16W SMT0402 LR
Should be connect to ICH8M and Crestline without T-ing(no stub)
H_BREQ# (13)
H_INIT# (24,31 )
H_LOCK# (13)
H_CPURST# (13)
H_RS#0 (13)
H_RS#1 (13)
H_RS#2 (13)
H_TRDY# (13)
H_HIT# (13)
H_HITM# (13)
1.05VDDM
R122
RES 75Ω 5% 1/16W SMT 0402 LR
0'' ~ 3''
H_PROCHOT#
H_THERMDA (10)
H_THERMDC (10)
CPU_BCLK (11)
CPU_BCLK# (11)
XDP P/U & P/D
R146 54.9Ω 1% 1/16W SMT0402 LR Sn(NU)
XDP_BPM#5
XDP_TDI
R149 54.9Ω 1% 1/16W SMT0402 LR Sn
R147 75Ω 1% 1/10W SMT0603 LR(NU)
XDP_TDO
XDP_TMS
R148 54.9Ω 1% 1/16W SMT0402 LR Sn
R144 54.9Ω 1% 1/16W SMT0402 LR Sn
XDP_TCK
XDP_TRST#
R145 649Ω 1% 1/10W SMT060 3 LR
1.05VDDM (9,13,15,24,31,46 )
X
1.05VDDM
"THERMDA" & "THERMDC" rount on same
layer trace 10 mil ,spacing 10 mil
Topology : PWRGOOD
Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#
Topology : THERMTRIP#
1.05VDDM
FSB Common Clock Signal Layout Guide :
H_D#[63..0] (13)
H_DSTBN#2 (13)
H_DSTBP#2 (13)
H_DINV#2 (13)
H_D#[63..0] (13)
H_DSTBN#3 (13)
H_DSTBP#3 (13)
H_DINV#3 (13)
H_PWRGD (39)
H_CPUSLP# (16,24)
H_FERR#
3VDDM
R665
10KΩ 5% 1/16W SMT0402 LR
Q58
TRANS NPN MMBT2222A 40V 600mA SOT-23 3PIN PSI LR
E C
B
1KΩ 5% 1/16W SMT0402 LR
R547
FERR# (24)
1.05VDDM
1.05VDDM
R151 470Ω 5% 1/16W SMT040 2 LR
H_DPRSTP#
Q19
DPRSLPVR(24,41)
Comp0,2 connect with Zo=27.4ohm, make
trace length shorter than 0.5" and width is
18mils.
Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils
B
E C
TRANS NPN MMBT3904 40V 200mA SOT-23 3PIN PSI LR
C
D
VCCP=1.05VDDM
ICH8MCPU
VCCP
CPU IMVP6
Rtt
L4
CPU
ICH8M
L1
L1
GMCHL2CPU ICH7m
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
RS[2..0]# , TRDY# , RESET#.
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
Strip-line(Int. Layer)
Micro-strip(Ext. Layer)
FSB So urce S ynchr onous Data Length Variation and Strobe Matching Requirements :
Signals Name
DATA#[15..0] , DINV0#
DATA#[31..16] , DINV1# +/- 100 mils
DATA#[47..32] , DINV2#
DATA#[63..48] , DINV3#
FSB Source Synchronous Data Signal Routing Topology#1 :
Signal Name
DINV#[3..0]
DATA#[63..0]
DSTBN#[3..0]
DSTBP#[3..0]
FSB So urce S ynchr onous Addres s Leng th Variation and Strobe Matching Requirements :
A#[16..3] , REQ#[4..0]
*** No length matching requirements exist between ADSTB0# and ADSTB1#
FSB Source Synchronous Address Signal Routing :
Signal Name
Address#[31..3]
REQ#[4..0]
ADSTB#[1..0]
VCCP L1
Rtt
L2
0.5" - 12"L1
VCCP
Rtt
L2+L1 L3 Strip-line
L1
Transmission Line
Micro-strip
0.5" - 12"
0.5" - 12" Strip-line
Transmission Line
L1CPU ICH8M
0.5" - 12" Micro-strip
Strip-line
0.5" - 12"
VCCP
RttL1 L4
Rtt
L3
1.0 ~ 6.5 inch 55+/-15%
Signals Matching
+/- 100 mils
+/- 100 mils
Transmission Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Total Trace Length
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
Signals MatchingSignals Name
+/- 200 mils
Transmission Line Type
Strip-line
Strip-line
Total Trace Length Normal Impedance
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
D
Rtt Transmission Line
L2
56 +/-5%
0" - 3.0" Microstrip0.5" - 12"
0" - 3.0"
0.5" - 6.5"
0.5" - 6.5"
56 +/-5%
L3 L4
0" - 3.0"
0" - 3.0"
Stripline
0" - 3.0"
0" - 3.0"
Rtt Transmission LineL2L1
Micro-strip75 +/-5%0.5" - 6.5"
75 +/-5%0.5" - 6.5"
Topology : CPUSLP#
GMCH
L1
Topology : RESET#
GMCH
L1
L1 L2
1" - 6" 0" - 3.0"
1" - 12"
1" - 12" 1" - 6"
Proces sor ITP Signal Default Strapping When ITP-XDP &
ITP700FLEX Dedbug Port Not Used.
Signal Resistor Value Connect To Resistor Placement
TDI
TMS
TRST#
TCK
TDO
Strobes associated with the group Strobe-to-Strobe Complement Matching
DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#
L3
L1+L3
1" - 12"
0" - 3.0"
1" - 12"
0" - 3.0"
54.9 OHM +/-5%
54.9 OHM +/-5%
649 OHM +/-5%
54.9 OHM +/-5%
OPEN
4 & 8 mils
5 & 10 mils
Normal Impedance
55+/-15%
55+/-15%
55+/-15%
55+/-15%
Strobes associated with the group
ADSTB0#+/- 200 mils
ADSTB1#A#[31..17]
55+/-15%
55+/-15%
55+/-15%Strip-line
1.05VDDM(9,13,15,24,31,46)
3VDDM(11,15,16,17,18,20,21,22,23,24,25,28,29,30,31,32,34,37,39,41,45,46 ,47)
1.05VDDM
Title
3VDDM
Size Document Number Rev
Date: Sheet
Rss
24 +/-5%
24 +/-5% 56 +/-5%
VCCP
VCCP
GND
GND
NC
+/- 25 mils+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils
Width & Spacing (mils)
Data-to-Data,Strobe-to-strobe Strobe-to-Data
4 & 8 mils
4 & 8 mils
4 & 12 mils
4 & 12 mils
Strobe to As soc. Address Signal Matching
+/- 200 mils
+/- 200 mils
Width & Spacing (mils)
4 & 8 mils
4 & 8 mils
4 & 8 mils
VY240D (Merom + VIA VN896 + VT8237A)
C
Merom Processor (1/2)
E
Transmission Line
L1CPU
0.5" - 12"
Micro-strip
Strip-line
0.5" - 12"
Transmission LineCPU
L1
Micro-strip
1" - 6"
Strip-line
1" - 6"
Transmission LineL4
Rtt
56 +/-5%
Micro-strip
Strip-line0" - 3.0"
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
N/A
N/A
N/A
4 & 12 mils
4 & 12 mils
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751 -8751
8 49Saturday, January 19, 2008
E
of
0.1
A
B
C
D
E
Place these inside socket cavity on L8
(North side secondary)
VCORE_CPU
4 4
HFM
ICC=41A
3 3
2 2
C199 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C193 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C190 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C185 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C180 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C204 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
Place these inside socket cavity on L1
(North side Primary)
C578 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C587 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C585 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C575 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C601 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C598 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C208 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C213 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
Place these inside socket cavity on
L8 (South side secondary)
C181 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C205 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C186 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C191 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
Place these inside socket cavity on L1
(South side Primary)
C577 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C584 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C600 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C214 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C200 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C194 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C597 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C209 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C586 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C574 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
U36C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
H_VID0 (41)
H_VID1 (41)
H_VID2 (41)
H_VID3 (41)
H_VID4 (41)
H_VID5 (41)
H_VID6 (41)
1.05VDDM
ICCP=4.5A,180mils
C211 0.1uF 16V ±10% SMD0603 X7R LR
C212 0.1uF 16V ±10% SMD0603 X7R LR
C182 0.1uF 16V ±10% SMD0603 X7R LR
12
12
12
VCORE_CPU
C158 T220uF 2.5V ±20% 9mΩ SMT7343 H=1.9mm V CASE A705V227M002ASE009 SDK(SDK-CAP) LR
C183 0.1uF 16V ±10% SMD0603 X7R LR
12
1.5VDDM
C567 0.01uF 16V 10% SMT0402 X7R LR
R755
100Ω 1% 1/16W SMT0402 LR(NU)
R756
100Ω 1% 1/16W SMT0402 LR(NU)
Place these inside socket cavity on L8
(North side secondary)
ICCA=130mA, 20mils
C566 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
VCCSENSE (41)
VSSSENSE (41)
Place Cap
Close To pin
B26
U36D
A4
VSS[001]
VSS[082]
A8
VSS[083]
VSS[002]
A11
A14
A16
A19
A23
AF2
B11
B13
B16
B19
B21
B24
C11
C14
C16
C19
C22
C25
D11
D13
D16
D19
D23
D26
E11
E14
E16
E19
E21
E24
F11
F13
F16
F19
F22
F25
G23
G26
H21
H24
J22
J25
K23
K26
L21
L24
M22
M25
N23
N26
VSS[084]
VSS[003]
VSS[085]
VSS[004]
VSS[086]
VSS[005]
VSS[087]
VSS[006]
VSS[088]
VSS[007]
VSS[089]
VSS[008]
B6
VSS[090]
VSS[009]
B8
VSS[091]
VSS[010]
VSS[092]
VSS[011]
VSS[093]
VSS[012]
VSS[094]
VSS[013]
VSS[095]
VSS[014]
VSS[096]
VSS[015]
VSS[097]
VSS[016]
C5
VSS[098]
VSS[017]
C8
VSS[099]
VSS[018]
VSS[100]
VSS[019]
VSS[101]
VSS[020]
VSS[102]
VSS[021]
VSS[103]
VSS[022]
C2
VSS[104]
VSS[023]
VSS[105]
VSS[024]
VSS[106]
VSS[025]
D1
VSS[107]
VSS[026]
D4
VSS[108]
VSS[027]
D8
VSS[109]
VSS[028]
VSS[110]
VSS[029]
VSS[111]
VSS[030]
VSS[112]
VSS[031]
VSS[113]
VSS[032]
VSS[114]
VSS[033]
VSS[115]
VSS[034]
E3
VSS[116]
VSS[035]
E6
VSS[117]
VSS[036]
E8
VSS[118]
VSS[037]
VSS[119]
VSS[038]
VSS[120]
VSS[039]
VSS[121]
VSS[040]
VSS[122]
VSS[041]
VSS[123]
VSS[042]
VSS[124]
VSS[043]
F5
VSS[125]
VSS[044]
F8
VSS[126]
VSS[045]
VSS[127]
VSS[046]
VSS[128]
VSS[047]
VSS[129]
VSS[048]
VSS[130]
VSS[049]
F2
VSS[131]
VSS[050]
VSS[132]
VSS[051]
VSS[133]
VSS[052]
G4
VSS[134]
VSS[053]
G1
VSS[135]
VSS[054]
VSS[136]
VSS[055]
VSS[137]
VSS[056]
H3
VSS[138]
VSS[057]
H6
VSS[139]
VSS[058]
VSS[140]
VSS[059]
VSS[141]
VSS[060]
J2
VSS[142]
VSS[061]
J5
VSS[143]
VSS[062]
VSS[144]
VSS[063]
VSS[145]
VSS[064]
K1
VSS[146]
VSS[065]
K4
VSS[147]
VSS[066]
VSS[067]
VSS[148]
VSS[149]
VSS[068]
L3
VSS[150]
VSS[069]
L6
VSS[151]
VSS[070]
VSS[152]
VSS[071]
VSS[153]
VSS[072]
M2
VSS[154]
VSS[073]
M5
VSS[155]
VSS[074]
VSS[156]
VSS[075]
VSS[157]
VSS[076]
N1
VSS[158]
VSS[077]
N4
VSS[159]
VSS[078]
VSS[160]
VSS[079]
VSS[080]
VSS[161]
P3 A25
VSS[081] VSS[162]
VSS[163]
Merom Ball-out Rev 1a
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50mil spacing.
Place PU and PD within 1 inch of CPU
1 1
Title
VY240D (Merom + VIA VN896 + VT8237A)
Size Document Number Rev
C
Yonah Processor (2/2)
A
B
C
D
Date: Sheet
1.05VDDM(8,13,15,24,31,46)
1.5VDDM(15,16,19,28,30,46)
VCORE_CPU(41)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
E
9 49Saturday, January 19, 2008
1.05VDDM
1.5VDDM
VCORE_CPU
of
0.1
8
7
6
5
4
3
2
1
D D
30mil
5VDDM
1000pF 50V 10% SMT0402 X7R LR (NU)
C C
C559
0Ω 5% 1/16W SMT0402 LR
FAN_PWM(39) FAN_SPEED(39)
Q52
TRANS M-FET-P APM2301AAC-TRL -20V -3A SOT23 3PIN ANPEC LR
DS
R504
G
1KΩ 5% 1/16W SMT0402 LR
R495
Q49
B
E C
C556
4.7uF 10V +80-20% 0805 Y5V LR(NU)
P N
NPN PDTC144EU SOT-323 PHILIPS LR
CN24
1
1
2
2
D9
DIODE ZENER GLZ6.2B 6.2V 20mA MIN I-MELF 2PIN PSI LR
30mil
345
345
CON HR A1250WV-S-03P SMD 3Pin P=1.25 Wire S/T LR
20-24197-30
THERMAL SENSOR
FAN connector
R87
B B
1/5 modify
SMCLK_PMU(39,42)
SMDAT_PMU(39,42)
10mil
10mil
LNR-IC Temperature Sensor G780P81U 3.0-5.5V MSOP-8 8PIN GMT LR
U7
8
SCLK
7
SDATA
6
ALRT#
1
VCC
2
D+
3
D-
45
THM#GND
HOT_DOWN#(39)
HOT_DOWN#
100Ω 5% 1/10W SMT060 3 LR
C122
0.1uF 16V 80-20% SMT0402 Y5V L R
C113
2200pF 50V 10% SMT0402 X7R LR
R82
10KΩ 5% 1/16W SMT0402 LR
5VDDM
H_THERMDA (8)
H_THERMDC (8)
3VDDA
10 mil
10 mil
10 mil
Minimum
10 mil
GND
THERMDA
THERMDC
GND
A A
Title
VY240D (Merom + VIA VN896 + VT8237A)
Size Document Number Rev
C
CPU Thermal
THER
8
7
6
5
4
3
Date: Sheet
2
3VDDA(20,22,23,24,25,26,28,30,32,39,45,47, 48)
5VDDM(21,23,32,33,35,36,4 5)
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)875 1-8751
1
3VDDA
5VDDM
10 49Saturday, January 19, 2008
of
0.1
5
SPWR 0 5% 1/16W 0603
L85
3VDDM
10pF 50V ±0.5pF SMT0402 NPO LR
C667
C664
D D
C C
H_BSEL0(8)
1KΩ 5% 1/16W SMT0402 LR
MMBT3904 40V 200mA SOT-23 PSI LR
B B
H_BSEL1(8)
1KΩ 5% 1/16W SMT0402 LR
MMBT3904 40V 200mA SOT-23 PSI LR
10pF 50V ±0.5pF SMT0402 NPO LR
X'TAL14.31818MHz SMD-49 2PIN 20pF ±30ppm XSA01431AFK1H-O H.ELE LR
33pF 50V 5% SMT0402 NPO LR(NU)
SMB_CLK(12,17,18,23,28,30)
SMB_DATA(12,17,18,23,28,30)
3VDDM
R760
R761
B
Q17
3VDDM
B
Q54
R111
10KΩ 5% 1/16W SMT0402 LR
E C
R529
10KΩ 5% 1/16W SMT0402 LR
E C
X1_CLK
Y6
X2_CLK
C287
C288
33pF 50V 5% SMT0402 NPO LR(NU)
G
G
R233 SHW 0 5% 1/16W 0402
R232 SHW 0 5% 1/16W 0402
R619 4.7KΩ 5% 1/16W SMT0402 LR
3VDDM
CLK_ENB(41)
FS0_A CLK66_2
DS
Q77
TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR
FS1_A
DS
Q78
TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR
3VDDM
U5
R57
10KΩ 1% 1/16W SMT0402 LR
A A
DISPCLKO(15)
5
SSON
1
VSS
SSON
2
NC
ModOUT
VDDCLKIN
ASIC Spread Spectrum for EMI ASM3P2598AF-06-OR TSOT-23 6PIN ALSC LR
05-23728-01
6
5
43
22Ω 1% 1/16W SMT0402 LR
R65
C79
0.1uF 16V 80-20% SMT0402 Y5V LR
4
3VDDM_CLK
C696 10uF 10V +80-20% SMT0805 Y5V LR
3VDDM
4
3
RP52
4.7KΩ 5% 1010 1/16W 4P2R LR(NU)
1
2
Q63
TRANS NPN RT1N441M-T111-1 50V 100mA SC-70 3PIN IDC LR
B
E C
DISPCLKI (15)
4
Pin & Cap. one by one
C682 0.01uF 50V +80-20% SMT0402 Y5V LR
C687 1uF 10V +80-20% 0603 Y5V LR
C683 0.01uF 50V +80-20% SMT0402 Y5V LR
C780
2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR(NU)
C678 0.01uF 50V +80-20% SMT0402 Y5V LR
C655 0.01uF 50V +80-20% SMT0402 Y5V LR
C680 0.01uF 50V +80-20% SMT0402 Y5V LR
C656 0.01uF 50V +80-20% SMT0402 Y5V LR
R632
10KΩ 5% 1/16W SMT0402 LR
R598
475Ω 1% 1/10W SMT0603 LR
Default
=======
AutoFS0
AutoFS1
Low
C679 0.01uF 50V +80-20% SMT0402 Y5V LR
C681 0.01uF 50V +80-20% SMT0402 Y5V LR
C657 0.01uF 50V +80-20% SMT0402 Y5V LR
X1_CLK
X2_CLK CPUC0
PCI6
FS0
FS1
FS2
FS3
PCI33_2
PCI33_3
PCI33_4
PCI33_5
MODE
SEL_48M
SCLK
SDAT
VTTPWRGD
IREF
ASIC CLOCK-G/Buffers ICS953009AFLF-T SSOP 56PIN ICS LR
R633 10KΩ 5% 1/16W SMT0402 LR
FS0
R525 10KΩ 5% 1/16W SMT0402 LR
FS1
R515 10KΩ 5% 1/16W SMT0402 LR
FS2
Reserve
H_BSEL2(8)
MMBT3904 40V 200mA SOT-23 PSI LR
FS4 FS3
0
0 0 1 66.67M
0 0
DISPCLKI, DISPCLKO
3
U40
6
X1
7
X2
1
VDDA
3
VDDREF
10
VDDPCI1
16
VDDPCI2
20
TURBO/PCI6
22
VDD48
26
VDD3V66
39
VDDPCIEX_1
45
VDDPCIEX_2
49
VDDCPU
4
FS0/REF0
5
FS1/REF1
11
FS2/PCI0
12
FS3/PCI1
13
PCI2/TB_EN
14
PCI3
17
PCI4
18
PCI5
23
48MHz/Mode0
24
SEL24_48#/24_48MHz
31
SCLK
48
SDATA
9
VTTPWGD/PD
21
RESET
55
IREF
Clock Layout :
1. Close to Clock generator
2. Trace as short as possible and use 12 mil
3. Place crystal within 500 mils of CLK Generator
MODE
FS3
FS4
R762
1KΩ 5% 1/16W SMT0402 LR
CPUT0
CPUC0
CPUT1
CPUC1
CPUT2/PCIEXT0
CPUC2/PCIEXC0
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
PCIEXT4/PEREQ1
PCIEXC4/PEREQ2
PCIEXT5/CPU_Stop
PCIEXC5/PCIEX_Stop
3V66_0
FS4/3V66_1
ITP_EN/3V66_2
GND
GNDREF
GNDPCI1
GNDPCI2
GND48
GND3V66
GNDPCIEX_1
GNDPCIEX_2
GNDCPU
GND
40
52
56
3VDDM
R522
10KΩ 5% 1/16W SMT0402 LR
B
E C
Q53
CPUT0
54
53
CPUT1
51
CPUC1
50
47
46
44
43
42
41
38
37
36
FS0_A
FS1_A
FS2_A
FS0_A
FS1_A
FS2_A
35
34
33
29
28
27
2
8
15
19
25
30
32
D45
D46
DIODE STKY RB751V-40 40V 200mA SOD-323 2PIN PSI LR(NU)
DIODE STKY RB751V-40 40V 200mA SOD-323 2PIN PSI LR(NU)
CLK66M#
FS4
CLK66_2
R759 10KΩ 5% 1/16W SMT0402 LR
R631 10KΩ 5% 1/16W SMT0402 LR
R519 1KΩ 5% 1/16W SMT0402 LR
R517 1KΩ 5% 1/16W SMT0402 LR
R516 1KΩ 5% 1/16W SMT0402 LR(NU)
R634 10KΩ 5% 1/16W SMT0402 LR(NU)
R627 10KΩ 5% 1/16W SMT0402 LR(NU)
R639 0Ω 5% 1/16W SMT0402 LR(NU)
R521 0Ω 5% 1/16W SMT0402 LR(NU)
R524 0Ω 5% 1/16W SMT0402 LR
R638 10KΩ 5% 1/16W SMT0402 LR
R626 10KΩ 5% 1/16W SMT0402 LR
DS
Q79
TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR(NU)
G
DIP SWITCH
pin1
pin2pin3
FS0
FS2
FS1
1
00 1
0
0 1
0
0
GND Shielding
GND Shielding 5 mil space
0
0
1
1
3
CPU
100.00M
133.33M
166.67M
200.00M
0
10 mil space
10 mil space
PCI
AGP
66.67M 33.33M 14.318M
66.67M
33.33M
33.33M
33.33M
66.67M
5 mil space
5 mil space
2
RP53
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
RP49
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
RP50
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
RP71
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR(NU)
RP51
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
CLKREQ1# (28)
CLKREQ2# (30)
PCI-E modify (AP403)
P N
P N
Jack suggest 10/12
PM_STPCPU# (23)
PM_STPPCI# (23)
3VDDM
R699 10KΩ 5% 1/16W SMT0402 LR
R700 10KΩ 5% 1/16W SMT0402 LR
3VDDM
FS2_A
REF
14.318M
14.318M
14.318M
V
AutoFS0
VV
AutoFS1
V
2
1
HCLKNB (13)
HCLKNB# (13)
CPU_BCLK (8)
CPU_BCLK# (8)
PEXCLKP_NB (16)
PEXCLKN_NB (16)
CLK_PCIE_MINICARD (28)
CLK_PCIE_MINICARD# (28)
CLK_PCIE_MINI (30)
CLK_PCIE_MINI# (30)
R234 49.9Ω 1% 1/16W SMT0402 LR
R748 49.9Ω 1% 1/16W SMT0402 LR(NU)
R747 49.9Ω 1% 1/16W SMT0402 LR(NU)
R227 49.9Ω 1% 1/16W SMT0402 LR
R226 49.9Ω 1% 1/16W SMT0402 LR
FS1
FS0
MODE
CLK66_2
CLK66_2
FS2
FS3
PCI33_2
PCI33_4
PCI33_5
CLK66M_NB
CLK66M_SB
R229 49.9Ω 1% 1/16W SMT0402 LR
R230 49.9Ω 1% 1/16W SMT0402 LR
R228 49.9Ω 1% 1/16W SMT0402 LR
R235 49.9Ω 1% 1/16W SMT0402 LR
22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
CLK14M_SB
CLK14M_GUI
CLK48M_SB
CLK33M_SB
CLK33M_EC
CLK33M_MINI
CLK33M_FWH
R231 49.9Ω 1% 1/16W SMT0402 LR
RP64
124
3
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
R630 RES 33Ω 1% 1/16W SMT 0402 LR
RP63
124
124
RP66
22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
R635 RES 33Ω 1% 1/16W SMT 0402 LR(NU)
RP65
124
33Ω 5% SMT1010 1/16W 4P2R RS2N-33R0-J2N CYNTEC LR
C353 22pF 50V 5% SMT0402 NPO LR
C354 22pF 50V 5% SMT0402 NPO LR
C691 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C690 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C694 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C688 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C689 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C693 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C692 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
Title
Size Document Number Rev
C
CLKG
Date: Sheet
CLK66M_NB
CLK66M_SB
3
3
3
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Clock Generator
CLK14M_SB (23)
CLK14M_GUI (15)
CLK48M_SB (22)
CLK66M_NB (16)
CLK66M_SB (24)
CLK33M_SB (24)
CLK33M_EC (39)
CLK33M_APIC (24)
CLK33M_FWH (31)
CLK33M_MINI (28)
3VDDM(8,15,16,17,18,20,21,22,23,24,25,28,29,30,31,32,34,37,39,41,45,46,47)
1
3VDDM
0.1
of
11 49Saturday, January 19, 2008
10
9
8
7
6
5
4
3
2
1
DDR CLOCK BUFFER
H H
1.8VDDM
L36
SPWR 0 5% 1/16W 0603
1.8VDDM_CLK
>40 mil
C630 0.1uF 16V 80-20% SMT0603 Y5V LR
C251 T10uF 10V ±20% SMT3216 ESR=4.0Ω T491A106M010AT KEMET LR
G G
C640 0.1uF 16V 80-20% SMT0603 Y5V LR
+
F F
E E
C650 0.1uF 16V 80-20% SMT0402 Y5V LR
SMB_DATA(11,17,18,23,28,30)
SMB_CLK(11,17,18,23,28,30)
DCLKO+(14)
DCLKO-(14)
2.5VDDM
C269 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C268 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
L92
SPWR 0 5% 1/16W 0603
0.1uF 16V 80-20% SMT0402 Y5V LR
100Ω 1% 1/16W SMT0402 LR
1.8VDDM_CLK
C627
C633
0.1uF 16V 80-20% SMT0402 Y5V LR
R195
For DDR DRAM
frequency
U38
21
VDD2.5/1.8
27
VDD2.5/1.8
10
VDD2.5/1.8
26
AVDD25
1
AVDD25
16
SDATA
15
SCLK
3
BUF_INT
4
BUF_INC
9
GND
22
GND
28
GND
25
AGND
2
AGND
ASIC CLOCK-BUFFER ICS9P936AFLF-T SSOP 28PIN ICS LR
FBOUT_T
FBOUT_C
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
DDRT0
5
DDRC0
6
DDRT1
7
DDRC1
8
DDRT2
13
DDRC2
14
DDRT3
18
DDRC3
17
20
19
24
23
11
12
RP45 22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
3
124
RP46 22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
3
124
RP48 22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
3
124
RP47 22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
124
3
R584 22Ω 1% 1/16W SMT0402 LR
C651
10pF 50V ±0.5pF SMT0402 NPO LR
DCLKI (14)
M_CLK_DDR1 (18)
M_CLK_DDR#1 (18)
M_CLK_DDR2 (17)
M_CLK_DDR#2 (17)
M_CLK_DDR3 (17)
M_CLK_DDR#3 (17)
M_CLK_DDR0 (18)
M_CLK_DDR#0 (18)
C647 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C634 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C638 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C636 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C653 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C652 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C648 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C649 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
22
10PF
L3: 4"
VIA
VN800
DIMM1 DIMM2
D D
C C
INPUT
FB_OUT
FB_IN
DDRCLK0
DDRCLK0#
DDRCLK1
DDRCLK1#
DDRCLK2
DDRCLK2#
L2: 6"
FWDSDCLKOU
22
L4: 12.6"
L4:L2+L3-L1+5.6"
10PF
0
L1=LMD1+LMD2
C_open
0
DDRCLK3
B B
DDRCLK3#
DDRCLK4
DDRCLK4#
DDRCLK5
DDRCLK5#
C_open
DDR Clock Buffer
A A
10
9
8
L3: 4"
1.8VDDM(47)
2.5VDDM(19,22,23,24,25,47)
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
CLKG
7
6
5
4
3
Date: Sheet
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
Clock Buffer
2
1.8VDDM
2.5VDDM
12 49Saturday, January 19, 2008
1
0.1
of
10
9
8
7
6
5
4
3
2
1
H H
Place these parts near N.B
as close as possible.
C65 0.01uF 50V +80-20% SMT0402 Y5V LR
C62 0.1uF 16V 80-20% SMT0402 Y5V LR
C66 0.01uF 50V +80-20% SMT0402 Y5V LR
C57 0.01uF 50V +80-20% SMT0402 Y5V LR
C58 0.01uF 50V +80-20% SMT0402 Y5V LR
C59 0.01uF 50V +80-20% SMT0402 Y5V LR
C67 10uF 10V +80-20% SMT1206 Y5V LR
C49 10uF 10V +80-20% SMT1206 Y5V LR
C63 0.01uF 50V +80-20% SMT0402 Y5V LR
C501 1uF 10V +80-20% 0603 Y5V LR
C48 10uF 10V +80-20% SMT1206 Y5V LR
G G
F F
E E
D D
close to N/B
Close to Ball, 20mil width
1.05VDDM
R64
49.9Ω 1% 1/10W SMT0603 LR
R61 100Ω 1% 1/10W SMT0603 LR
GTLVREF
C70 0.01uF 16V 10% SMT0402 X7R LR
C94 0.01uF 16V 10% SMT0402 X7R LR
C C
B B
Place these parts near N.B
as close as possible. And
place each capacitor per
pin.
C44 10uF 10V +80-20% SMT1206 Y5V LR
C43 10uF 10V +80-20% SMT1206 Y5V LR
C509 10uF 10V +80-20% SMT1206 Y5V LR
C42 10uF 10V +80-20% SMT1206 Y5V LR
A17
A18
A19
H_A#[31..3](8)
H_CPURST#(8)
HCLKNB(11)
HCLKNB#(11)
R60 180Ω 1% 1/10W SMT0603 LR
R59 RES 360Ω 1% 1/10W SMT 0603 LR
1.05VDDM
H_A#[31..3]
H_ADSTB#0(8)
H_ADSTB#1(8)
H_ADS#(8)
H_BNR#(8)
H_BPRI#(8)
H_BREQ#(8)
H_DBSY#(8)
H_DEFER#(8)
H_DRDY#(8)
H_HIT#(8)
H_HITM#(8)
H_LOCK#(8)
H_TRDY#(8)
H_REQ#0(8)
H_REQ#1(8)
H_REQ#2(8)
H_REQ#3(8)
H_REQ#4(8)
H_RS#0(8)
H_RS#1(8)
H_RS#2(8)
H_DINV#0(8)
H_DINV#1(8)
H_DINV#2(8)
H_DINV#3(8)
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
GTLCOMPP
GTLCOMPN
U32A
M33
HA03#
N34
VTT_1
VTT_2
VTT_3
HA04#
R33
HA05#
T33
HA06#
R34
HA07#
P36
HA08#
P34
HA09#
N35
HA10#
R36
HA11#
U36
HA12#
U34
HA13#
U35
HA14#
T30
HA15#
U32
HA16#
W35
HA17#
V32
HA18#
V36
HA19#
V34
HA20#
W36
HA21#
W34
HA22#
AA36
HA23#
V33
HA24#
AA34
HA25#
Y35
HA26#
Y33
HA27#
AA32
HA28#
W32
HA29#
V31
HA30#
W31
HA31#
Y31
HA32#
Y31, AB31 no pad on VN896
AB31
HA33#
R35
HADSTB0P#
W33
HADSTB1#
L35
ADS#
K35
BNR#
J32
BPRI#
M34
BREQ0#
K32
DBSY#
J33
DEFER#
K33
DRDY#
L36
HIT#
L34
HITM#
J34
HLOCK#
M35
HTRDY#
T32
HREQ0#
T31
HREQ1#
R32
HREQ2#
M32
HREQ3#
M31
HREQ4#
J35
RS0#
N36
RS1#
J36
RS2#
C31
HDBI0#
E35
HDBI1#
G27
HDBI2#
D22
HDBI3#
F22
CPURST#
AC29
HCLK+
AC30
HCLK-
U30
GTLVREF0
J25
GTLVREF1
G22
GTLCOMPP
H22
GTLCOMPN
ASIC NB VN896 HSBGA 951PIN VER:CD VIA LR
GND
GND
GND
GND
A1A2A8
A3
1.05VDDM
B17
B18
B19
B20
B21
C17
C18
C19
C20
C21
D17
D18
D19
D20
D21
E17
E18
E19
E20
E21
F17
F18
F19
F20
F21
G17
G18
G19
G20
A20
A21
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
Rev1.9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B2B3B4
A10
A22
A25
A27
B36C2C3C4C5E6C26
A29
A31
A33
A35
C27
D3
D4D5D6D8D11
GND
G21
B35
HD00#
A36
HD01#
C33
HD02#
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
C32
HD03#
E31
HD04#
B34
HD05#
B33
HD06#
A34
HD07#
D30
HD08#
A30
HD09#
B31
HD10#
B30
HD11#
E30
HD12#
C29
HD13#
B29
HD14#
C30
HD15#
D36
HD16#
F36
HD17#
G36
HD18#
H34
HD19#
H35
HD20#
F35
HD21#
G35
HD22#
C36
HD23#
D35
HD24#
F34
HD25#
F33
HD26#
G34
HD27#
G33
HD28#
E33
HD29#
H32
HD30#
G32
HD31#
E28
HD32#
E29
HD33#
D28
HD34#
D27
HD35#
C28
HD36#
H28
HD37#
G28
HD38#
F28
HD39#
E27
HD40#
D26
HD41#
D25
HD42#
E25
HD43#
F25
HD44#
G25
HD45#
H26
HD46#
H25
HD47#
B23
HD48#
B25
HD49#
E23
HD50#
B27
HD51#
B28
HD52#
A28
HD53#
B24
HD54#
B26
HD55#
A26
HD56#
C23
HD57#
C22
HD58#
A23
HD59#
G23
HD60#
A24
HD61#
B22
HD62#
E22
HD63#
A32
HDSTB0P#
B32
HDSTB0N#
C35
HDSTB1P#
C34
HDSTB1N#
G26
HDSTB2P#
E26
HDSTB2N#
C24
HDSTB3P#
C25
HDSTB3N#
T35
HADSTB0N#
L31
DPWR#
GND
GND
GND
D23
D24
GND
GND
GND
GND
GND
GND
GND
GND
D29
D31
D32
D34E2E4
E5
H_D#[63..0]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
01-23694-01 for A1 version
01-23694-02 for A2 version
01-23694-03 for A3 version
H_DSTBP#0 (8)
H_DSTBN#0 (8)
H_DSTBP#1 (8)
H_DSTBN#1 (8)
H_DSTBP#2 (8)
H_DSTBN#2 (8)
H_DSTBP#3 (8)
H_DSTBN#3 (8)
H_DPWR# (8)
H_D#[63..0] (8)
2006.10.15
1.05VDDM(8,9,15,24,31,46)
1.05VDDM
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
A A
10
9
8
7
6
5
4
3
Title
Size Document Number Rev
C
NBCC
Date: Sheet
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
VN896 Host ( 1/4 )
2
13 49Saturday, January 19, 2008
of
1
0.1
10
9
8
7
6
5
4
3
2
1
H H
Place these parts near N.B
1.8VDDS
> 80MIL
G G
M_DQ[63..0](17,18)
F F
E E
D D
C C
M_DM[7..0](17,18)
M_DQ0
M_DQ1
M_DQ2
M_DQ3
M_DQ4
M_DQ5
M_DQ6
M_DQ7
M_DQ8
M_DQ9
M_DQ10
M_DQ11
M_DQ12
M_DQ13
M_DQ14
M_DQ15
M_DQ16
M_DQ17
M_DQ18
M_DQ19
M_DQ20
M_DQ21
M_DQ22
M_DQ23
M_DQ24
M_DQ25
M_DQ26
M_DQ27
M_DQ28
M_DQ29
M_DQ30
M_DQ31
M_DQ32
M_DQ33
M_DQ34
M_DQ35
M_DQ36
M_DQ37
M_DQ38
M_DQ39
M_DQ40
M_DQ41
M_DQ42
M_DQ43
M_DQ44
M_DQ45
M_DQ46
M_DQ47
M_DQ48
M_DQ49
M_DQ50
M_DQ51
M_DQ52
M_DQ53
M_DQ54
M_DQ55
M_DQ56
M_DQ57
M_DQ58
M_DQ59
M_DQ60
M_DQ61
M_DQ62
M_DQ63
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
AF35
AG34
AJ36
AK35
AF34
AG35
AJ34
AK34
AG32
AF32
AH30
AJ31
AF31
AH32
AH31
AJ32
AK33
AL36
AP35
AL34
AL35
AM35
AT36
AM34
AK24
AL23
AM24
AJ22
AK23
AN24
AM23
AM22
AK20
AK19
AM19
AR18
AL20
AM20
AL18
AM18
AR17
AT16
AN16
AN15
AM17
AP17
AM16
AM15
AN22
AN21
AP19
AT18
AT21
AR21
AT19
AR19
AR14
AM14
AP13
AR11
AP14
AN14
AT12
AP12
AH36
AF30
AN36
AN23
AN20
AT15
AP21
AT13
U32B
MD00
MD01
MD02
MD03
MD04
MD05
MD06
MD07
MD08
MD09
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM0#
DQM1#
DQM2#
DQM3#
DQM4#
DQM5#
DQM6#
DQM7#
AC24
AD17
AD19
AD21
AJ28
AK25
AK27
AK29
AL26
AL28
AL30
AM25
AM29
AM31
AN26
AN27
AA24
AB24
VCCMEM
VCCMEM
AD23
AD24
AJ26
AD22
AD20
AD16
AD18
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
AN31
AM27
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
AT35
AN33
AP30
AR26
AR33
AT25
AT28
AT31
M_BA0
AR28
BA0
M_BA1
AP29
BA1
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
M_BA2
AP33
BA2
M_A0
AT29
MA00
M_A1
AR30
MA01
M_A2
AR29
MA02
M_A3
AT30
MA03
M_A4
AN30
MA04
M_A5
AP31
MA05
M_A6
AR31
MA06
M_A7
AT32
MA07
M_A8
AP32
MA08
M_A9
AN32
MA09
M_A10
AN29
MA10
M_A11
AR32
MA11
M_A12
AT33
MA12
M_A13
AR25
MA13
M_RAS#
AN28
SRAS#
M_CAS#
AR27
SCAS#
M_WE#
AP28
SWE#
AT27
CS0#
AP27
CS1#
AT24
CS2#
AP26
CS3#
AT34
CKE0
AP34
CKE1
AR34
CKE2
AN34
CKE3
AT26
ODT0
AP25
ODT1
AR24
ODT2
AN25
ODT3
DQS0+
DQS0-
DQS1+
DQS1-
DQS2+
DQS2-
DQS3+
DQS3-
DQS4+
DQS4-
DQS5+
DQS5-
DQS6+
DQS6-
DQS7+
DQS7-
MCLKI
MCLKO+
MCLKO-
MEMVREF0
MEMVREF1
MEMDET
DMCOMP
M_DQS0
AJ35
M_DQS#0
AH35
M_DQS1
AH33
M_DQS#1
AH34
M_DQS2
AR36
M_DQS#2
AP36
M_DQS3
AR22
M_DQS#3
AP23
M_DQS4
AP18
M_DQS#4
AN18
M_DQS5
AP15
M_DQS#5
AR15
M_DQS6
AP20
M_DQS#6
AR20
M_DQS7
AR12
M_DQS#7
AR13
AB34
RP38 22Ω 5% SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
AB35
AB36
AG29
AJ18
AF36
AM33
124
MEMVREF
MEMDET
DMCOMP
3
R508
10KΩ 5% 1/16W SMT0402 LR
R108
301Ω 1% 1/10W SMT0603 LR
M_BA0 (17,18)
M_BA1 (17,18)
M_BA2 (17,18)
M_A[13..0] (17,18)
M_RAS# (17,18)
M_CAS# (17,18)
M_WE# (17,18)
M_CS#0 (17,18)
M_CS#1 (17,18)
M_CS#2 (17)
M_CS#3 (17)
M_CKE0 (17,18)
M_CKE1 (17,18)
M_CKE2 (17)
M_CKE3 (17)
M_ODT0 (17,18)
M_ODT1 (17,18)
M_ODT2 (17)
M_ODT3 (17)
1.8VDDS
DCLKI (12)
DCLKO+ (12)
DCLKO- (12)
as close as possible. And
place each capacitor per
pin.
C170 1uF 10V +80-20% 0603 Y5V LR
C169 1uF 10V +80-20% 0603 Y5V LR
C139 1uF 10V +80-20% 0603 Y5V LR
C138 1uF 10V +80-20% 0603 Y5V LR
C162 0.1uF 16V 80-20% SMT0402 Y5V LR
C120 0.1uF 16V 80-20% SMT0402 Y5V LR
C121 0.1uF 16V 80-20% SMT0402 Y5V LR
C151 0.1uF 16V 80-20% SMT0402 Y5V LR
M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7
M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7
DCLKI = L_DDR + 2".
DCLKO as short as possible.
M_DQS[7..0]
M_DQS#[7..0]
70 ohm
M_DQS[7..0] (17,18)
M_DQS#[7..0] (17,18)
C174 4.7uF 10V +80-20% 0805 Y5V LR
C172 10uF 10V +80-20% SMT0805 Y5V LR
C147 0.01uF 50V +80-20% SMT0402 Y5V LR
C112 0.01uF 50V +80-20% SMT0402 Y5V LR
C142 0.01uF 50V +80-20% SMT0402 Y5V LR
C173 4.7uF 10V +80-20% 0805 Y5V LR
close to N/B
Close to Ball, 20mil width
C148 0.1uF 10V 10% SMT0402 X5R LR
C133 0.1uF 10V 10% SMT0402 X5R LR
1.8VDDS
C140 1uF 10V 10% SMT0603 X5R C1608X5R1A105KT TDK LR
R93
150Ω 1% 1/10W SMT0603 LR
R96 150Ω 1% 1/10W SMT0603 LR
MEMDET
ASIC NB VN896 HSBGA 951PIN VER:CD VIA LR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B B
E7
E9
GND
E34
E36F1F2F4F5F6F7
GND
F10
F14
F23
F26
F27
F29
F30
F32G1G2G4G7
G11
G29H2H4H7H23
H24
F24
H27
H31
GND
H36J2J4J5J6
H33
GND
J7
A A
10
9
8
7
6
0 =>DDR
1=>DDR2
1.8VDDS(16,17,18,47,48)
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
NBCC
5
4
3
Date: Sheet
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
VN896 DDR2 ( 2/4 )
2
1.8VDDS
14 49Saturday, January 19, 2008
1
0.1
of
10
9
8
7
6
5
4
3
2
1
1.5VDDM
H H
3VDDM
SPWR 0 5% 1/16W 0603
L69
> 20 mil
G G
3VDDM
SPWR 0 5% 1/16W 0603
L68
> 20 mil
F F
E E
VCC_DAC1
C506
1uF 10V 10% SMT0603 X5R C1608X5R1A105KT TDK LR
C515
0.1uF 10V 10% SMT0402 X5R LR
VCC_DAC2
C505
1uF 10V 10% SMT0603 X5R C1608X5R1A105KT TDK LR
C512
0.1uF 10V 10% SMT0402 X5R LR
width = 10mils
VL_PAR(24)
RED(21)
GREEN(21)
BLUE(21)
HSYNC(21)
VSYNC(21)
PCI_IRQA#(22)
ENVEE(19)
R50
GPOUT(19)
82Ω 1% 1/10W SMT0603 LR
CLK14M_GUI(11)
D D
C85 0.01uF 16V 10% SMT0402 X7R LR
C86 0.01uF 16V 10% SMT0402 X7R LR
VL_PAR
VCC_DAC1
VCC_DAC2
RSET
VCC_PLL1
VCC_PLL2
VCC_PLL3
AM1
AM3
AT5
AM6
AL2
AL1
AN6
AT6
AM4
C14
D14
E14
E12
F12
A13
A12
B13
B12
C13
H13
B8
A6
D12
A16
A15
A14
B16
B15
B14
3VDDM
SPWR 0 5% 1/16W 0603
L66
> 20 mil
C C
VCC_PLL1
10uf for 3D test issue
C500
C514
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
0.1uF 10V 10% SMT0402 X5R LR
3VDDM
SPWR 0 5% 1/16W 0603
L67
> 20 mil
B B
VCC_PLL2
C499
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C513
0.1uF 10V 10% SMT0402 X5R LR
10uf for 3D test issue
3VDDM
SPWR 0 5% 1/16W 0603
L70
A A
10
> 20 mil
C516
0.1uF 10V 10% SMT0402 X5R LR
9
VCC_PLL3
10uf for 3D test issue
C507
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
8
3VDDM
N15
N16
N17
U18
U19
U20
U21
U22
U23
U31
U33V2V5V7V14
GND
GND
GND
GND
GND
GND
GND
VCC33GFX
VCC33GFX
VCC33GFX
VD08
VD09
VD10
VD11
VD12
VD13
VD14
VD15
VPAR
AR
AG
AB
HSYNC
VSYNC
VCCA33DAC1
VCCA33DAC2
GNDADAC
GNDADAC
RSET
INTA#
GPO0
GPOUT
XIN
VCCA33PLL1
VCCA33PLL2
VCCA33PLL3
GNDAPLL
GNDAPLL
GNDAPLL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P21
P22
P35
R5R6R7
R14
R15
R16
P33
TV_D10
TV_D4
TV_D5
TV_D6
TV_D7
R2R4P23
R17
R43 10KΩ 5% 1/16W SMT0402 LR(NU)
R39 10KΩ 5% 1/16W SMT0402 LR(NU)
R37 10KΩ 5% 1/16W SMT0402 LR
R47 10KΩ 5% 1/16W SMT0402 LR
R42 10KΩ 5% 1/16W SMT0402 LR(NU)
R41 10KΩ 5% 1/16W SMT0402 LR
R35 10KΩ 5% 1/16W SMT0402 LR(NU)
R36 10KΩ 5% 1/16W SMT0402 LR(NU)
R40 10KΩ 5% 1/16W SMT0402 LR
R44 10KΩ 5% 1/16W SMT0402 LR
7
V15
V16
V17
V18
V19
V20
V22
V21
V23
V30
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ASIC NB VN896 HSBGA 951PIN VER:CD VIA LR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R23
R30
R31T2T4T5T7
GND
T14
T15
GND
R18
R19
R20
R21
R22
3VDDM
6
V35W2W5W7W14
GND
GND
GND
GND
T16
T17
W15
W16
W17
W18
W19
W20
W21
W22
W23
Y2
D13
F13
C12
U32D
H11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T18
T19
T20
T21
T22
T23
T34
T36U2U5U7U14
FP00
GND
GND
GND
GND
GND
GND
GND
GND
D10
FP01
C11
FP02
C10
FP03
E10
FP04
G10
FP05
F11
FP06
C9
FP07
E8
FP08
B7
FP09
F9
FP10
C7
FP11
C6
DVPDET
A5
DVP0VS
B9
FPCLK0
D9
FPDEN0
A9
FPDET0
E11
FPHS0
B10
FPVS0
LCD_SPCLK
C8
SPCLK1
SPCLK2
DISPCLKO
DISPCLKI
ENVDD
GND
GND
GND
GND
GND
GND
GND
U15
U16
U17
SPD1
SPD2
BUSY#
ENBLT
VECLK
G13
LCD_SPDAT
A7
VEDAT
E13
AC35
R58
H12
22Ω 5% 1/16W SMT0402 LR Sn
G12
A11
B11
3VDDM
RP1 10KΩ 5% SMT1010 1/16W 4P2R LR
VECLK
124
VEDAT
LCD_SPCLK
LCD_SPDAT
FD4 => port Muxing
0: Two 12-bit DVI interface (VT1637)
1: One 24-bit Panel interface(VT1634AL)
FD5 => Dedicate DVI Port Configuration
0: TMDS(DVI)
1: TV Encoder(TV)
FD6 => Dedicated DVI Port Selection
0: Disable(DVI)
1: Enable(TV)
FD7 => GFX clock select(Vck/LCDCK/ECK)
0: Refer Internal PLL(Default)
1: From External
FD10 => CPUCK/MCK clock select
0: From NB(Default)
1: From External
3
RP34 4.7KΩ 5% 1010 1/16W 4P2R LR
124
3
check with VIA FAE
5
RP32
TV_D3TV_D3
1
TV_D2
2
TV_D1
3
TV_D0
10KΩ 5% SMT2010 1/16W 8P4R LR
RP31
TV_D8
1
TV_D9
2
3
TV_D11
10KΩ 5% SMT2010 1/16W 8P4R LR
TV_D0
TV_D1
TV_D2
TV_D3
TV_D4
TV_D5
TV_D6
TV_D7
TV_D8
TV_D9
TV_D10
TV_D11
ENBKL (39)
ENVDD (19,20)
4
8
7
6
54
8
7
6
54
LCD_SPCLK (20)
VECLK (21)
LCD_SPDAT (20)
VEDAT (21)
AGP_BUSY# (24)
1.05VDDM(8,9,13,24,31,46)
1.5VDDM(9,16,19,28,30,46)
3VDDM(8,11,16,17,18,20,21,22,23,24,25,28,29,30,31,32,34,37,39,41,45,46,47)
C77 0.1uF 16V 80-20% SMT0402 Y5V LR
C75 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C105 0.1uF 16V 80-20% SMT0402 Y5V LR
C87 0.1uF 16V 80-20% SMT0402 Y5V LR
DISPCLKO (11)
DISPCLKI (11)
C71 MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C152 0.01uF 50V +80-20% SMT0402 Y5V LR
C570 0.01uF 50V +80-20% SMT0402 Y5V LR
C128 0.01uF 50V +80-20% SMT0402 Y5V LR
C108 0.01uF 50V +80-20% SMT0402 Y5V LR
C78 0.01uF 50V +80-20% SMT0402 Y5V LR
C111 0.01uF 50V +80-20% SMT0402 Y5V LR
C156 0.1uF 16V 80-20% SMT0402 Y5V LR
C80 0.01uF 50V +80-20% SMT0402 Y5V LR
C126 0.1uF 16V 80-20% SMT0402 Y5V LR
C161 0.1uF 16V 80-20% SMT0402 Y5V LR
C127 0.1uF 16V 80-20% SMT0402 Y5V LR
C90 0.1uF 16V 80-20% SMT0402 Y5V LR
1.05VDDM
C84 0.1uF 16V 80-20% SMT0402 Y5V LR
C100 0.1uF 16V 80-20% SMT0402 Y5V LR
C88 0.1uF 16V 80-20% SMT0402 Y5V LR
1.05VDDM
1.5VDDM
3VDDM
3
U32E
M17
M18
M19
N18
N19
GND
VTT
VTT
VTT
VTT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ASIC NB VN896 HSBGA 951PIN VER:CD VIA LR
GND
GND
GND
GND
GND
GND
AJ23
AJ20
AJ19
AJ33
AK17
AK18
AK22
Title
Size Document Number Rev
NBCC
Date: Sheet
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA31
AA33
AA35
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AD32
AE32
AE34
AG30
AG31
AG33
AG36
Y5
Y6
Y7
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y30
Y32
Y34
Y36
AA2
AA4
AA5
AA7
AB2
AB4
AB5
AB7
AC2
AC5
AC6
AC7
AD2
AD5
AE2
AE5
AF2
AF3
AF5
AG2
AG3
AG4
AG5
T24
R24
N22
N23
N24
P24
N20
N21
U24
V24
W24
Y24
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AK32
AL16
AL15
AK36
AL3
AL7
GND
GND
GND
GND
GND
GND
GND
GND
AN13
AN12
AM36
AL33
AL24
AL22
AL19
AL17
AM2
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
VY240D (Merom + VIA VN896 + VT8237A)
C
VN896 VIDEO ( 3/4 )
2
C176
T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
C160 0.1uF 16V 80-20% SMT0402 Y5V LR
C93 0.1uF 16V 80-20% SMT0402 Y5V LR
C571 0.1uF 16V 80-20% SMT0402 Y5V LR
+
AE14
AE16
AE18
AE20
AE21
AE22
AJ10
AJ11
AJ12
AJ13
AJ14
AK9
AK10
AK11
AK12
AK13
AK15
AL8
AL9
AL10
AL11
AL12
AL14
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AN7
AN8
AN9
AN10
AN11
AP7
AP8
AP9
AP10
AP11
AR7
AR8
AR9
AR10
AT7
AT8
AT9
AT10
AN17
AN19
AN35
AP2
AP3
AP6
AP16
AP22
AP24
AR2
AR6
AR16
AR23
AR35
AT4
AT11
AT14
AT17
AT20
AT22
AT23
GND
15 49Saturday, January 19, 2008
1
0.1
of
Loading...