first international computer VME40 Schematics
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First International Computer,Inc
D D
Portable Computer Group HW Department
Board name : MotherBoard Schematic
Project :
C C
Version : 0.3
VME40
Initial Date : 04/28/ 2009
B B
Manager Sign by: AVERY/RICHARD
Drawing by : Chris
A A
Total confirm by: RICHARD
檔
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet of
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Title
1
Confidential
1 47Friday, September 04, 2009
0.1
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3. Block Diagram :
6
5
VME40
0.1
4
3
2
1
D D
C C
B B
CLKGEN
RTM875N-606-VD-GR
RTC Bat
Reset Circuit
LED / DIP SW
Lid Switch
MAIN SW
ALCOR
AU6433
P4
P32
CardReader
4 in 1
P32
P18
P20
P23
P26
P30
CCD
P31
Bluetooth
eSATA
CDROM
HDD
Thermal Sensor
G780
CRT
LCD
USB X2 USB/B
P31
P5
S5
P28
P27
P27
SATA BUS
S0
SATA BUS
S1
SATA BUS
P9
P25
P24
USB 2.0
P0,P1 P2P9P3
P47
(667/800 MHz)
USB X1 M/B
P28
Intel
Penryn
Processor
FSB
Intel NB
Cantiga (G)MCH
GL40
P10~15
DMI
(x4)
Intel SB
ICH9M
P19~22
LPC BUS
P7,8
Mem_A Bus
Mem_B Bus
USB 2.0
PCIE-2
PCIE-3
PCIE-6
PCIE-1
CPU
CORE
P44
CPU
VCCP
P44
DDR2 667/800 MHz
DDRII SODIMM0 (A)
DDR2 667/800 MHz
DDRII SODIMM1 (B)
Mini Card (WLAN)
P7
Mini Card (Robson)
P8
LAN Chip
RTL8111DL-GR 10/100/1G
RTL8103EL-GR 10/100
Express Card
P6
P2231NF ENE
P31
P16
P17
P29
P29
P33
SIM Card
P29
RJ-45
P34
Flash ROM
BIOS
ACIN / DCIN
3VDD/5VDD
1.8 VDDS
A A
1.5/0.9/1.05 VDDM
CPU CORE
P41
P42
P43
P44
P44
P44
P23
SPI
PMX
MB90F372
Glide PadInt. KB
P30
P37
P30
Azalia CodecCharger
ALC272
AMP
APA2068KAI
P35
P35
Head Phone
Speaker
1.5W
P36
Azalia
8
7
6
5
4
3
P36
MDC
ML3054
Mic In
RJ-11
P28
P36
USB/B
P47
First International Computer, Inc.
P36
Title
Size Document Number Rev
C
Date: Sheet of
2
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Block Diagram
2 47Friday, September 04, 2009
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5
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4. Nat name Description :
1. Title
2. Block Diagram
3. ANNOTATIONS
Voltage Rails
DCIN
PMU5V 5.0V always on power rail by LATCH or ACIN
D D
PMU3V 3.3V always on power rail by LATCH or ACIN
5VDDA
3VDDA
3VDDM
1.5VDDM
VCC_CORE
1.05VDDM
1.8VDDS
0.9VDDT_DDRII
Primary DC system power supply
3.3V power rail by PSUSC#
5.0V power rail by PSUSC#
3.3V switched power rail by SUSTAT_B#
5.0V switched power rail by SUSTAT_B#5VDDM
1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE
for ICH7m by SUSTAT_B#
Core Voltage for CPU
1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#
1.8V power rail for DDRII by PSUSC#
0.9V DDRII Termination Voltage by SUSTAT_B#
Part Naming Conventions
C
=
Capacitor
CN
D
F
L
C C
Q
R
RP
U
Y
Connector
=
=
Diode
Fuse
=
Inductor
=
Transistor
=
Resistor
=
Resistor Pack
=
Arbitrary Logic Device
=
Crystal and Osc
=
Net Name Suffix
# =
Active Low signal
4. DDRII Layout Guideline
5. Timing Diagram
6. Schematic Modify
7. Penryn Processor(1/2)
8. Penryn Processor(2/2)
9. CPU Thermal
10. Candiga GL40 Host(1/6)
11.Candiga GL40 DMI/Graphic(2/6)
12. Candiga GL40 DDRII(3/6)
13. Candiga GL40 Power(4/6)
14. Candiga GL40 Power(5/6)
15. Candiga GL40 GND(6/6)
16. DDRII SDRAM SO-DIMM0
17. DDRII SDRAM SO-DIMM1
18. Clock Generator
19. ICH9M PCI/PCIE/DMI(1/4)
20. ICH9M CPU/IDE/SATA(2/4)
21. ICH9M GPIO(3/4)
22. ICH9M Power/GND(4/4)
23. Bios / Reset Circuit
24. LCD CNN
25. CRT CNN
26. DIP SW / LED / LID SW
27. HDD CNN / ODD CNN
5. Board Stack up Description
28. USB / MDC / ESATA
29. Mini-WLAN / 3G module
30. INT KB / GP / POW / MMB
PCB Layers
B B
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Single End Impedance
Host Clock
SRC Clock
Host Bus
DDR2 CLK
DDR2 Strobe
DDR2 Bus
DMI Bus
PCIE Bus
A A
SATA
SDVO
LVDS
USB
IEEE1394
Lan
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
42 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
50 ohm +/- 15%
8
Differential Impedance for Microstrip
95 ohm +/- 15%
95 ohm +/- 15%
70 ohm +/- 20%
95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%
Component Side, Microstrip signal Layer
Ground Plane
Stripline Layer(High Speed)
Stripline Layer(High Speed)
Power Plane
Solder Side,Microstrip signal Layer
Differential Impedance for Stripline
100 ohm +/- 15%
100 ohm +/- 15%
70 ohm +/- 20%
85 ohm +/- 20%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%
7
6
5
4
31. Express Card / CCD / BT
32. Card-Reader AU6433
33. LAN RTL8111DL
34. TRANSFORMER
35. Azalia ALC272 Codec
36. HP / MIC
37. PMX
38. Screw Hole
39. block
40. Power Block
41. ADPIN, BATIN, DCIN
42. Charger
43. 3/5VDDA/S/M , PMU3/5V
44. 1.8V , 0.9 / 1.05 / 1.5 VDDM
45. CPU CORE
46. MMB Board
47. USB Board
3
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet of
2
(886-2) 8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Annotations
3 47Friday, September 04, 2009
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8. Layout Guideline :
Crestline DDRII Layout Guidelines
DDRII Signal Groups
Group Signal Name
D D
Data
SA_DQ[63..0]/SB_DQ[63..0]
SA_DM[7..0]/SB_DM[7..0]
SA_DQS[7..0]/SA_DQS#[7..0]
SB_DQS[7..0]/SB_DQS#[7..0]
SA_MA[13..0]/SB_MA[13..0]Address
SA_BS[2..0]/SB_BS[2..0]
SA_RAS#/SB_RAS#
SA_CAS#/SB_CAS#
SA_WE#/SB_WE#
SM_CS#[3..0]Control
SM_CKE[3..0]
SM_ODT[3..0]
Clock SM_CK[3..0]
SM_CK#[3..0]
SA_RCVENOUT#/SB_RCVENOUT#FeedBack
SA_RCVENIN#/SB_RCVENIN#
CLK group : SM_CK[3..0],SM_CK#[3..0]
4/4/12 7/4/16 8/5/15
GMCH
C C
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width Inner Layer : 7 mils
Nominal CK to CK# Sp acing
(edge to edge)
Minimum Serpentine Spacing Inner Layer : 12 mils
Minimum Spacing to Other DDR2 Inner Layer : 16 mils
Minimum Isolation Spacing to non-DDR2 25 mils
Package Length Range - P1 1000 mils +/- 250 mils
Trace Length Limit - L0 Max = 50 mils (Escape)
Trace Length Limit - L1 Max = 500 mils (Breakout)
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils
B B
Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5 mils
Clock to Clock Length Match
(Total Length)
Breakout Exceptions (R educe geometries
for GMCH break-out region)
Breakin Exception s (Reduce geometries
for SO-DIMM break-in region)
Feedback group :
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#
These signals are routed internally on the GMCH package and don't require an y
routing on the MB. As a result, can be left as NC.
A A
4/4
P1P1L0L0L1L1L2L2S1
Escape Breakout Breakin
SLMS SL MS
5
Length Matching and Length Formulas
Signal Group Minimum Length Maximum Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe
Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Strobe - 220mils
SO-DIMM
S1
Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%
Outer Layer : 8 mils
Inner Layer : 4 mils
Outer Layer : 5 mils
Outer Layer : 15 mils
Outer Layer : 20 mils
Max = 4000 mils
Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1
Total Length for Channel A : X0
Total Length for Channel B : X1
Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils
Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2
Max. breakout length is 500 m ils
CK to CK# spacing rule waived at
connector spacing of 15 mils to
other DDR2
Max. breakin length is 2 00 mils
Clock - 0.0"
Clock + 1.0"
Clock + 1.0"
Strobe - 180mils
4
Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]
8/5/15
7/4/16
GMCH
P1
Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width
Minimum CTRL Trace Spac ing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Parallel Termination Resistor 56 +/- 5%
Maximim Via Count
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)
Command group :
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#
GMCH
P1
Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width
Minimum CMD Bus Trace Spacing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Trace Length L3
Parallel Termination Resistor
Maximim Via Count
CTRL to SCK/SCK # Length Matching
(Total Length including package)
for GMCH break-out region)
4/4/12
Escape
L1
L0
Breakout
SL
MS SL/MS
4/4
L1
Breakout
4/6,5/10
SL/MSMS SL
Escape
L0
L2
L3
SL/MS
S1
MS
SO-DIMM
Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 8 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 200 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 milsTrace Length L3
3
(CLK-1.0") </= CTRL </= (CLK-0.0")
Inner Layer : 4 mils spacing allowe d
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 m ils
4/6,5/10
L3
L2
SL/MS
S1
MS
SO-DIMM
Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 6 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 mils
56 +/- 5%
3
(CLK-1.0") </= CM D </= (CLK+1.0")
Inner Layer : 4 mils spacing allowe dBreakout Exceptions (R educe geometries
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 m ils
3
Vtt
Vtt
Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]
4/6
GMCH
P1 L0
4/4
Escape
L1
L2
Breakout
MS SLSL MS
S1
SO-DIMM
Topology
Reference Plane
Characteri stic Trace Impedance
Nominal Trace Width
Minimum DQ Bus Trace Spacing
Minimum Serpentine Spacing Same as DQ-to-DQ r outing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Trace Length L3
Maximim Via Count
DQ/DM to DQS Length Matching
(Total Length including
Breakout Exceptions (R educe geometries
package)
for GMCH break-out region)
Point-to-Point
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 6 mils
Outer Layer : 8 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 mils
2
Match DQ/DM to [SDQS - 200mils]
+/- 20mils, per byte lane
Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mi ls
Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#
GMCH
P1
P1
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width
Nominal DQS to DQS# Spacing
(edge to edge)
Minimum Serpentine Spacing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length Range - P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Maximim Via Count
DQS to DQS# Length Matching
Clock to Clock Length Match
(Total Length include package)
Breakout Exceptions (R educe geometries
for GMCH break-out region)
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)
Escape
L0
L0
4/4/8
L1
L1
Breakout
SL SL MS
4/4/12
L2
L2
SO-DIMM
5/5/10
S1
S1
Breakin
Differential Pair Point-to-Point
Ground
55 +/- 15%
85 +/- 20%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacin g
Outer Layer : 15 mils
Inner Layer : 8 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
2 (Per side)
Match total length to within 5 mils
(CLK-0.5") </= D QS </= (CLK+1.0")
Inner Layer : 8 mils to other DDR2
Outer Layer : 10 mils to other DDR2
Max. breakout length is 500 mi ls
DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2
Max. breakin length is 2 00 mils
2
Title
Size Document Number Rev
Date: Sheet of
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
C
DDRII Layout Guideline
1
4 47Friday, September 04, 2009
0.1
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5
4
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7. power on & off & S3 Sequence :
S3 SUSPEND AND RESUME TIMING
Power On Sequencing Timing Diag ram
D D
20060117A - DATA FROM NO.16809
PSI#
VID
t
SFT_START_VCC
VR_ON
-12%
t
-12%
t
Vccp_UP
BOOT
t
BOOT-VID-TR
V
CC-CORE
t
C C
CPU_UP
V
CCP
CPU_UP
Vccp_UP
-12%
V
CC_MCH
MCH_PWRGD
t
B B
MCH-PWRGD
CLK_ENABLE#
IMVP6_PWRGD
t
SFT_START_VCC
t
BOOT
t
BOOT-VID-TR
t
A A
CPU_UP
t
Vccp_UP
t
MCH-PWRGD
t
CPU_PWRGD
5
Max = 3 ms
Min = 10 us , Max = 100 us
Max = 100 us
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Min = 3 ms , Max = 20 ms
t
CPU_PWRGD
4
POWSW0
PMU5V/PMU3V
PM_RSMRST0
PM_SLP_S30
PM_SLP_S40/S50
SUSTAT_B0
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP,1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGOOD
PCI_RST0
AGTL+_CPURST0
BATTERY ONLY POWER ON TIMING
PMU5V/PMU3V
MAINSW0_ICH
PM_RSTRST0
PM_SLP_S30/S40/S50
SUSTAT_B0
VDDM,VDDS
SYS_PWROK
VRON_VCCP
VCCP/1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGD
PCI_RST0
AGTL+_CPURST0
DCON
VDDA
PSUSC0
VDDS
VDDM
VR_ON
POWSW0
DCON
VDDA
PSUSC0
PM_PWROK
VR_ON
H
H
H
H
H
H
H
3
To ICH4_M
From ICH4_M
From ICH4_M
From ASIC_B0
From ASIC_B0
1.5VDDS AND
DDR_PWRGD
Generator
To clock
ToICH4 and ODEM
From ICH4 to CPU
To ODEM/other
PCI device
From ODEM to CPU
To ICH4
To ICH4
From ICH4
From ASIC_B0
From ASIC_B0
To clock generator
To ODEM and ICH4
From ICH4 to CPU
To ODEM/other PCI device
From ODEM to CPU
IMVP6 Power On Sequencing Timing Diagram
VID
VR_ON
Vcc-core
CPU_UP
Vccp
Vccp_UP
Vccgmch
GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD
2
Tsft_star_vcc(3ms max)
Tboot
Tcpu_up
Tvccp_up
Tgmch_pwrgd
Title
Size Document Number Rev
C
Date: Sheet of
Vid
Vboot
Tboot-vid-tr(100uS max)
Tboot:10-100uS
Tcpu_pwrgd(3~20mS)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Timing Diagram
1
5 47Friday, September 04, 2009
0.1
檔
5
4
3
2
1
6.Schematic modify Item and History :
D D
C C
B B
A A
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Penryn+Candiga GL40+ICH9M(VME40)
Size Document Number Rev
C
5
4
3
2
Date: Sheet of
(886-2) 8751-8751
Schematic Modify
1
6 47Friday, September 04, 2009
0.1
檔
A
H_ADSTB#1(10)
H_A20M#(20)
H_FERR#(20)
H_IGNNE#(20)
H_STPCLK#(20)
H_INTR(20)
H_NMI(20)
H_SMI#(20)
H_QCTHERMDA(9)
H_QCTHERMDC(9)
4
3
0Ω 5% SMT1010 1/16W 4P2R LR(NU)
1
2
H_A#[35..3]
H_REQ#[4..0]
H_A#[35..3]
RP24
R19651Ω 5% 1/16W SMT0402 LR(NU)
R19251Ω 5% 1/16W SMT0402 LR(NU)
R21751Ω 5% 1/16W SMT0402 LR(NU)
H_QCBPM2
TDO_M
TDI_M
U35A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Penryn Ball-out Rev 1a
ADDR GROUP
0
ADDR GROUP
1
ICH
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_QCBPM1
H_QCBPM0
H_GTLREF2
Rout to TP via and place gnd via w/in 100mils
H_A#[35..3](10)
4 4
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
1.05VDDM
3 3
1.05VDDM
1.74KΩ 1% 1/10W SMT0603 LR(NU)
1.05VDDM
H_REQ#[4..0](10)
H_A#[35..3](10)
R259 1KΩ 1% 1/16W SMT0402 LR(NU)
R258
R212
51Ω 5% 1/16W SMT0402 LR(NU)
For Q.C CPU
A#[32-39], APM#[0-1]:Leave escape routing on for future functionality
H_D#[63..0](10)
2 2
H_DSTBN#0(10)
H_DSTBP#0(10)
H_DINV#0(10)
H_D#[63..0](10)
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
R172 1KΩ 1% 1/16W SMT0402 LR
1.05VDDM
1 1
2KΩ 1% 1/16W SMT0402 LR
For D.C 2K
For Q.C 1.74K
A
H_DSTBN#1(10)
H_DSTBP#1(10)
H_DINV#1(10)
12
R167
H_D#[63..0]
H_D#[63..0]
R229 1KΩ 5% 1/16W SMT0402 LR(NU)
R208 1KΩ 5% 1/16W SMT0402 LR(NU)
C211
0.1uF 10V 10% 0402 X5R LR(NU)
Place C181 close to the CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference to GND
and away from other nossy signale.
CPU_BSEL0(18)
CPU_BSEL1(18)
H_GTLREF
TEST3
TEST5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
XDP/ITP SIGNALS
DBR#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
U35B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
Penryn Ball-out Rev 1a
B
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
For Q.C CPU
DATA GRP 0
DATA GRP 1
MISC
B
H_IERR#
H_BPM0
H_BPM1
H_BPM2
H_BPM3
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
PWRGOOD
R213 56Ω 5% 1/16W SMT0402 LR
R159 51Ω 5% 1/16W SMT0402 LR(NU)
R166 51Ω 5% 1/16W SMT0402 LR(NU)
R169 51Ω 5% 1/16W SMT0402 LR(NU)
R162 51Ω 5% 1/16W SMT0402 LR(NU)
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
R543
100Ω 1% 1/16W SMT0402 LR(NU)
H_D#32
Y22
D[32]#
H_D#33
AB24
D[33]#
H_D#34
V24
D[34]#
H_D#35
V26
D[35]#
H_D#36
V23
D[36]#
H_D#37
T22
D[37]#
H_D#38
U25
D[38]#
H_D#39
U23
D[39]#
H_D#40
Y25
D[40]#
H_D#41
W22
D[41]#
H_D#42
Y23
D[42]#
H_D#43
W24
D[43]#
H_D#44
W25
D[44]#
H_D#45
AA23
D[45]#
H_D#46
AA24
D[46]#
H_D#47
AB25
D[47]#
Y26
AA26
U22
H_D#48
AE24
D[48]#
H_D#49
AD24
D[49]#
H_D#50
AA21
D[50]#
H_D#51
AB22
D[51]#
H_D#52
AB21
D[52]#
H_D#53
AC26
D[53]#
H_D#54
AD20
D[54]#
H_D#55
AE22
D[55]#
H_D#56
AF23
D[56]#
H_D#57
AC25
D[57]#
H_D#58
AE21
D[58]#
H_D#59
AD21
D[59]#
H_D#60
AC22
D[60]#
H_D#61
AD23
D[61]#
H_D#62
AF22
D[62]#
H_D#63
AC23
D[63]#
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
DPWR#
D6
D7
SLP#
AE6
PSI#
H_PWRGD rise time :
Max : 15ns
C
H_ADS# (10)
H_BNR# (10)
H_BPRI# (10)
H_DEFER# (10)
H_DRDY# (10)
H_DBSY# (10)
For D.C 56
H_BREQ# (10)
For Q.C 50
H_INIT# (20)
H_LOCK# (10)H_ADSTB#0(10)
H_RS#0 (10)
H_RS#1 (10)
H_RS#2 (10)
H_TRDY# (10)
H_HIT# (10)
H_HITM# (10)
1.05VDDM
1.05VDDM
H_CPURST# (10)
EMI
C310
1000pF 25V +80-20% SMT0603 Y5V LR(NU)
For Q.C 51
1.05VDDM
R218
68Ω 5% 1/16W SMT0402 TIN LR
0'' ~ 3''
H_THERMDA (9)
H_THERMDC (9)
PM_THRMTRIP# (11,20)
CLK_CPU_BCLK (18)
CLK_CPU_BCLK# (18)
R221 0Ω 5% 1/16W SMT0402 LR(NU)
Should be connect to ICH8M and Crestline without T-ing(no stub)
XDP P/U & P/D
XDP_DBRESET#
XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TCK
XDP_TRST#
H_D#[63..0]
H_D#[63..0]
R190 27.4Ω 1% SMT 0402 LR
R187 54.9Ω 1% 1/16W SMT0402 LR Sn
R180 27.4Ω 1% SMT 0402 LR
R181 54.9Ω 1% 1/16W SMT0402 LR Sn
H_DPRSTP# (11,20,45)
H_DPSLP# (20)
H_DPWR# (10)
H_CPUSLP# (10)
PSI# (45)CPU_BSEL2(18)
EMI
R257 1KΩ 5% 1/16W SMT0402 LR(NU)
R183 54.9Ω 1% 1/16W SMT0402 LR Sn
R185 54.9Ω 1% 1/16W SMT0402 LR Sn
R173 54.9Ω 1% 1/16W SMT0402 LR Sn
R176 54.9Ω 1% 1/16W SMT0402 LR Sn
R178 54.9Ω 1% 1/16W SMT0402 LR Sn
H_D#[63..0] (10)
H_DSTBN#2 (10)
H_DSTBP#2 (10)
H_DINV#2 (10)
H_D#[63..0] (10)
Comp0,2 connect with Zo=27.4ohm, make trace
length shorter than 0.5" and width is 18mils.
Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils
H_DSTBN#3 (10)
H_DSTBP#3 (10)
H_DINV#3 (10)
R26,AA1 For D.C 27.4 For Q.C 25.9
U26,Y1 For D.C 54.9 For Q.C 50
H_PWRGD (20)
C337
1000pF 25V +80-20% SMT0603 Y5V LR(NU)
C
H_PROCHOT# (45)
HOT_DOWN# (9,37)
D
Topology : FERR#
VCCP
Rtt
L4
VCCP=1.05VDDM
ICH8MCPU
CPU IMVP6
VCCP L1
Rtt
L2
0.5" - 12"L1
VCCP
Rtt
L2+L1 L3 Strip-line
Topology : PWRGOOD
CPU
L1
ICH8M
L1
Transmission Line
Micro-strip
0.5" - 12"
0.5" - 12" Strip-line
Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#
Transmission Line
L1CPU ICH8M
L1
Topology : THERMTRIP#
GMCHL2CPU ICH7m
0.5" - 12" Micro-strip
Strip-line
0.5" - 12"
VCCP
L3
RttL1 L4
3VDDM
1.05VDDM
FSB Common Clock Signal Layout Guide :
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
RS[2..0]# , TRDY# , RESET#.
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
Strip-line(Int. Layer)
Micro-strip(Ext. Layer)
FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :
Signals Name
DATA#[15..0] , DINV0#
DATA#[31..16] , DINV1# +/- 100 mil s
DATA#[47..32] , DINV2#
DATA#[63..48] , DINV3#
FSB Source Synchronous Data Signal Routing Topology#1 :
Signal Name
DINV#[3..0]
DATA#[63..0]
DSTBN#[3..0]
DSTBP#[3..0]
FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :
A#[16..3] , REQ#[4..0]
*** No length matching requirements exist between ADSTB0# and ADSTB1#
FSB Source Synchronous Address Signal Routing :
Signal Name
Address#[31..3]
REQ#[4..0]
ADSTB#[1..0]
1.0 ~ 6.5 inch 55+/-15%
Signals Matching
+/- 100 mils
+/- 100 mils
Transmission Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Signals MatchingSignals Name
+/- 200 mils
Transmission Line Type
Strip-line
Strip-line
D
Total Trace Length
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
Total Trace Length Normal Impedance
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
E
Rtt Transmission Line
L2
0" - 3.0" Microstrip0.5" - 12"
56 +/-5%
56 +/-5%
L3 L4
0" - 3.0"
0" - 3.0"
Stripline
0" - 3.0"
0" - 3.0"
Rtt Transmission LineL2L1
Micro-strip75 +/-5%0.5" - 6.5"
75 +/-5%0.5" - 6.5"
0" - 3.0"
0.5" - 6.5"
0.5" - 6.5"
Topology : CPUSLP#
Transmission Line
L1CPU
GMCH
0.5" - 12"
L1
0.5" - 12"
Micro-strip
Strip-line
Topology : RESET#
Transmission LineCPU
GMCH
L1
L1 L2
1" - 12"
Rtt
1" - 6" 0" - 3.0"
1" - 12" 1" - 6"
Processor ITP Signal Default Strapping When ITP-XDP &
ITP700FLEX Dedbug Port Not Used.
Signal Resistor Value Connect To Resistor Placement
TDI
TMS
TRST#
TCK
TDO
Strobes associated with the group Strobe-to-Strobe Complement Matching
DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#
Strobes associated with the group
ADSTB0#+/- 200 mils
ADSTB1#A#[31..17]
1.05VDDM(8,10,11,13,14,18,20,22,44)
3VDDM(9,11,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,39,43,44,45)
L3
L1+L3
0" - 3.0"
1" - 12"
0" - 3.0"
1" - 12"
54.9 OHM +/-5%
54.9 OHM +/-5%
649 OHM +/-5%
54.9 OHM +/-5%
OPEN
4 & 8 mils
5 & 10 mils
Normal Impedance
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%Strip-line
1.05VDDM
3VDDM
+/- 25 mils+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils
Width & Spacing (mils)
Data-to-Data,Strobe-to-strobe Strobe-to-Data
4 & 8 mils
4 & 8 mils
4 & 12 mils
4 & 12 mils
Strobe to Assoc. Address Signal Matching
+/- 200 mils
+/- 200 mils
Width & Spacing (mils)
4 & 8 mils
4 & 8 mils
4 & 8 mils
Title
Penryn+Candiga GL40+ICH9M(VME40)
Size Document Number Rev
C
Date: Sheet of
L1
1" - 6"
Micro-strip
Strip-line
1" - 6"
Rtt
Rss
56 +/-5%
24 +/-5%
24 +/-5% 56 +/-5%
VCCP
Within 2.0" of the CPU
VCCP
Within 2.0" of the CPU
GND
Within 2.0" of the CPU
GND
Within 2.0" of the CPU
NC
N/A
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
Merom Processor (1/2)
E
Transmission LineL4
Micro-strip
Strip-line0" - 3.0"
N/A
N/A
4 & 12 mils
4 & 12 mils
Confidential
7 47Friday, September 04, 2009
0.1
檔
A
B
C
D
E
Place these inside socket cavity on L8
(North side secondary)
VCORE_CPU
4 4
HFM
ICC=41A
3 3
2 2
C599 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C601 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C600 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
Place these inside socket cavity on L1
(North side Primary)
C571 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C572 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C617 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C227 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C619 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C618 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C597 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C231 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C228 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C234 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C233 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C232 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C598 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
North side secondary
South side secondary
Place these inside socket cavity on
L8 (South side secondary)
C229 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C620 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C291 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C288 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C289 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
Place these inside socket cavity on L1
(South side Primary)
C294 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C287 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C602 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C290 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C615 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C293 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C335 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C292 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C616 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C230 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C338 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
For D.C
0Ω 5% 1/16W SMT0402 LR
ICCP=4.5A,180mils
C261 0.1uF 16V ± 10% SMD0603 X7R LR
C284 0.1uF 16V ± 10% SMD0603 X7R LR
U35C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
BR1#
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Penryn Ball-out Rev 1a
R174
AB20
VCC[068]
AB7
VCC[069]
AC7
VCC[070]
AC9
VCC[071]
AC12
VCC[072]
AC13
VCC[073]
AC15
VCC[074]
AC17
VCC[075]
AC18
VCC[076]
AD7
VCC[077]
AD9
VCC[078]
AD10
VCC[079]
AD12
VCC[080]
AD14
VCC[081]
AD15
VCC[082]
AD17
VCC[083]
AD18
VCC[084]
AE9
VCC[085]
AE10
VCC[086]
AE12
VCC[087]
AE13
VCC[088]
AE15
VCC[089]
AE17
VCC[090]
AE18
VCC[091]
AE20
VCC[092]
AF9
VCC[093]
AF10
VCC[094]
AF12
VCC[095]
AF14
VCC[096]
AF15
VCC[097]
AF17
VCC[098]
AF18
VCC[099]
AF20
VCC[100]
G21
VCCP[01]
V6
VCCP[02]
J6
VCCP[03]
K6
VCCP[04]
M6
VCCP[05]
J21
VCCP[06]
K21
VCCP[07]
M21
VCCP[08]
N21
VCCP[09]
N6
VCCP[10]
R21
VCCP[11]
R6
VCCP[12]
T21
VCCP[13]
T6
VCCP[14]
V21
VCCP[15]
W21
VCCP[16]
B26
VCCA[01]
C26
VCCA[02]
AD6
VID[0]
AF5
VID[1]
AE5
VID[2]
AF4
VID[3]
AE3
VID[4]
AF3
VID[5]
AE2
VID[6]
AF7
VCCSENSE
AE7
VSSSENSE
0Ω 5% 1/16W SMT0402 LR
R164
ICCA=130mA, 20mils
Place C?
Close To pin
B26
H_VID0 (45)
H_VID1 (45)
H_VID2 (45)
H_VID3 (45)
H_VID4 (45)
H_VID5 (45)
H_VID6 (45)
For D.C 0
For Q.C 1.21K
R157
0Ω 5% 1/16W SMT0402 LR
VCORE_CPU
100Ω 1% 1/16W SMT0402 LR
1.05VDDM
C267 0.1uF 16V ± 10% SMD0603 X7R LR
C248 0.1uF 16V ± 10% SMD0603 X7R LR
C244 0.1uF 16V ± 10% SMD0603 X7R LR
C255 0.1uF 16V ± 10% SMD0603 X7R LR
1.5VDDM
C307
0.01uF 16V 10% SMT0402 X7R LR
R158
VCCSENSE (45)
VSSSENSE (45)
R160
100Ω 1% 1/16W SMT0402 LR
Place these inside socket cavity on L8
(North side secondary)
C278
+
T100uF 2V ± 20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
TDK
C309 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
For D.C ON
For Q.C NU
R225
0Ω 5% 1/16W SMT0402 LR
R211
0Ω 5% 1/16W SMT0402 LR
GTREF_CONT
U35D
A4
VSS[082]
VSS[001]
A8
VSS[002]
VSS[083]
A11
VSS[003]
VSS[084]
A14
VSS[004]
VSS[085]
A16
VSS[005]
VSS[086]
A19
VSS[006]
VSS[087]
A23
VSS[007]
VSS[088]
AF2
VSS[008]
VSS[089]
B6
VSS[009]
VSS[090]
B8
VSS[010]
VSS[091]
B11
VSS[011]
VSS[092]
B13
VSS[012]
VSS[093]
B16
VSS[013]
VSS[094]
B19
VSS[014]
VSS[095]
B21
VSS[015]
VSS[096]
B24
VSS[016]
VSS[097]
C5
VSS[017]
VSS[098]
C8
VSS[018]
VSS[099]
C11
VSS[019]
VSS[100]
C14
VSS[020]
VSS[101]
C16
VSS[021]
VSS[102]
C19
VSS[022]
VSS[103]
C2
VSS[023]
VSS[104]
C22
VSS[024]
VSS[105]
C25
VSS[025]
VSS[106]
D1
VSS[026]
VSS[107]
D4
VSS[027]
VSS[108]
D8
VSS[028]
VSS[109]
D11
VSS[029]
VSS[110]
D13
VSS[030]
VSS[111]
D16
VSS[031]
VSS[112]
D19
VSS[032]
VSS[113]
D23
VSS[033]
VSS[114]
D26
VSS[034]
VSS[115]
E3
VSS[035]
VSS[116]
E6
VSS[036]
VSS[117]
E8
VSS[037]
VSS[118]
E11
VSS[038]
VSS[119]
E14
VSS[039]
VSS[120]
E16
VSS[040]
VSS[121]
E19
VSS[041]
VSS[122]
E21
VSS[042]
VSS[123]
E24
VSS[043]
VSS[124]
F5
VSS[044]
VSS[125]
F8
VSS[045]
VSS[126]
F11
VSS[046]
VSS[127]
F13
VSS[047]
VSS[128]
F16
VSS[048]
VSS[129]
F19
VSS[049]
VSS[130]
F2
VSS[050]
VSS[131]
F22
VSS[051]
VSS[132]
F25
VSS[052]
VSS[133]
G4
VSS[053]
VSS[134]
G1
VSS[054]
VSS[135]
G23
VSS[055]
VSS[136]
G26
VSS[056]
VSS[137]
H3
VSS[057]
VSS[138]
H6
VSS[058]
VSS[139]
H21
VSS[059]
VSS[140]
H24
VSS[060]
VSS[141]
J2
VSS[061]
VSS[142]
J5
VSS[062]
VSS[143]
J22
VSS[063]
VSS[144]
J25
VSS[064]
VSS[145]
K1
VSS[065]
VSS[146]
K4
VSS[066]
VSS[147]
K23
VSS[148]
VSS[067]
K26
VSS[068]
VSS[149]
L3
VSS[069]
VSS[150]
L6
VSS[070]
VSS[151]
L21
VSS[071]
VSS[152]
L24
VSS[072]
VSS[153]
M2
VSS[073]
VSS[154]
M5
VSS[074]
VSS[155]
M22
VSS[075]
VSS[156]
M25
VSS[076]
VSS[157]
N1
VSS[077]
VSS[158]
N4
VSS[078]
VSS[159]
N23
VSS[079]
VSS[160]
N26
VSS[080]
VSS[161]
P3 A25
VSS[081] VSS[162]
VSS[163]
Penryn Ball-out Rev 1a
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
R175
AA8
0Ω 5% 1/16W SMT0402 LR
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
R171
AC8
0Ω 5% 1/16W SMT0402 LR
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
51Ω 5% 1/16W SMT0402 LR(NU)
AD25
AE1
AE4
H_QCBPM3
AE8
AE11
AE14
AE16
0Ω 5% 1/16W SMT0402 LR
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
R163
R165
1.5VDDM
For Q.C ON
Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50mil spacing.
Place PU and PD within 1 inch of CPU
1 1
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet of
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Merom Processor (2/2)
VCORE_CPU(45)
E
1.05VDDM(7,10,11,13,14,18,20,22,44)
1.5VDDM(13,14,19,20,22,29,31,44)
Confidential
8 47Friday, September 04, 2009
VCORE_CPU
1.05VDDM
1.5VDDM
0.1
檔
8
7
6
5
4
3
2
1
D D
Dual Core THERMAL SENSOR
Thermal sensor spec
20mil
THRM_VCC
SMCLK_PMU(30,37,41)
SMDAT_PMU(30,37,41)
3VDDM
C C
SMCLK_PMU
SMDAT_PMU
R262
10KΩ 5% 1/16W SMT0402 LR
10mil
TH_ALRT#
LNR-IC Temperature Sensor G780P81U 3.0-5.5V MSOP-8 8PIN GMT LR
10mil
U18
8
SCLK
7
SDATA
6
ALRT#
1
VCC
2
D+
3
D-
45
THM#GND
2200pF 50V 10% SMT0402 X7R LR
C347
10KΩ 5% 1/16W SMT0402 LR
R275
HOT_DOWN#
Quad Core THERMAL SENSOR
20mil
THRM_VCC
SMCLK_PMU
SMDAT_PMU
B B
10mil
10mil
TH_ALRT#
U17
8
SCLK
7
SDATA
6
ALRT#
LNR-IC Temperature Sensor G780-1P81U 3.0-5.5V MSOP-8 8PIN GMT LR(nu)
1
VCC
2
D+
3
D-
HOT_DOWN#
45
THM#GND
2200pF 50V 10% SM T0402 X7R LR(NU)
100Ω 5% 1/16W SMT0402 LR(NU)
C328
0.1uF 16V 80-20% SMT0402 Y5V LR(NU)
C343
R274
100Ω 5% 1/16W SMT0402 LR
C372
0.1uF 16V 80-20% 0402 Y5V LR
3VDDA
HOT_DOWN# (7,37)
R273
H_QCTHERMDA
H_QCTHERMDC
H_THERMDA (7)
H_THERMDC (7)
5VDDM
H_QCTHERMDA (7)
H_QCTHERMDC (7)
3VDDM
GND
10 mil
THERMDA
10 mil
Minimum
THERMDC
10 mil
10 mil
GND
FAN_PWM(37)
R137
5VDDM
MO-CAP 0.22uF 10V +80-20% SMT0402 Y5V LR(NU)
MO-CAP 2.2uF 6.3V 80-20% SMT0603 Y5V C1608Y5V0J225Z TDK LR
LNR-IC FAN DRIVER 1.6X G990P11U SOP-8 GMT LR(NU)
GND
10 mil
Minimum
10 mil
THERMDA
THERMDC
GND
10 mil
10 mil
3VDDM
R139
1KΩ 5% 1/16W SMT0402 LR(NU)
R138
0Ω 5% 1/16W SMT0402 LR
10KΩ 5% 1/16W SMT0402 LR(NU)
30mil
C171
PWM
CON Modify
CN21
20-22833-01
634
125
R152
PWM
C199
0Ω 5% 1/8W SMT0805 LR
Vo VsetVINVEN
123
45
VO
VIN
VEN
VSE TG ND
GND
GND
GND
678
GND
GNDGNDGND
30mil
U15
C180
MO-CAP 2.2uF 6.3V 80-20% SM T0603 Y5V C1608Y5V0J 225Z TDK LR
CON WAFER-M TIN SMT H=4.8mm 1ROW 4PIN 1.25mm 0° 5W1.2737C-11400.104 ARC LR
D18
DIODE ZENER GLZ6.2B 6.2V 20mA MINI-MELF 2PIN PSI LR (NU)
P N
FAN_SPEED(37)
3VDDM
3VDDM(7,11,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,39,43,44,45)
3VDDA
A A
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet of
2
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
CPU Thermal
3VDDA(18,19,20,21,22,23,24,28,29,30,31,33,37,41,43,44)
5VDDM
5VDDM(22,25,27,30,35,39,43,44,45)
Confidential
9 47Friday, September 04, 2009
1
0.1
檔
10
9
8
7
6
5
4
3
2
1
H H
H_A#[35..3]
H_REQ#[4..0]
G G
H_D#[63..0](7)
H_D#[63..0]
1.05VDDM
R539
RES 221Ω 1% 1/16W SMT0402 LR
H_SWING
F F
for D.C 100
for Q.C 75
for D.C 24.9
for Q.C 16.9
R540
100Ω 1% 1/16W SMT0402 LR
H_RCOMP
R535
RES 24.9Ω 1% 1/16W SMT0402 LR
C651
0.1uF 10V 10% 0402 X5R LR
10 mil wide / 20 mil spacing
E E
D D
H_SWING
H_RCOMP
C C
H_CPURST#(7)
1.05VDDM
H_CPUSLP#(7)
C312
0.1uF 10V 10% 0402 X5R LR(NU)
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
M11
N12
P13
N10
Y10
Y12
Y14
W2
AA8
AA9
AE9
AA2
AD8
AA3
AD3
AD7
AF3
AC1
AE3
AC3
AE8
AG2
AD6
C12
E11
A11
B11
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
Y9
C5
E3
U34A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA_1p0
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_A#4
C15
H_A#5
F16
H_A#6
H13
H_A#7
C18
H_A#8
M16
H_A#9
J13
H_A#10
P16
H_A#11
R16
H_A#12
N17
H_A#13
M13
H_A#14
E17
H_A#15
P17
H_A#16
F17
H_A#17
G20
H_A#18
B19
H_A#19
J16
H_A#20
E20
H_A#21
H16
H_A#22
J20
H_A#23
L17
H_A#24
A17
H_A#25
B17
H_A#26
L16
H_A#27
C21
H_A#28
J17
H_A#29
H20
H_A#30
B18
H_A#31
K17
H_A#32
B20
H_A#33
F21
H_A#34
K21
H_A#35
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
H_REQ#0
B15
H_REQ#1
K13
H_REQ#2
F13
H_REQ#3
B13
H_REQ#4
B14
B6
F12
C8
H_A#3
A14
H_A#[35..3] (7)
H_ADS# (7)
H_ADSTB#0 (7)
H_ADSTB#1 (7)
H_BNR# (7)
H_BPRI# (7)
H_BREQ# (7)
H_DEFER# (7)
H_DBSY# (7)
H_DPWR# (7)
H_DRDY# (7)
H_HIT# (7)
H_HITM# (7)
H_LOCK# (7)
H_TRDY# (7)
H_DINV#0 (7)
H_DINV#1 (7)
H_DINV#2 (7)
H_DINV#3 (7)
H_DSTBN#0 (7)
H_DSTBN#1 (7)
H_DSTBN#2 (7)
H_DSTBN#3 (7)
H_DSTBP#0 (7)
H_DSTBP#1 (7)
H_DSTBP#2 (7)
H_DSTBP#3 (7)
H_REQ#[4..0] (7)
H_RS#0 (7)
H_RS#1 (7)
H_RS#2 (7)
CLK_MCH_BCLK (18)
CLK_MCH_BCLK# (18)
R541
1KΩ 1% 1/16W SMT0402 LR
12
B B
R537
SPWR 0 5% 1/16W 0402
R542
2KΩ 1% 1/16W SMT0402 LR
C649
0.1uF 10V 10% 0402 X5R LR(NU)
A A
10
9
8
7
H_AVREF
H_DVREF
1.05VDDM
1.05VDDM(7,8,11,13,14,18,20,22,44)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
6
5
4
3
Date: Sheet of
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Crestline Host (1/6)
2
Confidential
10 47Friday, September 04, 2009
1
0.1
檔
10
H H
SM_RCOMP_VOH
SM_RCOMP_VOL
C205
C203
2.2uF 10V ± 10% SMT0603 X5R C1608X5R 1A225KT TDK LR
0.01uF 16V 10% SMT0402 X7R LR
C213
C208
2.2uF 10V ± 10% SMT0603 X5R C1608X5R 1A225KT TDK LR
0.01uF 16V 10% SMT0402 X7R LR
G G
F F
E E
PM_BMBUSY#(21)
D D
PM_EXTTS#0(16)
PM_EXTTS#1(17)
H_DPRSTP#(7,20,45)
DELAY_VR_PWRGOOD(23,45)
PLT_RST#(19)
PM_THRMTRIP#(7,20)
PM_DPRSLPVR(21,45)
C C
B B
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MCH_CFG_19
MCH_CFG_20
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
A A
MCH_CFG_6
MCH_CFG_20
SDVO_CTRL_DATA
R250 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R249 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R260 4.02KΩ 1% 1/10W SMT0603 LR
R256 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R234 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R231 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R243 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R242 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R232 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R233 RES 2.2KΩ 1% 1/16W SMT0402 LR(NU)
R201 RES 2.2KΩ 1% 1/16W SMT0402 LR
R248 RES 2.2KΩ 1% 1/16W SMT0402 LR
10
1.8VDDS
R154
1KΩ 1% 1/16W SMT0402 LR
R156
3.01K 1% 1/10W 0603 LR
R161
1KΩ 1% 1/16W SMT0402 LR
MCH_BSEL0(18)
MCH_BSEL1(18)
MCH_BSEL2(18)
R548
100Ω 5% 1/16W SMT0402 LR
9
9
T5
1
T4
1
MCH_CFG_5
MCH_CFG_6
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
PM_EXTTS#0
PM_EXTTS#1
RST_IN#_MCH
8
U34B
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
AL34
RSVD10
AK34
RSVD11
AN35
RSVD12
AM35
RSVD13
T24
AY21
BG23
BF23
BH18
BF18
AT40
AT11
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
3VDDM
B31
B2
M1
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
B7
N33
P32
T20
R32
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
CANTIGA_1p0
RSVD14
RSVD15
RSVD16
RSVD17
RSVD20
RSVD22
RSVD23
RSVD24
RSVD25
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
RSVD
SM_RCOMP_VOH
SM_RCOMP_VOL
DDR CLK/ CONTROL/COMPENSATIONCLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CFG
DMI
PM
GRAPHICS VIDMEHDA
DDPC_CTRLDATA
NC
SDVO_CTRLDATA
MISC
GMCH Strapping Requirements
CFG [2:0]
CFG5
CFG6 0 = ITPM is enabled
CFG9
CFG [12:13]
8
000=FSB1066
010=FSB800
0 = DMI * 2
1 = DMI * 4 ( Default )
1 = ITPM is disabled ( Default )
0 = Lane Reverse
1 = Normal Operation ( Default )
00 = Clock Gating Disable
01 = XOR Mode Enabled
10 = All Z Mode Enable
11 = Normal Operation ( Default )
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
SDVO_CTRLCLK
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
7
AP24
AT21
AV24
AU20
AR24
AR21
AU24
AV20
BC28
AY28
AY36
BB36
BA17
AY16
AV16
AR13
BD17
AY17
BF15
AY13
SM_RCOMP
BG22
SM_RCOMP#
BH21
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
SM_VREF
AV42
AR36
BF17
BC36
SM_DRAMRST#
B38
A38
E41
F41
F43
E43
DMI_TXP3
AE41
DMI_TXP2
AE37
DMI_TXP1
AE47
DMI_TXP0
AH39
DMI_TXN3
AE40
DMI_TXN2
AE38
DMI_TXN1
AE48
DMI_TXN0
AH40
DMI_RXP3
AE35
DMI_RXP2
AE43
DMI_RXP1
AE46
DMI_RXP0
AH42
DMI_RXN3
AD35
DMI_RXN2
AE44
DMI_RXN1
AF46
DMI_RXN0
AH43
B33
B32
G33
F33
E33
C34
R544
100KΩ 1% 1/16W SMT0402 LR(NU)
AH37
AH36
AN36
AJ35
AH34
N28
M28
SDVO_CTRL_CLK
G36
SDVO_CTRL_DATA
E36
CLK_MCH_OE#
K36
H36
B12
B28
B30
B29
C29
A28
011=FSB667
7
6
M_CLK_DDR0 (16)
M_CLK_DDR1 (16)
M_CLK_DDR3 (17)
M_CLK_DDR4 (17)
M_CLK_DDR#0 (16)
M_CLK_DDR#1 (16)
M_CLK_DDR#3 (17)
M_CLK_DDR#4 (17)
M_CKE0 (16)
M_CKE1 (16)
M_CKE3 (17)
M_CKE4 (17)
M_CS#0 (16)
M_CS#1 (16)
M_CS#2 (17)
M_CS#3 (17)
M_ODT0 (16)
M_ODT1 (16)
M_ODT2 (17)
M_ODT3 (17)
R510 RES 80.6Ω 1% 1/10W SMT 0603 LR
R511 RES 80.6Ω 1% 1/10W SMT 0603 LR
20miles
R170 200Ω 1% 1/16W SMT0402 LR
R177 200Ω 1% 1/16W SMT0402 LR
R155 499Ω 1% 1/16W SMT0402 LR
1
1
R236 56Ω 5% 1/16W SMT0402 LR
R182
DREFCLK (18)
DREFCLK# (18)
DREFSSCLK (18)
DREFSSCLK# (18)
CLK_PCIE_3GPLL (18)
CLK_PCIE_3GPLL# (18)
DMI_TXP3 (19)
DMI_TXP2 (19)
DMI_TXP1 (19)
DMI_TXP0 (19)
DMI_TXN3 (19)
DMI_TXN2 (19)
DMI_TXN1 (19)
DMI_TXN0 (19)
DMI_RXP3 (19)
DMI_RXP2 (19)
DMI_RXP1 (19)
DMI_RXP0 (19)
DMI_RXN3 (19)
DMI_RXN2 (19)
DMI_RXN1 (19)
DMI_RXN0 (19)
DFGT_VR_EN
CL_CLK0 (21)
CL_DATA0 (21)
MPWROK (21,23,37)
CL_RST#0 (21)
T7
0.1uF 10V 10% 0402 X5R LR
T8
CLK_MCH_OE# (18)
MCH_ICH_SYNC# (21)
C245
1.05VDDM
CL_REFCL_REF
0.35V
MCH_TSATN
CFG7
CFG10
CFG16
(PCIE)
CFG19
CFG20
6
1.8VDDS
C219
0.1uF 16V 80-20% 0402 Y5V LR(NU)
SM_VREF
C223
0.1uF 16V 80-20% 0402 Y5V LR(NU)
5
10KΩ 5% 1/16W SMT0402 LR
4
3VDDM
R255
Close To pin AV42
LCD_BRIGHTNESS(24,37)
LVDS_ENABKL(37)
1.8VDDS
SM_PWROK
10KΩ 1% 1/16W SMT0402 LR
R188
1KΩ 1% 1/16W SMT0402 LR
R189
499Ω 1% 1/16W SMT0402 LR
1.05VDDM
R207 0Ω 5% 1/16W SMT0402 LR(NU)
R227 0Ω 5% 1/16W SMT0402 LR
R214 100KΩ 5% 1/16W SMT0402 LR
LVDS_DDC_CLK(24)
LVDS_DDC_DATA(24)
LVDS_ENALCD(24)
1.8VDDS
LVDS_TXCLK_LN(24)
LVDS_TXCLK_LP(24)
LVDS_TXOUT_L0N(24)
LVDS_TXOUT_L1N(24)
LVDS_TXOUT_L2N(24)
LVDS_TXOUT_L0P(24)
LVDS_TXOUT_L1P(24)
LVDS_TXOUT_L2P(24)
R226 75Ω 1% 1/16W SMT0402 LR
TV_YU
TV_CU
R216 75Ω 1% 1/16W SMT0402 LR
R209 75Ω 1% 1/16W SMT0402 LR
R210 RES 150Ω 1% 1/16W SMT0402 LR
R219 RES 150Ω 1% 1/16W SMT0402 LR
R224 RES 150Ω 1% 1/16W SMT0402 LR
BLUE(25)
GREEN(25)
RED(25)
Q_VECLK(25)
Q_VEDAT(25)
HSYNC(25)
VSYNC(25)
For checklist v1.2
R228
RES 2.4KΩ 1% 1/16W SMT0402 LR
TV_DCONSEL0
TV_DCONSEL1
For checklist v1.2
0 = Isolators are bypassed
1= Isolators are active (Default)
0 = PCIE loopback enable
1= PCIE loopback disable(Default)
0 = Dynamic ODT Disabled
1 = DMI Lane Reversal Enabled ( Default )
0 = Normal ( Default )
1 = Lanes Reversed
0 = Only SDVO or PCIE X1 is operationl ( default )
1 = SDVO or PCIE X1 are operatingsimulaneously via the PEG port.
5
(DMI lane)
4
R254
10KΩ 5% 1/16W SMT0402 LR
U34C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA_1p0
R222
1KΩ 1% 1/16W SMT0402 LR
PM_EXTTS#0
PM_EXTTS#1
CLK_MCH_OE#
TV_DCONSEL0
TV_DCONSEL1
TV_DCONSEL0
TV_DCONSEL1
124
R247 10KΩ 5% 1/16W SMT0402 LR
124
Install it if GMCH
disable.
3
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
LVDS
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
TV
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
VGA
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
RP25
10KΩ 5% SMT1010 1/16W 4P2R LR
3
RP48
RP 2.2KΩ 5% SMT1010 4P2R 1/16W LR(NU)
RP47
0Ω 5% SMT1010 1/16W 4P2R LR
3
3
2
1.05VDDM_PEG
R199
RES 49.9Ω 1% 1/16W SMT0402
PEG_COMP
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
3VDDM
1.05VDDM_PEG(14)
1.05VDDM(7,8,10,13,14,18,20,22,44)
1.8VDDS(13,14,16,17,44)
3VDDM(7,9,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,39,43,44,45)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet of
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Crestline DMI/Graphic (2/6)
2
11 47Friday, September 04, 2009
1
1.05VDDM_PEG
1.05VDDM
1.8VDDS
3VDDM
1
0.1
檔
10
9
8
7
6
5
4
3
2
1
H H
G G
M_A_DQ[63..0](16) M_B_DQ[63..0](17)
F F
E E
D D
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AN38
AM38
AM44
AM42
AN43
AN44
AU40
AN41
AN39
AU44
AU42
BD43
BC40
BD38
AW36
BD13
AU11
BC11
AU13
BD12
BC12
AU10
AN10
AM11
AN12
AM13
AJ38
AJ41
AJ36
AJ40
AT38
AV39
AY44
BA40
AV41
AY43
BB41
AY37
AV37
AT36
AY38
BB38
AV36
BA12
AV13
BA11
AJ11
AJ12
BB9
BA9
AV9
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AM5
AJ9
AJ8
U34D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p0
BD21
SA_BS_0
BG18
SA_BS_1
AT25
SA_BS_2
BB20
SA_RAS#
BD20
SA_CAS#
AY20
SA_WE#
M_A_DM0M_A_DM0
AM37
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
M_A_DM1M_A_DM1
AT41
M_A_DM2M_A_DM2
AY41
M_A_DM3M_A_DM3
AU39
M_A_DM4M_A_DM4
BB12
M_A_DM5M_A_DM5
AY6
M_A_DM6M_A_DM6
AT7
M_A_DM7M_A_DM7
AJ5
M_A_DQS0M_A_DQS0
AJ44
M_A_DQS1M_A_DQS1
AT44
M_A_DQS2M_A_DQS2
BA43
M_A_DQS3M_A_DQS3
BC37
M_A_DQS4M_A_DQS4
AW12
M_A_DQS5
BC8
M_A_DQS6M_A_DQS6
AU8
M_A_DQS7M_A_DQS7
AM7
M_A_DQS#0M_A_DQS#0
AJ43
M_A_DQS#1M_A_DQS#1
AT43
M_A_DQS#2M_A_DQS#2
BA44
M_A_DQS#3M_A_DQS#3
BD37
M_A_DQS#4M_A_DQS#4
AY12
M_A_DQS#5M_A_DQS#5
BD8
M_A_DQS#6M_A_DQS#6
AU9
M_A_DQS#7M_A_DQS#7
AM8
M_A_A0M_A_A0
BA21
M_A_A1M_A_A1
BC24
M_A_A2M_A_A2
BG24
M_A_A3
BH24
M_A_A4
BG25
M_A_A5M_A_A5
BA24
M_A_A6M_A_A6
BD24
M_A_A7
BG27
M_A_A8M_A_A8
BF25
M_A_A9
AW24
M_A_A10
BC21
M_A_A11
BG26
M_A_A12
BH26
M_A_A13
BH17
M_A_A14 M_B_A13
AY25
M_A_DQS#[7..0]
M_A_DM[7..0]
M_A_DQS[7..0]
M_A_A[14..0]
M_A_BS0 (16)
M_A_BS1 (16)
M_A_BS2 (16)
M_A_RAS# (16)
M_A_CAS# (16)
M_A_WE# (16)
M_A_DM[7..0] (16)
M_A_DQS[7..0] (16)
M_A_DQS#[7..0] (16)
M_A_A[14..0] (16)
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AM48
BG43
BG38
BG35
BG39
BG34
BG12
AK47
AH46
AP47
AP46
AJ46
AJ48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BF43
BE45
BC41
BF40
BF41
BF38
BH35
BH40
BH34
BH14
BH11
BH12
BF11
BG8
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
U34E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_1p0
BC16
SB_BS_0
BB17
SB_BS_1
BB33
SB_BS_2
AU17
SB_RAS#
BG16
SB_CAS#
BF14
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A14
M_B_DM0
AM47
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_BS0 (17)
M_B_BS1 (17)
M_B_BS2 (17)
M_B_RAS# (17)
M_B_CAS# (17)
M_B_WE# (17)
M_B_DM[7..0] (17)
M_B_DQS[7..0] (17)
M_B_DQS#[7..0] (17)
M_B_A[14..0] (17)
C C
TV DAC Routing Guideline
1. The minimum spacing between each RGB is 40-mils while 50-mils is preferred
2. RGB signals should be routed on the same layer, have a similar number of bends,
same number of vias
3. All routing should be done with ground referencing as well
4. TV DAC route lengths should be lenght match to within 200 mils
Filter
0.5"
Mini
DIN7
B B
GMCH
0.5"
0.2"
12"
TV DAC
TV IRTN
150ohm
150ohm
Zo=37.5
Zo=50
A A
10
9
8
7
6
5
Zo=75
Title
Size Document Number Rev
C
4
3
Date: Sheet of
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Crestline DDR2 (3/6)
2
Confidential
12 47Friday, September 04, 2009
1
0.1
檔
10
9
8
7
6
5
4
3
2
1
H H
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
U34G
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC SMVCC GFX
POWER
VCC GFX NCTF
VCC_AXG_NCTF_1VCC_SM_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
W28AP33
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
C235
MO-CAP 5pF 50V ± 0.5pF SMT0402 NPO LR(NU)
RF
VCCSM_LF1
C212 MO-CAP 1uF 6.3V 10% SMT 0603 X5R C1608X5R0J105K TDK LR
VCCSM_LF2
C209 MO-CAP 1uF 6.3V 10% SMT 0603 X5R C1608X5R0J105K TDK LR
VCCSM_LF3
C236 0.47uF 10V ± 10% SMD0603 X5R LR
1 2
VCCSM_LF4
C217 0.22uF 10V 0603 X7R LR
VCCSM_LF5
C218 0.22uF 10V 0603 X7R LR
VCCSM_LF6
C240 0.1uF 10V 10% 0402 X5R LR
VCCSM_LF7
C216 0.1uF 10V 10% 0402 X5R LR
VIA=2400mA / 100mils
1.8VDDS
G G
10/2 MODIFY
C569 T100uF 2V ±20% ESR=18mΩ SMT 7343 EEFCD0D101ER PANASONIC LR
C570 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C574 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C576 0.1uF 10V 10% 0402 X5R LR
+
C210
MO-CAP 5pF 50V ± 0.5pF SMT0402 NPO LR(NU)
RF
F F
1.05VDDM
E E
VIA=7700mA / 320mils
20090429 modify VGA_VDD
change to 1.05VDDM
D D
C C
VCC_AXG_SENSE
VSS_AXG_SENSE
B B
CANTIGA_1p0
20090429 modify VGA_VDD
change to 1.05VDDM
EXT VGA VGA_VDD NEED PULL DOWN
1.05VDDM
C241 1uF 10V +80-20% 0603 Y5V LR(NU)
C249 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C237 10uF 10V +80-20% SMT0805 Y5V LR(NU)
C260 0.1uF 10V 10% 0402 X5R LR(NU )
C280 0.1uF 10V 10% 0402 X5R LR
C238 0.1uF 10V 10% 0402 X5R LR(NU )
C254 0.1uF 10V 10% 0402 X5R LR
C257 0.1uF 10V 10% 0402 X5R LR
C258 0.47uF 10V ± 10% SMD0603 X5R LR
12
+
1.05VDDM
C271 T100uF 2V ± 20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
C320 4.7uF 6.3V ± 10% SMT 0805 X5R C2012X5R0J475KT TDK LR
C247 220uF 2V ±20% 15mΩ 7343 PANA LR(NU )
+
308mils
C253 0.1uF 10V 10% 0402 X5R LR
C242 0.22uF 10V 0603 X7R LR
C279 0.22uF 10V 0603 X7R LR
C273 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C281
MO-CAP 5pF 50V ± 0.5pF SMT0402 NPO LR(NU)
RF
1.5VDDM
20mils
U34F
AG34
VCC_1
AC34
VCC_2
AB34
VCC_3
AA34
VCC_4
Y34
VCC_5
V34
VCC_6
U34
VCC_7
AM33
VCC_8
AK33
VCC_9
AJ33
VCC_10
AG33
VCC_11
AF33
VCC_12
AE33
VCC_13
AC33
VCC_14
AA33
VCC_15
Y33
VCC_16
W33
VCC_17
V33
VCC_18
U33
VCC_19
AH28
VCC_20
AF28
VCC_21
AC28
VCC_22
AA28
VCC_23
AJ26
VCC_24
AG26
VCC_25
AE26
VCC_26
AC26
VCC_27
AH25
VCC_28
AG25
VCC_29
AF25
VCC_30
AG24
VCC_31
AJ23
VCC_32
AH23
VCC_33
AF23
VCC_34
T32
VCC_35
CANTIGA_1p0
R252
RES 10Ω 5% 1/16W SMT0402 LR
VCC CORE
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
POWER
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
D23
PS355NS 80V 100mA SMT0805 PSI LR
1.05VDDM
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
PN
1.05VDDM
1.8VDDS
1.8VDDS(11,14,16,17,44)
1.05VDDM
1.05VDDM(7,8,10,11,14,18,20,22,44)
1.5VDDM
1.5VDDM(8,14,19,20,22,29,31,44)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
A A
10
9
8
7
6
5
4
3
Title
Size Document Number Rev
C
Date: Sheet of
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
Confidential
Penryn+Candiga GL40+ICH9M(VME40)
Crestline Power (4/6)
2
13 47Friday, September 04, 2009
1
0.1
檔
10
9
8
7
6
5
4
3
2
1
H H
RF
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
G G
F F
0.022uF 16V 10% SMT0402 X7R LR
E E
RF
C655
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
D D
C C
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
B B
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
A A
1.05VDDM
20mils
L19
C296
SPWR 0 5% 1/16W 0603
L18
SPWR 0 5% 1/16W 0603
1.05VDDM
L53
SPWR 0 5% 1/16W 0603
RF
C612
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
3VDDM
L54
RES 5.6Ω 5% 1/10W SMT0603 RTT035R6JTP RALEC LR
C327
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
9/14 modified
remove UMA
parts
SPWR 0 5% 1/16W 0603
1Ω 1% 1/10W SMT0603 LR
VCCA_TVDAC
C653
L50
R518
C648
0.1uF 10V 10% 0402 X5R LR
Caps used in 1.5VDDM_TVDAC
and 1.5VDDM_QTVDAC should
be within 250mils of edge
1.5VDDM
C336
RF
C275
10
0.1uf caps in 1.5VDDM_xPLL
need to be located as edge caps
within 200mils
VIA=80mA / 10mils
C313
0.1uF 10V 10% 0402 X5R LR
C315
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)
VIA=80mA / 10mils
C300
0.1uF 10V 10% 0402 X5R LR
C282
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)
C609
C608
0.1uF 10V 10% 0402 X5R LR
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C604
0.1uF 10V 10% 0402 X5R LR
C594
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
1.8VDDS_TXLVDS
3VDDM_TVDACA
1.05VDDM
R186
R251
SPWR 0 5% 1/16W 0402
(24mA)
100MHz 600Ω SMT0603 FCM1608KF-601T02 TAI-TECH LR
1.05VDDM
0.1uF 10V 10% 0402 X5R LR
L24
20060117A-EMI
(24mA)
SPWR 0 5% 1/16W 0603
L17
R197
1Ω 1% 1/10W SMT0603 LR
C270
RF
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
1.8VDDS
Caps used in 2.5VDDM_CRTDAC
should be within 250mils of
edge
9
10mils
C322
C319
C298
0.022uF 16V 10% SMT0402 X7R LR
0.1uF 10V 10% 0402 X5R LR
1.05VDDM_PEGPLL
C269
0.1uF 10V 10% 0402 X5R LR
R230
C297
0.022uF 16V 10% SMT0402 X7R LR
1.05VDDM_PEGPLL
8
1.05VDDM_DPLLA
1.05VDDM_DPLLB
VIA=50mA / 10mils
1.05VDDM_HPLL
VIA=150mA / 10mils
1.05VDDM_MPLL
0.1uF 10V 10% 0402 X5R LR
R179
1.05VDDM
SPWR 0 5% 1/16W 0603
C225
1.05VDDM
0.1uF 10V 10% 0402 X5R LR
SPWR 0 5% 1/16W 0402
C299
0.1uF 10V 10% 0402 X5R LR
R245 SPWR 0 5% 1/16W 0603
3VDDM
0.1uF 10V 10% 0402 X5R LR
C302MO-CAP 5pF 50V ± 0.5pF SMT0402 NPO LR(NU)
RF
1.5VDDM
R191
SPWR 0 5% 1/16W 0603
C263
SPWR 0 5% 1/16W 0603
C243
C214
T100uF 2 V ± 20% ESR =18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
+
C226
0.1uF 10V 10% 0402 X5R LR
10uF 10V ± 10% SMT 0805 X5R T =1.25mm C2012X5R1A 106KT TDK LR
VIA=100mA / 10mils
10uF 10V ± 10% SMT 0805 X5R T =1.25mm C2012X5R1A 106KT TDK LR
C268
C303
0.022uF 16V 10% SMT0402 X7R LR
C316
C311
0.022uF 16V 10% SMT0402 X7R LR
VCCA_TVDAC
C647
0.1uF 10V 10% 0402 X5R LR
1.05VDDM_DPLLA
1.05VDDM_DPLLB
1.05VDDM_HPLL
1.05VDDM_MPLL
R215 SPWR 0 5% 1/16W 0402
C305 0.1uF 10V 10% 0402 X5R LR
VIA=5mA / 10mils
C264
0.1uF 10V 10% 0402 X5R LR
4.7uF 6. 3V ± 10% SM T0805 X5R C2012X5R0 J475KT TD K LR
1.05VDDM_PEGPLL
C224
C239
MO-CAP 1uF 6.3V 1 0% SMT 06 03 X5R C1 608X5R0J10 5K TDK LR
10uF 6.3V 10% SMT 0805 X5R C 2012X5R0J 106K TDK LR(NU)
500mA
VIA=100mA / 10mils
VIA=200mA / 10mils
VIA=250mA / 10mils
C323
C256
3VDDM_TVDACA
0Ω 5% 1/16W SMT0402 LR
0.1uF 10V 10% 0402 X5R LR
150mA
20mils
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
7
40mA
R246
10mA
80mA
5mA
80mA
80mA
50mA
150mA
100mA
10mA
3VDDM
B27
A26
A25
B25
F47
L48
AD1
AE1
J48
J47
AD48
AA48
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
B24
A24
A32
M25
L28
AF1
AA47
M38
L37
C658
6
U34H
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCA_TV_DAC_1
VCCA_TV_DAC_2
VCC_HDA
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CANTIGA_1p0
R239
RES 10Ω 5% 1/16W SMT0402 LR
SPWR 0 5% 1/16W 0402
R545
RF
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
CRTPLLA PEGA SM
A LVDS
POWER
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
A CK
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
VCC_HV_1
D TV/CRT
DN1
VCC_HV_2
VCC_HV_3
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
DMI
VTTLF1
VTTLF2
VTTLF3
VTTLF
PN
20mils
3VDDM_HV
C654
0.1uF 10V 10% 0402 X5R LR
5
TV
HDA
LVDS
PS355NS 80V 100mA SMT0805 PSI LR
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
1.05VDDM
(70mA)
3VDDM_HV
VIA=850mA / 40mils
1.8VDDS_TXLVDS
3VDDM_HV
3VDDM_HV
VIA=100mA / 10mils
1.05VDDM_PEG
R520
0Ω 5% 1/10W SMT0603 LR
1.05VDDM_DMI
250mA
VTT_LF1
VTT_LF2
VTT_LF3
C623
12
0.47uF 10 V ± 10% SM D0603 X5R LR
12
C582
C635
+
T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
C626
C637
C246MO-CAP 5pF 50V ± 0.5pF SMT0402 NPO LR(NU)
RF
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
C650
MO-CAP 1uF 6.3V 10% SMT 0603 X5R C1608X5R0J105K TDK LR
1.05VDDM_PEG
C304
C652
12
12
0.47uF 10 V ± 10% SM D0603 X5R LR
0.47uF 10 V ± 10% SM D0603 X5R LR
0.47uF 10V ±10% SMD0603 X5R LR
C627
2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
R546
SPWR 0 5% 1/16W 0603
C332
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
SPWR 0 5% 1/16W 0603
C577
0.1uF 10V 10% 0402 X5R LR
C306
0.1uF 10V 10% 0402 X5R LR
C630
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C593
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)
R509 RES 1Ω 1% 1/16W SMT 0402 LR
C573
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C301
C277
RF
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
C584
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
4
1.05VDDM
VIA=350mA / 20mils
L47
VIA=200mA / 20mils
SPWR 0 5% 1/16W 0603
3
1.05VDDM
R220 0Ω 5% 1/4W SMT1206 LR
1.8VDDS
R515
VIA=1200mA / 60mils
R513
0Ω 5% 1/10W SMT0603 LR(NU)
VIA=250mA / 10mils
Title
Size Document Number Rev
Date: Sheet of
C565
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
RF
C566
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
1.8VDDS
C308
MO-CAP 5pF 50V ±0.5pF SMT0402 NPO LR(NU)
RF
1.05VDDM
1.05VDDM
1.8VDDS(11,13,16,17,44)
1.05VDDM(7,8,10,11,13,18,20,22,44)
1.05VDDM_PEG(11)
1.5VDDM(8,13,19,20,22,29,31,44)
1.5VDDS_DDR3
3VDDM(7,9,11,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,39,43,44,45)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Custom
Crestline Power (5/6)
2
Confidential
14 47Friday, September 04, 2009
1
1.8VDDS
1.05VDDM
1.05VDDM_PEG
1.5VDDM
1.5VDDS_DDR3
3VDDM
0.1
檔
8
7
6
5
4
3
2
1
DMI Routing Guideline
U34I
AU48
VSS_1
AR48
VSS_2
AL48
D D
C C
B B
AW47
AM46
AM43
BG42
AM41
BG40
AM39
AW37
BG36
BB47
AN47
AJ47
AF47
AD47
AB47
BD46
BA46
AY46
AV46
AR46
BF44
AH44
AD44
AA44
BC43
AV43
AU43
AY42
AT42
AN42
AJ42
AE42
BD41
AU41
AH41
AD41
AA41
BB40
AV40
AN40
AT39
AJ39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AT37
AN37
AJ37
BD36
AK15
AU36
Y47
T47
N47
L47
G47
V46
R46
P46
H46
F46
Y44
U44
T44
M44
F44
J43
C43
N42
L42
Y41
U41
T41
M41
G41
B41
H40
E40
N39
L39
B39
Y38
U38
T38
J38
F38
C38
H37
C37
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
AW21
AU21
AN21
AH21
BC20
AW20
AG20
BG19
BG17
BC17
AW17
AU16
AN16
BG15
AC15
BG14
BG13
BC13
AN13
AM12
BD11
AN11
AH11
BG10
AP21
AF21
AB21
BA20
AT20
AJ20
AT17
BA16
AA14
BA13
AJ13
AE13
BF12
AV12
AT12
AA12
BB11
AY11
AV10
AT10
AJ10
AE10
AA10
L12
R21
M21
J21
G21
Y20
N20
K20
F20
C20
A20
A18
R17
M17
H17
C17
N16
K16
G16
E16
W15
A15
C14
N13
L13
G13
E13
J12
A12
Y11
N11
G11
C11
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
U34J
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
CANTIGA_1p0
VSS
VSS NCTF
VSS SCB
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
R204 0Ω 5% 1/16W SMT0402 LR
U24
R193 0Ω 5% 1/16W SMT0402 LR
U28
R205 0Ω 5% 1/16W SMT0402 LR
U25
R202 0Ω 5% 1/16W SMT0402 LR
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
GMCH
LA
LBTx
LC LD LE
Rx
LZ LXLY LW LV
Breakout/in
Main Route
LA/LZ
LB/LY
Microstrip Same Routing layer as LA/LZ
Microstrip
Same Routing layer as LA/LZ
Microstrip
Same Routing layer as LA/LZ
Microstrip
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Stripline
Stripline
Same Routing layer as LA/LZ
Stripline
Same Routing layer as LA/LZ
Stripline
Same Routing layer as LA/LZ
Parameter Breakout Guideline
Uncoupled Single End Impedance
Nominal Trace Width
Pair-to-Pair Pitch
Bus-to-Bus Pitch
Reference Plane
Trace Length-LA (GMCH Breakout)
Trace Length-LB (GMCH Breakout to Via2)
Trace Length-LC (Via2 to Via3) Max = 5900 mils
Trace Length-LD (Via3 to ICH7m Breakout)
Trace Length-LE (ICH7m Breakout ) Max = 400 mils
Trace Length-LV ( ICH7m Breakout)
Trace Length-LX (Via2 to Via3)
Trace Length-LY (Via3 to GMCH Breakout) Max = 3600 mils
Trace Length-LZ (GMCH Breakout)
Trace Length-L2 (LV+LW+LX+LY+LZ) Max = 8000 mils
*** When routing near the edge of their reference plane , trace should maintain at least 40
mils space to the edge of the plane
*** Match the trace lengths of the complementary signals within each differenti al pair to +/- 5 mils
Main Route
LD/LW
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Main Route Guideline
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 7 milsNominal Didderential Pair-Pitch
Outer Layer : 7 mils
Inner Layer : 37 mils
Outer Layer : 37 mils
Inner Layer : 22 mils
Outer Layer : 20 mils
Ground Ground
No routing over plane spli tsSplits/Voids
No routing over voids
Max = 400 mils
Max = 3600 mils
Max = 3600 mils
Max = 8000 milsTrace Length-L1 (LA+LB+L C+LD+LE)
Max = 400 mils
Max = 3600 milsTrace Length-LW (ICH7m Breakout to Via2)
Max = 5900 mils
Max = 400 mils
ICH8M
Rx
Tx
Breakout/in
LE/LV
Microstrip
Stripline
Microstrip
Stripline
Stripline
Microstrip
Stripline
Microstrip
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 27 mils
Outer Layer : 27 mils
Inner Layer : 15 mils
Outer Layer : 12 mils
X O
PCIE Routing Guideline
GMCH
Tx
Rx
Breakout/in
Main Route
LA/LZ
LB/LC/LY
Stripline
Microstrip
Parameter
Uncoupled Single End Impedance
Nominal Trace Width
Nominal Differential Trace Space
Pair-to-Pair Pitch
Bus-to-Bus Pitch
Reference Plane
Splits/Voids
Trace Length-LA (ICH7m Breakout)
Trace Length-LB (ICH7m Breakout to
AC cap)
Trace Length-LC (AC cap to
PCIe CN)
Trace Length-L1 (LA+LB+LC)
Trace Length-LY (PCIe CN to ICH7m
Breakout)
Trace Length-LZ (ICH7m Breakout)
*** When routing near the edge of their reference plane , trace should maintain at least 40
mils space to the edge of the plane
*** Match the trace lengths of the complementary signals within each different ial pair to +/- 5 mils
LB
LA
LZ
LY
Main Route
LD/LW
Same Routing layer as LE/LV
Main Route Guideline
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 7 mils
Outer Layer : 7 mils
Inner Layer : 37 mils
Outer Layer : 37 mils Outer Layer : 27 mils
Inner Layer : 20 mils
Outer Layer : 20 mils
Ground
No routing over plane spli ts
No routing over voids
Max = 400 mils
Max = 10750 mils
Max = 10750 mils
Max = 12000 mils
Max = 11950 mils
Max = 400 mils
Max = 12000 milsTrace Length-L2 (LY+LZ)
X O
Express/Mini Card
LC
Breakout Guideline
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 27 mils
Inner Layer : 15 mils
Outer Layer : 12 mils
Ground
>3W
S < 2S
S = Spacing
S = Trace Width
Rx
Tx
Breakout/in
LE/LV
Microstrip
A A
8
7
6
5
>3W
S < 2S
S = Spacing
S = Trace Width
4
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
3
Date: Sheet of
2
(886-2)8751-8751
Penryn+Candiga GL40+ICH9M(VME40)
Crestline Ground (6/6)
Confidential
15 47Friday, September 04, 2009
1
0.1
檔
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