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First International Computer,Inc
D D
Portable Computer Group HW Department
Board name : MotherBoard Schematic
Project :
C C
Version : 0.4
MY050
Initial Date : May. 05 , 2008
1. Schematic Page Description :
2. PCI & IRQ & DMA Description :
3. Block Diagram :
4. Schematic modify Item and History :
5. power on & off & S3 Sequence :
6. Layout Guideline :
7. switch setting
B B
Manager Sign by: Avery Lee
Drawing by : Beckham Chen
Total confirm by: Jason Lee
LAN Circuit check by:
A A
Audio Circuit check by:
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
MY050
Title
1
5
Title
Size Document Number Rev
C
4
3
2
Date: Sheet of
Confidential
1 50Monday, May 05, 2008
0.3
8
7
6
1. Schematic Page Description :
MY050 Schematic Ver : 0.1
5
4
3
2
1
D D
C C
B B
1. Title
2. Schematic Page Description
3. Block Diagram
4. ANNOTATIONS
5. Schematic Modify
6. Timing Diagram
7. DDRII Layout Guideline
8. Penryn Processor(1/2)
9. Penryn Processor(2/2)
10. CPU Thermal
11. Cantiga Host(1/6)
12. Cantiga DMI/Graphic(2/6)
13. Cantiga DDRII(3/6)
14. Cantiga Power(4/6)
15. Cantiga Power(5/6)
16. Cantiga GND(6/6)
17. Clock Generator
18. DDRII SDRAM SO-DIMM0
19. DDRII SDRAM SO-DIMM1
20. ICH9M PCI/PCIE/DMI(1/4)
21. ICH9M CPU/IDE/SATA(2/4)
22. ICH9M GPIO(3/4)
23. ICH9M Power/GND(4/4)
24. Reset Circuit
25. DIP/LID SW; SCREW
26. LCD CNN
27. DVI Level Shift
28. DVI-I PORT
29. SPI/INT K/B/GP CNN
30. LED / SW CN
31. SATA HDD & ODD CNN
32. USB CNN
33. EXPRESS CARD
34. LAN RTL8111C
35. TRANSFORMER
36. RTS5158E (Card-Reader)
37. Azalia ALC269 Codec
38. SPDIF / MIC / HP / Int. MIC
2. PCI & IRQ & DMA Description :
39. MDC
40. Mini-WLAN/BT/CCD
41. PMX
42. Power Block
43. CPU Core Power
44. ADPIN, BATIN, ADPOUT1
45. Charger, DCIN
46. 3/5VDDA/M , PMU3/5V
47. 1.05V/1.5VDDM
48. 1.8VDDS / 0.9VDDS
49. VGA CORE
C1. SW BOARD
DMA Channel
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
A A
IRQ13
IRQ14
IRQ15
8
System timer
Keyboard
(Casacde)
LAN / MODEM
Serial Port
AUDIO / VGA / USB
FLOPPY DISK
LPT
RTC
ACPI
(Disable by default)
FIR
Cardbus
PS/2 mouse
FPU
HDD
CDROM
(MODEM/LAN)
7
DMA0 FIR
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
6
DeviceIRQ Channel Desciption
(disable by default)
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused
(MODEM / LAN)
5
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
4
3
Date: Sheet of
2
(886-2) 8751-8751
MY050
Schematic Page Description
2 50Monday, May 05, 2008
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3. Block Diagram :
D D
Thermal
Sensor
P10
(667/800 MHz)
Intel
Penryn
Processor
P8~9
FSB
DVI-I
P27,28
LCD
P26
C C
USB 2.0
Intel
Cantiga
(G)MCH
DMI
(x2/x4)
P11~P16
Mem_A Bus
Mem_B Bus
PCIE
CardReader
RTS5158E
Express Card
P36
P33
CCD
P40
Battery CON
P44
B B
ACIN / DCIN
DCIN+
P44
P44
Battery Charger
P45
Battery Voltage Sense
P44
B / T
P40
CDROM
HDD
P31
P31
USB 0,1,2
P32
SATA BUS
SATA BUS
Intel
ICH9M
SPI BUS
Flash ROM
P29
P20~23
MINI CARD
Azalia
LPC BUS
CPU
CORE
P43
CPU
VCCP
P47
DDR2 533/667 MHz
DDRII SODIMM0 (A)
DDR2 533/667 MHz
DDRII SODIMM1 (B)
P40
Express Card
Azalia Codec
ALC269
P18
P19
P33
P37
CLK ICS9LPRS365BKLFT
Reset Circuit
Brightness Control
RTC Bat
Fan CNN
Lid Switch
MAIN SW CNN/DIP SW
LED
GIGA LAN
RTL 8111C
MDC Modem
P39
RJ-45
RJ-11
P25
P17
P24
P41
P21
P10
P25
P30
P30
P34
P35
P39
PMX
M38859
3VDDA
5VDDA
3VDDM/5VDDM
A A
1.5VDDM
P46
P46
1.5VDDM/1.05VDDM
1.8VDDS
P47
DDRII Power
P47
P48
PMU3V
PMU5V
P48
P46
Int. KB
P41
Glide Pad
P29P29
Mic In
P38
Link In
P38
Headphone
SPDIF Out
P38
SPK
P37
OVP
8
P41
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
MY050
Block Diagram
(886-2) 8751-8751
3 50Monday, May 05, 2008
1
0.3
Title
Size Document Number Rev
C
7
6
5
4
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Date: Sheet of
2
8
7
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5
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4. Nat name Description :
Voltage Rails
DCIN
PMU5V 5.0V always on power rail by LATCH or ACIN
D D
PMU3V 3.3V always on power rail by LATCH or ACIN
3VDDA 3.3V always on power rail by DCON
3VDDS 3.3V power rail by PSUSC#
5VDDS 5.0V power rail by PSUSC#
3VDDM
VCC_CORE
1.05VDDM
1.5VDDM
1.8VDDS
0.9VDDT_DDRII
Part Naming Conventions
C
=
Capacitor
CN
C C
D
F
L
Q
R
RP
U
Y
Connector
=
Diode
=
Fuse
=
Inductor
=
Transistor
=
Resistor
=
Resistor Pack
=
Arbitrary Logic Device
=
Crystal and Osc
=
Net Name Suffix
# =
B B
Active Low signal
Primary DC system power supply
5.0V always on power rail by DCON5VDDA
3.3V switched power rail by SUSTAT_B#
5.0V switched power rail by SUSTAT_B#5VDDM
Core Voltage for CPU
1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#
1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE
for ICH7m by SUSTAT_B#
1.8V power rail for DDRII by PSUSC#
0.9V DDRII Termination Voltage by SUSTAT_B#
5. Board Stack up Description
PCB Layers
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Layers : 8 Depth 1.2mm Impence 55 ohms +/- 10%
Host Clock
SRC Clock
Host Bus
DDR2 CLK
DDR2 Strobe
DDR2 Bus
DMI Bus
PCIE Bus
SATA
SDVO
LVDS
USB
IEEE1394
Lan
Single End Impedance
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
42 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
50 ohm +/- 15%
Component Side, Microstrip signal Layer
Ground Plane
Stripline Layer(High Speed)
Normal Signal / Ground 1 Plane
Power Plane
Stripline Layer(High Speed)
Ground 2 Plane
Solder Side,Microstrip signal Layer
Differential Impedance for Microstrip
95 ohm +/- 15%
95 ohm +/- 15%
70 ohm +/- 20%
95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%
Differential Impedance for Stripline
100 ohm +/- 15%
100 ohm +/- 15%
70 ohm +/- 20%
85 ohm +/- 20%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%
A A
Title
Size Document Number Rev
C
Date: Sheet of
8
7
6
5
4
3
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
MY050
Annotations
2
4 50Monday, May 05, 2008
0.3
1
5
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GRATUITO - FOR FREE
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6.Schematic modify Item and History :
3
2
1
V01 ---> V02
1.Add SDVO/PCIE strapping ci rcuit.
2.Modify DVI level shift ci rcuit.
D D
3.Modify Audio mute cir cuit.
4.Modify CL_VREF0_ICH from 3VDDA to 3VDDM.
5.Tune 3VDDM/1.5VDDM/1.05VDDM timing
a. R233 change from 10K t o 12K
b. R510, R511 change from 0 to 33K
c. Add C551, C552 0.1uF
6.R321,R322,R323,R528,R526 chang e to NU
7.C622 is changed to 7343 220uF 15m ohm
8.Page 43 --- R490, R495 are changed to 4.7K ohm.
R169, R173 are changed to 10K ohm.
R524 is changed to 3K ohm.
5VDDA ---> 5VDDM
Page 46 --- Delete D48, Q53.
Add R637 10 K ohm
R582 is changed to 10K ohm
R579 is changed to 10K ohm and connected to GND_POWER
C623, C624, C625, C626 are changed to 0.47uF.
Page 47 --- 5VDDA ---> 5 VDDM.
Page 49 --- 5VDDA ---> 5 VDDM.
Add R417 47K
R390 change to pul l down
C C
9.Page 48 --- Add Q23 APM 2301.
Add Q53 RT1 N441.
Add R265 100K ohm.
5VDDA ---> 5 VDDS.
10.Page 49 --- R384 is changed to NU
R391 is changed to 0 ohm
R388 is changed to 82K ohm
R396 is changed to 9 .1K ohm
R424 is changed to 12K ohm
R426 is changed to 2 .2K ohm
R63 is changed to 0 ohm
R59 is changed to 0 ohm
R390 pull up to 3VDDM
Page 48 --- Add C42 220uF 15moh m 7343.
Page 10 --- R309 change to 0 ohm.
Page 45 --- R313 connect to CHG_EN
R290 change to 2 7K ohm
R291 change to 2K ohm
R292 change to 1 8K ohm
D26 change to RB751
Page 41 --- Add R638 to RE M net
B B
V02 ---> V03
1.R627,R629 stuff, R631,R633 chang e to NU
2.Add R639 2.2K.
3.U24 change to LFE9248
4.L32, L33, L34 change to FCM2012KF-600T09, C345,C348,C352 change to NU
5.EMI solution
1.Add C396 1000pF
2.Add C478,C479 22pF
3.Add C127,C194 1000pF
4.Modify L61,L62
5.Add C521, C527,C528,C533,C561,C 563 5pF
6.Add C32,C33 33pF
6.EPA solution
1.Change D38 to SS34A
2.Change Q34 to AO4411
3.Add 5VDDA, 3VDDA load switch circuit
4.L39, L40 change from Tai-tech to Chilisin
5.R359 NU
7.USB Cap cost down
1.C176, C577 change to NEC T-CAP 1 0V 100uF
A A
8.Add R229 between 3VDDA and Blueto oth Vcc
9.R112 change to 5.6 ohm for water w aveform.
10.Add R229 to NB VCCA_SM(1.05VDDM) pow er trace
11.R111 change to 2.4k.
12.Add CCD_ON pull down R653 10k.
13.R141, R147 change to 0 ohm.
14.Add C661 0.01uF.
5
4
V03 ---> V04
1.R597, R614 change from 100k to 56k ohm
2.Add R683 10 ohm
3.L63 size change from 0603 t o 0805
4.R445 change to NU
5.L32,L33,L34 change from 21-92603-01 to 12-01875-01 (For pass CRT test)
6.C276, C290 change t o NU
7.For pass DVI test
Add R283, R284 10k ohm, R285 change to NU, R274 cahn ge to 1k otm
Add R687,R688,R689,690 30 0 ohm
Add C692,C693,C694,C695 0.1uF
8.For 3/5VDDA, 3/5VDDM MOSFET gate d ischarge
Add R695, R696, R697, R698 0 ohm.
Add R691, R692, R693, R694 20 0 ohm.
9.For AC
10.For CPU Core MOSFET g ate
快速插拔不開機
Add R686 100K ohm, D57 6.2V Zener diode.
Add R266, R269 0 ohm.
3
降速
2
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
MY050
Schematic Modify
(886-2) 8751-8751
1
5 50Monday, May 05, 2008
Title
Size Document Number Rev
C
Date: Sheet of
0.3
5
4
3
2
1
7. power on & off & S3 Sequence :
S3 SUSPEND AND RESUME TIMING
Power On Sequencing Timing Diag ram
D D
20060117A - DATA FROM NO.16809
PSI#
VID
t
SFT_START_VCC
VR_ON
-12%
t
-12%
t
Vccp_UP
BOOT
t
BOOT-VID-TR
V
CC-CORE
t
C C
CPU_UP
V
CCP
CPU_UP
Vccp_UP
-12%
V
CC_MCH
MCH_PWRGD
t
B B
MCH-PWRGD
CLK_ENABLE#
IMVP6_PWRGD
t
SFT_START_VCC
t
BOOT
t
BOOT-VID-TR
t
A A
CPU_UP
t
Vccp_UP
t
MCH-PWRGD
t
CPU_PWRGD
5
Max = 3 ms
Min = 10 us , Max = 100 us
Max = 100 us
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Min = 3 ms , Max = 20 ms
t
CPU_PWRGD
4
POWSW0
PMU5V/PMU3V
PM_RSMRST0
PM_SLP_S30
PM_SLP_S40/S50
SUSTAT_B0
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP,1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGOOD
PCI_RST0
AGTL+_CPURST0
BATTERY ONLY POWER ON TIMING
PMU5V/PMU3V
MAINSW0_ICH
PM_RSTRST0
PM_SLP_S30/S40/S50
SUSTAT_B0
VDDM,VDDS
SYS_PWROK
VRON_VCCP
VCCP/1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGD
PCI_RST0
AGTL+_CPURST0
DCON
VDDA
PSUSC0
VDDS
VDDM
VR_ON
POWSW0
DCON
VDDA
PSUSC0
PM_PWROK
VR_ON
H
H
H
H
H
H
H
3
To ICH4_M
From ICH4_M
From ICH4_M
From ASIC_B0
From ASIC_B0
1.5VDDS AND
DDR_PWRGD
Generator
To clock
ToICH4 and ODEM
From ICH4 to CPU
To ODEM/other
PCI device
From ODEM to CPU
To ICH4
To ICH4
From ICH4
From ASIC_B0
From ASIC_B0
To clock generator
To ODEM and ICH4
From ICH4 to CPU
To ODEM/other PCI device
From ODEM to CPU
IMVP6 Power On Sequencing Timing Diagram
VID
VR_ON
Vcc-core
CPU_UP
Vccp
Vccp_UP
Vccgmch
GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD
2
Tsft_star_vcc(3ms max)
Tboot
Tcpu_up
Tvccp_up
Tgmch_pwrgd
Title
Size Document Number Rev
C
Date: Sheet of
Vid
Vboot
Tboot-vid-tr(100uS max)
Tboot:10-100uS
Tcpu_pwrgd(3~20mS)
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
MY050
Timing Diagram
1
6 50Monday, May 05, 2008
0.3
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8. Layout Guideline :
Crestline DDRII Layout Guidelines
DDRII Signal Groups
Group Signal Name
D D
Data
SA_DQ[63..0]/SB_DQ[63..0]
SA_DM[7..0]/SB_DM[7..0]
SA_DQS[7..0]/SA_DQS#[7..0]
SB_DQS[7..0]/SB_DQS#[7..0]
SA_MA[13..0]/SB_MA[13..0]Address
SA_BS[2..0]/SB_BS[2..0]
SA_RAS#/SB_RAS#
SA_CAS#/SB_CAS#
SA_WE#/SB_WE#
SM_CS#[3..0]Control
SM_CKE[3..0]
SM_ODT[3..0]
Clock SM_CK[3..0]
SM_CK#[3..0]
SA_RCVENOUT#/SB_RCVENOUT#FeedBack
SA_RCVENIN#/SB_RCVENIN#
CLK group : SM_CK[3..0],SM_CK#[3..0]
4/4/12 7/4/16 8/5/15
GMCH
C C
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width Inner Layer : 7 mils
Nominal CK to CK# Sp acing
(edge to edge)
Minimum Serpentine Spacing Inner Layer : 12 mils
Minimum Spacing to Other DDR2 Inner Layer : 16 mils
Minimum Isolation Spacing to non-DDR2 25 mils
Package Length Range - P1 1000 mils +/- 250 mils
Trace Length Limit - L0 Max = 50 mils (Escape)
Trace Length Limit - L1 Max = 500 mils (Breakout)
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils
B B
Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5 mils
Clock to Clock Length Match
(Total Length)
Breakout Exceptions (R educe geometries
for GMCH break-out region)
Breakin Exception s (Reduce geometries
for SO-DIMM break-in region)
Feedback group :
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#
These signals are routed internally on the GMCH package and don't require an y
routing on the MB. As a result, can be left as NC.
A A
4/4
P1P1L0L0L1L1L2L2S1
Escape Breakout Breakin
SLMS SL MS
5
Length Matching and Length Formulas
Signal Group Minimum Length Maximum Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe
Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Strobe - 220mils
SO-DIMM
S1
Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%
Outer Layer : 8 mils
Inner Layer : 4 mils
Outer Layer : 5 mils
Outer Layer : 15 mils
Outer Layer : 20 mils
Max = 4000 mils
Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1
Total Length for Channel A : X0
Total Length for Channel B : X1
Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils
Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2
Max. breakout length is 500 m ils
CK to CK# spacing rule waived at
connector spacing of 15 mils to
other DDR2
Max. breakin length is 2 00 mils
Clock - 0.0"
Clock + 1.0"
Clock + 1.0"
Strobe - 180mils
4
Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]
8/5/15
7/4/16
GMCH
P1
Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width
Minimum CTRL Trace Spac ing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Parallel Termination Resistor 56 +/- 5%
Maximim Via Count
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)
Command group :
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#
GMCH
P1
Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width
Minimum CMD Bus Trace Spacing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Trace Length L3
Parallel Termination Resistor
Maximim Via Count
CTRL to SCK/SCK # Length Matching
(Total Length including package)
for GMCH break-out region)
4/4/12
Escape
L1
L0
Breakout
SL
MS SL/MS
4/4
L1
Breakout
4/6,5/10
SL/MSMS SL
Escape
L0
L2
L3
SL/MS
S1
MS
SO-DIMM
Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 8 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 200 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 milsTrace Length L3
3
(CLK-1.0") </= CTRL </= (CLK-0.0")
Inner Layer : 4 mils spacing allowe d
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 m ils
4/6,5/10
L3
L2
SL/MS
S1
MS
SO-DIMM
Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 6 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 mils
56 +/- 5%
3
(CLK-1.0") </= CM D </= (CLK+1.0")
Inner Layer : 4 mils spacing allowe dBreakout Exceptions (R educe geometries
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 m ils
3
Vtt
Vtt
Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]
4/6
GMCH
P1 L0
4/4
Escape
L1
L2
Breakout
MS SLSL MS
S1
SO-DIMM
Topology
Reference Plane
Characteri stic Trace Impedance
Nominal Trace Width
Minimum DQ Bus Trace Spacing
Minimum Serpentine Spacing Same as DQ-to-DQ r outing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Trace Length L3
Maximim Via Count
DQ/DM to DQS Length Matching
(Total Length including
Breakout Exceptions (R educe geometries
package)
for GMCH break-out region)
Point-to-Point
Ground
55 +/- 15%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 6 mils
Outer Layer : 8 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
Max = 1500 mils
2
Match DQ/DM to [SDQS - 200mils]
+/- 20mils, per byte lane
Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mi ls
Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#
GMCH
P1
P1
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width
Nominal DQS to DQS# Spacing
(edge to edge)
Minimum Serpentine Spacing
Minimum Spacing to Other DDR2
Minimum Isolation Spacing to non-DDR2
Package Length Range - P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad
Maximim Via Count
DQS to DQS# Length Matching
Clock to Clock Length Match
(Total Length include package)
Breakout Exceptions (R educe geometries
for GMCH break-out region)
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)
Escape
L0
L0
4/4/8
L1
L1
Breakout
SL SL MS
4/4/12
L2
L2
SO-DIMM
5/5/10
S1
S1
Breakin
Differential Pair Point-to-Point
Ground
55 +/- 15%
85 +/- 20%
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 4 mils
Outer Layer : 5 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacin g
Outer Layer : 15 mils
Inner Layer : 8 mils
Outer Layer : 10 mils
Inner Layer : 12 mils
Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils
Max = 4500 mils
Max = 5000 mils
2 (Per side)
Match total length to within 5 mils
(CLK-0.5") </= D QS </= (CLK+1.0")
Inner Layer : 8 mils to other DDR2
Outer Layer : 10 mils to other DDR2
Max. breakout length is 500 mi ls
DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2
Max. breakin length is 2 00 mils
2
Title
Size Document Number Rev
Date: Sheet of
MY050
C
DDRII Layout Guideline
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
1
7 50Monday, May 05, 2008
0.3
A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#[35..3]
1
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
4 4
3 3
H_A#[35..3]11
H_ADSTB#011
H_REQ#[4..0]11
H_A#[35..3]
H_REQ#[4..0]
H_A#[35..3]11
H_ADSTB#111
H_A20M#21
H_FERR#21
H_IGNNE#21
H_STPCLK#21
H_INTR21
H_NMI21
H_SMI#21
T9
U26A
J4
ADDR
GROUP_0
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
ADDR
GROUP_1
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
ICH
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
D2
RSVD[06]
D22
RSVD[07]
D3
RSVD[08]
F6
RSVD[09]
Penryn
Rout to TP via and place gnd via w/in 100mils
A#[32-39], APM#[0-1]:Leave escape routing on for future functionality
H_D#[63..0]11
2 2
H_DSTBN#011
H_DSTBP#011
H_DINV#011
H_D#[63..0]11
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
R196 1KΩ 1% 1/16W SMT0402 LR
1.05VDDM
1 1
For Quad Core processor
change to 1.74K +/- 1%
RES 2KΩ 1% 1/16W SMT 0402 LR
A
H_DSTBN#111
H_DSTBP#111
H_DINV#111
R197
H_D#[63..0]
H_D#[63..0]
R182 1KΩ 5% 1/16W SMT0402 LR(NU)
C206
0.1uF 10V 10% SMT0402 X5R LR(NU)
Place C181 close to the CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference to GND
and away from other nossy signale.
CPU_BSEL017
CPU_BSEL117
H_GTLREF
TEST5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SI GNALS
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
U26B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn
B
H1
E2
G5
H5
F21
E1
F1
H_IERR#
R180 RES 56Ω 5% 1/16W SMT0402 LR
D20
B3
H4
C1
F3
F4
G3
G2
G6
HIT#
E4
AD4
AD3
AD1
AC4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
TCK
XDP_TDI
AA6
TDI
AB3
TDO
XDP_TMS
AB5
TMS
XDP_TRST#
AB6
XDP_DBRESET#
C20
D21
A24
B25
C7
A22
A21
H_ADS# 11
H_BNR# 11
H_BPRI# 11
H_DEFER# 11
H_DRDY# 11
H_DBSY# 11
H_BREQ# 11
H_INIT# 21
H_LOCK# 11
H_RS#0 11
H_RS#1 11
H_RS#2 11
H_TRDY# 11
H_HIT# 11
H_HITM# 11
0'' ~ 3''
H_THERMDA 10
H_THERMDC 10
PM_THRMTRIP# 12,21
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
1.05VDDM
R114 51Ω 5% 1/16W SMT0402 LR(NU)
1.05VDDM
R181
68Ω 5% 1/16W SMT0402 TIN LR
R189
0Ω 5% 1/16W SMT0402 LR(NU)
Should be connect to ICH9M and Crestline without T-ing(no stub)
XDP P/U & P/D
MISC
DATA GRP 0
DATA GRP 1
B
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
DATA GRP 2DATA GRP 3
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
XDP_DBRESET#
XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TCK
XDP_TRST#
H_D#[63..0]
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
SLP#
AE6
PSI#
H_D#[63..0]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
R190 RES 27.4Ω 1% 1/16W SMT 0402 LR
COMP1
R191 54.9Ω 1% 1/16W SMT0402 LR Sn
COMP2
R133 RES 27.4Ω 1% 1/16W SMT 0402 LRR183 1KΩ 5% 1/16W SMT0402 LR(NU)
COMP3TEST3
R132 54.9Ω 1% 1/16W SMT0402 LR Sn
H_DPRSTP# 12,21,43
H_DPSLP# 21
H_DPWR# 11
H_CPUSLP# 11
PSI# 43CPU_BSEL217
H_PWRGD rise time :
Max : 15ns
R178 1KΩ 5% 1/16W SMT0402 LR(NU)
R135 54.9Ω 1% 1/16W SMT0402 LR Sn
R134
R136
R138 54.9Ω 1% 1/16W SMT0402 LR Sn
R137 54.9Ω 1% 1/16W SMT0402 LR Sn
H_D#[63..0] 11
H_DSTBN#2 11
H_DSTBP#2 11
H_DINV#2 11
H_D#[63..0] 11
Comp0,2 connect with Zo=27.4ohm, make trace
length shorter than 0.5" and width is 18mils.
Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils
H_DSTBN#3 11
H_DSTBP#3 11
H_DINV#3 11
T12
Close to cpu
1
C
1.05VDDM
H_CPURST# 11
H_PROCHOT# 43
54.9Ω 1% 1/16W SMT0402 LR Sn
54.9Ω 1% 1/16W SMT0402 LR Sn
H_PWRGD 21
C
D
Topology : FERR#
VCCP
Rtt
L4
VCCP=1.05VDDM
ICH8MCPU
CPU IMVP6
VCCP L1
Rtt
L2
0.5" - 12"L1
VCCP
Rtt
L2+L1 L3 Strip-line
Topology : PWRGOOD
CPU
L1
ICH8M
L1
Transmission Line
Micro-strip
0.5" - 12"
0.5" - 12" Strip-line
Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#
Transmission Line
L1CPU ICH8M
L1
Topology : THERMTRIP#
GMCHL2CPU ICH7m
0.5" - 12" Micro-strip
Strip-line
0.5" - 12"
VCCP
L3
RttL1 L4
Rtt
3VDDM
1.05VDDM
FSB Common Clock Signal Layout Guide :
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
RS[2..0]# , TRDY# , RESET#.
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
Strip-line(Int. Layer)
Micro-strip(Ext. Layer)
FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :
Signals Name
DATA#[15..0] , DINV0#
DATA#[31..16] , DINV1# +/- 100 mil s
DATA#[47..32] , DINV2#
DATA#[63..48] , DINV3#
FSB Source Synchronous Data Signal Routing Topology#1 :
Signal Name
DINV#[3..0]
DATA#[63..0]
DSTBN#[3..0]
DSTBP#[3..0]
FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :
A#[16..3] , REQ#[4..0]
*** No length matching requirements exist between ADSTB0# and ADSTB1#
FSB Source Synchronous Address Signal Routing :
Signal Name
Address#[31..3]
REQ#[4..0]
ADSTB#[1..0]
1.0 ~ 6.5 inch 55+/-15%
Signals Matching
+/- 100 mils
+/- 100 mils
Transmission Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Signals MatchingSignals Name
+/- 200 mils
Transmission Line Type
Strip-line
Strip-line
D
Total Trace Length
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
Total Trace Length Normal Impedance
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
E
L2
Rtt Transmission Line
0" - 3.0" Microstrip0.5" - 12"
56 +/-5%
56 +/-5%
L3 L4
0" - 3.0"
0" - 3.0"
Stripline
0" - 3.0"
0" - 3.0"
Rtt Transmission LineL2L1
Micro-strip75 +/-5%0.5" - 6.5"
75 +/-5%0.5" - 6.5"
0" - 3.0"
0.5" - 6.5"
0.5" - 6.5"
Topology : CPUSLP#
Transmission Line
L1CPU
GMCH
0.5" - 12"
L1
0.5" - 12"
Micro-strip
Strip-line
Topology : RESET#
Transmission LineCPU
GMCH
L1
L1 L2
1" - 6" 0" - 3.0"
1" - 12"
1" - 12" 1" - 6"
Processor ITP Signal Default Strapping When ITP-XDP &
ITP700FLEX Dedbug Port Not Used.
Signal Resistor Value Connect To Resistor Placement
TDI
TMS
TRST#
TCK
TDO
Strobes associated with the group Strobe-to-Strobe Complement Matching
DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#
Strobes associated with the group
ADSTB0#+/- 200 mils
ADSTB1#A#[31..17]
1.05VDDM9,11,12,14,15,17,21,23,47
3VDDM10,12,15,17,18,19,20,21,22,23,24,25,26,27,28,30,33,34,36,37,40,41,43,46,49
L3
L1+L3
0" - 3.0"
1" - 12"
0" - 3.0"
1" - 12"
54.9 OHM +/-5%
54.9 OHM +/-5%
649 OHM +/-5%
54.9 OHM +/-5%
OPEN
4 & 8 mils
5 & 10 mils
Normal Impedance
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%
55+/-15%Strip-line
1.05VDDM
3VDDM
+/- 25 mils+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils
Width & Spacing (mils)
Data-to-Data,Strobe-to-strobe Strobe-to-Data
4 & 8 mils
4 & 8 mils
4 & 12 mils
4 & 12 mils
Strobe to Assoc. Address Signal Matching
+/- 200 mils
+/- 200 mils
Width & Spacing (mils)
4 & 8 mils
4 & 8 mils
4 & 8 mils
Title
MY050
Size Document Number Rev
C
Date: Sheet of
L1
Micro-strip
1" - 6"
Strip-line
1" - 6"
Rtt
Rss
56 +/-5%
24 +/-5%
24 +/-5% 56 +/-5%
VCCP
Within 2.0" of the CPU
VCCP
Within 2.0" of the CPU
GND
Within 2.0" of the CPU
GND
Within 2.0" of the CPU
NC
N/A
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
Merom Processor (1/2)
E
Transmission LineL4
Micro-strip
Strip-line0" - 3.0"
N/A
N/A
4 & 12 mils
4 & 12 mils
Confidential
8 50Monday, May 05, 2008
0.3
A
hexainf@hotmail.com
GRATUITO - FOR FREE
B
C
D
E
Place these inside socket cavity on L8
(North side secondary)
VCORE_CPU
4 4
HFM
ICC=41A
3 3
2 2
C140 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
Place these inside socket cavity on L1
(North side Primary)
C155 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C517 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
North side secondary
C175 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C169 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C160 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C146 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C152 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C515 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C540 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C516 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C162 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C174 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C145 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C179 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C185 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
South side secondary
Place these inside socket cavity on
L8 (South side secondary)
C184 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C159 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C168 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C151 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C177 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C147 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C141 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C178 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C173 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C539 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
Place these inside socket cavity on L1
(South side Primary)
C139 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C187 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C518 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C135 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C537 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C538 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
1.05VDDM
C132 0.1uF 16V ± 10% SMD0603 X7R LR
C190 0.1uF 16V ± 10% SMD0603 X7R LR
C136 0.1uF 16V ± 10% SMD0603 X7R LR
C192 0.1uF 16V ± 10% SMD0603 X7R LR
C191 0.1uF 16V ± 10% SMD0603 X7R LR
C131 0.1uF 16V ± 10% SMD0603 X7R LR
U26C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
AB9
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
H_VID0 43
H_VID1 43
H_VID2 43
H_VID3 43
H_VID4 43
H_VID5 43
H_VID6 43
VCORE_CPU
ICCP=4.5A,180mils
1/29 EMI
C163
+
220uF 2V ± 20% 15mΩ 7343 PANA LR
Place these inside socket cavity on L8
(North side secondary)
1.5VDDM
ICCA=130mA, 20mils
C202 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C195
0.01uF 16V 10% SMT0402 X7R LR
TDK
near
processor.
R165
100Ω 1% 1/16W SMT0402 LR
VCCSENSE 43
R161
100Ω 1% 1/16W SMT0402 LR
VSSSENSE 43
+
Place C?
Close To pin
B26
C656
220uF 2V ± 20% 15mΩ 7343 PANA LR(NU)
U26D
A4
VSS[082]
VSS[001]
A8
VSS[002]
VSS[083]
A11
VSS[003]
VSS[084]
A14
VSS[004]
VSS[085]
A16
VSS[005]
VSS[086]
A19
VSS[006]
VSS[087]
A23
VSS[007]
VSS[088]
AF2
VSS[008]
VSS[089]
B6
VSS[009]
VSS[090]
B8
VSS[010]
VSS[091]
B11
VSS[011]
VSS[092]
B13
VSS[012]
VSS[093]
B16
VSS[013]
VSS[094]
B19
VSS[014]
VSS[095]
B21
VSS[015]
VSS[096]
B24
VSS[016]
VSS[097]
C5
VSS[017]
VSS[098]
C8
VSS[018]
VSS[099]
C11
VSS[019]
VSS[100]
C14
VSS[020]
VSS[101]
C16
VSS[021]
VSS[102]
C19
VSS[022]
VSS[103]
C2
VSS[023]
VSS[104]
C22
VSS[024]
VSS[105]
C25
VSS[025]
VSS[106]
D1
VSS[026]
VSS[107]
D4
VSS[027]
VSS[108]
D8
VSS[028]
VSS[109]
D11
VSS[029]
VSS[110]
D13
VSS[030]
VSS[111]
D16
VSS[031]
VSS[112]
D19
VSS[032]
VSS[113]
D23
VSS[033]
VSS[114]
D26
VSS[034]
VSS[115]
E3
VSS[035]
VSS[116]
E6
VSS[036]
VSS[117]
E8
VSS[037]
VSS[118]
E11
VSS[038]
VSS[119]
E14
VSS[039]
VSS[120]
E16
VSS[040]
VSS[121]
E19
VSS[041]
VSS[122]
E21
VSS[042]
VSS[123]
E24
VSS[043]
VSS[124]
F5
VSS[044]
VSS[125]
F8
VSS[045]
VSS[126]
F11
VSS[046]
VSS[127]
F13
VSS[047]
VSS[128]
F16
VSS[048]
VSS[129]
F19
VSS[049]
VSS[130]
F2
VSS[050]
VSS[131]
F22
VSS[051]
VSS[132]
F25
VSS[052]
VSS[133]
G4
VSS[053]
VSS[134]
G1
VSS[054]
VSS[135]
G23
VSS[055]
VSS[136]
G26
VSS[056]
VSS[137]
H3
VSS[057]
VSS[138]
H6
VSS[058]
VSS[139]
H21
VSS[059]
VSS[140]
H24
VSS[060]
VSS[141]
J2
VSS[061]
VSS[142]
J5
VSS[062]
VSS[143]
J22
VSS[063]
VSS[144]
J25
VSS[064]
VSS[145]
K1
VSS[065]
VSS[146]
K4
VSS[066]
VSS[147]
K23
VSS[148]
VSS[067]
K26
VSS[068]
VSS[149]
L3
VSS[069]
VSS[150]
L6
VSS[070]
VSS[151]
L21
VSS[071]
VSS[152]
L24
VSS[072]
VSS[153]
M2
VSS[073]
VSS[154]
M5
VSS[074]
VSS[155]
M22
VSS[075]
VSS[156]
M25
VSS[076]
VSS[157]
N1
VSS[077]
VSS[158]
N4
VSS[078]
VSS[159]
N23
VSS[079]
VSS[160]
N26
VSS[080]
VSS[161]
P3 A25
VSS[081] VSS[162]
VSS[163]
Penryn
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
.
1 1
Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50mil spacing.
Place PU and PD within 1 inch of CPU
A
B
C
D
Title
MY050
Size Document Number Rev
C
Merom Processor (2/2)
Date: Sheet of
VCORE_CPU43
1.05VDDM8,11,12,14,15,17,21,23,47
1.5VDDM14,15,20,21,23,33,40,47
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
E
VCORE_CPU
1.05VDDM
1.5VDDM
Confidential
9 50Monday, May 05, 2008
0.3
8
D D
7
5VDDM
1000pF 50V 10% SM T0402 X7R LR(NU)
30mil
v0.4 update
6
C382
R308
1KΩ 5% 1/16W SMT0402 LR
0Ω 5% 1/16W SMT0402 LR
FAN_PWM41
5
Q27
DS
TRANS M-FET-P APM2301AAC-TRL -20V -3A SOT23 3PIN ANPEC LR
G
v0.3 update
R309
DIODE ZENER GLZ6.2B 6.2V 20mA MINI-MELF 2PIN PSI LR
Q26
B
NPN PDTC144EU SOT-323 PHILIPS LR
E C
P N
30mil
D28
4
v0.3 update
C396
MO-CAP 1000pF 16V 10% SMT0402 X7R LR
CN14
FAN1
FAN_SPEED41
1
2
345
CON ACES SMT TYPE 85205-03001 WIRE 1.25P 3PIN LR DO'NT CARE
20-24197-20
L-20-24197-20
3
2
1
C C
THERMAL SENSOR
3VDDM
RP4
RP 2.2KΩ 5% SMT1010 4P2R 1/16W LR
10mil
TH_ALRT#
8
7
6
U9
SMBCLK
SMBDATA
ALERT
U8
8
7
6
SCLK
SDATA
ALRT#
VCC
DXP
DXN
THERMGND
VCC
D+
THM#GND
QSMCLK_PMU
QSMDAT_PMU
R200
3VDDM
10KΩ 5% 1/16W SMT0402 LR
LNR-IC TEMPERATURE SENSOR G780RD1U 3-5.5V TDFN 8PIN GMT LR
B B
QSMCLK_PMU
QSMDAT_PMU
TH_ALRT#
LNR-IC Temperature Sensor G780P81U 3.0-5.5V MSOP-8 8PIN GMT LR(NU)
20mil
C204
0.1uF 16V 80-20% SMT0402 Y5V LR
1
2
3
45
1
H_THERMDA
2
H_THERMDC
3
D-
HOT_DOWN#
45
C211
2200pF 50V 10% SMT0402 X7R LR
HOT_DOWN#
R195
10KΩ 5% 1/16W SMT0402 LR
3VDDM
HOT_DOWN# 41
3VDDA
H_THERMDA
H_THERMDC
H_THERMDA 8
H_THERMDC 8
SMCLK_PMU41,44
3VDDM
SMDAT_PMU41,44
A A
3VDDM
10 mil
10 mil
D S
D S
GND
10 mil
THERMDA
Minimum
THERMDC
10 mil
GND
Q15
QSMCLK_PMU
TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR
G
G
Q14
QSMDAT_PMU
TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR
First International Computer, Inc.
MY050
CPU Thermal
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
1
Confidential
10 50Monday, May 05, 2008
0.3
3VDDA20,21,22,23,24,25,26,29,30,33,34,39,40,41,44,46,48
3VDDM8,12,15,17,18,19,20,21,22,23,24,25,26,27,28,30,33,34,36,37,40,41,43,46,49
5VDDM23,28,29,31,37,38,43,46,47,49
8
7
6
5
4
3
3VDDA
3VDDM
Title
5VDDM
Size Document Number Rev
C
Date: Sheet of
2
10
hexainf@hotmail.com
GRATUITO - FOR FREE
9
8
7
6
5
4
3
2
1
H H
G G
1.05VDDM
R122
RES 221Ω 1% 1/16W SMT0402 RR0510S-2210-FN CYNTEC LR
For Quad Core processor
F F
change to 75 +/- 1%
R121
100Ω 1% 1/16W SMT0402 LR
H_SWING
C107
0.1uF 10V 10% SMT0402 X5R LR
H_D#[63..0]8
H_D#[63..0]
close to the pin
Trace should be 10-mil wide with 20-mil spacing.
For Quad Core processor
change to 16.9 +/- 1%
H_RCOMP
R129
RES 24.9Ω 1% 1/16W SMT0402 LR
E E
D D
H_SWING
H_RCOMP
H_CPURST#8
C C
1.05VDDM
R116
1KΩ 1% 1/16W SMT0402 LR
B B
R125
RES 2KΩ 1% 1/16W SMT 0402 LR
H_CPUSLP#8
H_AVREF
U25A
H_D#0
F2
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
AD14
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
AA13
H_D#_42
AA9
H_D#_43
AA11
H_D#_44
AD11
H_D#_45
AD10
H_D#_46
AD13
H_D#_47
AE12
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
AE14
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
AE11
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DRDY#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_HIT#
H_A#3
A14
H_A#4
C15
H_A#5
F16
H_A#6
H13
H_A#7
C18
H_A#8
M16
H_A#9
J13
H_A#10
P16
H_A#11
R16
H_A#12
N17
H_A#13
M13
H_A#14
E17
H_A#15
P17
H_A#16
F17
H_A#17
G20
H_A#18
B19
H_A#19
J16
H_A#20
E20
H_A#21
H16
H_A#22
J20
H_A#23
L17
H_A#24
A17
H_A#25
B17
H_A#26
L16
H_A#27
C21
H_A#28
J17
H_A#29
H20
H_A#30
B18
H_A#31
K17
H_A#32
B20
H_A#33
F21
H_A#34
K21
H_A#35
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
H_REQ#0
B15
H_REQ#1
K13
H_REQ#2
F13
H_REQ#3
B13
H_REQ#4
B14
B6
F12
C8
H_A#[35..3]
H_REQ#[4..0]
H_A#[35..3] 8
H_ADS# 8
H_ADSTB#0 8
H_ADSTB#1 8
H_BNR# 8
H_BPRI# 8
H_BREQ# 8
H_DEFER# 8
H_DBSY# 8
H_DPWR# 8
H_DRDY# 8
H_HIT# 8
H_HITM# 8
H_LOCK# 8
H_TRDY# 8
H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8
H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8
H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8
H_REQ#[4..0] 8
H_RS#0 8
H_RS#1 8
H_RS#2 8
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
First International Computer, Inc.
A A
10
9
8
7
6
5
4
1.05VDDM8,9,12,14,15,17,21,23,47 1.05VDDM
3
Title
Size Document Number Rev
C
Date: Sheet of
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
MY050
Crestline Host (1/6)
2
Confidential
11 50Monday, May 05, 2008
0.3
1
10
H H
SM_RCOMP_VOH
C203
C197
2.2uF 6.3V 80-20% SMT0603 Y5V LR
0.01uF 16V 10% SMT0402 X7R LR
SM_RCOMP_VOL
C201
C196
2.2uF 6.3V 80-20% SMT0603 Y5V LR
0.01uF 16V 10% SMT0402 X7R LR
G G
F F
E E
PM_SYNC#22
D D
C C
MCH_CFG_19
MCH_CFG_20
MCH_CFG_5
MCH_CFG_6
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
H_DPRSTP#8,21,43
PM_EXTTS#018
PM_EXTTS#119
DELAY_VR_PWRGOOD24,43
PLT_RST#20
PM_THRMTRIP#8,21
PM_DPRSLPVR22,43,49
R153 4.02KΩ 1% 1/16W SMT0402 LR
R152 4.02KΩ 1% 1/16W SMT0402 LR(NU)
R482 2.21KΩ 1% 1/16W SMT0402 LR(NU)
R151 2.21KΩ 1% 1/16W SMT0402 LR(NU)
R481 2.21KΩ 1% 1/16W SMT0402 LR(NU)
R150 2.21KΩ 1% 1/16W SMT0402 LR(NU)
R156 2.21KΩ 1% 1/16W SMT0402 LR(NU)
R144 2.21KΩ 1% 1/16W SMT0402 LR(NU)
B B
GMCH Strapping Requirements
CFG [2:0]
CFG5
CFG9
A A
CFG [12:13]
011 = 667 MT/s ( 677MHz ) FSB
001 = 533 MT/s ( 533MHz ) FSB
0 = DMI * 2
1 = DMI * 4 ( Default )
0 = Lane Reverse
1 = Normal Operation( Default )
00 = Clock Gating Disable
01 = XOR Mode Enabled
10 = All Z Mode Enable
11 = Normal Operation ( Default )
10
1.8VDDS
R193
1KΩ 1% 1/16W SMT0402 LR
R198
3.01K 1% 1/10W 0603 LR
R192
1KΩ 1% 1/16W SMT0402 LR
MCH_BSEL017
MCH_BSEL117
MCH_BSEL217
1
T15
R174
100Ω 1% 1/16W SMT0402 LR
9
9
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
PM_EXTTS#0
PM_EXTTS#1
RST_IN#_MCH
3VDDM
8
U25B
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
T24
RSVD14
B31
RSVD15
M1
RSVD17
AY21
RSVD20
B2
RSVD21
BG23
RSVD22
BF23
RSVD23
BH18
RSVD24
BF18
RSVD25
AL34
ME_JTAG_TCK
AK34
ME_JTAG_TDI
AN35
ME_JTAG_TDO
AM35
ME_JTAG_TMS
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC_1
BF48
NC_2
BD48
NC_3
BC48
NC_4
BH47
NC_5
BG47
NC_6
BE47
NC_7
BH46
NC_8
BF46
NC_9
BG45
NC_10
BH44
NC_11
BH43
NC_12
BH6
NC_13
BH5
NC_14
BG4
NC_15
BH3
NC_16
BF3
NC_17
BH2
NC_18
BG2
NC_19
BE2
NC_20
BG1
NC_21
BF1
NC_22
BD1
NC_23
BC1
NC_24
F1
NC_25
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
CFG16
CFG18
(PCIE)
CFG19
CFG20
CFG6
RSVD
ME JTAG
CFG
PM
NC
0 = Dynamic ODT Disabled
1 = DMI Lane Reversal Enabled ( Default )
0 = VCC->1.05V ( Default )
1 = VCC->1.5V
0 = Normal ( Default )
1 = Lanes Reversed
0 = Only SDVO or PCIE X1 is operationl ( default )
1 = SDVO or PCIE X1 are operatingsimulaneously via the PEG port.
0 = ITPM Host Interface is Enabled
1 = ITPM Host Interface is Disabled( Default )
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DDR CLK/ CONTROL/COMPENSATIONCLK
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VIDMEHDA
CL_PWROK
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MISC
HDA_BCLK
HDA_RST#
HDA_SDO
HDA_SYNC
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
PEG_CLK
CL_CLK
CL_DATA
CL_RST#
CL_VREF
TSATN#
HDA_SDI
8
7
AP24
AT21
AV24
AU20
AR24
AR21
AU24
AV20
BC28
AY28
AY36
BB36
BA17
AY16
AV16
AR13
BD17
AY17
BF15
AY13
SM_RCOMP
BG22
SM_RCOMP#
BH21
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
AV42
AR36
BF17
BC36
SM_DRAMRST#
B38
A38
E41
F41
F43
E43
DMI_TXP0
AE41
DMI_TXP1
AE37
DMI_TXP2
AE47
DMI_TXP3
AH39
DMI_TXN0
AE40
DMI_TXN1
AE38
DMI_TXN2
AE48
DMI_TXN3
AH40
DMI_RXP0
AE35
DMI_RXP1
AE43
DMI_RXP2MCH_CFG_6
AE46
DMI_RXP3
AH42
DMI_RXN0
AD35
DMI_RXN1
AE44
DMI_RXN2
AF46
DMI_RXN3
AH43
DFGT_VID_0
B33
DFGT_VID_1
B32
DFGT_VID_2
G33
DFGT_VID_3
F33
DFGT_VID_4
E33
C34
R127
100KΩ 1% 1/16W SMT0402 LR
AH37
AH36
AN36
AJ35
AH34
0.1uF 10V 10% SMT0402 X5R LR
DDPC_CTRLCLK
N28
DDPC_CTRLDATA
M28
SDVO_CTRL_CLK
G36
SDVO_CTRL_DATA
E36
CLK_MCH_OE#
K36
H36
MCH_TSATN#
B12
B28
B30
B29
C29
A28
7
M_CLK_DDR0 18
M_CLK_DDR1 18
M_CLK_DDR3 19
M_CLK_DDR4 19
M_CLK_DDR#0 18
M_CLK_DDR#1 18
M_CLK_DDR#3 19
M_CLK_DDR#4 19
M_CKE0 18
M_CKE1 18
M_CKE3 19
M_CKE4 19
M_CS#0 18
M_CS#1 18
M_CS#2 19
M_CS#3 19
M_ODT0 18
M_ODT1 18
M_ODT2 19
M_ODT3 19
R188 80.6Ω 1% 1/16W SMT0402 LR
R187 80.6Ω 1% 1/16W SMT0402 LR
20miles
DDR_VREF
R179
499Ω 1% 1/16W SMT0402 LR
CL_REF
1
DREFCLK 17
DREFCLK# 17
DREFSSCLK 17
DREFSSCLK# 17
CLK_PCIE_3GPLL 17
CLK_PCIE_3GPLL# 17
DFGT_VID_0 49
DFGT_VID_1 49
DFGT_VID_2 49
DFGT_VID_3 49
DFGT_VID_4 49
DFGT_VR_EN 49
CL_CLK0 22
CL_DATA0 22
MPWROK 22,24,41
CL_RST#0 22
C156
CLK_MCH_OE# 17
MCH_ICH_SYNC# 22
R115 RES 56Ω 5% 1/16W SMT0402 LR
6
1.8VDDS
R175
10KΩ 1% 1/16W SMT0402 LR
T13
DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20
DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20
DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20
DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20
1.05VDDM
R172
1KΩ 1% 1/16W SMT0402 LR
CL_REF
R171
511Ω 1% 1/10W SMT0603 LR
VECLK27
VEDAT27
(DMI lane)
6
5
NB_BRIGHTNESS26
LVDS_ENABKL41
LVDS_DDC_CLK26
LVDS_DDC_DATA26
LVDS_ENALCD26
LVDS_TXCLK_LN26
LVDS_TXCLK_LP26
LVDS_TXCLK_UN26
LVDS_TXCLK_UP26
LVDS_TXOUT_L0N26
LVDS_TXOUT_L1N26
LVDS_TXOUT_L2N26
LVDS_TXOUT_L0P26
LVDS_TXOUT_L1P26
LVDS_TXOUT_L2P26
LVDS_TXOUT_U0N26
LVDS_TXOUT_U1N26
LVDS_TXOUT_U2N26
LVDS_TXOUT_U0P26
LVDS_TXOUT_U1P26
LVDS_TXOUT_U2P26
R139 75Ω 1% 1/16W SMT0402 LR
R143 75Ω 1% 1/16W SMT0402 LR
R146 75Ω 1% 1/16W SMT0402 LR
R142 RES 150Ω 1% 1/16W SMT0402 LR
R140 RES 150Ω 1% 1/16W SMT0402 LR
R130 RES 150Ω 1% 1/16W SMT0402 LR
BLUE28
GREEN28
RED28
HSYNC28
VSYNC28
0.35V
1.05VDDM
R627 0Ω 5% 1/16W SMT0402 LR
R629 0Ω 5% 1/16W SMT0402 LR
R631 0Ω 5% 1/16W SMT0402 LR(NU)
R633 0Ω 5% 1/16W SMT0402 LR(NU)
5
4
3VDDM
R124
R154
TV_DCONSEL0
TV_DCONSEL1
CRT_DDC_CLK
CRT_DDC_DATA
TV_Y
TV_C
10KΩ 5% 1/16W SMT0402 LR
R131
100KΩ 5% 1/16W SMT0402 LR
RES 2.4KΩ 1% 1/16W SMT0402 LR
R141 0Ω 5% 1/16W SMT0402 LR
R147 0Ω 5% 1/16W SMT0402 LR
V 0.3
PM_EXTTS#0
PM_EXTTS#1
CLK_MCH_OE#
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CRT_DDC_CLK
CRT_DDC_DATA
V 0.2
DDPC_CTRLCLK
DDPC_CTRLDATA
4
3
1.05VDDM_PEG
R149
10KΩ 5% 1/16W SMT0402 LR
U25C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
R128
1.02KΩ 1% 1/16W SMT0402 LR
If the total motherboard route length is less than 12 ”, the
recommended reference resistor value is 1 k Ω ±1% .
For longer route lengths between 12 ”-15.3”, the
recommended reference resistor value is 976 Ω ±1%
RP3
124
R148 10KΩ 5% 1/16W SMT0402 LR
R628 2.2KΩ 5% 1/16W SMT0402 LR
R630 2.2KΩ 5% 1/16W SMT0402 LR
R632 2.2KΩ 5% 1/16W SMT0402 LR
R634 2.2KΩ 5% 1/16W SMT0402 LR
R635 2.2KΩ 5% 1/16W SMT0402 LR
R636 2.2KΩ 5% 1/16W SMT0402 LR
1.05VDDM8,9,11,14,15,17,21,23,47
3VDDM8,10,15,17,18,19,20,21,22,23,24,25,26,27,28,30,33,34,36,37,40,41,43,46,49
1.8VDDS14,15,18,19,48
DDR_VREF18,19,48
1.05VDDM_PEG15
LVDS
TV
PCI-EXPRESS GRAPHICS
VGA
10KΩ 5% SMT1010 1/16W 4P2R LR
3
1.05VDDM
3VDDM
1.8VDDS
DDR_VREF
1.05VDDM_PEG
3
T37
PEG_COMPI
T36
PEG_COMPO
H44
PEG_RX#_0
J46
PEG_RX#_1
L44
PEG_RX#_2
L40
PEG_RX#_3
N41
PEG_RX#_4
P48
PEG_RX#_5
N44
PEG_RX#_6
T43
PEG_RX#_7
U43
PEG_RX#_8
Y43
PEG_RX#_9
Y48
PEG_RX#_10
Y36
PEG_RX#_11
AA43
PEG_RX#_12
AD37
PEG_RX#_13
AC47
PEG_RX#_14
AD39
PEG_RX#_15
H43
PEG_RX_0
J44
PEG_RX_1
L43
PEG_RX_2
L41
PEG_RX_3
N40
PEG_RX_4
P47
PEG_RX_5
N43
PEG_RX_6
T42
PEG_RX_7
U42
PEG_RX_8
Y42
PEG_RX_9
W47
PEG_RX_10
Y37
PEG_RX_11
AA42
PEG_RX_12
AD36
PEG_RX_13
AC48
PEG_RX_14
AD40
PEG_RX_15
J41
PEG_TX#_0
M46
PEG_TX#_1
M47
PEG_TX#_2
M40
PEG_TX#_3
M42
PEG_TX#_4
R48
PEG_TX#_5
N38
PEG_TX#_6
T40
PEG_TX#_7
U37
PEG_TX#_8
U40
PEG_TX#_9
Y40
PEG_TX#_10
AA46
PEG_TX#_11
AA37
PEG_TX#_12
AA40
PEG_TX#_13
AD43
PEG_TX#_14
AC46
PEG_TX#_15
J42
PEG_TX_0
L46
PEG_TX_1
M48
PEG_TX_2
M39
PEG_TX_3
M43
PEG_TX_4
R47
PEG_TX_5
N37
PEG_TX_6
T39
PEG_TX_7
U36
PEG_TX_8
U39
PEG_TX_9
Y39
PEG_TX_10
Y46
PEG_TX_11
AA36
PEG_TX_12
AA39
PEG_TX_13
AD42
PEG_TX_14
AD46
PEG_TX_15
3VDDM
Title
Size Document Number Rev
C
Date: Sheet of
2
500 mil
R160
49.9Ω 1% 1/16W SMT0402 LR
PEG_ COMP
TMDS_B_HPD# 27
PEG_TX#_0
C487
PEG_TX#_1
C490
PEG_TX#_2
C492
PEG_TX#_3
C493
0.1uF 10V 10% SMT0402 X5R LR
PEG_TX_0
C488
PEG_TX_1
C489
PEG_TX_2
C491
PEG_TX_3
C494
0.1uF 10V 10% SMT0402 X5R LR
TV_DCONSEL0
TV_DCONSEL1
R120 0Ω 5% 1/16W SMT0402 LR
R119 0Ω 5% 1/16W SMT0402 LR
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
MY050
Crestline DMI/Graphic (2/6)
2
1
DVI_HPD
TMDS_B_DATA2# 27
TMDS_B_DATA1# 27
TMDS_B_DATA0# 27
TMDS_B_CLK# 27
TMDS_B_DATA2 27
TMDS_B_DATA1 27
TMDS_B_DATA0 27
TMDS_B_CLK 27
Confidential
12 50Monday, May 05, 2008
1
DVI
DVI
0.3
10
hexainf@hotmail.com
GRATUITO - FOR FREE
9
8
7
6
5
4
3
2
1
H H
G G
M_A_DQ[63..0]18 M_B_DQ[63..0]19
F F
E E
D D
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U25D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BD21
BG18
AT25
BB20
BD20
AY20
M_A_DM0M_A_DM0
AM37
M_A_DM1M_A_DM1
AT41
M_A_DM2M_A_DM2
AY41
M_A_DM3M_A_DM3
AU39
M_A_DM4M_A_DM4
BB12
M_A_DM5M_A_DM5
AY6
M_A_DM6M_A_DM6
AT7
M_A_DM7M_A_DM7
AJ5
M_A_DQS0M_A_DQS0
AJ44
M_A_DQS1M_A_DQS1
AT44
M_A_DQS2M_A_DQS2
BA43
M_A_DQS3M_A_DQS3
BC37
M_A_DQS4M_A_DQS4
AW12
M_A_DQS5
BC8
M_A_DQS6M_A_DQS6
AU8
M_A_DQS7M_A_DQS7
AM7
M_A_DQS#0M_A_DQS#0
AJ43
M_A_DQS#1M_A_DQS#1
AT43
M_A_DQS#2M_A_DQS#2
BA44
M_A_DQS#3M_A_DQS#3
BD37
M_A_DQS#4M_A_DQS#4
AY12
M_A_DQS#5M_A_DQS#5
BD8
M_A_DQS#6M_A_DQS#6
AU9
M_A_DQS#7M_A_DQS#7
AM8
M_A_A0M_A_A0
BA21
M_A_A1M_A_A1
BC24
M_A_A2M_A_A2
BG24
M_A_A3
BH24
M_A_A4
BG25
M_A_A5M_A_A5
BA24
M_A_A6M_A_A6
BD24
M_A_A7
BG27
M_A_A8M_A_A8
BF25
M_A_A9
AW24
M_A_A10
BC21
M_A_A11
BG26
M_A_A12
BH26
M_A_A13
BH17
M_A_A14 M_B_A13
AY25
M_A_DM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_BS0 18
M_A_BS1 18
M_A_BS2 18
M_A_RAS# 18
M_A_CAS# 18
M_A_WE# 18
M_A_DM[7..0] 18
M_A_DQS[7..0] 18
M_A_DQS#[7..0] 18
M_A_A[14..0] 18
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U25E
AK47
SB_DQ_0
AH46
SB_DQ_1
AP47
SB_DQ_2
AP46
SB_DQ_3
AJ46
SB_DQ_4
AJ48
SB_DQ_5
AM48
SB_DQ_6
AP48
SB_DQ_7
AU47
SB_DQ_8
AU46
SB_DQ_9
BA48
SB_DQ_10
AY48
SB_DQ_11
AT47
SB_DQ_12
AR47
SB_DQ_13
BA47
SB_DQ_14
BC47
SB_DQ_15
BC46
SB_DQ_16
BC44
SB_DQ_17
BG43
SB_DQ_18
BF43
SB_DQ_19
BE45
SB_DQ_20
BC41
SB_DQ_21
BF40
SB_DQ_22
BF41
SB_DQ_23
BG38
SB_DQ_24
BF38
SB_DQ_25
BH35
SB_DQ_26
BG35
SB_DQ_27
BH40
SB_DQ_28
BG39
SB_DQ_29
BG34
SB_DQ_30
BH34
SB_DQ_31
BH14
SB_DQ_32
BG12
SB_DQ_33
BH11
SB_DQ_34
BG8
SB_DQ_35
BH12
SB_DQ_36
BF11
SB_DQ_37
BF8
SB_DQ_38
BG7
SB_DQ_39
BC5
SB_DQ_40
BC6
SB_DQ_41
AY3
SB_DQ_42
AY1
SB_DQ_43
BF6
SB_DQ_44
BF5
SB_DQ_45
BA1
SB_DQ_46
BD3
SB_DQ_47
AV2
SB_DQ_48
AU3
SB_DQ_49
AR3
SB_DQ_50
AN2
SB_DQ_51
AY2
SB_DQ_52
AV1
SB_DQ_53
AP3
SB_DQ_54
AR1
SB_DQ_55
AL1
SB_DQ_56
AL2
SB_DQ_57
AJ1
SB_DQ_58
AH1
SB_DQ_59
AM2
SB_DQ_60
AM3
SB_DQ_61
AH3
SB_DQ_62
AJ3
SB_DQ_63
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
DDR SYSTEM MEMORY B
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
BC16
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A14
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_BS0 19
M_B_BS1 19
M_B_BS2 19
M_B_RAS# 19
M_B_CAS# 19
M_B_WE# 19
M_B_DM[7..0] 19
M_B_DQS[7..0] 19
M_B_DQS#[7..0] 19
M_B_A[14..0] 19
C C
TV DAC Routing Guideline
1. The minimum spacing between each RGB is 40-mils while 50-mils is preferred
2. RGB signals should be routed on the same layer, have a similar number of bends,
same number of vias
3. All routing should be done with ground referencing as well
4. TV DAC route lengths should be lenght match to within 200 mils
Filter
0.5"
Mini
DIN7
B B
GMCH
0.5"
0.2"
12"
TV DAC
TV IRTN
150ohm
150ohm
Zo=37.5
Zo=50
A A
10
9
8
7
6
5
Zo=75
Title
Size Document Number Rev
C
4
3
Date: Sheet of
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
MY050
Crestline DDR2 (3/6)
2
Confidential
13 50Monday, May 05, 2008
1
0.3
10
9
8
7
6
5
4
3
2
1
H H
BG32
AW32
BG31
BG30
BG29
AW29
AW16
AW13
AG21
AM15
AG15
AM14
AN33
BH32
BF32
BD32
BC32
BB32
BA32
AY32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BF31
BH29
BF29
BD29
BC29
BB29
BA29
AY29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AT13
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AL15
AE15
AJ15
AH15
AF15
AB15
AA15
Y15
V15
U15
AN14
U14
T14
AJ14
AH14
U25G
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC SMVCC GFX
VCC_AXG_NCTF_1VCC_SM_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
POWER
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC GFX NCTF
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
W28AP33
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C157 1uF 10V +80-20% 0603 Y5V LR(NU)
C133 0.1uF 10V 10% SMT 0402 X5R LR
C148 0.47u F 10V ± 10% SMD 0603 X5R LR
C138 10uF 6.3V 10% SMT 0805 X5R C2012X 5R0J106K TDK LR
C164 0.1uF 10V 10% SMT 0402 X5R LR
12
C167 0.1uF 10V 10% SMT0402 X5R LR
C180 MO-CAP 0 .22uF 6.3V 10% SMT0402 X5R LR
C182 MO-CAP 0 .22uF 6.3V 10% SMT0402 X5R LR
C186 0.1uF 10V 10% SMT 0402 X5R LR
C181 1uF 10V +80-20% SMT 0603 Y5V LMK10 7F105ZA-T TAIYO LR
C166 MO-CAP 0 .47UF 6.3V 10% SMT0402 X5R LR
C183 1uF 10V +80-20% SMT0603 Y5V LMK107F105ZA-T TAIYO LR
1.8VDDS
1/29 EMI
VIA=2400mA / 100mils
C205 10uF 6.3V 10% SMT 0805 X5R C2012X 5R0J106K TDK LR(NU)
C189 0.1uF 10V 10% SMT 0402 X5R LR
C200 10uF 6.3V 10% SMT 0805 X5R C2012X 5R0J106K TDK LR(NU)
C215 220uF 2V ± 20% 15mΩ 7343 P ANA LR
+
G G
F F
VCC_SM_36
VCC_SM_37
For DDR2, VCC_SM_36/37/38/40/42 could
be left NC.
VGA_VDD
VCC_SM_38
VCC_SM_40
VCC_SM_42
VIA=7700mA / 320mils
E E
D D
C C
VCC_AXG_SENSE49
VSS_AXG_SENSE49
VGA_VDD
C42 P220uF 2V ±20% 15mΩ 7343 PANA LR
C458 P220u F 2V ± 20% 15mΩ 7343 PANA LR(NU)
C457 10uF 6.3V 10% SMT 0805 X5R C2012X5R0J106K TDK LR(NU)
v0.3 update
+
+
1.05VDDM
C501 220uF 2V ± 20% 15mΩ 7343 P ANA LR(NU)
+
Close to GMCH
0Ω 5% 1/4W SMT1206 LR
1.5VDDM
20mils
C171 10uF 6.3V 10% SMT 0805 X5R C2012X 5R0J106K TDK LR
C506 0.22u F 10V 10% SMT0603 X7R LR
C505 0.22u F 10V 10% SMT 0603 X7R LR
R164
308mils
C143 0.1uF 10V 10% SMT 0402 X5R LR
+VCC_MCH_35
R194
RES 10Ω 1% 1/16W SMT0402 LR
U25F
AG34
VCC_1
AC34
VCC_2
AB34
VCC_3
AA34
VCC_4
Y34
VCC_5
V34
VCC_6
U34
VCC_7
AM33
VCC_8
AK33
VCC_9
AJ33
VCC_10
AG33
VCC_11
AF33
VCC_12
AE33
VCC_13
AC33
VCC_14
AA33
VCC_15
Y33
VCC_16
W33
VCC_17
V33
VCC_18
U33
VCC_19
AH28
VCC_20
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
VCC CORE
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
POWER
VCC NCTF
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
D8
N P
DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
1.05VDDM
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
1.05VDDM
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
B B
1.05VDDM8,9,11,12,15,17,21,23,47
1.5VDDM9,15,20,21,23,33,40,47
A A
10
9
8
7
6
5
4
1.8VDDS12,15,18,19,48
VGA_VDD20,49
3
1.05VDDM
1.5VDDM
1.8VDDS
VGA_VDD
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet of
(886-2)8751-8751
MY050
Crestline Power (4/6)
2
Confidential
14 50Monday, May 05, 2008
1
0.3
10
hexainf@hotmail.com
GRATUITO - FOR FREE
9
8
7
6
5
4
3
2
1
20mils
1.05VDDM
H H
G G
1.05VDDM
L10 SPWR 0 5% 1/16W 0603
L15 SPWR 0 5% 1/16W 0603
20mils
L51 SPWR 0 5% 1/16W 0603
L54 SPWR 0 5% 1/16W 0603
F F
T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
E E
D D
1.5VDDM
C C
1.05VDDM
B B
VIA=80mA / 10mils
C117
0.1uF 10V 10% SMT0402 X5R LR
C106
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)
C126
C129
0.1uF 10V 10% SMT0402 X5R LR
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR(NU)
C514
0.1uF 10V 10% SMT0402 X5R LR
C513
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C519
0.1uF 10V 10% SMT0402 X5R LR
R489
RES 1Ω 1% 1/16W SMT 0402 LR
C524
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
1.05VDDM
3VDDM
FER-BEAD 150Ω±25% 100MHz 2000mA SMT0603 PBY160808T-151Y-N CHILISIN LR
L9 SPWR 0 5% 1/16W 0603
(24mA)
L16
FER-BEAD 150Ω±25% 100MHz 2000mA SMT0603 PBY160808T-151Y-N CHILISIN LR
RES 1Ω 1% 1/16W SMT 0402 LR
C144
10uF 10V +80-20% SMT0805 Y5V LR
1.05VDDM_DPLLA
VIA=80mA / 10mils
1.05VDDM_DPLLB
VIA=50mA / 10mils
1.05VDDM_HPLL
VIA=150mA / 10mils
1.05VDDM_MPLL
R229 SPWR 0 5% 1/16W 0402
L20 SPWR 0 5% 1/16W 0603
C511
+
L11
R166
C210
C208
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
1.05VDDM
VCCA_TVDAC
(24mA)
L12
FER-BEAD 150Ω±25% 100MHz 2000mA SMT0603 PBY160808T-151Y-N CHILISIN LR
C124
0.1uF 10V 10% SMT0402 X5R LR
1.8VDDS
R145 0Ω 5% 1/16W SMT0402 LR
3VDDM
R112
RES 5.6Ω 5% 1/10W SMT0603 LR
C544
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C115
0.1uF 10V 10% SMT0402 X5R LR
10mils
C128
0.1uF 10V 10% SMT0402 X5R LR
C125
0.01uF 16V 10% SMT0402 X7R LR
1.05VDDM_PEGPLL
1.05VDDM_PEGPLL
C142
0.1uF 10V 10% SMT0402 X5R LR
V02 ->V03
0.1uF 10V 10% SMT0402 X5R LR
0.1uF 10V 10% SMT0402 X5R LR
C113
C110
C112
0.01uF 16V 10% SMT0402 X7R LR
C109
0.01uF 16V 10% SMT0402 X7R LR
1.05VDDM_DPLLA
1.05VDDM_DPLLB
1.05VDDM_HPLL
1.05VDDM_MPLL
1.8VDDS_TXLVDS
C120
1.5VDDM
1000pF 50V 10% SMT0402 X7R LR
C158
0.1uF 10V 10% SMT0402 X5R LR
1.05VDDM_PEGPLL
C207
C209
1uF 10V +80-20% SMT0603 Y5V LMK107F105ZA-T TAIYO LR
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
C153
C172
0.1uF 10V 10% SMT0402 X5R LR
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C119
0.01uF 16V 10% SMT0402 X7R LR
VIA=200mA / 10mils
VIA=250mA / 10mils
C130
0.01uF 16V 10% SMT0402 X7R LR
VIA=100mA / 10mils
1.05VDDM
C154
C137
0.1uF 10V 10% SMT0402 X5R LR
0.1uF 10V 10% SMT0402 X5R LR
C123
1uF 6.3V 10% SMT0402 X5R LR
VIA=5mA / 10mils
VIA=100mA / 10mils
500mA
40mA
R123
0Ω 5% 1/16W SMT0402 LR
100mA
150mA
U25H
10mA
80mA
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
5mA
A25
VCCA_DAC_BG
B25
80mA
80mA
50mA
150mA
10mA
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS_1
L37
VCCD_LVDS_2
CRTPLLA PEGA SM
A LVDS
POWER
A CK
TV
HDA
D TV/CRT
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
DMI
LVDS
ASIC NB Cantiga GM45 EB88CTGM(892466) QR32 ES2 FCBGA 1329PIN VER:B0 INTEL LR
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
VTTLF
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
VTT_LF1
VTT_LF2
VTT_LF3
VIA=850mA / 40mils
C149
MO-CAP 0.47uF 6.3V 10% SMT0402 X5R LR
C118
1uF 10V +80-20% SMT0603 Y5V LMK107F105ZA-T TAIYO LR
C170
C541
2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
R113
0Ω 5% 1/10W SMT0603 LR
C116
10uF 6.3V 80-20% SMT0805 Y5V H=1.25mm LR(NU)
RES 1Ω 1% 1/16W SMT 0402 LR
C193
0.1uF 10V 10% SMT0402 X5R LR
1.8VDDS_TXLVDS
C121
0.1uF 10V 10% SMT0402 X5R LR
3VDDM_HV
VIA=100mA / 10mils
1.05VDDM_PEG
R167
0Ω 5% 1/10W SMT0603 LR
1.05VDDM_DMI
100MHz 300Ω 25% SMT0603 HCB1608 KF-301T20 TAI-TECH LR(NU)
C500
C510
MO-CAP 0.47uF 6.3V 10% SMT0402 X5R LR
MO-CAP 0.47uF 6.3V 10% SMT0402 X5R LR
1.05VDDM_PEG
C512
22uF 6.3V ±20% SMT0805 X5R C2012X5R0J226MT TDK LR
C150
0.1uF 10V 10% SMT0402 X5R LR
C114
MO-CAP 0.47uF 6.3V 10% SMT0402 X5R LR
1.05VDDM
C547
+
T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR
C499
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
VIA=350mA / 20mils
L19
INDUCTOR 1μH ± 20% GLF2012T1R0MT TDK LR
R186
R126 0Ω 5% 1/10W SMT0603 LR
C122
10uF 6.3V 80-20% SMT0805 Y5V H=1.25mm LR
C507
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
L17
1.05VDDM
C213
10uF 6.3V 80-20% SMT0805 Y5V H=1.25mm LR
R163 0Ω 5% 1/10W SMT0603 LR
12
v0.3 update
C522
+
T220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR T520B227M2R5ATE035 KEMET LR
R168
0Ω 5% 1/10W SMT0603 LR(NU)
VIA=200mA / 20mils
1.8VDDS
1.8VDDS
VIA=1200mA / 60mils
1.05VDDM
1.05VDDM
3VDDM
20mils
RES 10Ω 1% 1/16W SMT0402 LR
R117
DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR
R118 0Ω 5% 1/10W SMT0603 LR
A A
10
9
8
DN1
N P
VIA=100mA / 10mils
C111
0.1uF 10V 10% SMT0402 X5R LR
7
VIA=100mA / 10mils
1.05VDDM
3VDDM_HV
1.5VDDM9,14,20,21,23,33,40,47
1.05VDDM8,9,11,12,14,17,21,23,47
1.05VDDM_PEG12
1.8VDDS12,14,18,19,48
3VDDM8,10,12,17,18,19,20,21,22,23,24,25,26,27,28,30,33,34,36,37,40,41,43,46,49
6
5
4
3
1.5VDDM
1.05VDDM
1.05VDDM_PEG
1.8VDDS
3VDDM
First International Computer, Inc.
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
Custom
Date: Sheet of
(886-2)8751-8751
MY050
Crestline Power (5/6)
2
Confidential
15 50Monday, May 05, 2008
1
0.3
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