first international computer CW001 Schematics

First International Computer,Inc

D D

Advance Platform Group HW Department

Board name : Mother Board Schematic Project : CW001 ( Diamondville+945GSE+ICH7M )

C C

Version : 0.1

Initial Date :

1. Schematic Page Description :

2. PCI & IRQ & DMA Description :

3. Block Diagram :

4. Net name Description :

5. Board Stack up Description :

6. Schematic modify Item and History :

7. power on & off & S3 Sequence :

8. Layout Guideline :

9. switch setting

B B

Manager Sign by: Drawing by :

Justin Ai

Total confirm by:

A A

LAN Circuit check by:

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

Audio Circuit check by:

Title

Size Document Number Rev

Date: Sheet

CW001

Title

(886-2)8751-8751

0.1

147Monday, August 04, 2008

1. Schematic Page Description :

CW001 Schematic Ver : 0.1

D D

Page 01 Title Page 02 Schematic Page Description Page 03 Block Diagram Page 04 Annotations Page 05 Schematic Modify Page 06 Timing Diagram Page 07 DDR2 Layout Guide Page 08 Diamondville (1/2) Page 09 Diamondville (2/2) Page 10 CPU Thermal Page 11 945GMS Host(1/5)

C C

Page 12 945GMS DMI/Graph(2/5) Page 13 945GMS DDR2(3/5) Page 14 945GMS Power(4/5) Page 15 945GMS Power(5/5) Page 16 Clock Generator Page 17 DDR2 SDRAM SO-DIMM0 Page 18 ICH7m PCI/PCIE/DMI(1/4) Page 19 ICH7m CPU/IDE/SATA(2/4)

Page 21 ICH7m Power/GND(4/4) Page 22 CRT Port Page 23 LCD Conn Page 24 HDD / DOM / KB Page 25 Power Good Page 26 Bios / Screw Page 27 New Card Page 28 Mini Card Page 29 LAN RTL8102E (NEW)* Page 30 Transformer Page 31 Card Reader(RTS5158) Page 32 Audio Codec(ALC269) Page 33 HP / INT MIC / EXT MIC Page 34 EXT USB / GPS / WEB-CAM Page 35 BT / Touch Screen Cnn Page 36 LED / LID / GP / SW Page 37 Touch Panel Page 38 EC_PMX Page 39 Blank

POWER CIRCUIT

Page 40 Power Block Page 41 CPU Core Power Page 42 ACIN / Battery CNN Page 43 Charger Circuit Page 44 5V / 5VDDM, 3VDDA / M Page 45 5V/1.8V/ 0.9V/1.05V

Page 20 ICH7m GPIO(3/4)

2. PCI & IRQ & DMA Description :

B B

IDSEL

CHIP

AD19

LAN

AD23

CHIPPCIINT

IRQA

LAN IRQB IRQC IRQD

BUSMASTER

REQ

A A

REQ0 / GNT0 REQ1 / GNT1 REQ2 / GNT2 REQ3 / GNT3 REQ4 / GNT4

CHIP LAN

IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15

System timer Keyboard (Cascade) LAN / MODEM Serial Port AUDIO / VGA / USB FLOPPY DISK LPT RTC ACPI

(Disable by default)

FIR Cardbus PS/2 mouse FPU HDD CDROM

(MODEM/LAN)

DMA Channel DMA0 FIR DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7

DeviceIRQ Channel Desciption

ECP FLOPPY DISK AUDIO (Cascade) Unused Unused Unused

(disable by default)

(MODEM / LAN)

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu

5FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2) 8751-8751

(886-2) 8751-8751

Title

Size Document Number Rev

Date: Sheet

(886-2) 8751-8751

CW001

Page Description

247Monday, August 04, 2008

0.1

CLK GEN

3. Block Diagram :

D D

CPU

Thermal Sensor

(G780P81U)

Processor

Intel Diamondvile

P10 P43

N270 1.6GHZ

22mm X 22mm

VRM

MAX8796

one phase Vcore

ICS9LPRS501PKLFT

Reset Circuit

Leakage Protect

Brightness Control

RTC Bat

P16

Fan CNN

P25

Lid Switch

Switch Board/LED/DIP SW

MAIN SW CNN

P39

P19

P10

P36

P35

FSB Bus 533MHZ

LCD PANEL

DCIN+

Battery Voltage Sense

C C

Battery Charger

Battery CON

P42

P39

P42

P41

USB Port 2

Web Cam

BISON

1.3M Pixle

B B

ACIN / DCIN

PMU3V/5V 3VDDA/5VDDA 5VDDS 3VDDM/5VDDM

A A

DDRII Power

1.5VDDM/1.05VDDM OVP

P44

P45

P44

P45

P44

P39

CPT CLAA102NA0ACW(10.2") 1024*600

CRT PORT

UXGA

(1600X1200)

CardReader 4 in1 RTS5158E 48 pin

USB Port 3

USB Port 7

Bluetooth

P34 P34P35

Billionton GUBTCR42M

HDD(2.5")

SPI FLASH

P24

P26

EC Fujitsu MB90F372 144P

Int. KB

LVDS interface

P23

VGA Interface

P22

P31

USB 2.0 interface

Port 1

USB

Port 4

SPI interface

LPC Interface

TPM

P39

Glide Pad

SLB9635TT 28P

P36P24

SATA BUS

North Bridge

Intel

945GSE

FCBGA

27 mm x 27 mm

1Gb/s

South Bridge

Intel

ICH7M

31 mm x 31 mm

P38

Speak Out-2 chanel

(internal)

Mem_A Bus

P11

DMI X2 BandWidth Max:

1Gb/s

USB Port 0

PCI-E interface

HDA

P18

Headphone

DDRII SLOT

533MHZ(Max.1GB)

2Gb/s

MINI CARD x1

3.5G HSDPA

7.2Mbit/s

Realtek Codec

ALC 269 Q-GR 48-pin

P37 P27 P29

P32

Mic In 1

(External)(External)

P17

NEW CARD Express card

USB Port 5 PCIE Port 2PCIE Port 4

Mic In 2

mono(internal)

P33P33 P33P33

RJ-45

Lan10/100M RTL8102E (OPTION 1G RTL8111C)

PCIE Port 1

PCIE Port 3 USB Port 6

Wireless LAN

MINI CARD x1

802.11 b/g

Title

Size Document Number Rev

Date: Sheet

P28

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW001

Block Diagram

0.1

347Monday, August 04, 2008

4. Nat name Description :

Voltage Rails

DCIN

D D

PMU5V PMU3V 5VDDA 3VDDA 3VDDS 5VDDS 3VDDM 5VDDM

VCC_CORE

1.05VDDM

1.5VDDM

1.8VDDS

0.9VDDT_DDRII

Part Naming Conventions

Capacitor

C C

Connector

Diode

Fuse

Inductor Transistor

Resistor Resistor Pack

Arbitrary Logic Device

U Y

Crystal and Osc

Net Name Suffix

Active Low signal

5. Board Stack up Description

PCB Layers

B B

Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6

Single End Impedance

55 ohm +/- 15%

Host Clock

55 ohm +/- 15%

SRC Clock

55 ohm +/- 15%

Host Bus DDR2 CLK

42 ohm +/- 15% 55 ohm +/- 15%

DDR2 Strobe DDR2 Bus

55 ohm +/- 15% 55 ohm +/- 15%

DMI Bus

55 ohm +/- 15%

PCIE Bus

A A

SATA

55 ohm +/- 15%

SDVO LVDS USB IEEE1394

50 ohm +/- 15%

Lan

Primary DC system power supply

5.0V always on power rail by LATCH or ACIN

3.3V always on power rail by LATCH or ACIN

5.0V always on power rail by DCON

3.3V always on power rail by DCON

3.3V power rail by PSUSC#

5.0V power rail by PSUSC#

3.3V switched power rail by SUSTAT_B#

5.0V switched power rail by SUSTAT_B# Core Voltage for CPU

1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#

1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE for ICH7m by SUSTAT_B#

1.8V power rail for DDRII by PSUSC#

0.9V DDRII Termination Voltage by SUSTAT_B#

Component Side, Microstrip signal Layer Power Plane Stripline Layer(AGTL,CLOCK,DDR) Stripline Layer(Analog,LVDS,other) Ground Plane Solder Side,Microstrip signal Layer

Differential Impedance for Microstrip

95 ohm +/- 15% 95 ohm +/- 15%

70 ohm +/- 20%

95 ohm +/- 15% 95 ohm +/- 15% 95 ohm +/- 15% 95 ohm +/- 15% 100 ohm +/- 15% 90 ohm +/- 15% 110 ohm +/- 15%

Differential Impedance for Stripline

100 ohm +/- 15% 100 ohm +/- 15%

70 ohm +/- 20% 85 ohm +/- 20%

100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 100 ohm +/- 15% 90 ohm +/- 15% 110 ohm +/- 15%

Power Rail

VCORE_CPU

1.05VDDM

1.5VDDM

1.8VDDS:

DDR_0.9VDDM:

2.5VDDM

3VDDM

3VDDA

PMU3V

5VDDM

5VDDS 5VDDA USB: X 2 Ports

PMU5V 5VDDM

Destination

Diamondville HFM:

Diamondville: Core Diamondville: AGTL+termination 945GSE: Core 945GSE: AGTL+termination ICH7M: Core ICH7M: V_CPU_IO CLK Generator: VDDIO Diamondville: PLL 945GSE: VccAUX(DDR DLLS,DDRII,FSB HSIO) 945GSE: PCIe 945GSE: LVDS(Digital) 945GSE: Various PLLS analog supply ICH7M: Vcc_A 640mA ICH7M: Vcc_B ICH7M: PLL(DMI,USB,SATA) Express Card: 945GSE: DDR 2 I/O SO-DIMM: DDRII Terminator: 945GSE: PCIe(Analog) 945GSE: LVDS(Analog) 945GSE: LVDS(I/O) 945GSE: CRT DAC/CRT Sync 945GSE: HV COMS ICH7M: VCC3_3(PCI/IDE) ICH7M: VccLAN3_3 ICH7M: VccHDA CLK Gen: VDD(PCI,48,PLL3,REF,SRC,CPU) DDR II Socket: EEPROM Power Supply Express Card: Card Reader: SD/MMC/MS/CF AUDIO: Digital Core Power BULE TOOTH: PWM: MAX8796(V3p3) ICH7M: VccSus3_3(USB) ICH7M: VccSus_HDA LCD CONN: LCD Power SPI Power: Express Card: PCIe Mini Card: Wireless Lan Power LAN: RTL8102E-GR(VDD33/AVDD33) Web Cam: CAM_3VDDA PCIe Mini Card: 3.5G Power ICH7M: RTC Power EC_PMX: MB90F372 Power Battery: BAT+ 3VDDM 3VDDA Thermal Sensor: CPU FAN Power: LCD CNN: LED Power HDD: SATA AUDIO: Analog AUDIO: Analog BTL PWM: MAX8796 GP:AVC_TPA2U2PA99

2.5VDDM Quad Output Controller: MAX17017

5VDDS

5VDDA 15V_Load Switch

LFM:

Voltage

0.80V~1.10V

0.75V~0.85V

1.2V(Boot)

1.00V~1.05V~1.10V

0.9975V~1.05V~1.1025V

0.998V~1.05V~1.102V

0.945V~1.05V~1.25V

0.995V~1.05V~3.465V

1.425V~1.5V~1.575V

1.35V~1.5V~1.65V

1.7V~1.8V~1.9V

0.855V~0.9V~0.945V

2.32V~2.5V~2.625V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

3.3V~5.0V

3.0V~3.3V~3.6V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

2.0V~3.0V~3.6V

3.0V~3.3V~3.6V

3.0V~5.0V~5.5V

2.5V~5.0V~5.5V

4.5V~5.0V~5.5V

3.3V~5.0V~5.25

4.5V~5.0V~5.5V

5.0V 1.0A

S0 Current

3.0A

1.5A 2940mA 780mA 940mA 14mA 80mA 130mA 1250mA 400mA 20mA 340mA

770mA 110mA

1720mA

2.0A 2mA 10mA 60mA 70mA 40mA 270mA 40mA 56mA 250mA

50mA 60mA

45mA 10mA 250mA 20mA

660mA 201mA 130mA 1000mA

30mA

766mA 2316mA 320uA

0.3A 500mA 700mA5.0V 48mA 600mA

5.2mA 142mA

2295.52mA

1.0A

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW001

Annotations

(886-2)8751-8751

Title

Size Document Number Rev

Date: Sheet

3.0A

6.974A

3.66A

1.72A

2.0A

0.142A

0.766A

2.316A

3.112A

2.29552A

1.0A

3.29552A

447Monday, August 04, 2008

0.1

6.Schematic modify Item and History :

POWER STATE (ADAPTER)

State

Power

D D

DCIN+ ADPOUT1 PMU5V

PMU3V

DCIN

5VDDA

3VDDA

C C

5VDDS

5VDDM

3VDDM

1.05VDDM

1.5VDDM

DDR_1.8VDDS

DDR_0.9VDDM

B B

V V V

Description

Adapter power supply

Always on by ADPOUT1

Always power on by DCIN_ON

Always power on by DCON

Power on by S4

Power on by S3

Power on by S4

Power on by S3

(Peripheral Circuit)

1025 R479 change from 150ohm(NU) to 75ohm(NU)

POWER STATE (BATTERY)

State

Power

DCIN+ ADPOUT1 PMU5V

PMU3V

DCIN

5VDDA

3VDDA

5VDDS

5VDDM

3VDDM

1.05VDDM

1.5VDDM

DDR_1.8VDDS

DDR_0.9VDDM

Description

Power on by Power Switch Power on by Power Switch Power on by Power Switch Power on by Power Switch

Always power on by DCIN_ON

Always power on by DCON

Power on by S4

Power on by S3

Power on by S4

Power on by S3

(Peripheral Circuit)

LED INDICATOR

STATUS

BUTTON FUNCTION

BUTTON

POWER

INTERNET

A A

MAIL

CAMERA

SW3

SW1

SW4

SW2

NOTELOCATION POWER ON/OFF SWITCH

DIRECTLY INTERNET ACCESS

DIRECTLY E-MAIL ACCESS

CAMERA ON/OFF SWITCH

INDICATOR

POWER

BATTERY

WIRELESS

HDD/DOM/ODD

Caps Lock

LOCATION

D16

D60

D19

D20

D21

NOTE

Battery status indicator:

Charge state: green

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW060

Schematic Modify

(886-2)8751-8751

0.1

547Monday, August 04, 2008

Title

Size Document Number Rev

Date: Sheet

7. power on & off & S3 Sequence :

S3 SUSPEND AND RESUME TIMING

IMVP6 Power On Sequencing Timing Diagram

D D

VID VR_ON Vcc-core CPU_UP Vccp Vccp_UP Vccgmch GMCHPWRGD CLK_ENABLE# IMVP4_PWRGD

C C

BATTERY ONLY POWER ON TIMING

POWSW0

PMU5V/PMU3V

DCON

VDDA

MAINSW0_ICH

PM_RSTRST0

PM_SLP_S30/S40/S50

PSUSC0

B B

A A

SUSTAT_B0

VDDM,VDDS

PM_PWROK

SYS_PWROK

VRON_VCCP

VCCP/1.2VDDM

VCORE_ON

VR_ON

VCORE_CPU

CK408_PWRGD0

PM_VGATE

CPU_PWRGD

PCI_RST0

AGTL+_CPURST0

Tsft_star_vcc(3ms max)

Tboot

Tcpu_up

Tvccp_up

Vid

Vboot Tboot-vid-tr(100uS max)

Tgmch_pwrgd

Tcpu_pwrgd(3~20mS)

Tboot:10-100uS

To ICH4

From ICH4

From ASIC_B0 From ASIC_B0

To clock generator To ODEM and ICH4

From ICH4 to CPU

To ODEM/other PCI device

From ODEM to CPU

POWSW0

PMU5V/PMU3V

DCON

VDDA PM_RSMRST0 PM_SLP_S30

PM_SLP_S40/S50

PSUSC0

SUSTAT_B0

VDDS

VDDM

PM_PWROK SYS_PWROK

VRON_VCCP

VCCP,1.2VDDM

VCORE_ON

VR_ON

VCORE_CPU

CK408_PWRGD0 PM_VGATE

CPU_PWRGOOD

PCI_RST0

AGTL+_CPURST0

H H H H

H H

To ICH4_M From ICH4_M

From ICH4_M From ASIC_B0 From ASIC_B0

1.5VDDS AND DDR_PWRGD

To clock

Generator

ToICH4 and ODEM

From ICH4 to CPU

To ODEM/other PCI device

From ODEM to CPU

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW001

Timing Diagram

(886-2)8751-8751

0.1

647Monday, August 04, 2008

Title

Size Document Number Rev

Date: Sheet

8. Layout Guideline :

Calistoga (945GSE) DDRII Layout Guidelines

DDRII Signal Groups

Group

D D

Signal Name

Data

SA_DQ[63..0]/SB_DQ[63..0] SA_DM[7..0]/SB_DM[7..0] SA_DQS[7..0]/SA_DQS#[7..0] SB_DQS[7..0]/SB_DQS#[7..0]

Address

SA_BS[2..0]/SB_BS[2..0] SA_RAS#/SB_RAS# SA_CAS#/SB_CAS# SA_WE#/SB_WE#

SM_CS#[3..0]

Control

SM_CKE[3..0] SM_ODT[3..0]

Clock

SM_CK[3..0] SM_CK#[3..0]

SA_RCVENOUT#/SB_RCVENOUT#

FeedBack

SA_RCVENIN#/SB_RCVENIN#

CLK group : SM_CK[3..0],SM_CK#[3..0]

4/4/12

Breakout SL

7/4/16

L1 L1

GMCH

C C

B B

Feedback group : SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#

A A

These signals are routed internally on the GMCH package and don't require any routing on the MB. As a result, can be left as NC.

Escape

L0 S1

MS Topology Reference Plane Single Ended Trace Impedance 42 +/- 15% Differential Mode Impedance Nominal Trace Width

Nominal CK to CK# Spacing (edge to edge) Minimum Serpentine Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2 Package Length Range - P1 Trace Length Limit - L0 Trace Length Limit - L1 Stub Length S1-Stub from via to SO-DIMM MB Length Limits - L0 + L1 + L2 + S1

Total Length - P1 + L0 + L1 + L2 + S1

Maximim Via Count SCK to SCK# Length Matching Clock to Clock Length Match

(Total Length) Breakout Exceptions (Reduce geometries for GMCH break-out region)

Breakin Exceptions (Reduce geometries for SO-DIMM break-in region)

Length Matching and Length Formulas

Signal Group

Control-to-Clock Command-to-Clock Strobe-to-Clock Data-to-Strobe

SO-DIMM

8/5/15

L2 L2

MS Differential Pair Point-to-Point Ground

70 +/- 20% Inner Layer : 7 mils

Outer Layer : 8 mils Inner Layer : 4 mils

Outer Layer : 5 mils Inner Layer : 12 mils

Outer Layer : 15 mils Inner Layer : 16 mils

Outer Layer : 20 mils 25 mils 750 mils +/- 250 mils Max = 50 mils (Escape) Max = 500 mils (Breakout) Max = 200 mils (Breakin) Min = 500 mils

Max = 3250 mils Max = 4000 mils Total Length for Channel A : X0

Total Length for Channel B : X1 2 (Per side) Match total length to within 5 mils Match Channel A clocks to X0 +/- 20mils

Match Channel B clocks to X1 +/- 20mils Inner Layer : 4/12 mils to other DDR2

Outer Layer : 5/15 mils to other DDR2 Max. breakout length is 500 mils CK to CK# spacing rule waived at

connector spacing of 15 mils to other DDR2

Max. breakin length is 200 mils

Minimum Length

Clock - 1.0" Clock - 1.0" Clock - 0.5" Strobe - 210mils

Maximum Length

Clock - 0.0" Clock + 1.0" Clock + 0.5" Strobe - 190mils

Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]

GMCH

5/5 Escape

Topology Reference Plane Characteristic Trace Impedance Nominal Trace Width

Minimum CTRL Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2 Package Length P1

Trace Length Limit - L1 Stub Length S1-Stub from via to SO-DIMM MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Trace Length L3+L4

Parallel Termination Resistor Maximim Via Count CTRL to SCK/SCK# Length Matching

(Total Length including package) Breakout Exceptions (Reduce geometries for GMCH break-out region)

trace length limit -L3

4/8,6/8

4/4

5/10,8/10

Breakout

SL/MS

5/10

Point-to-Point with parallel termination Ground or VDD 55 +/- 15% Inner Layer : 4 milsSA_MA[13..0]/SB_MA[13..0]

Outer Layer : 5 mils Inner Layer : 8 mils

Outer Layer : 10 mils Inner Layer : 12 mils

Outer Layer : 15 mils 25 mils 500 mils +/- 250 mils Max = 50 mils (Escape) Max = 500 mils (Breakout) Max = 200 mils (Breakin) Min = 500 mils

Max = 3500 mils Max = 4000 mils

Max = 1500 mils 56 +/- 5% 3 (CLK-1.0") </= CTRL </= (CLK-0.0")

Inner Layer : 4 mils spacing allowed Outer Layer : 5 mils spacing allowed Max. breakout length is 500 milsBreakin

Max = 1300 mils

4/8

SL/MS MS

SO-DIMM

L2 segment:45 +/- 15%

5/10

Vtt

L2 segment:Inner Layer : 6 mils L2 segment:outer Layer : 8 mils

L2 segment:Inner Layer : 12 mils L2 segment:outer Layer : 16 mils

Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#

SO-DIMM

5/5/10

4/4/12

GMCH

P1 P1

Topology Reference Plane Single Ended Trace Impedance Differential Mode Impedance Nominal Trace Width

Nominal DQS to DQS# Spacing (edge to edge) Minimum DQS to DQ Spacing

Minimum Serpentine Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2

Trace Length Limit - L0 Trace Length Limit - L1 Stub Length S1-Stub from via to SO-DIMM MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Maximim Via Count

DQS to DQS# Length Matching DQS to SCK/SCK# Length Match

(Total Length include package) Breakout Exceptions (Reduce geometries

for GMCH break-out region)

Breakin Exceptions (Reduce geometries for SO-DIMM break-in region)

Escape

L0 L0

4/4/8

L1 L1

Breakout SL

L2 L2

S1 S1

Breakin

MS Differential Pair Point-to-Point Ground 55 +/- 15% 85 +/- 20% Inner Layer : 4 mils

Outer Layer : 5 mils Inner Layer : 4 mils

Outer Layer : 5 mils Inner Layer : 12 mils

Outer Layer : 10 mils Inner Layer : 8 mils

Outer Layer : 10 mils Inner Layer : 12 mils

Outer Layer : 15 mils 25 mils 600 mils +/- 300 mils Max = 50 mils (Escape) Max = 500 mils (Breakout) Max = 250 mils (Breakin) Min = 500 mils

Max = 4000 mils Max = 4500 mils

2 (Per side) Match total length to within 5 mils (CLK-0.5") </= DQS </= (CLK+0.5")

Inner Layer : 4mil trace and 4 mils pair spacing allowed Outer Layer :5 mil trace and 5 mils pair spacing allowed

Minimum DQS to DQ Spacing:8 mils Max. breakout length is 500 mils

DQS to DQS# spacing rule waived at connector spacing of 10 mils to other DDR2

Max. breakin length is 200 mils

Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]

GMCH

Escape

4/4

Breakout SL

5/5

4/6

SO-DIMM

Topology Reference Plane Characteristic Trace Impedance Nominal Trace Width

Minimum DQ Bus Trace Spacing

Minimum Serpentine Spacing Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2 Package Length P1Trace Length Limit - L0 Trace Length Limit - L0 Trace Length Limit - L1 Stub Length S1-Stub from via to SO-DIMM MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Maximim Via Count

DQ/DM to DQS Length Matching (Total Length including package)

Breakout Exceptions (Reduce geometries for GMCH break-out region)

Command group : SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#, SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#

GMCH

Topology Reference Plane Characteristic Trace Impedance Nominal Trace Width

Minimum CMD Bus Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2 Package Length P1 Trace Length Limit - L0 Trace Length Limit - L1 Stub Length S1-Stub from via to SO-DIMM MB Length Limits - L0 + L1 + L2 + S1

- From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1

Trace Length L3+L4 Parallel Termination Resistor Maximim Via Count CTRL to SCK/SCK# Length Matching

(Total Length including package) Breakout Exceptions (Reduce geometries for GMCH break-out region)

trace length limit -L3

Point-to-Point Ground 55 +/- 15% Inner Layer : 4 mils

Outer Layer : 5 mils Inner Layer : 8 mils

Outer Layer : 10 mils Same as DQ-to-DQ routing Inner Layer : 12 mils

Outer Layer : 15 mils 25 mils 600 mils +/- 300 mils Max = 50 mils (Escape) Max = 500 mils (Breakout) Max = 250 mils (Breakin) Min = 500 mils

Max = 4000 mils Max = 4500 mils

Match DQ/DM to [SDQS - 200mils] +/- 10mils, per byte lane

Inner Layer :4 mils trace and 4 mils spacing allowed Outer Layer :5 mils trace and 5 mils spacing allowed

Max. breakout length is 500 mils

Escape

5/5

4/6,5/10

4/4

L1 L2

Breakout

SL/MS

5/10

Title

CW001

Size Document Number Rev

DDRII Layout Guideline

Date: Sheet

5/10

4/6

SL/MS

SO-DIMM

Point-to-Point with parallel termination Ground 55 +/- 15% Inner Layer : 4 mils

Outer Layer : 5 mils Inner Layer : 6 mils

Outer Layer : 10 mils Inner Layer : 12 mils

Outer Layer : 15 mils 25 mils 500 mils +/- 300 mils Max = 50 mils (Escape) Max = 500 mils (Breakout)Package Length Range - P1 Max = 200 mils (Breakin) Min = 500 mils

Max = 4500 mils Max = 5000 mils

Max = 1300 mils 56 +/- 5% 3 (CLK-1.0") </= CMD </= (CLK+1.0")

Inner Layer : 4 mils spacing allowed Outer Layer : 5 mils spacing allowed Max. breakout length is 500 mils

Max = 1300 mils

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

Vtt

0.1

747Monday, August 04, 2008

H_A#[31..3]

D D

1.05VDDM

0521_NU(R12/R13)

C C

B B

Zo=55ohm, 0.5" max for GTLREF, Space any other switch signals away from GTLREF with a minimum of 25mils. Don't allow the GTLREF routing to create splits or discontinuities in the reference planes of the FSB signals

A A

H_A20M#[19]

H_IGNNE#[19]

R39

1KΩ 5% 1/16W SMT0402 LR(NU)

1.05VDDM

R527

R527 1KΩ 1% 1/16W SMT0402 LR

1KΩ 1% 1/16W SMT0402 LR

R525

R525 RES 2KΩ 1% 1/16W SMT 0402 LR

RES 2KΩ 1% 1/16W SMT 0402 LR

R81

R81 1KΩ 5% 1/16W SMT0402 LR(NU)

1KΩ 5% 1/16W SMT0402 LR(NU)

C491

0.1uF 10V ±10% SMT0402 X5R LR

H_ADSTB#0[11]

H_REQ#[4..0][11]

5mils

H_A#[31..3][11]

H_REQ#[4..0]

H_A#[31..3]

H_A#[31..3][11]

H_ADSTB#1[11]

H_FERR#[19]

H_STPCLK#[19]

H_INTR[19]

H_NMI[19]

H_SMI#[19]

H_D#[63..0]

H_D#[63..0][11]

H_DSTBN#0[11] H_DSTBP#0[11]

H_DINV#0[11]

H_D#[63..0]

H_D#[63..0][11]

H_DSTBN#1[11] H_DSTBP#1[11]

H_DINV#1[11]

R513 1KΩ 5% 1/16W SMT0402 LR(NU)R513 1KΩ 5% 1/16W SMT0402 LR(NU) R514 1KΩ 5% 1/16W SMT0402 LR(NU)R514 1KΩ 5% 1/16W SMT0402 LR(NU)

CPU_BSEL0[16] CPU_BSEL1[16] CPU_BSEL2[16]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_GTLREF

EXTBGREF

H_A20M# H_FERR#

H_STPCLK# H_INTR H_NMI H_SMI#

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

ACLKPH DCLKPH

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

U33A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14

A[22]#

C18

A[23]#

C20

A[24]#

E20

A[25]#

D20

A[26]#

B18

A[27]#

C15

A[28]#

B16

A[29]#

B17

A[30]#

C16

A[31]#

A17

A[32]#

B14

A[33]#

B15

A[34]#

A14

A[35]#

B19

ADSTB[1]#

M18

AP1

U18

A20M#

T16

FERR#

IGNNE#

R16

STPCLK#

T15

LINT0

R15

LINT1

U17

SMI#

NC1

NC2

NC3

NC4

NC5

M15

NC6

L16

NC7

Diamondville_SC_Rev1

U33B

Y11

D[0]#

W10

D[1]#

Y12

D[2]#

AA14

D[3]#

AA11

D[4]#

W12

D[5]#

AA16

D[6]#

Y10

D[7]#

D[8]#

Y13

D[9]#

W15

D[10]#

AA13

D[11]#

Y16

D[12]#

W13

D[13]#

AA9

D[14]#

D[15]#

Y14

DSTBN[0]#

Y15

DSTBP[0]#

W16

DINV[0]#

DP#0

AA5

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

D[21]#

D[22]#

AA6

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

AA8

D[29]#

D[30]#

D[31]#

DSTBN[1]#

DSTBP[1]#

DINV[1]#

DP#1

GTLREF

ACLKPH

DCLKPH

T17

BINIT#

EDM

EXTBGREF

N15

FORCEPR#

HFPLL

P17

MCERR#

RSP#

BSEL[0]

BSEL[1]

BSEL[2]

Diamondville_SC_Rev1

H=2.0(mm)

ADDR

GROUP

ADDR

GROUP

DEFER#

CONTROLXDP/ITP SIGNALS

RESET#

BPM[0]# BPM[1]# BPM[2]#

ADDR GROUP 1

BPM[3]#

PROCHOT#

THRMDA THRMDC

THERMTRIP#

BCLK[0] BCLK[1]

H CLK THERM

DATA GRP 0 DATA GRP 1

DATA GRP 2DATA GRP 3

DSTBN[2]# DSTBP[2]#

DINV[2]#

DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

MISC

DPRSTP#

DPSLP# DPWR#

PWRGOOD

CORE_DET

CMREF[1]

DRDY# DBSY#

LOCK#

RS[0]# RS[1]# RS[2]# TRDY#

PRDY# PREQ#

TRST#

RSVD3 RSVD2 RSVD1

ADS# BNR# BPRI#

IERR#

HITM#

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

H_ADS#

V19 Y19 U21

T21 T19 Y18

T20

BR0#

F16 V16

INIT#

W20

D15 W18 Y17 U20 W19

AA17

HIT#

V20

K17 J18 H15 J15 K18 J16 M17

TCK

N16

TDI

M16

TDO

L17

TMS

K16 V15

BR1#

G17 E4 E5

H17

V11 V12

C21 C1 A3

R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 M4

DP#2

C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 D4

DP#3

T1 T2 F20 F21

R18 R17 U4 V17 N18

SLP#

A13 B7

H_ADS# [11]

H_BNR#

H_BNR# [11]

H_BPRI#

H_BPRI# [11]

H_DEFER#

H_DEFER# [11]

H_DRDY#

H_DRDY# [11]

H_DBSY#

H_DBSY# [11]

H_BREQ#

H_BREQ# [11]

IERR# INIT#

H_LOCK#

H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY#

H_HIT# H_HITM#

XDP_BPM#5 XDP_TCK XDP_TDI

XDP_TMS XDP_TRST#

BR1#

-PROCHOT H_THERMDA H_THERMDC

PM_THRMTRIP#

CLK_CPU_BCLK CLK_CPU_BCLK#

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR#

H_PWRGD H_CPUSLP# PSI#

CPU_CMREF

R26 1KΩ 5% 1/16W SMT0402 LRR26 1KΩ 5% 1/16W SMT0402 LR

H_LOCK# [11]

H_RS#0 [11] H_RS#1 [11] H_RS#2 [11] H_TRDY# [11]

H_HIT# [11] H_HITM# [11]

2008/4/11 ADD SYSRST CONNECT TO ICH7

PM_SYSRST# [20]

R250Ω 5%(NU) R250Ω 5%(NU)

R89 22Ω 1% 1/16W SMT0402 LRR89 22Ω 1% 1/16W SMT0402 LR

H_THERMDA [10] H_THERMDC [10]

PM_THRMTRIP# [12,19]

CLK_CPU_BCLK [16] CLK_CPU_BCLK# [16]

H_D#[63..0]

R517 RES 27.4Ω 1% 1/16W SMT 0402 LRR517 RES 27.4Ω 1% 1/16W SMT 0402 LR R518 54.9Ω 1% 1/16W SMT0402 LR SnR518 54.9Ω 1% 1/16W SMT0402 LR Sn R109 RES 27.4Ω 1% 1/16W SMT 0402 LRR109 RES 27.4Ω 1% 1/16W SMT 0402 LR R100 54.9Ω 1% 1/16W SMT0402 LR SnR100 54.9Ω 1% 1/16W SMT0402 LR Sn

H_DPRSTP# [19,43] H_DPSLP# [19] H_DPWR# [11]

TP5TP5

H_PWRGD rise time : Max : 15ns

1.05VDDM

0521_NU(R10)

H_D#[63..0] [11]

H_DSTBN#2 [11] H_DSTBP#2 [11] H_DINV#2 [11]

H_D#[63..0] [11]

H_DSTBN#3 [11] H_DSTBP#3 [11] H_DINV#3 [11]

TP4TP4

0'' ~ 3''

1.05VDDM

R97

R97 RES 56Ω 5% 1/16W SMT0402 LR

RES 56Ω 5% 1/16W SMT0402 LR

H_CPURST# [11]

1.05VDDM

R90

R90 68Ω 5% 1/16W SMT0402 TIN LR

68Ω 5% 1/16W SMT0402 TIN LR

H_CPUSLP# [11]

TP3TP3

2008/05/13 ADD PSI# TP

R27

R27 330Ω 5% 1/16W SMT0402 LR

330Ω 5% 1/16W SMT0402 LR

H_INIT# [19]

H_PROCHOT# [43]

H_PWRGD [19]

TP2TP2

XDP P/U & P/D

R77 RES 56Ω 5% 1/16W SMT0402 LRR77 RES 56Ω 5% 1/16W SMT0402 LR

XDP_TMS XDP_TDI

R65 RES 56Ω 5% 1/16W SMT0402 LRR65 RES 56Ω 5% 1/16W SMT0402 LR

XDP_BPM#5

R80 RES 56Ω 5% 1/16W SMT0402 LRR80 RES 56Ω 5% 1/16W SMT0402 LR

XDP_TCK

R70 RES 56Ω 5% 1/16W SMT0402 LRR70 RES 56Ω 5% 1/16W SMT0402 LR R74 RES 56Ω 5% 1/16W SMT0402 LRR74 RES 56Ω 5% 1/16W SMT0402 LR

XDP_TRST#

RP41

H_A#35

1 8

H_A#33H_IGNNE#

2 7

H_A#32

3 6

H_A#34

4 5

1KΩ 5% SMT2010 1/16W 8P4R LR

2008/4/11

H_NMI

H_SMI#

H_INTR

H_STPCLK#

H_DPSLP#

H_DPRSTP#

H_PWRGD

H_DPWR#

R63

R63 1KΩ 1% 1/16W SMT0402 LR

1KΩ 1% 1/16W SMT0402 LR

R62

R62 RES 2KΩ 1% 1/16W SMT 0402 LR

RES 2KΩ 1% 1/16W SMT 0402 LR

1.05VDDM[9,11,13,14,16,19,21,45]

Replace 51 ohm to 1k ohm

R47 1KΩ 5% 1/16W SMT0402 LR(NU)R47 1KΩ 5% 1/16W SMT0402 LR(NU)

R35 1KΩ 5% 1/16W SMT0402 LR(NU)R35 1KΩ 5% 1/16W SMT0402 LR(NU)

R31 1KΩ 5% 1/16W SMT0402 LR(NU)R31 1KΩ 5% 1/16W SMT0402 LR(NU)

R58 1KΩ 5% 1/16W SMT0402 LR(NU)R58 1KΩ 5% 1/16W SMT0402 LR(NU)

R61 1KΩ 5% 1/16W SMT0402 LR(NU)R61 1KΩ 5% 1/16W SMT0402 LR(NU)

R51 1KΩ 5% 1/16W SMT0402 LR(NU)R51 1KΩ 5% 1/16W SMT0402 LR(NU)

R33 1KΩ 5% 1/16W SMT0402 LR(NU)R33 1KΩ 5% 1/16W SMT0402 LR(NU)

R516 1KΩ 5% 1/16W SMT0402 LR(NU)R516 1KΩ 5% 1/16W SMT0402 LR(NU)

R515 1KΩ 5% 1/16W SMT0402 LR(NU)R515 1KΩ 5% 1/16W SMT0402 LR(NU)

Layout note:Zo=55 ohm,

0.5'' max for EXTGBTEF

5mils 5mils

EXTBGREF

C80

MO-CAP 1uF 6.3V 10% SMT0402 X5R JMK105BJ105KV-T TAIYO LR

2008/4/11 Replace 0.1uf to 1uf

1.05VDDM

Layout note:Zo=55 ohm,

1.05VDDM1.05VDDM

0.5'' max for EXTGBTEF

R528

1KΩ 1% 1/16W SMT0402 LR

CPU_CMREF

R526

R526 RES 2KΩ 1% 1/16W SMT 0402 LR

RES 2KΩ 1% 1/16W SMT 0402 LR

C492

0.1uF 10V ±10% SMT0402 X5R LR

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu

5FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2) 8751-8751

(886-2) 8751-8751

CW001

Diamondville (1/2)

(886-2) 8751-8751

847Monday, August 04, 2008

Title

Size Document Number Rev

Date: Sheet

0.1

MN1

HEATSINK

GND1

GND2

4 4

FCBGA_437P_HSK

U33D

VSS1

VSS2

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

VSS9

VSS10

VSS11

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

VSS16

C17

VSS17

VSS18

VSS19

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

VSS24

VSS25

VSS26

VSS27

E15

3 3

2 2

VSS28

E16

VSS29

E19

VSS30

VSS31

VSS32

VSS33

VSS34

F17

VSS35

F18

VSS36

VSS37

VSS38

VSS39

VSS41

G13

VSS42

G21

VSS45

VSS46

VSS48

VSS49

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

VSS56

VSS57

VSS58

J13

VSS59

J17

VSS60

VSS61

VSS62

VSS63

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

VSS78

VSS79

VSS80

VSS81

M13

VSS82

M21

VSS83

VSS84

Diamondville_SC_Rev1

VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100

VSS99 VSS98 VSS97 VSS96 VSS95

N5 N7 N9 N13 N17 P3 P4 P5 P6 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 V18 V21 W1 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20

VCORE_CPU

ICC=3000mA

Place these inside socket cavity on L8 (South side secondary)

C120 1uF 6.3V 10% SMT0402 X5R LRC120 1uF 6.3V 10% SMT0402 X5R LR

C144 1uF 6.3V 10% SMT0402 X5R LRC144 1uF 6.3V 10% SMT0402 X5R LR

C102 1uF 6.3V 10% SMT0402 X5R LRC102 1uF 6.3V 10% SMT0402 X5R LR

C72 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LRC72 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/C YOCERA LR

C97 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LRC97 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/C YOCERA LR

C87 1uF 6.3V 10% SMT0402 X5R LRC87 1uF 6.3V 10% SMT0402 X5R LR

C123 1uF 6.3V 10% SMT0402 X5R LRC123 1uF 6.3V 10% SMT0402 X5R LR

C498 1uF 6.3V 10% SMT0402 X5R LRC498 1uF 6.3V 10% SMT0402 X5R LR

C138 1uF 6.3V 10% SMT0402 X5R LRC138 1uF 6.3V 10% SMT0402 X5R LR

C107 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC107 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C85 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LRC85 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/C YOCERA LR

C113 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC113 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

Place these inside socket cavity on L8 (North side secondary)

C151 1uF 6.3V 10% SMT0402 X5R LRC151 1uF 6.3V 10% SMT0402 X5R LR

C105 1uF 6.3V 10% SMT0402 X5R LRC105 1uF 6.3V 10% SMT0402 X5R LR

C73 1uF 6.3V 10% SMT0402 X5R LRC73 1uF 6.3V 10% SMT0402 X5R LR

C495 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC495 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C171 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC171 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C172 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC172 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C153 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC153 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C493 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC493 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C152 1uF 6.3V 10% SMT0402 X5R LRC152 1uF 6.3V 10% SMT0402 X5R LR

C497 1uF 6.3V 10% SMT0402 X5R LRC497 1uF 6.3V 10% SMT0402 X5R LR

C170 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC170 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR+C164 P-CAP (SP-CAP) 220uF 2V -35 to +10% 9mΩ SMT 7343 EEFSX0D221EY PANASONIC LR+C164 P-CAP (SP-CAP) 220uF 2V -35 to +10% 9mΩ SMT 7343 EEFSX0D221EY PANASONIC LR

C496 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LRC496 10uF 6.3V ±20% SMT0805 X5R C M21X5R106M06AT AVX/CYOCERA LR

C119 1uF 6.3V 10% SMT0402 X5R LRC119 1uF 6.3V 10% SMT0402 X5R LR

C140 1uF 6.3V 10% SMT0402 X5R LRC140 1uF 6.3V 10% SMT0402 X5R LR

C141 1uF 6.3V 10% SMT0402 X5R LRC141 1uF 6.3V 10% SMT0402 X5R LR

C111 1uF 6.3V 10% SMT0402 X5R LRC111 1uF 6.3V 10% SMT0402 X5R LR

1.05VDDM

U33C

V10

VCCF

VCCQ1

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

Diamondville_SC_Rev1

VCCPC64 VCCPC63 VCCPC62 VCCPC61

VCCSENSE

VSSSENSE

VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32

VCCA

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VTT1

C127 0.1uF 10V ±10% SMT0402 X5R LR (NU)C127 0.1uF 10V ±10% SMT0402 X5R LR (NU)

C118 0.1uF 10V ±10% SMT0402 X5R LR (NU)C118 0.1uF 10V ±10% SMT0402 X5R LR (NU)

C79 0.1uF 10V ±10% SMT0402 X5R LRC79 0.1uF 10V ±10% SMT0402 X5R LR

C61 1uF 6.3V 10% SMT0402 X5R LRC61 1uF 6.3V 10% SMT0402 X5R LR

C108 0.1uF 10V ±10% SMT0402 X5R LRC108 0.1uF 10V ±10% SMT0402 X5R LR

VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9

C150 0.1uF 10V ±10% SMT0402 X5R LR (NU)C150 0.1uF 10V ±10% SMT0402 X5R LR (NU)

E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 L14 M8 M14 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14

F14 F13 E14 E13

H_VID0

F15

H_VID0 [43]

H_VID1

D16

H_VID1 [43]

H_VID2

E18

H_VID2 [43]

H_VID3

G15

H_VID3 [43]

H_VID4

G16

H_VID4 [43]

H_VID5

E17

H_VID5 [43]

H_VID6

G18

H_VID6 [43]

C13

D13

C149

0.1uF 10V ±10% SMT0402 X5R LR(NU)

1.05VDDM

C66 1uF 6.3V 10% SMT0402 X5R LRC66 1uF 6.3V 10% SMT0402 X5R LR

C115 1uF 6.3V 10% SMT0402 X5R LRC115 1uF 6.3V 10% SMT0402 X5R LR

C95 1uF 6.3V 10% SMT0402 X5R LRC95 1uF 6.3V 10% SMT0402 X5R LR

C63

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

1.5VDDM

ICCP=2500mA

C106

C96

C96 T 220uF 2.5V ±20% ESR=15mΩ SMT7343 2R5TPE220MF SANYO LR(NU)

T 220uF 2.5V ±20% ESR=15mΩ SMT7343 2R5TPE220MF SANYO LR(NU)

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

2008/4/14 N/C 220UF (FOLLOW CRB )

ICCA=130mA, 20mils

Place C? Close

C58

C142

10uF 6.3V 20% SMT0603 X5R LR(NU)

0.1uF 10V ±10% SMT0402 X5R LR

Route VCCSENSE and VSSSENSE traces at 27.4 ohms with 50mil spacing. Place PU and PD within 1 inch of CPU

To pin D7

VCCSENSE [43]

VSSSENSE [43]

1 1

VCORE_CPU[43]

1.05VDDM[8,11,13,14,16,19,21,45]

1.5VDDM[12,13,14,18,21,27,28,37,45]

VCORE_CPU

1.05VDDM

1.5VDDM

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu

5FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2) 8751-8751

(886-2) 8751-8751

CW001

Diamondville (2/2)

(886-2) 8751-8751

947Monday, August 04, 2008

Title

Size Document Number Rev

Date: Sheet

0.1

FAN Power Control

R19 10KΩ 5% 1/16W SMT0402 LRR19 10KΩ 5% 1/16W SMT0402 LR

FAN_PWM[39]

5VDDM

30mil

D D

2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

C35

0.22uF 10V 10% 0603 X7R

FAN_VIN

VIN

VEN

C38

VSET

U2 LNR-IC FAN DRIVER 1.6X G990P11U SOP-8 GMT LR

LNR-IC FAN DRIVER 1.6X G990P11U SOP-8 GMT LR

GND5GND6GND7GND

H=4.7mm

30mil

C34

2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

FAN_SPEED[39]

CON ACES 1.25MM S/T WIRE TO BOARD SMT TYPE 85205-0300L (LEAD FREE) 3PIN P=1

CN17

20-24197-10

2008/07/23 modify

Topology : PROCHOT#

Topology : FERR#

VCCP

VCCP=1.05VDDM

Rtt

VCCP

Rtt

0.5" - 12"

L1 1" - 6.5" 1" - 6.5"

L2 0" - 2.0" 0" - 2.0"

L2 1" - 6.5" 1" - 6.5"

ICH

CPU

Rtt

L2+L1

Rtt

VCCP

IMVP6

56 +/-5% 56 +/-5%

L3 0" - 3.0" 0" - 3.0"

Transmission Line Microstrip Stripline

Rtt

0" - 3.0"

75 +/-5%

0" - 3.0"

75 +/-5%

Transmission Line Micro-strip Strip-lineL4

Topology : PWRGOOD

CPU

ICH

2008/06/20 update FAN CTRL circuit

C C

SMCLK_PMU[39,41]

SMDAT_PMU[39,41]

B B

FSB Common Clock Signal Layout Guide :

ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# , RS[2..0]# , TRDY# , RESET#.

Transmission Line Type

Strip-line(Int. Layer) Micro-strip(Ext. Layer)

FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :

Signals Name

DATA#[15..0] , DINV0# DATA#[31..16] , DINV1#

A A

DATA#[47..32] , DINV2# DATA#[63..48] , DINV3#

Total Breakout Length ((G)MCH + CPU)

0 ~ 0.8 inch

Signals Matching

+/- 100 mils +/- 100 mils +/- 100 mils +/- 100 mils

Strobes associated with the group

DSTBP0#,DSTBN0# DSTBP1#,DSTBN1# DSTBP2#,DSTBN2# DSTBP3#,DSTBN3#

THERMAL SENSOR

U12

10mil 10mil

Total Trace Length

1.0 ~ 5 inch

Normal Impedance

55+/-15%

Strobe-to-Strobe Complement Matching

+/- 25 mils +/- 25 mils +/- 25 mils +/- 25 mils

U12

SCLK

SDATA

ALRT#

GND

LNR-IC Temperature Sensor G780P81U 3.0-5.5V MSOP-8 8PIN GMT LR

VCC

D+

D-

THM#

Spacing (mils)

4 & 8 mils 5 & 10 mils

0521_3VDDM replace 5VDDM

20mil

THRM_VCC

C191

C191 2200pF 50V 10% SMT0402 X7R LR

2200pF 50V 10% SMT0402 X7R LR

R155

10KΩ 5% 1/16W SMT0402 LR

HOT_DOWN#

3VDDA[18,20,21,23,25,26,27,28,29,31,35,36,37,38,39,41,44,45]

3VDDM[12,13,14,16,17,18,19,20,21,22,23,24,25,27,28,29,31,32,33,35,37,38,39,43,44,45]

5VDDM[21,22,23,24,32,34,36,43,44]

FSB Source Synchronous Data Signal Routing Topology#1 :

Signal Name

DINV#[3..0] DATA#[63..0] DSTBN#[3..0] DSTBP#[3..0]

FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :

Signals Name

A#[16..3] , REQ#[4..0] A#[31..17]

*** No length matching requirements exist between ADSTB0# and ADSTB1#

FSB Source Synchronous Address Signal Routing :

Signal Name

Address#[31..3] REQ#[4..0] ADSTB#[1..0]

Transmission Line Type

Strip-line Strip-line Strip-line Strip-line

Transmission Line Type

Strip-line Strip-line Strip-line

R132

R132 100Ω 5% 1/16W SMT0402 LR

100Ω 5% 1/16W SMT0402 LR

C178

0.1uF 16V 80-20% SMT0402 Y5V LR

H_THERMDA

H_THERMDC

3VDDA

HOT_DOWN# [39]

3VDDA

3VDDM

5VDDM

Total Trace Length

0.1 ~ 5.5 inch

0.1~ 5.5 inch

Signals Matching

+/- 200 mils +/- 200 mils

Total Trace Length

0.1 ~ 6.5 inch

H_THERMDA [8]

H_THERMDC [8]

10 mil

Minimum

10 mil

Normal Impedance

55+/-15% 55+/-15% 55+/-15% 55+/-15%

Strobes associated with the group

ADSTB0# ADSTB1#

Normal Impedance

55+/-15% 55+/-15%

55+/-15%

3VDDM

Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#

Topology : CPUSLP#

Topology : RESET#

Topology : THERMTRIP#

GND THERMDA THERMDC GND

Width & Spacing (mils) Data-to-Data,Strobe-to-strobe

4 & 8 mils 4 & 8 mils 4 & 12 mils 4 & 12 mils

Strobe to Assoc. Address Signal Matching

+/- 200 mils +/- 200 mils

Width & Spacing (mils)

4 & 8 mils 4 & 8 mils 4 & 12 mils

ICH

CPU

GMCH

CPU

GMCH

CPU

GMCH

1" - 12"

L1+L3

1" - 12"

1" - 6" 1" - 6"

Processor ITP Signal Default Strapping When ITP-XDP & ITP700FLEX Dedbug Port Not Used.

Signal TDI TMS TRST# TCK TDO

0" - 3.0"

1" - 12"

0" - 3.0"

Resistor Value

54.9 OHM +/-5%

54.9 OHM +/-5% 649 OHM +/-5% Within 2.0" of the CPU

54.9 OHM +/-5% OPEN

Strobe-to-Data

N/A N/A 4 & 16 mils 4 & 16 mils

Transmission Line

Micro-strip

0.5" - 12" Strip-line

0.5" - 12"

Transmission Line Micro-strip

0.5" - 12"

Strip-line

Transmission Line

0.5" - 12"

Micro-strip

0.5" - 12"

Strip-line

Transmission Line

L1 1" - 5"

Micro-strip

1" - 5"

Strip-line

VCCP

ICH7

L4 0" - 3.0" 0" - 3.0"

Rtt

Rss 24 +/-5%1" - 12" 24 +/-5%

Connect To

VCCP VCCP GND GND NC

Title

CW001

Size Document Number Rev

CPU Thermal

Date: Sheet

Transmission Line

Rtt

Micro-strip

56 +/-5%

Strip-line

56 +/-5%

Resistor Placement Within 2.0" of the CPU Within 2.0" of the CPU

Within 2.0" of the CPU N/A

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu

5FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

Confidential

10 47Monday, August 04, 2008

0.1

H H

MN2

HEATSINK

GND1

GND2

G G

F F

E E

D D

C C

B B

FCBGA_437P_HSK

1.05VDDM 1.05VDDM

R504

54.9Ω 1% 1/16W SMT0402 LR

H_XSCOMP

H_XRCOMP

R505

R505 RES 24.9Ω 1% 1/16W SMT0402 LR

RES 24.9Ω 1% 1/16W SMT0402 LR

Trace should be 10-mil wide with 20-mil spacing

1.05VDDM 1.05VDDM

R524

54.9Ω 1% 1/16W SMT0402 LR

H_YSCOMP

H_YRCOMP

R523

R523 RES 24.9Ω 1% 1/16W SMT0402 LR

RES 24.9Ω 1% 1/16W SMT0402 LR

R508

R508 RES 221Ω 1% 1/16W SMT0402 LR

RES 221Ω 1% 1/16W SMT0402 LR

R509

R509 100Ω 1% 1/16W SMT0402 LR

100Ω 1% 1/16W SMT0402 LR

R522

R522 RES 221Ω 1% 1/16W SMT0402 LR

RES 221Ω 1% 1/16W SMT0402 LR

R521

R521 100Ω 1% 1/16W SMT0402 LR

100Ω 1% 1/16W SMT0402 LR

H_XSWING

C469

0.1uF 10V ±10% SMT0402 X5R LR

H_YSWING

C475

0.1uF 10V ±10% SMT0402 X5R LR

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

H_D#[63..0]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_D#[63..0][8]

H=2.41(mm)

U32A

HD0#

HD1#

HD2#

HD3#

HD4#

HD5#

HD6#

HD7#

HD8#

HD9#

HD10#

HD11#

HD12#

HD13#

HD14#

HD15#

HD16#

HD17#

HD18#

HD19#

HD20#

HD21#

HD22#

HD23#

HD24#

HD25#

HD26#

HD27#

HD28#

HD29#

HD30#

HD31#

HD32#

HD33#

HD34#

HD35#

HD36#

HD37#

HD38#

HD39#

HD40#

HD41#

HD42#

HD43#

HD44#

HD45#

HD46#

HD47#

HD48#

HD49#

HD50#

HD51#

HD52#

HD53#

HD54#

AB4

HD55#

AB8

HD56#

HD57#

AA9

HD58#

AA8

HD59#

AB1

HD60#

AB7

HD61#

AA2

HD62#

AB5

HD63#

A10

HXRCOMP

HXSCOMP

C15

HXSWING

HYRCOMP

HYSCOMP

HYSWING

945GMS

HADSTB0# HADSTB1#

HCPURST#

HOST

HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3#

HCPUSLP#

H_AVREF

HBREQ0#

HDVREF

HDBSY#

HDEFER#

HDINV0# HDINV1# HDINV2# HDINV3#

HDPWR#

HDRDY#

HHITM# HLOCK# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4#

HTRDY#

HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS#

HBNR# HBPRI#

HCLKN HCLKP

HHIT#

HRS0# HRS1# HRS2#

H_A#3

HA3#

H_A#4

D12

HA4#

H_A#5

C13

HA5#

H_A#6

HA6#

H_A#7

E13

HA7#

H_A#8

E12

HA8#

H_A#9

J12

HA9#

H_A#10

B13

H_A#11

A13

H_A#12

G13

H_A#13

A12

H_A#14

D14

H_A#15

F14

H_A#16

J13

H_A#17

E17

H_A#18

H15

H_A#19

G15

H_A#20

G14

H_A#21

A15

H_A#22

B18

H_A#23

B15

H_A#24

E14

H_A#25

H13

H_A#26

C14

H_A#27

A17

H_A#28

E15

H_A#29

H17

H_A#30

D17

H_A#31

G17

H_ADS#

F10

H_ADSTB#0

C12

H_ADSTB#1

H16 E2

H_BNR#

H_BPRI#

H_BREQ#

H_CPURST#

B10 E1

CLK_MCH_BCLK#

AA6

CLK_MCH_BCLK

AA5

H_DBSY#

C10

H_DEFER#

H_DINV#0

H_DINV#1

H_DINV#2

H_DINV#3

H_DPWR#

H_DRDY#

H_DSTBN#0

H_DSTBN#1

H_DSTBN#2

H_DSTBN#3

AA3

H_DSTBP#0

H_DSTBP#1

H_DSTBP#2

H_DSTBP#3

AB3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#0

H_REQ#1

H_REQ#2

G12

H_REQ#3

H_REQ#4

F12

H_RS#0

H_RS#1

H_RS#2

G10

H_CPUSLP#

H_TRDY#

E10

H_A#[31..3]

H_REQ#[4..0]

H_A#[31..3] [8]

H_ADS# [8] H_ADSTB#0 [8] H_ADSTB#1 [8]

H_BNR# [8] H_BPRI# [8] H_BREQ# [8] H_CPURST# [8]

CLK_MCH_BCLK# [16] CLK_MCH_BCLK [16] H_DBSY# [8] H_DEFER# [8] H_DINV#0 [8] H_DINV#1 [8] H_DINV#2 [8] H_DINV#3 [8] H_DPWR# [8] H_DRDY# [8] H_DSTBN#0 [8] H_DSTBN#1 [8] H_DSTBN#2 [8] H_DSTBN#3 [8] H_DSTBP#0 [8] H_DSTBP#1 [8] H_DSTBP#2 [8] H_DSTBP#3 [8]

H_HIT# [8] H_HITM# [8] H_LOCK# [8]

H_REQ#[4..0] [8]

H_RS#0 [8] H_RS#1 [8] H_RS#2 [8] H_CPUSLP# [8] H_TRDY# [8]

1.05VDDM

10mils

H_VREF

C473

0.1uF 10V ±10% SMT0402 X5R LR

C472

0.1uF 10V 10% SMT0402 X5R LR(NU)

R519

R519 100Ω 1% 1/16W SMT0402 LR

100Ω 1% 1/16W SMT0402 LR

R520

R520 200Ω 1% 1/16W SMT0402 LR

200Ω 1% 1/16W SMT0402 LR

First International Computer, Inc.

A A

1.05VDDM[8,9,13,14,16,19,21,45]

1.05VDDM

Title

Size Document Number Rev

Date: Sheet

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW001

945GMS Host (1/5)

0.1

11 47Monday, August 04, 2008

H H

R510 RES 150Ω 1% 1/16W SMT0402 LRR510 RES 150Ω 1% 1/16W SMT0402 LR

R511 RES 150Ω 1% 1/16W SMT0402 LRR511 RES 150Ω 1% 1/16W SMT0402 LR

R512 RES 150Ω 1% 1/16W SMT0402 LRR512 RES 150Ω 1% 1/16W SMT0402 LR

G G

U32B

Y29 Y32 Y28 Y31

V28 V31 V29 V32

AF33

AG1

AM30

AG33

AF1

AK1

AN30

AN21 AN22 AF26 AF25

AG14 AF12 AK14 AH12

AJ21 AF11

AE12 AF14 AJ14 AJ12

AN12 AN14 AA33

AE1

AJ1

U32B

DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1

DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1

SM_CK0 SM_CK1

SM_CK2 SM_CK3

SM_CK0# SM_CK1#

SM_CK2# SM_CK3#

SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3

SM_CS0# SM_CS1# SM_CS2# SM_CS3#

SMOCDCOMP0 SMOCDCOMP1

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

SMRCOMPN SMRCOMPP SMVREF0 SMVREF1

DMI

MCH_RSVD1 MCH_RSVD2 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9

CFG/RSVD

DDR2 MUXING

EXT_TS1#/DPRSLPVR

THRMTRIP#

DREF_CLKN DREF_CLKP

CLK

DREF_SSCLKN DREF_SSCLKP

945GMS

DMI_TXN0

DMI_TXN0[18]

DMI_TXN1

DMI_TXN1[18]

DMI_TXP0

DMI_TXP0[18]

DMI_TXP1

DMI_TXP1[18]

DMI_RXN0

DMI_RXN0[18]

DMI_RXN1

DMI_RXN1[18]

DMI_RXP0

DMI_RXP0[18]

DMI_RXP1

F F

E E

1.8VDDS

R131

R131 10KΩ 1% 1/16W SMT0402 LR

D D

10KΩ 1% 1/16W SMT0402 LR

R128

R128 10KΩ 1% 1/16W SMT0402 LR

10KΩ 1% 1/16W SMT0402 LR

C487

0.1uF 10V ±10% SMT0402 X5R LR

DMI_RXP1[18]

M_CLK_DDR0

M_CLK_DDR0[17]

M_CLK_DDR1

M_CLK_DDR1[17]

M_CLK_DDR#0[17] M_CLK_DDR#1[17]

C176

0.1uF 10V ±10% SMT0402 X5R LR

M_CLK_DDR#0 M_CLK_DDR#1

M_CKE0

M_CKE0[17]

M_CKE1

M_CKE1[17]

M_CS#0

M_CS#0[17]

M_CS#1

M_CS#1[17]

M_ODT0

M_ODT0[17]

M_ODT1

M_ODT1[17]

M_RCOMP# M_RCOMP

M_VREF_MCH

C189

C189 MO-CAP 2.2uF 6.3V 10% SMT0603 X5R H=0.9mm CM105X5R225K06AT AVX LR

MO-CAP 2.2uF 6.3V 10% SMT0603 X5R H=0.9mm CM105X5R225K06AT AVX LR

ICHSYNC#

BM_BUSY#

EXT_TS0#

PWROK

RSTIN#

CLKREQB

CFG0 CFG1 CFG2 CFG3 CFG5 CFG6

MCH_BSEL0

C18

MCH_BSEL1

E18

MCH_BSEL2

G20

CFG3

G18

CFG5

J20

CFG6

J18

K32 K31 C17 F18 A3

CFG_3

CFG_5

CFG_6

MCH_ICH_SYNC

E31

PM_BMBUSY#

G21

R_PM_EXTTS#0

F26

PM_EXTTS#1

H26

PM_THRMTRIP#

J15

DELAY_VR_PWRGOOD

AB29

MCH_RSTIN#

W27

DREFCLK#

A27

DREFCLK

A26

DREFSSCLK#

J33

DREFSSCLK

H33

MCH_CLKREQ#

J22

MCH_BSEL0 [16] MCH_BSEL1 [16] MCH_BSEL2 [16]

R506

R507

R48

2.2KΩ 5% 1/16W SMT0402 LR(NU)

2.2KΩ 5% 1/16W SMT0402 LR

2.2KΩ 5% 1/16W SMT0402 LR(NU)

2008/04/24 ADD CFG table

Reserve

Low = DMIx2 Defalt High = DMIx4 (945GSE not support)

Reserve

R44 0Ω 5% 1/16W SMT0402 LRR44 0Ω 5% 1/16W SMT0402 LR R502 0Ω 5% 1/16W SMT0402 LRR502 0Ω 5% 1/16W SMT0402 LR

R88 100Ω 1% 1/16W SMT0402 LRR88 100Ω 1% 1/16W SMT0402 LR

DREFCLK# [16] DREFCLK [16] DREFSSCLK# [16] DREFSSCLK [16] MCH_CLKREQ# [16]

MCH_ICH_SYNC# [18] PM_BMBUSY# [20] PM_EXTTS#0 [17] PM_DPRSLPVR [20,43] PM_THRMTRIP# [8,19] DELAY_VR_PWRGOOD [20,43] PLTRST# [18,20,27,28,29,37,38,39]

2008/04/28 CONNECT R72

CRT_VSYNC[22] CRT_HSYNC[22]

RES 1.5KΩ 1% 1/16W SMT0402 LR

CRT_BLUE

CRT_GREEN

CRT_RED

R8 RES 39 5% 1/16W SMT0402 LRR8 RES 39 5% 1/16W SMT0402 LR R9 RES 39 5% 1/16W SMT0402 LRR9 RES 39 5% 1/16W SMT0402 LR R41 255Ω 1% 1/16W SMT0402 LRR41 255Ω 1% 1/16W SMT0402 LR

LBKLT_CTRL[23]

LVDS_ENABKL[39]

100KΩ 5% 1/16W SMT0402 LR

R50

1.5VDDM

R60

R60 RES 24.9Ω 1% 1/16W SMT0402 LR

RES 24.9Ω 1% 1/16W SMT0402 LR

U32F

H27

SDVOCTRL_DATA

J27

SDVOCTRL_CLK

CRT_DDC_CLK CRT_DDC_DATA CRT_BLUE

VGA_VSYNC_MCH VGA_HSYNC_MCH CRT_REFSET

LVDS_TXCLK1_LN LVDS_TXCLK1_LP

LVDS_TXOUT_L0N LVDS_TXOUT_L1N LVDS_TXOUT_L2N

LVDS_TXOUT_L0P LVDS_TXOUT_L1P LVDS_TXOUT_L2P

Y26

GCLKN

AA26

GCLKP

H20

DDCCLK

H22

DDCDATA

A24

BLUE

A23

BLUE#

E25

GREEN

F25

GREEN#

C25

RED

D25

RED#

F27

VSYNC

D27

HSYNC

H25

REFSET

H30

LBKLT_CTRL

G29

LBKLT_EN

F28

LCTLA_CLK

E28

LCTLB_CLK

G28

LDDC_CLK

H28

LDDC_DATA

K30

LVDD_EN

K27

LIBG

J29

LVBG

J30

LVREFH

K29

LVREFL

D30

LACLKN

C30

LACLKP

A30

LBCLKN

A29

LBCLKP

G31

LADATAN0

F32

LADATAN1

D31

LADATAN2

H31

LADATAP0

G32

LADATAP1

C31

LADATAP2

F33

LBDATAN0

D33

LBDATAN1

F30

LBDATAN2

E33

LBDATAP0

D32

LBDATAP1

F29

LBDATAP2

CLK_PCIE_3GPLL#[16]

CLK_PCIE_3GPLL[16]

CRT_DDC_CLK[22]

CRT_DDC_DATA[22]

CRT_BLUE[22]

CRT_GREEN

CRT_GREEN[22]

CRT_RED

CRT_RED[22]

R40

LVDS_DDC_CLK[23]

LVDS_DDC_DATA[23]

LVDS_ENALCD[23]

LVDS_TXCLK1_LN[23] LVDS_TXCLK1_LP[23]

LVDS_TXOUT_L0N[23] LVDS_TXOUT_L1N[23] LVDS_TXOUT_L2N[23]

LVDS_TXOUT_L0P[23] LVDS_TXOUT_L1P[23] LVDS_TXOUT_L2P[23]

LVDS_ENABKL L_CTLA_CLK L_CTLB_DATA L_DDC_CLK L_DDC_DATA LVDS_ENALCD LIBG

SDV0_TVCLKIN#

SDVO_FLDSTALL#

MISC

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVO

SDVOB_GREEN#

SDVOB_GREEN

LVDS VGA

945GMS

EXP_COMPI

EXP_ICOMPO

SDVO_INT#

SDVO_INT

SDVOB_RED#

SDVOB_BLUE#

SDVOB_CLKN

SDVOB_RED

SDVOB_BLUE SDVOB_CLKP

TVDAC_A TVDAC_B TVDAC_C

TV_REFSET

TV_IRTNA

TV_IRTNB TV_IRTNC

TV_DCONSEL0 TV_DCONSEL1

PEG_COMP

R28 M28

N30 R30 T29

M30 P30 T30

P28 N32 P32 T32

N28 M32 P33 R32

1.5VDDM

A21 C20 E20 G23 B21 C21 D21

G26 J26

C C

1.8VDDS

R529

R529 RES 80.6Ω 1% 1/16W SMT0402 RR0510S-80R6-FN CYNTEC LR

RES 80.6Ω 1% 1/16W SMT0402 RR0510S-80R6-FN CYNTEC LR

B B

M_RCOMP#

M_RCOMP

R531

R531 RES 80.6Ω 1% 1/16W SMT0402 RR0510S-80R6-FN CYNTEC LR

RES 80.6Ω 1% 1/16W SMT0402 RR0510S-80R6-FN CYNTEC LR

3VDDM 3VDDM

R38 10KΩ 5% 1/16W SMT0402 LRR38 10KΩ 5% 1/16W SMT0402 LR

R501 10KΩ 5% 1/16W SMT0402 LR(NU)R501 10KΩ 5% 1/16W SMT0402 LR(NU)

R14 10KΩ 5% 1/16W SMT0402 LRR14 10KΩ 5% 1/16W SMT0402 LR

2008/05/22 modify NU

R_PM_EXTTS#0

PM_EXTTS#1

MCH_CLKREQ#

RP2

6543

10KΩ 5% SMT2010 1/16W 8P4R LR

L_CTLB_DATA L_CTLA_CLK L_DDC_CLK L_DDC_DATA

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

A A

1.5VDDM[9,13,14,18,21,27,28,37,45]

1.8VDDS[14,17,45]

3VDDM[10,13,14,16,17,18,19,20,21,22,23,24,25,27,28,29,31,32,33,35,37,38,39,43,44,45]

1.5VDDM

1.8VDDS

3VDDM

Title

Size Document Number Rev

Date: Sheet

(886-2)8751-8751

CW001

945GMS DMI/Graph (2/5)

0.1

12 47Monday, August 04, 2008

H H

1.05VDDM

U32H

G G

M_A_DQ[63..0][17]

F F

E E

D D

C C

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U32C

AC31

SA_DQ0

AB28

SA_DQ1

AE33

SA_DQ2

AF32

SA_DQ3

AC33

SA_DQ4

AB32

SA_DQ5

AB31

SA_DQ6

AE31

SA_DQ7

AH31

SA_DQ8

AK31

SA_DQ9

AL28

SA_DQ10

AK27

SA_DQ11

AH30

SA_DQ12

AL32

SA_DQ13

AJ28

SA_DQ14

AJ27

SA_DQ15

AH32

SA_DQ16

AF31

SA_DQ17

AH27

SA_DQ18

AF28

SA_DQ19

AJ32

SA_DQ20

AG31

SA_DQ21

AG28

SA_DQ22

AG27

SA_DQ23

AN27

SA_DQ24

AM26

SA_DQ25

AJ26

SA_DQ26

AJ25

SA_DQ27

AL27

SA_DQ28

AN26

SA_DQ29

AH25

SA_DQ30

AG26

SA_DQ31

AM12

SA_DQ32

AL11

SA_DQ33

AH9

SA_DQ34

AK9

SA_DQ35

AM11

SA_DQ36

AK11

SA_DQ37

AM8

SA_DQ38

AK8

SA_DQ39

AG9

SA_DQ40

AF9

SA_DQ41

AF8

SA_DQ42

AK6

SA_DQ43

AF7

SA_DQ44

AG11

SA_DQ45

AJ6

SA_DQ46

AH6

SA_DQ47

AN6

SA_DQ48

AM6

SA_DQ49

AK3

SA_DQ50

AL2

SA_DQ51

AM5

SA_DQ52

AL5

SA_DQ53

AJ3

SA_DQ54

AJ2

SA_DQ55

AG2

SA_DQ56

AF3

SA_DQ57

AE7

SA_DQ58

AF6

SA_DQ59

AH5

SA_DQ60

AG3

SA_DQ61

AG5

SA_DQ62

AF5

SA_DQ63

AG19

SB_CAS#

AG21

SB_RAS#

AG20

SB_WE#

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

DDR2 SYSTEM MEMORY

SA_RCVENINB

SA_RCVENOUTB

945GMS

SA_BS_0 SA_BS_1 SA_BS_2

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_WEB

SB_BS_0 SB_BS_1 SB_BS_2

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SA_BS0

AK12

SA_BS1

AH11

SA_BS2

AG17

M_A_DM0

AB30

M_A_DM1

AL31

M_A_DM2

AF30

M_A_DM3

AK26

M_A_DM4

AL9

M_A_DM5

AG7

M_A_DM6

AK5

M_A_DM7

AH3

M_A_DQS0

AC28

M_A_DQS1

AJ30

M_A_DQS2

AK33

M_A_DQS3

AL25

M_A_DQS4

AN9

M_A_DQS5

AH8

M_A_DQS6

AM2

M_A_DQS7

AE3

M_A_DQS#0

AC29

M_A_DQS#1

AK30

M_A_DQS#2

AJ33

M_A_DQS#3

AM25

M_A_DQS#4

AN8

M_A_DQS#5

AJ8

M_A_DQS#6

AM3

M_A_DQS#7

AE2

M_A_A0

AJ15

M_A_A1

AM17

M_A_A2

AM15

M_A_A3

AH15

M_A_A4

AK15

M_A_A5

AN15

M_A_A6

AJ18

M_A_A7

AF19

M_A_A8

AN17

M_A_A9

AL17

M_A_A10

AG16

M_A_A11

AL18

M_A_A12

AG18

M_A_A13

AL14

M_A_CAS#

AJ17

M_A_RAS#

AK18

-RCVENIN

AN28

TP7TP7

-RCVENOUT

AM28 AH17

AH21 AJ20 AE27

AN20 AL21 AK21 AK22 AL22 AH22 AG22 AF21 AM21 AE21 AL20 AE22 AE26 AE20

M_A_WE#

TP6TP6

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[13..0]

M_A_BS0 [17] M_A_BS1 [17] M_A_BS2 [17] M_A_DM[7..0] [17]

M_A_DQS[7..0] [17]

M_A_DQS#[7..0] [17]

M_A_A[13..0] [17]

M_A_CAS# [17] M_A_RAS# [17]

M_A_WE# [17]

1.05VDDM

U32H

T25

VCC_NCTF1

R25

VCC_NCTF2

P25

VCC_NCTF3

N25

VCC_NCTF4

M25

VCC_NCTF5

P24

VCC_NCTF6

N24

VCC_NCTF7

M24

VCC_NCTF8

Y22

VCC_NCTF9

W22

VCC_NCTF10

V22

VCC_NCTF11

U22

VCC_NCTF12

T22

VCC_NCTF13

R22

VCC_NCTF14

P22

VCC_NCTF15

N22

VCC_NCTF16

M22

VCC_NCTF17

Y21

VCC_NCTF18

W21

VCC_NCTF19

V21

VCC_NCTF20

U21

VCC_NCTF21

T21

VCC_NCTF22

R21

VCC_NCTF23

P21

VCC_NCTF24

N21

VCC_NCTF25

M21

VCC_NCTF26

Y20

VCC_NCTF27

W20

VCC_NCTF28

V20

VCC_NCTF29

U20

VCC_NCTF30

T20

VCC_NCTF31

R20

VCC_NCTF32

P20

VCC_NCTF33

N20

VCC_NCTF34

M20

VCC_NCTF35

Y19

VCC_NCTF36

P19

VCC_NCTF37

N19

VCC_NCTF38

M19

VCC_NCTF39

Y18

VCC_NCTF40

P18

VCC_NCTF41

N18

VCC_NCTF42

NCTF

VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64

VTT_NCTF1 VTT_NCTF2 VTT_NCTF3 VTT_NCTF4 VTT_NCTF5 VTT_NCTF6

MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6

NCTF

945GMS

M18

Y17

P17 N17 M17

Y16

P16 N16 M16

Y15

P15 N15 M15

Y14 W14

V14 U14

T14 R14

P14 N14 M14

T10 R10

P10 N10

L10

M10

A18

AB10 AA10

VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8

VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8

VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 VSS_NCTF13 VSS_NCTF14 VSS_NCTF15 VSS_NCTF16 VSS_NCTF17 VSS_NCTF18 VSS_NCTF19

CFG19

MCH_RSVD10 MCH_RSVD11 MCH_RSVD12 MCH_RSVD13 MCH_RSVD14 MCH_RSVD15 MCH_RSVD16 MCH_RSVD17 MCH_RSVD18 MCH_RSVD19 MCH_RSVD20 MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25

AD25 AC25 AB25 AD24 AC24 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 K14 AD13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 AD12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 AD11 AD10 K10 AN33 AA25 V25 U25 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 A4 A33 B2 AN1 C1

K28

K25 K26 R24 T24 K21 K19 K20 K24 K22 J17 K23 K17 K12 K13 K16 K15

1.5VDDM

3VDDM

LANE_REV

CFG_19

(DMI LANE REVERSAL)

R34

R34 1KΩ 5% 1/16W SMT0402 LR(NU)

1KΩ 5% 1/16W SMT0402 LR(NU)

2008/04/24 ADD CFG19 table

Low = Normal High = LANES REVERSED (945GSE not support)

B B

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

CW001

945GMS DDR2 (3/5)

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

0.1

13 47Monday, August 04, 2008

A A

1.05VDDM[8,9,11,14,16,19,21,45]

1.5VDDM[9,12,14,18,21,27,28,37,45]

3VDDM[10,12,14,16,17,18,19,20,21,22,23,24,25,27,28,29,31,32,33,35,37,38,39,43,44,45]

1.05VDDM

1.5VDDM

3VDDM

Title

Size Document Number Rev

Date: Sheet

Via:5A

1.05VDDM

H H

1.5VDDM

0521 modify to 10uH

30mils

INDUCTOR 10μH ±10% GLF2012T100KT TDK LR

G G

120Ω±25% 100MHz 2500mA SMT0603 MLB-160808-0120P-N2 MAG.LAYERS LR

0521 modify to 100uF

C21

C21 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

INDUCTOR 10μH ±10% GLF2012T100KT TDK LR

C75

C75 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

L40

F F

L41

120Ω±25% 100MHz 2500mA SMT0603 MLB-160808-0120P-N2 MAG.LAYERS LR

E E

INTER RECOMMEND 91nH 0521 modify to 82nH

1.5VDDM

L8 82nH ±5% 300mA SMT0603 CLH1608T-82NJ-N CHILISIN LR

D D

82nH ±5% 300mA SMT0603 CLH1608T-82NJ-N CHILISIN LR

(400mA)

H=2.1(mm)

INDUCTOR 1μH ±20% GLF2012T1R0MT TDK LR

0521 modify to 1uH INTER RECOMMEND 1uH

0.1uf caps in 1.5VDDM_xPLL need to be located as edge caps within 200mils

(50mA)

10mils

C31

0.1uF 10V ±10% SMT0402 X5R LR

C15

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

H=2.1(mm)

C74

C74 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

H=2.1(mm)

C481

C481 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

C484

C484 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

0.1uF 10V ±10% SMT0402 X5R LR

(50mA)

10mils

C69

0.1uF 10V ±10% SMT0402 X5R LR

10mils

(45mA)

C482

0.1uF 10V ±10% SMT0402 X5R LR

(45mA)

10mils

C483

0.1uF 10V ±10% SMT0402 X5R LR

0521 modify to 100uF

Used in 1.5VDDM_PCIE should be on top layer

>60mils

1.5VDDM_PCIE

C88 0.1uF 10V ±10% SMT0402 X5R LRC880.1uF 10V ±10% SMT0402 X5R LR

C98

C99

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

1.5VDDM_3GPLL

10mils

10uf caps used in

1.5VDDM_3GPLL should be placed in cavity

1.5VDDM_DPLLA

1.5VDDM_DPLLB

1.5VDDM_HPLL

1.5VDDM_MPLL

200mils

C45

C476

C42

C477

C101

MO-CAP 4.7uF 10V 10% SMT0603 X5R H=0.8mm LMK107BJ475KA-T TAIYO LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

T 220uF 2.5V ±20% ESR=15mΩ SMT7343 2R5TPE220MF SANYO LR

1.05VDDM

(780mA)

C43

MO-CAP 4.7uF 10V 10% SMT0603 X5R H=0.8mm LMK107BJ475KA-T TAIYO LR

C100

MO-CAP 4.7uF 10V 10% SMT0603 X5R H=0.8mm LMK107BJ475KA-T TAIYO LR

T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR

MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

C C

(2940mA)

C471

C90

C109

0.1uF 10V ±10% SMT0402 X5R LR

1.5VDDM

C134

0.1uF 10V ±10% SMT0402 X5R LR

C68

VTT39

C480

C480 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

(1250mA)

VTT0

C468

C468 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

VTT11

C467

VTT40

C474

C474 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

U32D

T26

VCC0

R26

VCC1

P26

VCC2

N26

VCC3

M26

VCC4

V19

VCC5

U19

VCC6

T19

VCC7

W18

VCC8

V18

VCC9

T18

VCC10

R18

VCC11

W17

VCC12

U17

VCC13

R17

VCC14

W16

VCC15

V16

VCC16

T16

VCC17

R16

VCC18

V15

VCC19

U15

VCC20

T15

VCC21

AD33

VCC_AUX1

AD32

VCC_AUX2

AD31

VCC_AUX3

AD30

VCC_AUX4

AD29

VCC_AUX5

AD28

VCC_AUX6

AD27

VCC_AUX7

AC27

VCC_AUX8

AD26

VCC_AUX9

AC26

VCC_AUX10

AB26

VCC_AUX11

AE19

VCC_AUX12

AE18

VCC_AUX13

AF17

VCC_AUX14

AE17

VCC_AUX15

AF16

VCC_AUX16

AE16

VCC_AUX17

AF15

VCC_AUX18

AE15

VCC_AUX19

J14

VCC_AUX20

J10

VCC_AUX21

H10

VCC_AUX22

AE9

VCC_AUX23

AD9

VCC_AUX24

VCC_AUX25

AD8

VCC_AUX26

AD7

VCC_AUX27

AD6

VCC_AUX28

A14

VTT0

D10

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VTT23

VTT24

VTT25

VTT26

VTT27

VTT28

VTT29

VTT30

VTT31

VTT32

VTT33

VTT34

VTT36

VTT35

VTT37

VTT38

AA1

VTT39

VTT40

945GMS

VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1

VCCA_TVBG VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2

VCCHV0 VCCHV1 VCCHV2 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8

VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51

VCCA_MPLL

VCCA_HPLL VCCA_DPLLA VCCA_DPLLB

POWER

VCCD_HMPLL1 VCCD_HMPLL2 VCCTX_LVDS0 VCCTX_LVDS1

VCC3G0

VCC3G1 VCCA_3GPLL VCCA_3GBG

VSSA_3GBG

VCC_SYNC VCCA_CRTDAC0 VCCA_CRTDAC1

VSSA_CRTDAC

VCCA_LVDS

VSSALVDS

VTT41 VTT42 VTT43 VTT44 VTT45

B20 A20 B22 A22 D22 C22 D23 E23 F20 F22 C28 B28 A28 E26 D26 C26 AB33 AM32 AN29 AM29 AL29 AK29 AJ29 AH29 AG29 AF29 AE29 AN24 AM24 AL24 AK24 AJ24 AH24 AG24 AF24 AE24 AN18 AN16 AM16 AL16 AK16 AJ16 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AN4 AM10 AL10 AK10 AH1 AH10 AG10 AF10 AE10 AN7 AM7 AL7 AK7 AJ7 AH7 AN10 AJ10 AD1 AD2 B26 J32 AE5 AD5 D29 C29 U33 T33 V26 N33 M33 J23 C24 B24 B25 B31 B32

P1 L1 G1 U1 Y1

1.5VDDM

(120mA)

DISABLE TV

(20mA)

VCCSM0

VCCSM1

C112

C500

1uF 6.3V 10% SMT0402 X5R LR

VCCSM20

C499

C499 1uF 6.3V 10% SMT0402 X5R LR

1uF 6.3V 10% SMT0402 X5R LR

VCCSM35

VCCSM39

C488

C488 1uF 6.3V 10% SMT0402 X5R LR

1uF 6.3V 10% SMT0402 X5R LR

1.5VDDM_MPLL

1.5VDDM_HPLL

1.5VDDM_DPLLA

1.5VDDM_DPLLB

1.5VDDM

1.5VDDM_PCIE

(10mA)

2.5VDDM

C12

C33

0.1uF 10V ±10% SMT0402 X5R LR

0.01uF 16V 10% SMT0402 X7R LR

1.05VDDM

1.5VDDM 3VDDM

R23

R23 RES 0Ω 1% 1/16W SMT0402 RTT02000FTH RALEC LR

C466

C51

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

0.1uF 10V ±10% SMT0402 X5R LR

RES 0Ω 1% 1/16W SMT0402 RTT02000FTH RALEC LR

(40mA)

C36

C47

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

0.1uF 10V ±10% SMT0402 X5R LR

(1720mA)

C504

C278

C146

MO-CAP 4.7uF 10V 10% SMT0603 X5R H=0.8mm LMK107BJ475KA-T TAIYO LR

1uF 6.3V 10% SMT0402 X5R LR

C490

C490 1uF 6.3V 10% SMT0402 X5R LR

1uF 6.3V 10% SMT0402 X5R LR

C211

T 220uF 2.5V ±20% ESR=15mΩ SMT7343 2R5TPE220MF SANYO LR

MO-CAP 4.7uF 10V 10% SMT0603 X5R H=0.8mm LMK107BJ475KA-T TAIYO LR

Intel recommend three 330uF cap.

(60mA)

C114

C103

C103 10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

2.5VDDM

C19

C70

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

0.1uF 10V ±10% SMT0402 X5R LR

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR

0.1uF 10V ±10% SMT0402 X5R LR

C28

0.022uF 16V 10% SMT0402 X7R LR

1.8VDDS

1.5VDDM_3GPLL

C56

C20

C20 MO-CAP 4.7uF 10V 10% SMT0603 X5R LR

MO-CAP 4.7uF 10V 10% SMT0603 X5R LR

0.1uF 10V ±10% SMT0402 X5R LR

C32

0.1uF 10V ±10% SMT0402 X5R LR

2.5VDDM_CRTDAC

C37

0.1uF 10V ±10% SMT0402 X5R LR

2.5VDDM

B B

(70mA)

120Ω±25% 100MHz 2500mA SMT0603 MLB-160808-0120P-N2 MAG.LAYERS LR

A A

D1 DIODE STKY BAT54C 30V 200mA SOT-23 3PIN PHILIPS LRD1 DIODE STKY BAT54C 30V 200mA SOT-23 3PIN PHILIPS LR

20mils

10Ω 1% 1/10W SMT0603 LR

R12

1.05VDDM

20mils

2.5VDDM_CRTDAC

C16

10uF 6.3V ±20% SMT0805 X5R CM21X5R106M06AT AVX/CYOCERA LR(NU)

C16

2008/04/23 ADD 10uf 0805

X5R(DEFUALT NU)

1.5VDDM

C81 1uF 6.3V 10% SMT0402 X5R LR(NU)C81 1uF 6.3V 10% SMT0402 X5R LR(NU)

C82 1uF 6.3V 10% SMT0402 X5R LR(NU)C82 1uF 6.3V 10% SMT0402 X5R LR(NU)

C59 1uF 6.3V 10% SMT0402 X5R LR(NU)C59 1uF 6.3V 10% SMT0402 X5R LR(NU)

C86 1uF 6.3V 10% SMT0402 X5R LR(NU)C86 1uF 6.3V 10% SMT0402 X5R LR(NU)

C137 0.1uF 10V ±10% SMT0402 X5R LR(NU)C137 0.1uF 10V ±10% SMT0402 X5R LR(NU)

C136 0.1uF 10V ±10% SMT0402 X5R LR(NU)C136 0.1uF 10V ±10% SMT0402 X5R LR(NU)

1.8VDDS1.05VDDM

C139 1uF 6.3V 10% SMT0402 X5R LR(NU)C139 1uF 6.3V 10% SMT0402 X5R LR(NU)

C156 1uF 6.3V 10% SMT0402 X5R LR(NU)C156 1uF 6.3V 10% SMT0402 X5R LR(NU)

C165 1uF 6.3V 10% SMT0402 X5R LR(NU)C165 1uF 6.3V 10% SMT0402 X5R LR(NU)

C143 1uF 6.3V 10% SMT0402 X5R LR(NU)C143 1uF 6.3V 10% SMT0402 X5R LR(NU)

C166 1uF 6.3V 10% SMT0402 X5R LR(NU)C166 1uF 6.3V 10% SMT0402 X5R LR(NU)

C160 1uF 6.3V 10% SMT0402 X5R LR(NU)C160 1uF 6.3V 10% SMT0402 X5R LR(NU)

C145 1uF 6.3V 10% SMT0402 X5R LR(NU)C145 1uF 6.3V 10% SMT0402 X5R LR(NU)

1.05VDDM[8,9,11,13,16,19,21,45]

1.5VDDM[9,12,13,18,21,27,28,37,45]

3VDDM[10,12,13,16,17,18,19,20,21,22,23,24,25,27,28,29,31,32,33,35,37,38,39,43,44,45]

2.5VDDM[45]

1.8VDDS[12,17,45]

1.05VDDM

1.5VDDM

3VDDM

2.5VDDM

1.8VDDS

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

CW001

945GMS Power (4/5)

(886-2)8751-8751

14 47Monday, August 04, 2008

Title

Size Document Number Rev

Date: Sheet

0.1

H H

U32E

AH33

VSS1

Y33

VSS2

V33

VSS3

R33

VSS4

G33

VSS5

AK32

VSS6

AG32

VSS7

AE32

VSS8

AC32

VSS9

AA32

VSS10

U32

VSS11

H32

VSS12

G G

E32

VSS13

C32

VSS14

AM31

VSS15

AJ31

VSS16

AA31

VSS17

U31

VSS18

T31

VSS19

R31

VSS20

P31

VSS21

N31

VSS22

M31

VSS23

J31

VSS24

F31

VSS25

AL30

VSS26

AG30

VSS27

AE30

VSS28

AC30

VSS29

AA30

VSS30

Y30

VSS31

F F

V30

VSS32

U30

VSS33

G30

VSS34

E30

VSS35

B30

VSS36

AA29

VSS37

U29

VSS38

R29

VSS39

P29

VSS40

N29

VSS41

M29

VSS42

H29

VSS43

E29

VSS44

B29

VSS45

AK28

VSS46

AH28

VSS47

AE28

VSS48

AA28

VSS49

U28

E E

VSS50

T28

VSS51

J28

VSS52

D28

VSS53

AM27

VSS54

AF27

VSS55

AB27

VSS56

AA27

VSS57

Y27

VSS58

U27

VSS59

T27

VSS60

R27

VSS61

P27

VSS62

N27

VSS63

M27

VSS64

G27

VSS65

E27

VSS66

C27

VSS67

B27

VSS68

D D

AL26

VSS69

AH26

VSS70

W26

VSS71

U26

VSS72

AN25

VSS73

AK25

VSS74

AG25

VSS75

AE25

VSS76

J25

VSS77

G25

VSS78

A25

VSS79

H23

VSS80

F23

VSS81

B23

VSS82

AM22

VSS83

AJ22

VSS84

AF22

VSS85

G22

VSS86

E22

C C

VSS87

J21

VSS88

H21

VSS89

F21

VSS90

AM20

VSS91

AK20

VSS92

AH20

VSS93

AF20

VSS94

D20

VSS95

W19

VSS96

R19

VSS97

AM18

VSS98

AH18

VSS99

AF18

VSS100

U18

VSS101

H18

VSS102

D18

VSS103

AK17

VSS104

V17

VSS105

T17

B B

VSS106

F17

VSS107

B17

VSS108

AH16

VSS109

U16

VSS110

945GMS

VSS

VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185

J16 AL15 AG15 W15 R15 F15 D15 AM14 AH14 AE14 H14 B14 F13 D13 AL12 AG12 H12 B12 AN11 AJ11 AE11 AM9 AJ9 AB9 W9 R9 M9 J9 F9 C9 A9 AL8 AG8 AE8 U8 AA7 V7 R7 N7 H7 E7 B7 AL6 AG6 AE6 AB6 W6 T6 M6 K6 AN5 AJ5 B5 AA4 V4 R4 N4 K4 H4 E4 AL3 AD3 W3 T3 B3 AK2 AH2 AF2 AB2 M2 K2 H2 F2 V1 R1

U32G

W33

NC1

AM33

NC2

AL33

NC3

C33

NC4

B33

NC5

AN32

NC6

A32

NC7

AN31

NC8

W28

NC9

V27

NC10

W29

NC11

J24

NC12

H24

NC13

W32

NC14

G24

NC15

F24

NC16

E24

NC17

D24

NC18

K33

NC19

A31

NC20

E21

NC21

C23

NC22

AN19

NC23

AM19

NC24

AL19

NC25

AK19

NC26

AJ19

NC27

AH19

NC28

AN3

NC29

NC30

J19

NC31

H19

NC32

G19

NC33

F19

NC34

E19

NC35

D19

NC36

C19

NC37

B19

NC38

A19

NC39

NC40

G16

NC41

F16

NC42

E16

NC43

D16

NC44

C16

NC45

B16

NC46

AN2

NC47

A16

NC48

NC49

AM4

NC50

AF4

NC51

AD4

NC52

AL4

NC53

AK4

NC54

W31

NC55

AJ4

NC56

AH4

NC57

AG4

NC58

AE4

NC59

AM1

NC60

945GMS

MCH_RSVD26 MCH_RSVD27 MCH_RSVD28 MCH_RSVD29 MCH_RSVD30 MCH_RSVD31 MCH_RSVD32 MCH_RSVD33 MCH_RSVD34 MCH_RSVD35 MCH_RSVD36 MCH_RSVD37 MCH_RSVD38 MCH_RSVD39 MCH_RSVD40 MCH_RSVD41 MCH_RSVD42

W30

NC61

NC62

AL1

NC63

NC64

Y10

NC65

W10

NC66

W25

NC67

V24

NC68

U24

NC69

V10

NC70

U10

NC71

K18

NC72

Y25 Y24 AB22 AB21 AB19 AB16 AB14 AA12 W24 AA24 AB24 AB20 AB18 AB15 AB13 AB12 AB17

A A

DMI Routing Guideline

GMCH

Parameter

Uncoupled Single End Impedance specfication

Uncoupled Single End Impedance target Microstrip Nominal Trace Width

Microstrip Nominal Didderential Pair-Pitch

Microstrip Pair-to-Pair Pitch

Microstrip Bus-to-Bus Pitch Stripline Nominal Trace Width Stripline Nominal Didderential Pair-Pitch Stripline Pair-to-Pair Pitch

Stripline Bus-to-Bus Pitch Reference Plane Splits/Voids

Bends

Breakout/in

Main Route

LB/LY

LA/LZ

Same Routing layer as LA/LZ

Microstrip Microstrip

Same Routing layer as LA/LZ

Stripline

Same Routing layer as LA/LZ

Stripline

Same Routing layer as LA/LZ

Parameter Trace Length-LA Trace Length-LB Trace Length-LD Trace Length-LE Trace Length-L1

Trace Length-LV Trace Length-LW Trace Length-LY Trace Length-LZ Trace Length-L2

*** When routing near the edge of their reference plane , trace should maintain at least 40 mils space to the edge of the plane *** Match the trace lengths of the complementary signals within each differential pair to +/- 5 mils

Description GMCH Breakout GMCH Breakout to via2 Route Via2 to Intel 82801GBM Breakout Route Intel 82801GBM Breakout LA+LB+LD+LE

Intel 82801GBM BreakoutRoute Intel 82801GBM BreakoutRoute to via2 Route Via2 to GMCH Breakout Route GMCH Breakout Route LV+LW+LY-LZ

Main Route Guideline 55 +/- 15% N/A 5 mils 12 mils Min= 37 mils

Min= 20 mils 4 mils 11 mils Min= 37 mils

Min= 22 mils Ground

No routing over plane splits

No routing over voids Match left and rght turn

bends where possible NO 90-degree bends

Main Route

LD/LW

Same Routing layer as LE/LV Same Routing layer as LE/LV

Same Routing layer as LE/LV

ICH7m

LELB

LD LW

MAX Length(for all Three Via configurlation)

>3W

< 2S

S = Spacing S = Trace Width

Rx Tx

Breakout Guideline Same Same 5 mils 5 mils GMCH: min= 27 mils

Intel 82801GBM: min= 27 mils

Min= 12 mils 4 mils 4 mils GMCH: min= 27 mils

Intel 82801GBM: min= 27 mils

Min= 15 mils Same

Same

Maxmum total

Breakout/in

LE/LV

Microstrip Stripline MicrostripSame Routing layer as LE/LV Stripline

Max = 400 mils Max = 7.1 inches Max = 7.1 inches Max = 400 mils Max = 8 inches

length

8 inches 8 inches 8 inches 8 inches

PCIE Routing Guideline

GMCH

Tx Rx

Breakout

LA/LZ

Stripline

Microstrip

Parameter Uncoupled Single End Impedance Microstrip Nominal Trace Width Microstrip Nominal Trace Space Microstrip Differential Pair Pitch Microstrip Pair to Pair Pitch Microstrip Bus-to-Bus Spacing Stripline Nominal Trace Width Stripline Nominal Trace Space Stripline Differential Pair Pitch Stripline Pair to Pair Pitch Stripline Bus-to-Bus Spacing Reference Plane Splits/Voids

Bends

Parameter

Trace Length-LA Trace Length-LB Trace Length-LC Trace Length-L1

Trace Length-LY Trace Length-LZ Trace Length L2

Main Route

LB/LC/LY

Maximum Total Length

12 inches

Main Route Guideline 55 +/- 15% 5 mils 7 mils 12 mils Min = 37 mils Min = 20 mils 4 mils 7 mils 11 mils Min = 37 mils Min = 20 mils Ground

No routing over plane splits No routing over voids

Match left and right turn bends where possible Same NO 90-degree bends

Description

Intel 82801GBM to Express Card or PCI ExpressMini Card Intel 82801GBM BreakoutRoute Intel 82801GBM BreakoutRoute to AC cap Route AC cap to Connector Intel 82801GBM to connector TX route(LA+LB+LC) Express Card or PCI ExpressMini Card to Intel 82801GBM Connector to Intel 82801GBM Breakout Route Intel 82801GBM Breakout Connector to Intel 82801GBM RX Route(LY+LZ)

Title

CW001

Size Document Number Rev

945GMS Power (5/5)

Date: Sheet

Express/Mini Card

Breakout Guideline 55 +/- 15% 5 mils 5 mils 10 mils ICH : Min = 27 mils Min = 12 mils 4 mils 4 mils 8 mils ICH : Min = 27 mils Min = 15 mils Same

Same

MAX Length For all Routing Option

Max=400mils Max=10.76 inches Max=10.76 inches Max=12 inches

Max=11.96 inches Max=400mils Max=12 inches

>3W

< 2S

S = Spacing S = Trace Width

First International Computer, Inc.

2FL.,NO.300,Yang Guang St.,NeiHu

2FL.,NO.300,Yang Guang St.,NeiHu 114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC

114 TAIPEI, TAIWAN ,ROC (886-2)8751-8751

(886-2)8751-8751

15 47Monday, August 04, 2008

0.1

+ 32 hidden pages

first international computer CW001 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual