Finisar 10GBASE-LRM X2, FTLX1341E2 User Manual

Product Specification

RoHS-6 Compliant

10GBASE-LRM X2 Transponder

FTLX1341E2

PRODUCT FEATURES

 Hot pluggable X2 MSA form factor
 Total power consumption: 4.0 W maximum
 RoHS-6 compliant (lead-free)
 Temperature range 0°C to 70°C
 Transmission distance up to 220m
 Uncooled 1310 nm directly modulated

Fabry-Perot (FP) laser

 Built In Advanced Electronic Dispersion

Compensation (EDC)

 SC connector, multimode fiber
 Full duplex transmission mode
 Digital Optics Monitoring (DOM)
 Power supply: +5.0 V, +3.3 V
 Adaptable Power Supply (APS: +1.2 V)
 XAUI electrical interface

- 4 x 3.125 Gb/s Ethernet

 Management and control via MDIO

2-wire bus

 70-pin connector
 Separated signal/chassis ground
 Mid Pak module variance for

front panel mounting

 De-latch mechanism with low

extraction force

*

APPLICATIONS

 IEEE 802.3aq-2006

 10 Gb/s Ethernet transmission on

legacy multimode fiber.

The Finisar FTLX1341E2 transponder incorporates Electronic Dispersion Compensation (EDC)
which provides correction for the severe modal dispersion that may occur during propagation
through links up to 220m on legacy installed FDDI multimode fiber. The EDC device
incorporates a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). The
EDC also contains sophisticated clock recovery architecture for extracting a robust clock from
extremely distorted signals.

PRODUCT SELECTION

FTLX1341E2

* Maximum reach as defined by IEEE. Longer reach possible depending upon link implementation.

© Finisar Corporation – October 2008 Rev B Page 1

FTLX1341E2 Product Specification – October 2008

I. Pin Description

Signal Name Level I/O Pin No. Description
Management and Monitoring Ports

MDIO Open Drain

(output)

1.2V CMOS
(input)

MDC 1.2 V

CMOS

PRTAD4 1.2 V

CMOS

PRTAD3 1.2 V

CMOS

PRTAD2 1.2 V

CMOS

PRTAD1 1.2 V

CMOS

PRTAD0 1.2 V

CMOS

LASI Open Drain O 9 Link Alarm Status Interrupt Output.

RESET 1.2 V

CMOS

Vendor Specific 11,15,16,24 Vendor Specific Pins.

TX ON/OFF 1.2 V

CMOS

MOD DETECT O 14 Module Detect. Pulled low inside

Transmit Functions

Reserved
Reserved
TX LANE 3–
TX LANE 3+

TX LANE 2–
TX LANE 2+
TX LANE 1–
TX LANE 1+
TX LANE 0–
TX LANE 0+

I

AC-coupled,
Internally biased
differential
XAUI

I/O 17 Management Data I/O. Requires

external 10 - 22 kΩ pull-up to the
APS on host.

I 18 Management Data Clock Input

1 19 Port Address Input bit 4

I 20 Port Address Input bit 3

I 21 Port Address Input bit 2

I 22 Port Address Input bit 1

I 23 Port Address Input bit 0

Open Drain Compatible Output with
10 - 20 kΩ pull-up on host.
Logic high = Normal Operation
Logic low = Status Flag Triggered

I 10 Reset Input.

Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Normal Operation
Logic low = RESET

Leave unconnected when not used.

I 12 TX ON/OFF Input.

Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Transmitter On
Logic low = Transmitter Off

transponder through a 1 kΩ resistor
to Ground

68
I
I
I

I
I
I
I
I
I

67

65

64

62

61

59

58

56

55

Reserved For Future Use
Reserved For Future Use
Module XAUI Input Lane 3–
Module XAUI Input Lane 3+

Module XAUI Input Lane 2–
Module XAUI Input Lane 2+
Module XAUI Input Lane 1–
Module XAUI Input Lane 1+
Module XAUI Input Lane 0–
Module XAUI Input Lane 0+

© Finisar Corporation – October 2008 Rev B Page 2

FTLX1341E2 Product Specification – October 2008

Receive Functions

Reserved
Reserved
RX LANE 0+
RX LANE 0–

RX LANE 1+
RX LANE 1–
RX LANE 2+
RX LANE 2–
RX LANE 3+
RX LANE 3–

DC Power

GND 0 V DC 1, 2, 3, 33, 34,

APS +1.2 V 7, 8, 28, 29 Input from Adaptive Power Supply
APS SENSE +1.2 V 27 APS Sense Output. Connected to the

APS SET 25 Feedback input from APS.

3.3 V +3.3 V DC 5, 6, 30, 31 DC Power Input, +3.3 V DC,

5.0 V +5.0 V DC 4, 32 DC Power Input, +5.0 V DC,

Reserved 26 Reserved for APD.
Reserved 13 Reserved.

O

O

AC-coupled,
Internally biased
differential
XAUI

O
O

O
O
O
O
O
O

38

39

41

42

44

45

47

48

50

51

35, 36, 37, 40,

43, 46, 49, 52,

53, 54, 57, 60,

63, 66, 69, 70

Reserved For Future Use
Reserved For Future Use
Module XAUI Output Lane 0+
Module XAUI Output Lane 0–

Module XAUI Output Lane 1+
Module XAUI Output Lane 1–
Module XAUI Output Lane 2+
Module XAUI Output Lane 2–
Module XAUI Output Lane 3+
Module XAUI Output Lane 3–

Ground connection for signal ground
on the module

APS input inside transponder.

Connected to GND through a 1180Ω
resistor inside the transponder.

Nominal

Nominal

© Finisar Corporation – October 2008 Rev B Page 3