Fic MR030, Amilo Si2636 Schematic

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First International Computer,Inc

D D

Portable Computer Group HW Department

Board name : MotherBoard Schematic
Project :

C C

Version : 0.6

MR030

Initial Date : Oct. 17 , 2007

1. Schematic Page Description :

2. PCI & IRQ & DMA Description :

3. Block Diagram :

4. Nat name Description :

5. Board Stack up Description :

6. Schematic modify Item and History :

7. power on & off & S3 Sequence :

8. Layout Guideline :

9. switch setting

B B

Manager Sign by: AVERY
Drawing by : Spruce

Total confirm by: AVERY
LAN Circuit check by:

A A

Audio Circuit check by:

5

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Title

Size Document Number Rev

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2

Date: Sheet

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

Title

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Confidential

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1. Schematic Page Description :

MR030T Schematic Ver : 0.6

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1. Title

2. Schematic Page Description

3. Block Diagram

4. ANNOTATIONS

5. Schematic Modify

6. Timing Diagram

7. DDRII Layout Guideline

8. Merom Processor(1/2)

9. Merom Processor(2/2)

10. CPU Thermal

11. Crestline Host(1/6)

12. Crestline DMI/Graphic(2/6)

C C

13. Crestline DDRII(3/6)

14. Crestline Power(4/6)

15. Crestline Power(5/6)

16. Crestline GND(6/6)

17. Clock Generator

18. DDRII SDRAM SO-DIMM0

19. DDRII SDRAM SO-DIMM1

20. ICH8M PCI/PCIE/DMI(1/4)

21. ICH8M CPU/IDE/SATA(2/4)

22. ICH8M GPIO(3/4)

23. ICH8M Power/GND(4/4)

24. Reset Circuit

25. Screw Hole

26. SPI/TPM

27. LCD CNN

28. HDMI Transmitter

29. HDMI CNN

30. INT KB / LID / GP / SW CNN

31. DIP SW / LED

32. SATA & IDE CNN

33. USB CNN

34. EXPRESS CARD

35. E-SATA

36. PCIE GIGA LAN 88E8055

37. TRANSFORMER

38. RTS5158 (Card-reader)

39. FW322 (IEEE-1394)

40. Azalia CX20561 Codec

41. AMP APA2068KAI

42. HP/ Ext. Mic/Int. Mic/Buzzer

43. Mini-Robson

44. Mini-WLAN/BT/CCD

45. Empty page

46. PMX

47. CPU Core Power

48. Power Block

49. ADPIN, BATIN, ADPOUT1

50. Charger MAX8730

51. 3/5VDDA/M , PMU3/5V

52. 1.05V/1.5VDDM

53. 1.8VDDS / 0.9VDDS

54. GPU Core Power(MAX8797)

55. 1.25VDDM

56. SW board(LAN conn)

57. GP board

58. Modify list

B B

2. PCI & IRQ & DMA Description :

IDSEL

AD19

BUSMASTER

REQ
REQ0 / GNT0
REQ1 / GNT1

A A

REQ2 / GNT2
REQ3 / GNT3
REQ4 / GNT4

CHIP CHIPPCIINT

FW322(1394) FW322(1394)

CHIP
X
FW322(1394)
X
X
X

8

7

IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15

System timer
Keyboard
(Casacde)
LAN / MODEM
Serial Port
AUDIO / VGA / USB
FLOPPY DISK
LPT
RTC
ACPI

(Disable by default)

FIR
Cardbus
PS/2 mouse
FPU
HDD
CDROM

6

(MODEM/LAN)

5

DMA Channel
DMA0 FIR
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7

DeviceIRQ Channel Desciption

(disable by default)

ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused

4

(MODEM / LAN)

3

IRQA
IRQB
IRQC
IRQD
IRQE / GPIO2
IRQE / GPIO3
IRQE / GPIO4
IRQE / GPIO5

X
X
X
X
X
X
X

2

20051228A

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

Date: Sheet

(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

Schematic Page Description

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3. Block Diagram :

D D

Intel

Thermal
Sensor

P10

(667/800 MHz)

HDMI
SiI1392CNU

P28,29

LCD

P27

C C

P32

P32

USB 2.0

USB 0,1,2

P33,35

PATA BUS

SATA BUS

Realtek

RTS5158-GR

CardReader
3 in 1

B B

ACIN / DCIN

DCIN+

P49

P49

P38

P38

Express Card

Battery CON

P49

Battery Charger

P50

Battery Voltage Sense

P46

P34

CCD

P44

B / T

P44

CDROM

HDD

Merom
Processor

FSB

Intel

Crestline
(G)MCH

DMI

(x2/x4)

Intel

ICH8M

32Bit PCI BUS

P11~P16

P20~23

SPI BUS

P26

Flash ROM

P8~9

Mem_A Bus

Mem_B Bus

PCIE

MINI CARD

Azalia

LPC BUS

P44

PMX

M38859

Int. KB

3VDDA
5VDDA

P51

3VDDM/5VDDM

P51

1.5VDDM

P52

1.8VDDS

P53

DDRII Power

PMU3V
PMU5V

P53

P51

AGERE

FW3227

IEEE 1394

P38

CPU

CORE

P47

CPU

VCCP

P52

DDR2 533/667 MHz

DDRII SODIMM0 (A)

DDR2 533/667 MHz

DDRII SODIMM1 (B)

MINI CARD

HDMI

P46

P43

P28

Glide Pad

P30P30

P18

P19

Express Card

P34

Azalia Codec

CX20561

SPDIF OutMic In

P42

P42

CLK SLG8SP512TTR

Reset Circuit

Brightness Control

RTC Bat

Fan CNN

Lid Switch

MAIN SW CNN/DIP SW

LED

E-SATA
SiI3531A

P35

P40

Headphone

GIGA LAN

88E8055

RJ-45

Audio AMP

APA2068KAI

SPK

P42

P56

P17

P24

P44

P21

P10

P56

P30

P31

P36

P37

P41

P41

A A

1.5VDDM/1.05VDDM

OVP

8

P34

P52

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

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Date: Sheet

2

(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

Block Diagram

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4. Nat name Description :

Voltage Rails

DCIN
PMU5V 5.0V always on power rail by LATCH or ACIN

D D

PMU3V 3.3V always on power rail by LATCH or ACIN
3VDDA 3.3V always on power rail by DCON

1.25VDDM
VGA_CORE
3VDDM

VCC_CORE

1.05VDDM

1.5VDDM

1.8VDDS

0.9VDDT_DDRII

Part Naming Conventions

C

=

Capacitor

CN

C C

D
F
L
Q
R
RP
U
Y

Connector

=

Diode

=

Fuse

=

Inductor

=

Transistor

=

Resistor

=

Resistor Pack

=

Arbitrary Logic Device

=

Crystal and Osc

=

Net Name Suffix

#=

B B

Active Low signal

Primary DC system power supply

5.0V always on power rail by DCON5VDDA

1.25V switchedpower rail by SUSTAT_B#
VGA_CORE switchedpower rail by SUSTAT_B#

3.3V switched power rail by SUSTAT_B#

5.0V switched power rail by SUSTAT_B#5VDDM
Core Voltage for CPU

1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#

1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE
for ICH7m by SUSTAT_B#

1.8V power rail for DDRII by PSUSC#

0.9V DDRII Termination Voltage by SUSTAT_B#

5. Board Stack up Description

PCB Layers

Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8

Layers : 8 Depth 1.2mm Impence 55 ohms +/- 10%

Single End Impedance

Host Clock
SRC Clock
Host Bus
DDR2 CLK
DDR2 Strobe
DDR2 Bus
DMI Bus
PCIE Bus
SATA
SDVO
LVDS
USB
IEEE1394
Lan

55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
42 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%
55 ohm +/- 15%

55 ohm +/- 15%

50 ohm +/- 15%

Component Side, Microstrip signal Layer
Ground Plane
Stripline Layer(High Speed)
Normal Signal / Ground 1 Plane
Power Plane
Stripline Layer(High Speed)
Ground 2 Plane
Solder Side,Microstrip signal Layer

Differential Impedance for Microstrip

95 ohm +/- 15%
95 ohm +/- 15%

70 ohm +/- 20%

95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
95 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%

Differential Impedance for Stripline

100 ohm +/- 15%
100 ohm +/- 15%

70 ohm +/- 20%
85 ohm +/- 20%

100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
100 ohm +/- 15%
90 ohm +/- 15%
110 ohm +/- 15%

A A

Title

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Date: Sheet

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First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

Annotations

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6.Schematic modify Item and History :

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D D

Power Rail

VCC_CORE

1.25VDDM

C C

1.5VDDM

B B

1.8VDDS:

0.9VDDT_DDRII:

Ball Name

VCCP
VTT(VCCP)
VCC
VCC_PEG

VCCR_RX_DMI
VCC_AXM

VCC1_05
VCCSUS1_05
VCCCL1_05
VCCLAN1_05
VCCA_SM
VCCA_SM_CK
VCCA_PEG_PLL
VCCD_PEG_PLL
VCC_DMI
VCCA_HPLL
VCCD_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCC_AXG
VCC_AXF
VCC_DMI

VCCA
VCCD_QDAC
VCCD_TVDAC
VCCD_CRT
VCCD_QDAC
VCC1_5_A
VCC1_5_B
VCCSUS1_5
VCCGLAN1_5
VCCCL1_5
VCCUSBPLL
VCCDMIPLL
VCCSATAPLL
VCCGLANPLL

+1.5V
TBD

VCC_SM
VCC_SM_CK
VCCD_LVDS
VCC_TX_LVDS
VCCA_LVDS

1.8VDDS:

Destination S0 Current

HFM:

Merom

LFM:
Merom: AGTL+ termination
Crestline: AGTL+ termination
Crestline: Core chipset
Crestline: PCI Express Based Graphics
Crestline: Rx and I/O Logic for DMI
Crestline: Controller Link/ME voltage supply
ICH8M: ICH8 Core
ICH8M:
ICH8M:
ICH8M:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
Crestline:
ICH8M:

Merom PLL
Crestline: TV DAC
Crestline: TV DAC
Crestline: CRT
Crestline: CRT
ICH8M: I/O
ICH8M: I/O
ICH8M: Resume well I/O
ICH8M: Integrated Gigabit LAN I/O
ICH8M: Controller Link
ICH8M: USB PLL
ICH8M: DMI PLL
ICH8M: SATA PLL
ICH8M: Integrated Gigabit LAN PLL

Mini Card:
Express Card:

Crestline: I/O Voltage
Crestline: Clock I/O Voltage
Crestline:
Crestline:
Crestline:
SO-DIMM:
DDRII Terminator:

Voltage

1.0375V~?~1.3000V
TBD~TBD

0.9975V~1.05V~1.1025V

0.9975V~1.05V~1.1025V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.425V~1.5V~1.575V

1.7V~1.8V~1.9V

0.855V~0.9V~0.945V

44A
TBD

4.5A1.05VDDM 1.00V~1.05V~1.10V

0.8A

1.3A

130mA

1.5A
60mA
24mA
320mA

3.1A

1.0A

Power Rail

Ball Name

2.5VDDM

3VDDM VCCA_PEG_BG

VCC_HV
VCC_SYNC
VCCA_CRT_DAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_DAC_BG

3VDDS

3VDDA

5VDDM

5VDDS

PMU3V

Need Modify

Destination

945GM: PCIE analog
945GM: LVDS analog
945GM: LVDS I/O
945GM: CRT DAC
CH7307:
Crestline: PCI Express Base Graphics
Crestline: HV buffer power
Crestline: H/VSYNC power
Crestline: CRT DAC
Crestline: TV Out
Crestline: TV Out
Crestline: TV Out
Crestline: TV DAC

ICH7m:
Mini Card:
Express Card:
CLK Generator: ICS954226
KBC: KB3886
Flash ROM: BIOS
Azalia Codec: ALC260
Azalia MDC:
HDD: SATA

Lan: Broadcom BCM4401
Card Reader: SD/MMC/MS
Azalia MDC: For wake up

ICH7m:
ICH7m:
ICH7m:
LCD:

Azalia Codec: ALC260
Azalia MDC:
HDD: SATA
ODD: PATA
Audio AMP: G1420
Inverter:

USB: x 4 ports
EC: PMU08

ICH7m: RTC

Voltage

2.32V~2.5V~2.625V

2.375V~2.5V~2.625V

2.375V~2.5V~2.625V

2.32V~2.5V~2.625V

3.135V~3.3V~3.465V

3.135V~3.3V~3.465V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

3.0V~3.3V~3.6V

3.0V~3.3V~3.6V

3.0V~3.3V~3.6V

4.75V~5.0V~5.25V

4.75V~5.0V~5.25V

5V

S0 Current

2mA
10mA
60mA
70mA

40mA
120mA

400mA

1.0A

Max: 1.0A ; R/W
Max: 1.8A ; R/W: 900mA

2.0A

A A

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

5

4

3

2

Date: Sheet

(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

Schematic Modify

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7. power on & off & S3 Sequence :

S3 SUSPEND AND RESUME TIMING

Power On Sequencing Timing Diagram

D D

C C

B B

A A

20060117A - DATA FROM NO.16809

PSI#

VID

t

SFT_START_VCC

VR_ON

-12%

V

CC-CORE

t

CPU_UP

V

CCP

CPU_UP

Vccp_UP

-12%

V

CC_MCH

MCH_PWRGD

CLK_ENABLE#

IMVP6_PWRGD

t

SFT_START_VCC

t

BOOT

t

BOOT-VID-TR

t

CPU_UP

t

Vccp_UP

t

MCH-PWRGD

t

CPU_PWRGD

5

t

BOOT

-12%

t

Vccp_UP

t

MCH-PWRGD

Max = 3 ms

Min = 10 us , Max = 100 us

Max = 100 us

Min = 10 us , Max = 30 us

Min = 10 us , Max = 30 us

Min = 10 us , Max = 30 us

Min = 3 ms , Max = 20 ms

t

BOOT-VID-TR

t

CPU_PWRGD

4

POWSW0

PMU5V/PMU3V

PM_RSMRST0
PM_SLP_S30

PM_SLP_S40/S50

SUSTAT_B0

PM_PWROK
SYS_PWROK

VRON_VCCP

VCCP,1.2VDDM

VCORE_ON

VCORE_CPU

CK408_PWRGD0
PM_VGATE

CPU_PWRGOOD

PCI_RST0

AGTL+_CPURST0

BATTERY ONLY POWER ON TIMING

PMU5V/PMU3V

MAINSW0_ICH

PM_RSTRST0

PM_SLP_S30/S40/S50

SUSTAT_B0

VDDM,VDDS

SYS_PWROK

VRON_VCCP

VCCP/1.2VDDM

VCORE_ON

VCORE_CPU

CK408_PWRGD0

PM_VGATE

CPU_PWRGD

PCI_RST0

AGTL+_CPURST0

DCON
VDDA

PSUSC0

VDDS
VDDM

VR_ON

POWSW0

DCON

VDDA

PSUSC0

PM_PWROK

VR_ON

H
H
H
H

H
H

H

3

To ICH4_M
From ICH4_M

From ICH4_M
From ASIC_B0
From ASIC_B0

1.5VDDS AND
DDR_PWRGD

To clock

Generator

ToICH4 and ODEM

From ICH4 to CPU

To ODEM/other
PCI device

From ODEM to CPU

To ICH4

To ICH4

From ICH4

From ASIC_B0
From ASIC_B0

To clock generator
To ODEM and ICH4

From ICH4 to CPU

To ODEM/other PCI device

From ODEM to CPU

IMVP6 Power On Sequencing Timing Diagram

VID
VR_ON
Vcc-core
CPU_UP
Vccp
Vccp_UP
Vccgmch
GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD

2

Tsft_star_vcc(3ms max)

Tboot

Tcpu_up

Tvccp_up

Tgmch_pwrgd

Title

Size Document Number Rev

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Date: Sheet

Vid

Vboot
Tboot-vid-tr(100uS max)

Tboot:10-100uS

Tcpu_pwrgd(3~20mS)

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

Timing Diagram

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Crestline DDRII Layout Guidelines

DDRII Signal Groups

Group Signal Name

D D

Data

SA_DQ[63..0]/SB_DQ[63..0]
SA_DM[7..0]/SB_DM[7..0]
SA_DQS[7..0]/SA_DQS#[7..0]
SB_DQS[7..0]/SB_DQS#[7..0]

SA_MA[13..0]/SB_MA[13..0]Address
SA_BS[2..0]/SB_BS[2..0]
SA_RAS#/SB_RAS#
SA_CAS#/SB_CAS#
SA_WE#/SB_WE#

SM_CS#[3..0]Control
SM_CKE[3..0]
SM_ODT[3..0]

Clock SM_CK[3..0]

SM_CK#[3..0]
SA_RCVENOUT#/SB_RCVENOUT#FeedBack

SA_RCVENIN#/SB_RCVENIN#

CLK group : SM_CK[3..0],SM_CK#[3..0]

4/4

GMCH

P1P1L0

C C

Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width

Nominal CK to CK# Spacing
(edge to edge)
Minimum Serpentine Spacing Inner Layer : 12 mils

Minimum Spacing to Other DDR2 Inner Layer : 16 mils

Minimum Isolation Spacing to non-DDR2 25 mils
Package Length Range - P1 1000 mils +/- 250 mils
Trace Length Limit - L0 Max = 50 mils (Escape)
Trace Length Limit - L1 Max = 500 mils (Breakout)
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils

B B

Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5 mils
Clock to Clock Length Match

(Total Length)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)

Feedback group :
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#

These signals are routed internally on the GMCH package and don't require any
routing on the MB. As a result, can be left as NC.

A A

4/4/12 7/4/16 8/5/15

L2L2S1

L0L1L1

Escape Breakout Breakin

SLMS SL MS

5

Length Matching and Length Formulas

Signal Group Minimum Length Maximum Length

Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe

Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Strobe - 220mils

SO-DIMM

S1

Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%
Inner Layer : 7 mils

Outer Layer : 8 mils
Inner Layer : 4 mils

Outer Layer : 5 mils

Outer Layer : 15 mils

Outer Layer : 20 mils

Max = 4000 mils
Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1
Total Length for Channel A : X0

Total Length for Channel B : X1

Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils

Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2

Max. breakout length is 500 mils
CK to CK# spacing rule waived at

connector spacing of 15 mils to
other DDR2

Max. breakin length is 200 mils

Clock - 0.0"
Clock + 1.0"
Clock + 1.0"
Strobe - 180mils

4

Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]

GMCH

Escape

P1

L0

MS SL/MS

4/4/12

L1

Breakout
SL

7/4/16

L2

8/5/15

L3

SL/MS

S1

MS

Vtt

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum CTRL Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad

Parallel Termination Resistor 56 +/- 5%
Maximim Via Count
CTRL to SCK/SCK# Length Matching

(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Command group :
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#

GMCH

P1

Escape

L0

4/4

Breakout

Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 8 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 200 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 milsTrace Length L3

3
(CLK-1.0") </= CTRL </= (CLK-0.0")

Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

4/6,5/10

4/6,5/10

L1

L3

L2

SL/MS

SL/MSMS SL

S1

MS

Vtt

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum CMD Bus Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Trace Length L3

Parallel Termination Resistor
Maximim Via Count
CTRL to SCK/SCK# Length Matching

(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Point-to-Point with parallel termination
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 6 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 mils
56 +/- 5%
3
(CLK-1.0") </= CMD </= (CLK+1.0")

Inner Layer : 4 mils spacing allowed
Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

3

Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]

4/4

L1

Breakout

4/6

L2

S1

GMCH

Escape

P1 L0

MS SLSL MS

SO-DIMM

Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width

Minimum DQ Bus Trace Spacing

Minimum Serpentine Spacing Same as DQ-to-DQ routing
Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Trace Length L3

Maximim Via Count
DQ/DM to DQS Length Matching

(Total Length including
package)

Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Point-to-Point
Ground
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 6 mils

Outer Layer : 8 mils

Inner Layer : 12 mils
Outer Layer : 15 mils

25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

Max = 1500 mils
2
Match DQ/DM to [SDQS - 200mils]

+/- 20mils, per byte lane
Inner Layer : 4 mils spacing allowed

Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils

Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#

SO-DIMM

5/5/10

4/4/12

GMCH

P1
P1

Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Nominal Trace Width

Nominal DQS to DQS# Spacing
(edge to edge)

Minimum Serpentine Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2
Package Length Range - P1
Trace Length Limit - L0
Trace Length Limit - L1
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 + L1 + L2 + S1 -

From GMCH ball to SO-DIMM pad
Total Length - P1 + L0 + L1 + L2 + S1 ­From GMCH die to SO-DIMM pad
Maximim Via Count

DQS to DQS# Length Matching
Clock to Clock Length Match

(Total Length include package)
Breakout Exceptions (Reduce geometries
for GMCH break-out region)

Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)

Escape

L0
L0

4/4/8

L2

L1

L2

L1

Breakout
SL SL MS

Differential Pair Point-to-Point
Ground
55 +/- 15%
85 +/- 20%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacing

Outer Layer : 15 mils
Inner Layer : 8 mils

Outer Layer : 10 mils
Inner Layer : 12 mils

Outer Layer : 15 mils
25 mils
750 mils +/- 350 mils
Max = 50 mils (Escape)
Max = 500 mils (Breakout)
Max = 200 mils (Breakin)
Min = 500 mils

Max = 4500 mils
Max = 5000 mils

2 (Per side)
Match total length to within 5 mils
(CLK-0.5") </= DQS </= (CLK+1.0")

Inner Layer : 8 mils to other DDR2
Outer Layer : 10 mils to other DDR2
Max. breakout length is 500 mils

DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2

Max. breakin length is 200 mils

2

S1
S1

Breakin

Title

Size Document Number Rev

C

Date: Sheet

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751

MR030>Merom+Crestline GM965+ICH8M

DDRII Layout Guideline

1

758Wednesday, October 17, 2007

0.6

of

A

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14

H_A#[35..3]

H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

4 4

3 3

H_A#[35..3]11

H_ADSTB#011

H_REQ#[4..0]11

H_A#[35..3]11

H_ADSTB#111

H_IGNNE#21

H_STPCLK#21

H_A#[35..3]

H_REQ#[4..0]

H_A20M#21

H_FERR#21

H_INTR21

H_NMI21

H_SMI#21

U9A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ICH

THERMTRIP#

Rout to TP via and place gnd via w/in 100mils

A#[32-39], APM#[0-1]:Leave escape routing on for future functionality

H_D#[63..0]11

2 2

H_DSTBN#011

H_DSTBP#011

H_DINV#011

H_D#[63..0]11

Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.

Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals

R513 1KΩ 1% 1/16W SMT0402 LR

1.05VDDM

1 1

2KΩ 1% 1/16W SMT0402 LR

A

R514

H_DSTBN#111

H_DSTBP#111

H_DINV#111

12

H_D#[63..0]

H_D#[63..0]

R499 1KΩ 5% 1/16W SMT0402 LR(NU)
R511 1KΩ 5% 1/16W SMT0402 LR(NU)

C600

0.1uF 10V 10% SMT0402 X5R LR(NU)

Place C181 close to the CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference to GND

and away from other nossy signale.

CPU_BSEL017
CPU_BSEL117

H_GTLREF

TEST3

TEST5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

AD26

AF26

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

B22
B23
C21

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#
TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

RESERVED

U9B

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

Merom Ball-out Rev 1a

B

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

DATA GRP 0

DATA GRP 1

B

H_IERR#

R510 56Ω 5% 1/16W SMT0402 LR

XDP_BPM#5
XDP_TCK
XDP_TDI

XDP_TMS
XDP_TRST#
XDP_DBRESET#

Y22

D[32]#

AB24

D[33]#

V24

D[34]#

V26

D[35]#

V23

D[36]#

T22

D[37]#

U25

D[38]#

U23

D[39]#

Y25

D[40]#

W22

D[41]#

Y23

D[42]#

W24

D[43]#

W25

D[44]#

AA23

D[45]#

AA24

D[46]#

DATA GRP 2DATA GRP 3

AB25

D[47]#

Y26

DSTBN[2]#

AA26

DSTBP[2]#

U22

DINV[2]#

AE24

D[48]#

AD24

D[49]#

AA21

D[50]#

AB22

D[51]#

AB21

D[52]#

AC26

D[53]#

AD20

D[54]#

AE22

D[55]#

AF23

D[56]#

AC25

D[57]#

AE21

D[58]#

AD21

D[59]#

AC22

D[60]#

AD23

D[61]#

AF22

D[62]#

AC23

D[63]#

AE25

DSTBN[3]#

AF24

DSTBP[3]#

AC20

DINV[3]#

R26

COMP[0]

U26

COMP[1]

AA1

COMP[2]

Y1

COMP[3]

E5

DPRSTP#

B5

DPSLP#

D24

DPWR#

D6

PWRGOOD

D7

SLP#

AE6

PSI#

C

H_ADS# 11
H_BNR# 11
H_BPRI# 11

H_DEFER# 11
H_DRDY# 11
H_DBSY# 11

H_BREQ# 11

H_INIT# 21

H_LOCK# 11

H_CPURST# 11
H_RS#0 11
H_RS#1 11
H_RS#2 11
H_TRDY# 11

H_HIT# 11
H_HITM# 11

1.05VDDM

1.05VDDM

R509
75Ω 1% 1/16W SMT0402 LR

0'' ~ 3''

H_THERMDA 10
H_THERMDC 10 HOT_DOWN# 10,46

PM_THRMTRIP# 12,21

CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17

R508 0Ω 5% 1/16W SMT0402 LR(NU)

Should be connect to ICH8M and Crestline without T-ing(no stub)

XDP P/U & P/D

XDP_DBRESET#

XDP_TMS
XDP_TDI
XDP_BPM#5

XDP_TCK

XDP_TRST#

H_D#[63..0]

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#[63..0]

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0

R515 27.4Ω 1% 1/16W SMT0402 LR

COMP1

R507 54.9Ω 1% 1/16W SMT0402 LR Sn

COMP2

R436 27.4Ω 1% 1/16W SMT0402 LR

COMP3

R435 54.9Ω 1% 1/16W SMT0402 LR Sn

H_DPRSTP# 12,21,47
H_DPSLP# 21
H_DPWR# 11
H_PWRGD 21
H_CPUSLP# 11
PSI# 47CPU_BSEL217

H_PWRGD rise time :
Max : 15ns

R505 1KΩ 5% 1/16W SMT0402 LR(NU)

R442 RES 39Ω 1% 1/16W SMT0402 LR
R440 150Ω 5% 1/16W SMT0402 LR
R441 54.9Ω 1% 1/16W SMT0402 LR Sn(NU)

R443 RES 27Ω 5% 1/16W SMT0402 LR

R437 649Ω 1% 1/10W SMT0603 LR

H_D#[63..0] 11

H_DSTBN#2 11
H_DSTBP#2 11
H_DINV#2 11
H_D#[63..0] 11

Comp0,2 connect with Zo=27.4ohm, make trace
length shorter than 0.5" and width is 18mils.

Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils

H_DSTBN#3 11
H_DSTBP#3 11
H_DINV#3 11

C

H_PROCHOT# 47

D

Topology : FERR#

VCCP

Rtt

L4

VCCP=1.05VDDM

ICH8MCPU

CPU IMVP6

VCCP L1

Rtt

L2

0.5" - 12"L1

VCCP

Rtt

L2+L1 L3 Strip-line

0.5" - 6.5"

Topology : PWRGOOD

ICH8M

L1

Transmission Line
Micro-strip

0.5" - 12"

0.5" - 12" Strip-line

CPU

L1

Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#

Transmission Line

L1CPU ICH8M

L1

Topology : THERMTRIP#

GMCHL2CPU ICH7m

0.5" - 12" Micro-strip
Strip-line

0.5" - 12"

VCCP

L3

RttL1 L4

3VDDM

1.05VDDM

FSB Common Clock Signal Layout Guide :

ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
RS[2..0]# , TRDY# , RESET#.

Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)

Strip-line(Int. Layer)
Micro-strip(Ext. Layer)

FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :

Signals Name

DATA#[15..0] , DINV0#
DATA#[31..16] , DINV1# +/- 100 mils
DATA#[47..32] , DINV2#
DATA#[63..48] , DINV3#

FSB Source Synchronous Data Signal Routing Topology#1 :

Signal Name

DINV#[3..0]
DATA#[63..0]
DSTBN#[3..0]
DSTBP#[3..0]

FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :

A#[16..3] , REQ#[4..0]

1.0 ~ 6.5 inch 55+/-15%

Signals Matching

+/- 100 mils
+/- 100 mils

Transmission Line Type

Strip-line
Strip-line
Strip-line
Strip-line

Signals MatchingSignals Name

+/- 200 mils

Total Trace Length

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

0.5 ~ 5.5 inch

*** No length matching requirements exist between ADSTB0# and ADSTB1#

FSB Source Synchronous Address Signal Routing :

Signal Name

Address#[31..3]
REQ#[4..0]
ADSTB#[1..0]

Transmission Line Type

Strip-line
Strip-line

D

Total Trace Length Normal Impedance

0.5 ~ 6.5 inch

0.5 ~ 6.5 inch

0.5 ~ 6.5 inch

E

Rtt Transmission Line

L2
0" - 3.0" Microstrip0.5" - 12"

56 +/-5%
56 +/-5%

L3 L4
0" - 3.0"
0" - 3.0"

Stripline

0" - 3.0"
0" - 3.0"

Rtt Transmission LineL2L1

Micro-strip75 +/-5%

75 +/-5%0.5" - 6.5"

0" - 3.0"

0.5" - 6.5"

0.5" - 6.5"

Topology : CPUSLP#

L1CPU

GMCH

L1

0.5" - 12"

0.5" - 12"

Transmission Line
Micro-strip
Strip-line

Topology : RESET#

Transmission LineCPU

GMCH

L1

L1 L2
1" - 12"

Rtt

1" - 12" 1" - 6"

Strobes associated with the group Strobe-to-Strobe Complement Matching

DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#

Strobes associated with the group

ADSTB0#+/- 200 mils
ADSTB1#A#[31..17]

L1+L3

1" - 6" 0" - 3.0"

Processor ITP Signal Default Strapping When ITP-XDP &
ITP700FLEX Dedbug Port Not Used.

Signal Resistor Value
TDI
TMS
TRST#
TCK
TDO

1.05VDDM9,11,14,15,17,21,23,52

3VDDM10,12,15,17,18,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

L3
0" - 3.0"

1" - 12"
1" - 12"

0" - 3.0"

54.9 OHM +/-5%

54.9 OHM +/-5%
649 OHM +/-5%

54.9 OHM +/-5%
OPEN

4 & 8 mils
5 & 10 mils

Normal Impedance

55+/-15%
55+/-15%
55+/-15%
55+/-15%

55+/-15%
55+/-15%
55+/-15%Strip-line

1.05VDDM

3VDDM

+/- 25 mils+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils

Width & Spacing (mils)
Data-to-Data,Strobe-to-strobe Strobe-to-Data

4 & 8 mils
4 & 8 mils
4 & 12 mils
4 & 12 mils

Strobe to Assoc. Address Signal Matching

+/- 200 mils
+/- 200 mils

Width & Spacing (mils)

4 & 8 mils
4 & 8 mils
4 & 8 mils

Title

MR030>Merom+Crestline GM965+ICH8M

Size Document Number Rev

C

Date: Sheet

L1

Micro-strip

1" - 6"

Strip-line

1" - 6"

Rss

Rtt
24 +/-5%
24 +/-5%

Connect To Resistor Placement

VCCP
VCCP
GND
GND
NC

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

Transmission LineL4

56 +/-5%

Micro-strip
Strip-line0" - 3.0"

56 +/-5%

Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
N/A

Merom Processor (1/2)

E

N/A
N/A
4 & 12 mils
4 & 12 mils

Confidential

858Wednesday, October 17, 2007

of

0.6

A

B

C

D

E

Place these inside socket cavity on L8
(North side secondary)

VCORE_CPU

4 4

HFM
ICC=41A

3 3

2 2

C223 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C590 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C543 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C219 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

Place these inside socket cavity on L1
(North side Primary)

C574 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C581 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C577 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C561 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

North side secondary

1 1

C203 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C209 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C213 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C553 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C565 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C545 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C206 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C231 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

South side secondary

Place these inside socket cavity on
L8 (South side secondary)

C588 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C222 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

Place these inside socket cavity on L1
(South side Primary)

C552 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C205 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C198 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C202 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C208 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C218 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C212 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C576 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C560 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C580 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C571 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C591 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C544 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C564 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

U9C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

C586 0.1uF 16V ±10% SMD0603 X7R LR

C573 0.1uF 16V ±10% SMD0603 X7R LR

H_VID0 47
H_VID1 47
H_VID2 47
H_VID3 47
H_VID4 47
H_VID5 47
H_VID6 47

C572 0.1uF 16V ±10% SMD0603 X7R LR

C585 0.1uF 16V ±10% SMD0603 X7R LR

C546 0.1uF 16V ±10% SMD0603 X7R LR

VCORE_CPU

1.05VDDM

C547 0.1uF 16V ±10% SMD0603 X7R LR

+

R492
100Ω 1% 1/16W SMT0402 LR

R491
100Ω 1% 1/16W SMT0402 LR

ICCP=4.5A,180mils

C609

220uF 2V ±20% 15mΩ 7343 PANA LR

Place these inside socket cavity on L8
(North side secondary)

1.5VDDM

ICCA=130mA, 20mils

C604 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR

C599

0.01uF 16V 10% SMT0402 X7R LR

Place C?
Close To pin
B26

TDK

VCCSENSE 47

VSSSENSE 47

U9D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VCORE_CPU47

VCORE_CPU

1.05VDDM

1.05VDDM8,11,14,15,17,21,23,52

1.5VDDM

1.5VDDM14,15,20,21,23,34,43,44,52

Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50mil spacing.
Place PU and PD within 1 inch of CPU

A

B

C

D

Title

Size Document Number Rev

C

Date: Sheet

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

Confidential

MR030>Merom+Crestline GM965+ICH8M

Merom Processor (2/2)

E

958Wednesday, October 17, 2007

0.6

of

8

D D

7

THERMAL SENSOR

6

5

4

1000pF 50V 10% SMT0402 X7R LR(NU)

5VDDM

C140

FAN_PWM46

3

Q16

TRANS M-FET-P APM2301AAC-TRL -20V -3A SOT23 3PIN ANPEC LR

DS

G

R116

1KΩ 5% 1/16W SMT0402 LR

R114

0Ω 5% 1/16W SMT0402 LR

Q17

B

NPN PDTC144EU SOT-323 PHILIPS LR

E C

2

1

30mil

5VDDM

D9

10 mil
10 mil

FAN1

C743

MO-CAP 1000pF 16V 10% SMT0402 X7R LR

P N

10 mil
Minimum
10 mil

FAN_SPEED46

DIODE ZENER GLZ6.2B 6.2V 20mA MINI-MELF 2PIN PSI LR (NU)

QSMCLK_PMU

QSMDAT_PMU

RP54

3VDDM

4

3

1

2

10mil
10mil

U30

8

SCLK

7

SDATA

6

ALRT#

5

GND

LNR-IC Temperature Sensor G784P81U 3.0-5.5V MSOP-8 8PIN GMT LR

THM#

1

VCC

2

D+

3

D-

4

20mil

THRM_VCC

C602
2200pF 50V 10% SMT0402 X7R LR

R535

10KΩ 5% 1/16W SMT0402 LR

R528
100Ω 5% 1/16W SMT0402 LR

C610

0.1uF 16V 80-20% SMT0402 Y5V LR

H_THERMDA

H_THERMDA 8

H_THERMDC

H_THERMDC 8

3VDDA

C C

10KΩ 5% SMT1010 1/16W 4P2R LR(NU)

CN10

1

4

1

4

2

2

3

5

3

C744

GND
THERMDA
THERMDC
GND

5

CON HR A1250WV-S-03P SMD 3Pin P=1.25 Wire S/T LR

20-24197-30

MO-CAP 1000pF 16V 10% SMT0402 X7R LR

Close to switch buttom

B B

3VDDM

C750

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

U46

SMB_DAT_THERM217,18,19,22,34,44

SMB_CLK_THERM217,18,19,22,34,44

5VDDM

1/29 EMI

SMCLK_PMU46,49

C125

0.1uF 16V 80-20% SMT0603 Y5V LR

SMDAT_PMU46,49

8

R93

2.2KΩ 5% 1/16W SMT0402 LR(NU)

A A

OT_ENV46

R693

0Ω 5% 1/16W SMT0402 LR

Q13

D S

G

G

D S

R694

0Ω 5% 1/16W SMT0402 LR

QSMCLK_PMU

TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR(NU)

Q15

QSMDAT_PMU

TRANS M-FET-N 2N7002 60V 115mA SOT-23 3PIN PSI LR(NU)

1

SMBDATA

2

SMBCLK

3

O.S.

4

GND

LNR-IC Temperature Sensor G752P82U 3.0-5.5V MSOP-8 8PIN GMT LR(NU)

7

8

+Vs

7

A0

6

A1

5

A2

SMB_DAT_THERM117,18,19,22,34,44

SMB_CLK_THERM117,18,19,22,34,44

PM_EXTTS#012,18

8/6 modify

6

Close to bottom side DDR socket

R691

0Ω 5% 1/16W SMT0402 LR

5

HOT_DOWN#

HOT_DOWN#8,46

3VDDM

C749

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

U45

1

SMBDATA

2

SMBCLK

3

O.S.

4

GND

LNR-IC Temperature Sensor G752P82U 3.0-5.5V MSOP-8 8PIN GMT LR(NU)

8

+Vs

7

A0

6

A1

5

A2

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

4

3

Date: Sheet

2

(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

CPU Thermal

3VDDM

3VDDM8,12,15,17,18,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

3VDDA

3VDDA20,21,22,23,24,26,27,30,31,34,36,37,43,44,46,49,51,52,53

5VDDM

5VDDM23,29,30,31,32,38,41,42,51

Confidential

10 58Wednesday, October 17, 2007

of

1

0.6

10

9

8

7

6

5

4

3

2

1

NB 965PM：05-23767-01 (REV. B0)

：

NB 965GM

H H

05-23768-01 (REV. B0)

G G

H_D#[63..0]8

1.05VDDM

R140
RES 221Ω 1% 1/16W SMT0402 LR

H_SWING

F F

R139
100Ω 1% 1/16W SMT0402 LR

H_RCOMP

R141
RES 24.9Ω 1% 1/16W SMT0402 LR

C217

0.1uF 10V 10% SMT0402 X5R LR

E E

1.05VDDM

R142

54.9Ω 1% 1/16W SMT0402 LR Sn

H_SCOMP

D D

C C

1.05VDDM

R143

54.9Ω 1% 1/16W SMT0402 LR Sn

H_SCOMP#

H_CPURST#8
H_CPUSLP#8

H_D#[63..0]

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1.05VDDM

AD12

AC14
AD11
AC11

AJ14

AE11
AH12

AH13

E2
G2
G7

M6

H7
H3
G4
F3
N8

H2
M10
N12

N9

H5
P13

K9

M2

W10

Y8

V4

M3

J1

N5

N3

W6
W9

N2

Y7

Y9

P4

W3

N1

AE3

AD9
AC9
AC7

AB2

AD7

AB1

Y3

AC6

AE2

AC5
AG3

AJ9

AH8

AE9

AJ5

AH5

AJ6
AE7
AJ7
AJ2
AE5
AJ3

AH2

B3

C2

W1
W2

B6

E5

B9

A9

U8A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

HOST

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_ADSTB#_0
H_ADSTB#_1

H_BNR#
H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#[35..3]

H_REQ#[4..0]

H_A#[35..3] 8

H_ADS# 8
H_ADSTB#0 8
H_ADSTB#1 8
H_BNR# 8

H_BPRI# 8

H_BREQ# 8

H_DEFER# 8

H_DBSY# 8

H_DPWR# 8
H_DRDY# 8
H_HIT# 8

H_HITM# 8
H_LOCK# 8
H_TRDY# 8

H_DINV#0 8

H_DINV#1 8

H_DINV#2 8

H_DINV#3 8

H_DSTBN#0 8

H_DSTBN#1 8

H_DSTBN#2 8

H_DSTBN#3 8

H_DSTBP#0 8

H_DSTBP#1 8

H_DSTBP#2 8

H_DSTBP#3 8

H_REQ#[4..0] 8

H_RS#0 8
H_RS#1 8
H_RS#2 8

CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17

R130
1KΩ 1% 1/16W SMT0402 LR

12

B B

R135
SPWR 0 5% 1/16W 0402

R131
2KΩ 1% 1/16W SMT0402 LR

C207

0.1uF 10V 10% SMT0402 X5R LR

A A

10

9

8

7

H_AVREF

H_DVREF

1.05VDDM

1.05VDDM8,9,14,15,17,21,23,52

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

6

5

4

3

Date: Sheet

(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

Crestline Host (1/6)

2

Confidential

11 58Wednesday, October 17, 2007

of

1

0.6

10

1.8VDDS

H H

SM_RCOMP_VOH

SM_RCOMP_VOL

C192

2.2uF 6.3V 80-20% SMT0603 Y5V LR

C185

2.2uF 6.3V 80-20% SMT0603 Y5V LR

C190

0.01uF 16V 10% SMT0402 X7R LR

C186

0.01uF 16V 10% SMT0402 X7R LR

G G

F F

E E

PM_BMBUSY#22 DFGT_VID_1 54

D D

H_DPRSTP#8,21,47
PM_EXTTS#010,18
PM_EXTTS#119

DELAY_VR_PWRGOOD24,47

PLT_RST#20,28
PM_THRMTRIP#8,21
PM_DPRSLPVR22,47,54

C C

9

R125
1KΩ 1% 1/16W SMT0402 LR

R124

3.01K 1% 1/10W 0603 LR

R123
1KΩ 1% 1/16W SMT0402 LR

M_A_A1418
M_B_A1419

MCH_BSEL017
MCH_BSEL117
MCH_BSEL217

R487
100Ω 5% 1/16W SMT0402 LR

MCH_CFG_5

MCH_CFG_9

MCH_CFG_12
MCH_CFG_13

MCH_CFG_16

MCH_CFG_19
MCH_CFG_20

PM_EXTTS#0
PM_EXTTS#1

RST_IN#_MCH

P36
P37
R35

N35
AR12
AR13

AM12

AN13

J12

AR37

AM36

AL36

AM37

D20

H10

B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23

BG23

BC23
BD24
BJ29
BE24
BH39

AW20

BK20

C48

D47

B44

C44

A35

B37

B36

B34

C34

P27
N27
N24
C21
C23
F23
N23

G23

J20
C20
R24

L23

J23
E23
E20
K23
M20
M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20
G36

BJ51
BK51
BK50
BL50
BL49

BL3
BL2
BK1
BJ1

E1

A5
C51
B50
A50
A49
BK2

CRESTLINE_1p0

U8B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

8

CFGRSVD

PM

NC

7

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

BL15

SM_RCOMP

BK14

SM_RCOMP#

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

BK31
BL31

AR49
AW4

20miles

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

0.1uF 10V 10% SMT0402 X5R LR

H35
K36
G39
G40

A37
R32

SM_RCOMP_VOH
SM_RCOMP_VOL

DDR MUXINGCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GRAPHICS VID

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

M_CLK_DDR0 18
M_CLK_DDR1 18
M_CLK_DDR3 19
M_CLK_DDR4 19

M_CLK_DDR#0 18
M_CLK_DDR#1 18
M_CLK_DDR#3 19
M_CLK_DDR#4 19

M_CKE0 18
M_CKE1 18
M_CKE3 19
M_CKE4 19

M_CS#0 18
M_CS#1 18
M_CS#2 19
M_CS#3 19

M_ODT0 18
M_ODT1 18
M_ODT2 19

SM_RCOMP
SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

R495 10KΩ 1% 1/16W SMT0402 LR(NU)
R493 0Ω 5% 1/16W SMT0402 LR
R494 10KΩ 1% 1/16W SMT0402 LR(NU)

DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0

DMI_TXN3
DMI_TXN2
DMI_TXN1
DMI_TXN0

DMI_RXP3
DMI_RXP2
DMI_RXP1
DMI_RXP0

DMI_RXN3
DMI_RXN2
DMI_RXN1
DMI_RXN0

DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3

SDVO_CTRL_CLK
SDVO_CTRL_DATA

CLK_MCH_OE#

R122 0Ω 5% 1/16W SMT0402 LR
R430 20KΩ 1% 1/16W SMT0402 LR

M_ODT3 19

R128 RES 20Ω 1% 1/16W SMT0402 LR
R129 RES 20Ω 1% 1/16W SMT0402 LR

DREFCLK 17
DREFCLK# 17
DREFSSCLK 17
DREFSSCLK# 17

CLK_PCIE_3GPLL 17
CLK_PCIE_3GPLL# 17

DMI_TXP3 20
DMI_TXP2 20
DMI_TXP1 20
DMI_TXP0 20

DMI_TXN3 20
DMI_TXN2 20
DMI_TXN1 20
DMI_TXN0 20

DMI_RXP3 20
DMI_RXP2 20
DMI_RXP1 20
DMI_RXP0 20

DMI_RXN3 20
DMI_RXN2 20
DMI_RXN1 20
DMI_RXN0 20

DFGT_VID_0 54

DFGT_VID_2 54
DFGT_VID_3 54
DFGT_VR_EN 54

CL_CLK0 22
CL_DATA0 22

MPWROK 22,24,46

CL_RST#0 22

C149

SDVO_CTRL_CLK 28

SDVO_CTRL_DATA 28
CLK_MCH_OE# 17
MCH_ICH_SYNC# 22

6

R? , R?

For Crestline

1.8VDDS

1.25VDDM

1KΩ 1% 1/16W SMT0402 LR

CL_REFCL_REF

1.8VDDS
M_VREF

R107

80.6 ohmFor Calero
20 ohm

LCD_BRIGHTNESS27,46

LVDS_ENABKL46

3VDDM

R451 2.2KΩ 5% 1/16W SMT0402 LR
R461 2.2KΩ 5% 1/16W SMT0402 LR

0801 modify

R111
RES 392Ω 1% 1/16W SMT0402 LR

5

R413 0Ω 5% 1/16W SMT0402 LR(NU)

R421 SHW 0 5% 1/16W 0402

LVDS_DDC_CLK27

LVDS_DDC_DATA27

LVDS_ENALCD27

R404

RES 2.4KΩ 1% 1/16W SMT0402 LR

LVDS_TXCLK_LN27
LVDS_TXCLK_LP27

LVDS_TXOUT_L0N27
LVDS_TXOUT_L1N27
LVDS_TXOUT_L2N27

LVDS_TXOUT_L0P27
LVDS_TXOUT_L1P27
LVDS_TXOUT_L2P27

R483 75Ω 1% 1/16W SMT0402 LR
R482 75Ω 1% 1/16W SMT0402 LR
R481 75Ω 1% 1/16W SMT0402 LR

0Ω 5% SMT1010 1/16W 4P2R LR

RP60

124

R475 75Ω 1% 1/16W SMT0402 LR

R439 75Ω 1% 1/16W SMT0402 LR

R476 75Ω 1% 1/16W SMT0402 LR

R715 0Ω 5% 1/16W SMT0402 LR(NU)

R716 0Ω 5% 1/16W SMT0402 LR(NU)

3

TV_DCONSEL0
TV_DCONSEL1

Q_VECLK
Q_VEDAT

4

3

2

1

1.25VDDM_PEG

R412
RES 24.9Ω 1% 1/16W SMT0402 LR

U8C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

R422100KΩ 5% 1/16W SMT0402 LR

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0
R438
RES 1.3KΩ 1% 1/16W SMT0402 RR0510S-132-FN CYNTEC LR

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1

TV VGA

PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PEG_COMP

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

C455 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

N45

C457 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

U39

C459 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

U47

C461 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

C454 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

M45

C456 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

T38

C458 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

T46

C460 MO-CAP 0.1UF 16V 10% SMT0402 X7R LR

N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

SDVOB_INTN 28

SDVOB_INTP 28

SDVOB_REDN 28
SDVOB_GREENN 28
SDVOB_BLUEN 28
SDVOB_CLKN 28

SDVOB_REDP 28
SDVOB_GREENP 28
SDVOB_BLUEP 28
SDVOB_CLKP 28

3VDDM

TV_DCONSEL0

R432 2.2KΩ 5% 1/16W SMT0402 LR(NU)

TV_DCONSEL1

R427 2.2KΩ 5% 1/16W SMT0402 LR(NU)

PM_EXTTS#0
PM_EXTTS#1

CLK_MCH_OE#

RP50

3

124

10KΩ 5% SMT1010 1/16W 4P2R LR

R423 10KΩ 5% 1/16W SMT0402 LR

B B

1.25VDDM_PEG15

GMCH Strapping Requirements

3VDDM

MCH_CFG_19
MCH_CFG_20

MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13

A A

MCH_CFG_16

R429 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R428 4.02KΩ 1% 1/10W SMT0603 LR(NU)

R490 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R486 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R489 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R480 4.02KΩ 1% 1/10W SMT0603 LR(NU)
R488 4.02KΩ 1% 1/10W SMT0603 LR(NU)

CFG [2:0]

CFG5

CFG9

CFG [12:13]

10

9

8

011 = 667 MT/s ( 677MHz ) FSB
001 = 533 MT/s ( 533MHz ) FSB
0 = DMI * 2
1 = DMI * 4 ( Default )
0 = Lane Reverse
1 = Normal Operation ( Default )
00 = Clock Gating Disable
01 = XOR Mode Enabled
10 = All Z Mode Enable
11 = Normal Operation ( Default )

7

(PCIE)

CFG16

CFG18

CFG19

CFG20

0 = Dynamic ODT Disabled
1 = DMI Lane Reversal Enabled ( Default )

0 = VCC->1.05V ( Default )
1 = VCC->1.5V

0 = Normal ( Default )

1 = Lanes Reversed
0 = Only SDVO or PCIE X1 is operationl ( default )
1 = SDVO or PCIE X1 are operatingsimulaneously via the PEG port.

6

5

(DMI lane)

4

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

3

Date: Sheet

(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

Crestline DMI/Graphic (2/6)

2

M_VREF18,19,53

1.25VDDM15,17,23,55

1.8VDDS14,15,18,19,53,55

3VDDM8,10,15,17,18,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

5VDDM10,23,29,30,31,32,38,41,42,51

Confidential

12 58Wednesday, October 17, 2007

1.25VDDM_PEG

M_VREF

1.25VDDM

1.8VDDS

3VDDM

5VDDM

of

1

0.6

10

9

8

7

6

5

4

3

2

1

H H

G G

M_A_DQ[63..0]18 M_B_DQ[63..0]19

F F

E E

D D

M_A_DQ[63..0]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AW44

AW47

AW43

AW40

AW36
AW41

AW11

AR43

BA45
AY46
AR41
AR45
AT42

BB45
BF48
BG47

BB47
BG50
BH49
BE45

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AT39

AY41
AV38
AT38
AV13
AT13

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AN10

AN11

BJ45

BD8
AY9

AW9

BD7
BB9
BB5
AY7

AT5

AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8

AT9
AN9
AM9

U8D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

M_A_DM0M_A_DM0
M_A_DM1M_A_DM1
M_A_DM2M_A_DM2
M_A_DM3M_A_DM3
M_A_DM4M_A_DM4
M_A_DM5M_A_DM5
M_A_DM6M_A_DM6
M_A_DM7M_A_DM7

M_A_DQS0M_A_DQS0
M_A_DQS1M_A_DQS1
M_A_DQS2M_A_DQS2
M_A_DQS3M_A_DQS3
M_A_DQS4M_A_DQS4
M_A_DQS5
M_A_DQS6M_A_DQS6
M_A_DQS7M_A_DQS7
M_A_DQS#0M_A_DQS#0
M_A_DQS#1M_A_DQS#1
M_A_DQS#2M_A_DQS#2
M_A_DQS#3M_A_DQS#3
M_A_DQS#4M_A_DQS#4
M_A_DQS#5M_A_DQS#5
M_A_DQS#6M_A_DQS#6
M_A_DQS#7M_A_DQS#7

M_A_A0M_A_A0
M_A_A1M_A_A1
M_A_A2M_A_A2
M_A_A3
M_A_A4
M_A_A5M_A_A5
M_A_A6M_A_A6
M_A_A7
M_A_A8M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[13..0]

M_A_BS0 18
M_A_BS1 18
M_A_BS2 18
M_A_CAS# 18

M_A_DM[7..0] 18

M_A_DQS[7..0] 18 M_B_DQS[7..0] 19

M_A_DQS#[7..0] 18

M_A_RAS# 18

M_A_WE# 18

M_B_DQ[63..0]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AW50
AW51

AP49
AR51

AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10

BK10

BL9

BK5

BL5

BK9

BJ8

BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

U8E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[13..0]

M_B_BS0 19
M_B_BS1 19
M_B_BS2 19
M_B_CAS# 19

M_B_DM[7..0] 19

M_B_DQS#[7..0] 19

M_B_A[13..0] 19M_A_A[13..0] 18

M_B_RAS# 19

M_B_WE# 19

C C

TV DAC Routing Guideline

1. The minimum spacing between each RGB is 40-mils while 50-mils is preferred

2. RGB signals should be routed on the same layer, have a similar number of bends,
same number of vias

3. All routing should be done with ground referencing as well

4. TV DAC route lengths should be lenght match to within 200 mils

Filter

0.5"

Mini
DIN7

B B

GMCH

0.5"

0.2"

12"

TV DAC

150ohm

150ohm

TV IRTN

Zo=37.5

Zo=50

A A

10

9

8

7

6

5

Zo=75

Title

Size Document Number Rev

C

4

3

Date: Sheet

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

Confidential

MR030>Merom+Crestline GM965+ICH8M

Crestline DDR2 (3/6)

2

13 58Wednesday, October 17, 2007

of

1

0.6

10

9

8

7

6

5

4

3

2

1

H H

G G

1.8VDDS

F F

E E

D D

VGA_VDD

VIA=7700mA / 320mils

C C

1.05VDDM

VIA=1300mA /
60mils

0Ω 5% 1/16W SMT0402 LR

VIA=2400mA / 100mils

C177 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C178 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C135 220uF 2V ±20% 15mΩ 7343 PANA LR

C509 0.1uF 10V 10% SMT0402 X5R LR

+

10/2 MODIFY

R433

AW33
AW35

AT35
AT34
AH28
AC32
AC31
AK32

AH32
AH31
AH29
AF32

AU32
AU33
AU35
AV33

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BK32
BK33
BK34
BK35
BL33
AU30

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AN14

AJ31
AJ28

BJ32
BJ33
BJ34

W13
W14

AJ20

R30

R20

T14

Y12

U8G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VGA_VDD

C533 0.1uF 10V 10% SMT0402 X5R LR

C535 0.1uF 10V 10% SMT0402 X5R LR

C532 0.1uF 10V 10% SMT0402 X5R LR

C569 0.22uF 10V +80-20% SMT0402 Y5V LR

C498 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

C555 0.22uF 10V +80-20% SMT0402 Y5V LR

C499 1uF 6.3V 10% SMT0402 X5R LR

C557 0.1uF 10V 10% SMT0402 X5R LR

C563 0.1uF 10V 10% SMT0402 X5R LR

9/20 modify

C548 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C534 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

C242 220uF 2V ±20% 15mΩ 7343 PANA LR(NU)

+

C491 1uF 6.3V 10% SMT0402 X5R LR

1.05VDDM

C538 0.1uF 10V 10% SMT0402 X5R LR(NU)

C549 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C530 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

C539 0.1uF 10V 10% SMT0402 X5R LR(NU)

1.05VDDM

For AMT

308mils

C513 0.22uF 10V +80-20% SMT0402 Y5V LR

C507 0.22uF 10V +80-20% SMT0402 Y5V LR

C501 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

VIA=540mA / 40mils

C520 0.22uF 10V +80-20% SMT0402 Y5V LR

C502 0.22uF 10V +80-20% SMT0402 Y5V LR

C508 10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

AB33

C510 0.1uF 10V 10% SMT0402 X5R LR

C504 0.1uF 10V 10% SMT0402 X5R LR

AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

AL24
AL26

C522 0.1uF 10V 10% SMT0402 X5R LR

C506 0.1uF 10V 10% SMT0402 X5R LR

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

1.5VDDM

20mils

U8F

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

CRESTLINE_1p0

R416

1 2

10Ω 5% 1/16W SMT0402 LR

VCC NCTF

POWER

VCC AXM NCTF

T27

VSS_NCTF_1

T37

VSS_NCTF_2

U24

VSS_NCTF_3

U28

VSS_NCTF_4

V31

VSS_NCTF_5

V35

VSS_NCTF_6

AA19

VSS_NCTF_7

AB17

VSS_NCTF_8

AB35

VSS_NCTF_9

AD19

VSS_NCTF_10

AD37

VSS_NCTF_11

AF17

VSS_NCTF_12

AF35

VSS_NCTF_13

AK17

VSS_NCTF_14

AM17

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

VSS NCTF

VSS SCBVCC AXM

AT33

VCC_AXM_1

AT31

VCC_AXM_2

AK29

VCC_AXM_3

AK24

VCC_AXM_4

AK23

VCC_AXM_5

AJ26

VCC_AXM_6

AJ23

VCC_AXM_7

D37

N P

DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR

1.05VDDM

1.05VDDM

B B

CRESTLINE_1p0

VGA_VDD

VGA_VDD54

1.05VDDM

1.05VDDM8,9,11,15,17,21,23,52

1.5VDDM

1.5VDDM9,15,20,21,23,34,43,44,52

1.8VDDS

1.8VDDS12,15,18,19,53,55

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu

A A

Title

Size Document Number Rev

C

10

9

8

7

6

5

4

3

Date: Sheet

114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

Confidential

MR030>Merom+Crestline GM965+ICH8M

Crestline Power (4/6)

2

14 58Wednesday, October 17, 2007

of

1

0.6

10

9

8

7

6

5

4

3

2

1

H H

G G

F F

E E

D D

9/14 modified
remove UMA
parts

C C

B B

A A

1.25VDDM

20mils

L20 SPWR 0 5% 1/16W 0603

L18 SPWR 0 5% 1/16W 0603

1.25VDDM

L29 SPWR 0 5% 1/16W 0603

L30

1Ω 1% 1/10W SMT0603 LR

3VDDM

L21
SPWR 0 5% 1/16W 0603

VCCA_TVDAC

C187

MO-CAP 10uF 6.3V 20% SMT0603 X5R CL10A106MQ8NNNC SAMSUNG LR

100MHz 600Ω SMT0603 FCM1608KF-601T02 TAI-TECH LR

10

C156

C159

0.1uF 10V 10% SMT0402 X5R LR

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C139

C142

0.1uF 10V 10% SMT0402 X5R LR

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C232

C226

0.1uF 10V 10% SMT0402 X5R LR

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

SPWR 0 5% 1/16W 0603

R144

0.1uF 10V 10% SMT0402 X5R LR

C227

0.1uF 10V 10% SMT0402 X5R LR

C233

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

Caps used in 1.5VDDM_TVDAC
and 1.5VDDM_QTVDAC should
be within 250mils of edge

1.5VDDM

(24mA)

R478 0Ω 5% 1/16W SMT0402 LR

1.25VDDM

(24mA)

L19 SPWR 0 5% 1/16W 0603

C133

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

9

VIA=80mA / 10mils

L59

0.1uF 10V 10% SMT0402 X5R LR

C527

20060117A-EMI

R112

1Ω 1% 1/10W SMT0603 LR

1.8VDDS

0.1uf caps in 1.5VDDM_xPLL
need to be located as edge caps
within 200mils

VIA=80mA / 10mils

1.25VDDM_DPLLA

1.25VDDM_DPLLB

VIA=50mA / 10mils

1.25VDDM_HPLL

VIA=150mA / 10mils

1.25VDDM_MPLL

3VDDM_TVDACA

3VDDM_TVDACB

0.1uF 10V 10% SMT0402 X5R LR

3VDDM_TVDACC

1.25VDDM

10mils

C511

0.022uF 16V 10% SMT0402 X7R LR

C514

C526

0.022uF 16V 10% SMT0402 X7R LR

R400 0Ω 5% 1/16W SMT0402 LR

1.25VDDM

1.25VDDM_PEGPLL

C143

0.1uF 10V 10% SMT0402 X5R LR

0.1uF 10V 10% SMT0402 X5R LR

C480

0.1uF 10V 10% SMT0402 X5R LR

8

3VDDM

3VDDM

0.1uF 10V 10% SMT0402 X5R LR

1.8VDDS_TXLVDS

R120 0Ω 5% 1/16W SMT0402 LR

3VDDM

C474

1.25VDDM

C550 4.7uF 10V SMT0603 Y5V H=0.8mm TAIYO LR

C587

T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR

+

C523

C524

0.1uF 10V 10% SMT0402 X5R LR

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

VIA=250mA / 10mils

C528

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

VIA=100mA / 10mils

C144

C495

0.022uF 16V 10% SMT0402 X7R LR

7

C181

0.022uF 16V 10% SMT0402 X7R LR

VCCA_TVDAC

C189

0.1uF 10V 10% SMT0402 X5R LR

1.25VDDM_DPLLA

1.25VDDM_DPLLB

1.25VDDM_HPLL

1.25VDDM_MPLL

C173 0.1uF 10V 10% SMT0402 X5R LR

VIA=5mA / 10mils

C477

0.1uF 10V 10% SMT0402 X5R LR

1.25VDDM_PEGPLL

C536 1uF 6.3V 10% SMT0402 X5R LR

500mA

C537

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

VIA=200mA / 10mils

3VDDM_TVDACA

3VDDM_TVDACB

3VDDM_TVDACC

C228

0.1uF 10V 10% SMT0402 X5R LR

C512

0.1uF 10V 10% SMT0402 X5R LR

C182

10mA
80mA

5mA

80mA
80mA
50mA
150mA

10mA

VIA=100mA / 10mils

40mA
40mA
40mA

100mA

150mA

3VDDM

20mils

U8H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

Caps used in 2.5VDDM_CRTDAC
should be within 250mils of
edge

R415
10Ω 5% 1/16W SMT0402 LR

1 2

R121 0Ω 5% 1/16W SMT0402 LR

6

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

AXD

VCC_AXD_NCTF

SM CK

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VTTLF1
VTTLF2
VTTLF3

U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

VTTLF

DN3

N P

DIODE SWITCHING 1SS355 80V 100mA SOD-323 2PIN PSI LR

5

20mils

C179

0.1uF 10V 10% SMT0402 X5R LR

VIA=850mA / 40mils

MO-CAP 4.7uF 10V 80-20% SMT0603 Y5V H=0.8mm LMK107F475ZA-T TAIYO LR

1uF 6.3V 10% SMT0402 X5R LR

1uF 6.3V 10% SMT0402 X5R LR

1.8VDDS_TXLVDS

100mA

VIA=100mA / 10mils

3VDDM_HV

1.25VDDM_PEG

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

R115

0Ω 5% 1/10W SMT0603 LR

250mA

VTT_LF1
VTT_LF2
VTT_LF3

100MHz 300Ω 25% SMT0603 HCB1608 KF-301T20 TAI-TECH LR(NU)

C229 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

C225 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

1.05VDDM

(70mA)

3VDDM_HV

4

C230

C235

+

C237

C238

C236

2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

MO-CAP 4.7uF 10V 80-20% SMT0603 Y5V H=0.8mm LMK107F475ZA-T TAIYO LR

C518

C531

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

C194

C197

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

C145

0.1uF 10V 10% SMT0402 X5R LR

C195

0.1uF 10V 10% SMT0402 X5R LR

C168

0.1uF 10V 10% SMT0402 X5R LR

C146

C147

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR(NU)

C211 MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR

MO-CAP 0.47UF 6.3V 10% SMT0402 X5R LR

R479
0Ω 5% 1/10W SMT0603 LR

R127
0Ω 5% 1/10W SMT0603 LR

R714 0Ω 5% 1/10W SMT0603 LR

R126
1Ω 1% 1/16W SMT0402 LR

C196

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

C165

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

L16 SPWR 0 5% 1/16W 0603

L17

1.05VDDM

VIA=200mA / 20mils

VIA=350mA / 20mils

VIA=100mA / 10mils

7/5

VIA=200mA / 20mils

R117 0Ω 5% 1/16W SMT0402 LR

1.25VDDM

1.25VDDM

1.25VDDM

0Ω 5% 1/10W SMT0603 LR(NU)

R99
0Ω 5% 1/10W SMT0603 LR

R104
0Ω 5% 1/10W SMT0603 LR(NU)

R100
0Ω 5% 1/10W SMT0603 LR(NU)

3

1.8VDDS

C199

10uF 6.3V 80-20% SMT0603 Y5V H=0.8mm JMK107F106ZA-T TAIYO LR

1.8VDDS

R103

VIA=1200mA / 60mils

1.25VDDM

1.05VDDM

VIA=250mA / 10mils

1.25VDDM

1.05VDDM

1.05VDDM8,9,11,14,17,21,23,52

1.25VDDM_PEG12

1.25VDDM12,17,23,55

1.5VDDM9,14,20,21,23,34,43,44,52

1.8VDDS12,14,18,19,53,55

3VDDM8,10,12,17,18,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

Custom

Date: Sheet

(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

Crestline Power (5/6)

2

Confidential

15 58Wednesday, October 17, 2007

1

1.05VDDM

1.25VDDM_PEG

1.25VDDM

1.5VDDM

1.8VDDS

3VDDM

of

0.6

8

7

6

5

4

3

2

1

DMI Routing Guideline

U8I

A13

VSS_1

A15

VSS_2

AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50

AE10
AE14

AF20
AF23
AF24
AF31

AG38
AG43
AG47
AG50

AH40
AH41

AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW12
AW16

A17
A24

AC3

AD1

AD3

AD5

AD8

AE6

AG2

AH3

AH7

AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49

AL1

AM3

AM4

AN1

AN5

AN7

AP4

AR2

AR7

AU1

AU3

AW1

VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

D D

C C

B B

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U8J

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45

J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49

M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7
P19

P2

P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

CRESTLINE_1p0

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29

R484 0Ω 5% 1/16W SMT0402 LR

T29

R474 0Ω 5% 1/16W SMT0402 LR

T31

R473 0Ω 5% 1/16W SMT0402 LR

T33

R485 0Ω 5% 1/16W SMT0402 LR

R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

GMCH

LA

LBTx

LC LD LE

Rx

LZ LXLY LW LV

Breakout/in

LA/LZ

Microstrip Same Routing layer as LA/LZ
Microstrip
Microstrip
Microstrip
Stripline
Stripline
Stripline
Stripline

Parameter Breakout Guideline
Uncoupled Single End Impedance
Nominal Trace Width

Pair-to-Pair Pitch

Bus-to-Bus Pitch

Reference Plane

Trace Length-LA (GMCH Breakout)
Trace Length-LB (GMCH Breakout to Via2)
Trace Length-LC (Via2 to Via3) Max = 5900 mils
Trace Length-LD (Via3 to ICH7m Breakout)
Trace Length-LE (ICH7m Breakout) Max = 400 mils

Trace Length-LV ( ICH7m Breakout)

Trace Length-LX (Via2 to Via3)
Trace Length-LY (Via3 to GMCH Breakout) Max = 3600 mils
Trace Length-LZ (GMCH Breakout)
Trace Length-L2 (LV+LW+LX+LY+LZ) Max = 8000 mils

*** When routing near the edge of their reference plane , trace should maintain at least 40
mils space to the edge of the plane
*** Match the trace lengths of the complementary signals within each differential pair to +/- 5 mils

Main Route

LB/LY

Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ

Main Route

LD/LW

Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV

Main Route Guideline
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 7 milsNominal Didderential Pair-Pitch

Outer Layer : 7 mils
Inner Layer : 37 mils

Outer Layer : 37 mils
Inner Layer : 22 mils

Outer Layer : 20 mils
Ground Ground
No routing over plane splitsSplits/Voids

No routing over voids
Max = 400 mils
Max = 3600 mils

Max = 3600 mils

Max = 8000 milsTrace Length-L1 (LA+LB+LC+LD+LE)

Max = 400 mils
Max = 3600 milsTrace Length-LW (ICH7m Breakout to Via2)
Max = 5900 mils

Max = 400 mils

ICH8M

Rx
Tx

Breakout/in

LE/LV

Microstrip
Stripline
Microstrip
Stripline
Stripline
Microstrip
Stripline
Microstrip

55 +/- 15%

Inner Layer : 4 mils
Outer Layer : 5 mils

Inner Layer : 27 mils
Outer Layer : 27 mils

Inner Layer : 15 mils
Outer Layer : 12 mils

X O

PCIE Routing Guideline

GMCH

Tx
Rx

Breakout/in

Main Route

LA/LZ

LB/LC/LY

Stripline

Microstrip

Parameter
Uncoupled Single End Impedance
Nominal Trace Width

Nominal Differential Trace Space

Pair-to-Pair Pitch

Bus-to-Bus Pitch

Reference Plane
Splits/Voids

Trace Length-LA (ICH7m Breakout)
Trace Length-LB (ICH7m Breakout to

AC cap)
Trace Length-LC (AC cap to
PCIe CN)
Trace Length-L1 (LA+LB+LC)

Trace Length-LY (PCIe CN to ICH7m
Breakout)
Trace Length-LZ (ICH7m Breakout)

*** When routing near the edge of their reference plane , trace should maintain at least 40
mils space to the edge of the plane
*** Match the trace lengths of the complementary signals within each differential pair to +/- 5 mils

LB

LA
LZ

LY

Main Route

LD/LW

Same Routing layer as LE/LV

Main Route Guideline
55 +/- 15%
Inner Layer : 4 mils

Outer Layer : 5 mils
Inner Layer : 7 mils

Outer Layer : 7 mils
Inner Layer : 37 mils

Outer Layer : 37 mils
Inner Layer : 20 mils

Outer Layer : 20 mils
Ground
No routing over plane splits

No routing over voids
Max = 400 mils
Max = 10750 mils

Max = 10750 mils

Max = 12000 mils

Max = 11950 mils

Max = 400 mils
Max = 12000 milsTrace Length-L2 (LY+LZ)

X O

Express/Mini Card

LC

Breakout Guideline
55 +/- 15%

Inner Layer : 4 mils
Outer Layer : 5 mils

Inner Layer : 27 mils
Outer Layer : 27 mils

Inner Layer : 15 mils
Outer Layer : 12 mils

Ground

>3W

S < 2S

S = Spacing
S = Trace Width

Rx
Tx

Breakout/in

LE/LV

Microstrip

A A

>3W

S < 2S

S = Spacing
S = Trace Width

8

7

6

5

4

3

Title

Size Document Number Rev

C

Date: Sheet

2

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

Confidential

MR030>Merom+Crestline GM965+ICH8M

Crestline Ground (6/6)

16 58Wednesday, October 17, 2007

of

1

0.6

5

4

3

2

1

D D

VDD_CK505

R214

3VDDM

0Ω 5% 1/8W SMT0805 LR

VDD_CK505

R230 10KΩ 5% 1/16W SMT0402 LR

R233 10KΩ 5% 1/16W SMT0402 LR(NU)

VDDIO_CLK

CLK_SATA_QE#22

10mil

CLK_PCI_FWH

CLK_PCI_1394

CLK_PCI_MINI

CLK_PCI_EC
CLK_PCIF_ICH

CPU_BSEL0
CPU_BSEL1

CPU_BSEL2

124

CLK_48M_ICH22

R231

2.2KΩ 5% 1/16W SMT0402 LR

R173 10KΩ 5% 1/16W SMT0402 LR

CLK_14M_ICH22

C C

Placed within
500 mils of
CK410M

CLK_LPC_TPM26

CLK_PCI_139439

CLK_PCI_MINI44

CLK_PCI_EC46

CLK_PCIF_ICH20

Y3

X'TAL 14.318180MHz 20pF ±30PPM 2PIN SMT8.0*4.5*1.4mm F81430020 eCERA LR

C287
C290
27pF 50V 5% SMT0402 NPO LR

27pF 50V 5% SMT0402 NPO LR

1.05VDDM

CPU_BSEL08
CPU_BSEL18

CPU_BSEL28

1KΩ 5% 1/16W SMT0402 LR(NU)

CPU_BSEL0

CPU_BSEL2

B B

1KΩ 5% 1/16W SMT0402 LR(NU)

R168

R177

1KΩ 5% 1/16W SMT0402 LR(NU)

R178

1KΩ 5% 1/16W SMT0402 LR(NU)

R169

R171

1KΩ 5% 1/16W SMT0402 LR(NU)

CPU_BSEL1

1KΩ 5% SMT1010 1/16W 4P2R LR

R172 1KΩ 5% 1/16W SMT0402 LR

RP17

124

01/31

3

MCH_BSEL0 12
MCH_BSEL1 12

MCH_BSEL2 12

VDD_CK505

9/13 modify

VDDIO_CLK

R209

RES 475Ω 1% 1/16W SMT0402 LR

R217 22Ω 1% 1/16W SMT0402 LR

R218 22Ω 1% 1/16W SMT0402 LR

R219 22Ω 1% 1/16W SMT0402 LR

RP26

22Ω 5% SMT1010 1/16W 4P2R LR

3

10mil

CLK_48M_ICH

CLK_14M_ICH

R222
33Ω 5% 1/16W SMT0402 LR Sn

R174 33Ω 5% 1/16W SMT0402 LR Sn

C308 0.1uF 10V 10% SMT0402 X5R LR

C307 0.1uF 10V 10% SMT0402 X5R LR

PCIF5 PCIF4

R221

C302 0.1uF 10V 10% SMT0402 X5R LR

C268 0.1uF 10V 10% SMT0402 X5R LR

C269 0.1uF 10V 10% SMT0402 X5R LR

7/27 modify

10KΩ 5% 1/16W SMT0402 LR(NU)

C304 0.1uF 10V 10% SMT0402 X5R LR

R220

10KΩ 5% 1/16W SMT0402 LR

C272 0.1uF 10V 10% SMT0402 X5R LR

PCI0_OE#_R

PCI1

PCI2_TMD

PCIF4

PCIF5

XTAL_IN

XTAL_OUT

FSA

FSC

U10

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

39

VDD_SRC

55

VDD_CPU

12

VDD_IO

20

VDD_PLL3_IO

26

VDD_SRC_IO_1

36

VDD_SRC_IO_2

45

VDD_SRC_IO_3

49

VDD_CPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/SRC5_EN

7

PCIF5/ITP_EN

60

XTAL_IN

59

XTAL_OUT

10

USB/FSA

57

FSB/TEST_MODE

62

REF/FSC/TEST_SEL

8

VSS_PCI

11

VSS_48

15

VSS_IO

19

VSS_PLL3

52

VSS_CPU

23

VSS_SRC1

29

VSS_SRC2

42

VSS_SRC3

58

VSS_REF

ASIC IC IC SLG8SP512TTR TSSOP 64P LR

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

SRC8#/ITP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

CKPWRGD/PWRDWN#

IO_VOUT

SCLK

SDA

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC1/SE1

48

64

63

38
37

54
53

51
50

47
46

35
34

33
32

30
31

44
43

41
40

27
28

24
25

21
22

17
18

13
14

56

IO_VOUT

SMB_CLK_OTHER 10,18,19,22,34,44

SMB_DAT_OTHER 10,18,19,22,34,44

PM_STPPCI# 22

CPU0
CPU0#

CPU1
CPU1#

SRC8
SRC8#

SRC10#
SRC10

CLK_MCH_R_OE#

SRC9
SRC9#

SRC6
SRC6#

SRC4
SRC4#

SRC3
SRC3#

SRC2
SRC2#

SS_CLK
SS_CLK#

DOT96
DOT96#

PM_STPCPU# 22

RP12 0Ω 5% SMT1010 1/16W 4P2R LR

124

124

124

124

R170

124

124

124

124

124

124

124

124

3

3

3

3

475Ω 1% 1/10W SMT0603 LR

3

3

3

3

3

3

3

3

CLK_PCI_1394

CLK_PCI_EC

CLK_PCI_MINI

CLK_PCI_FWH

CLK_PCIF_ICH

CLK_48M_ICH

CLK_14M_ICH

RP13 0Ω 5% SMT1010 1/16W 4P2R LR

RP14 0Ω 5% SMT1010 1/16W 4P2R LR

RP18 0Ω 5% SMT1010 1/16W 4P2R LR

RP32 0Ω 5% SMT1010 1/16W 4P2R LR

RP15 0Ω 5% SMT1010 1/16W 4P2R LR

RP16 0Ω 5% SMT1010 1/16W 4P2R LR

RP31 0Ω 5% SMT1010 1/16W 4P2R LR

RP30 0Ω 5% SMT1010 1/16W 4P2R LR

RP29 0Ω 5% SMT1010 1/16W 4P2R LR

RP28 0Ω 5% SMT1010 1/16W 4P2R LR

RP27 0Ω 5% SMT1010 1/16W 4P2R LR

CLK_PWRGD 22

C326 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C328 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C327 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C317 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C329 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C330 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

C259 5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

1.25VDDM

215

6

Q23

D

M-FET-N AO6400 30V 6.9A TSOP-6 6PIN AOS LR(NU)

3

S

4

CLK_CPU_BCLK 8
CLK_CPU_BCLK# 8

CLK_MCH_BCLK 11
CLK_MCH_BCLK# 11

CLK_PCIE_EXPCARD 34
CLK_PCIE_EXPCARD# 34

CLK_PCIE_3GPLL# 12
CLK_PCIE_3GPLL 12

CLK_MCH_OE# 12

CLK_PCIE_ESATA 35
CLK_PCIE_ESATA# 35

CLK_PCIE_LAN 36
CLK_PCIE_LAN# 36

CLK_PCIE_ICH 20
CLK_PCIE_ICH# 20

CLK_PCIE_ROBSON 43
CLK_PCIE_ROBSON# 43

CLK_PCIE_MINICARD 44
CLK_PCIE_MINICARD# 44

CLK_PCIE_SATA 21
CLK_PCIE_SATA# 21

DREFSSCLK 12
DREFSSCLK# 12

DREFCLK 12
DREFCLK# 12

R198
0Ω 5% 1/10W SMT0603 LR

VDDIO_CLK

VDDIO_CLK

C271 0.1uF 10V 10% SMT0402 X5R LR

C273 0.1uF 10V 10% SMT0402 X5R LR

C305 0.1uF 10V 10% SMT0402 X5R LR

C303 0.1uF 10V 10% SMT0402 X5R LR(NU)

C306 0.1uF 10V 10% SMT0402 X5R LR

C270 0.1uF 10V 10% SMT0402 X5R LR

C275 10uF 6.3V 80-20% SMT0805 Y5V H=1.25mm JMK212F106ZG-T TAIYO LR(NU)

C281 10uF 10V +80-20% SMT0805 Y5V TDK LR

1.05VDDM

SS2

A A

FSC

FSB

CPU_BSEL1

01

0

1 2000

5

FSA

Host Clock

1

Frequency MHz

166

CPU_BSEL0CPU_BSEL2

SS3
0
0

0
0
0
0
0

SS1

0 +/- 0.3

0
0

0
0

1
1

0
1

0

1

0

1

1

1

4

SS0
0
1
0
1
0
1
0
1

Spread Mode

DOWN
DOWN
DOWN
DOWN
DOWN
DOWN
DOWN
DOWN

Spread Amount %

0.8

1.0

1.25

1.5

1.75

2.0

2.51

3.0 1 1

SS3
1
1
1
1
1
1
1

3

SS2
0
0
0
0
1
1
1
1

SS1
0
0
1
1
0
0
1
1

SS0
0
1
0
1
0
1
0

Spread Mode

Center
Center
Center
Center
Center
Center
Center
Center

Spread Amount %

+/- 0.4
+/- 0.50
+/- 0.6
+/- 0.8
+/- 1.0
+/- 1.25
+/- 1.5

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC

Title

Size Document Number Rev

C

2

Date: Sheet

(886-2)8751-8751

MR030>Merom+Crestline GM965+ICH8M

Clock Generator IC ICS9LP505-1

1.05VDDM8,9,11,14,15,21,23,52

1.25VDDM

1.25VDDM12,15,23,55

3VDDM

3VDDM8,10,12,15,18,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

Confidential

1

17 58Wednesday, October 17, 2007

0.6

of

5

SO-DIMM0

D D

5pF 50V ±0.5pF -55 TO +125C SMT0402 NPO LR

M_CLK_DDR012

M_CLK_DDR#012

M_CLK_DDR112

M_CLK_DDR#112

C C

C117

C118

C201

C200

4

3

RP53
10KΩ 5% SMT1010 1/16W 4P2R LR

1

2

M_CLK_DDR012

M_CLK_DDR#012

M_CLK_DDR112

M_CLK_DDR#112

SMB_CLK_DDR10,17,19,22,34,44

SMB_DAT_DDR10,17,19,22,34,44

M_A_DM[7..0]13

M_A_DQS[7..0]13

M_A_DQS#[7..0]13

M_A_A[14..0]

M_A_BS2

M_A_BS213

M_A_BS1

M_A_BS113

M_A_BS0

M_A_BS013

M_CS#0

M_CS#012

M_CS#1

M_CS#112

M_CKE0

M_CKE012

M_CKE1

M_CKE112
M_A_CAS#13
M_A_RAS#13

M_A_CAS#
M_A_RAS#
M_A_WE#

M_A_WE#13

M_ODT0

M_ODT012

M_ODT1

M_ODT112

M_A_DM[7..0]
M_A_DQS[7..0]

M_A_DQS#[7..0]

1.8VDDS

20mil

3VDDM

C570

1.8VDDS

B B

M_VREF

Other signal
M_VREF 20mil
Other signal

R300 10KΩ 1% 1/16W SMT0402 LR(NU)
R299 0Ω 5% 1/16W SMT0402 LR
R301 10KΩ 1% 1/16W SMT0402 LR(NU)

20mil
20mil

0.1uF 16V 80-20% SMT0402 Y5V LR

C375

C373

MO-CAP 2.2uF 16V 80-20% SMT0805 Y5V LR

0.1uF 16V 80-20% SMT0402 Y5V LR

20mil

PM_EXTTS#010,12

4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

CN24

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

106

BA1

107

BA0

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF1

203

GND0

204

GND1

132

VSS42

144

VSS43

156

VSS44

168

VSS45

2

VSS46

3

VSS47

15

VSS48

27

VSS49

39

VSS50

149

VSS51

161

VSS52

28

VSS53

40

VSS54

138

VSS55

150

VSS56

162

REV TYPE

VSS57

SCKT FOXCONN SMT DDR2 H=4.0 STD AS0A421-N4SN-4F LR

20-10289-00

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

3

M_A_DQ[63..0]

M_A_DQ[63..0] 13M_A_A[14..0]12,13

Place these 2.2uF caps near
So-Dimm0

1.8VDDS

2

M_A_A10

R118

56Ω 5% 1/16W SMT0402 LR

M_A_A11

1 8

M_A_A9

2 7

M_A_A12

3 6

M_A_BS2

4 5

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

M_CS#0

1 8

M_A_BS1

2 7

M_A_A0

3 6

M_A_A1

4 5

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

M_ODT1

1 8

M_CS#1

2 7

M_A_A13

3 6

M_A_CAS#

4 5

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

M_CKE1
M_CKE0

56Ω 5% SMT1010 1/16W 4P2R LR

M_A_WE#

1 8

M_ODT0

2 7

M_A_BS0

3 6

M_A_RAS#

4 5

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

M_A_A4

1 8

M_A_A2

2 7

M_A_A14

3 6

M_A_A5

4 5

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

M_A_A3
M_A_A8
M_A_A6
M_A_A7

56Ω 5% SMT2010 1/16W 8P4R 0.5mm LR

160mil

C554 T100uF 2V ±20% ESR=18mΩ SMT7343 EEFCD0D101ER PANASONIC LR

+

0.9VDDT_DDRII

40 mils

RP3

RP6

RP8

RP2

124

3

RP7

RP4

RP5

1 8
2 7
3 6
4 5

C175 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

C169 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

C163 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

C152 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

C166 0.1uF 16V 80-20% SMT0402 Y5V LR

C180 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR

Place one cap close to every 2 pullup resistors
terminated to 0.9VDDT_DDRII

C476

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C162

0.1uF 16V 80-20% SMT0402 Y5V LR

C158

0.1uF 16V 80-20% SMT0402 Y5V LR

C155

0.1uF 16V 80-20% SMT0402 Y5V LR

C490

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C153

0.1uF 16V 80-20% SMT0402 Y5V LR

C493

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C484

0.1uF 16V 80-20% SMT0402 Y5V LR

C464

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C479

0.1uF 16V 80-20% SMT0402 Y5V LR

C500

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C468

0.1uF 16V 80-20% SMT0402 Y5V LR(NU)

C496

0.1uF 16V 80-20% SMT0402 Y5V LR

Place these 0.1uF caps near
So-Dimm0 pin79~pin115

C161 0.1uF 16V 80-20% SMT0402 Y5V LR

C171 0.1uF 16V 80-20% SMT0402 Y5V LR

area

C157 1000pF 50V 10% SMT0603 X7R LR

C154 0.1uF 16V 80-20% SMT0402 Y5V LR

C148 1000pF 50V 10% SMT0603 X7R LR

1

1.8VDDS12,14,15,19,53,55

3VDDM8,10,12,15,17,19,20,21,22,23,24,26,27,28,31,32,34,35,36,37,38,39,40,43,44,46,47,51,52,54,55

M_VREF

0.9VDDT_DDRII

1.8VDDS

3VDDM

Confidential

18 58Wednesday, October 17, 2007

of

0.6

M_VREF12,19,53

A A

Title

MR030>Merom+Crestline GM965+ICH8M

Size Document Number Rev

C

DDR2 SDRAM SO-DIMM0

5

4

3

2

Date: Sheet

0.9VDDT_DDRII19,53

First International Computer, Inc.

5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751

1