Fic md02 Service Manual CHAP3

Chapter

Software Functional Overview

3.1 Overview

The MD02 is an IBM PC/AT compatible Notebook PC, which supports the Intel Micro­PGA Pentium M CPU processors family. The following are the major features that MD02
supports.

§ Microsoft PC99 logo and Win XP logo approval.

§ Offer 1024x768 XGA display with 13.3 XGA LCD panel.

§ Support ACPI 1.0B (or above).

§ Support PCI 2.1 (or above).

§ Support AGP 2.0.

§ Support SMBIOS 2.3.

§ Support DDR266/200 SDRAM.

§ Support 100/133 Mhz CPU front side bus.

3.2 Summary of the BIOS Specification

The summary of the BIOS specification is as the below description:

Controller Chip Description

BIOS Feature § Microsoft PC99 logo and WinXP logo approval.

§ Support Boot Block / Crisis Rescue.

§ APM 1.2 Compliance

§ Support ACPI 1.0B (or above) Spec.

§ Support PCI 2.1 (or above) Spec.

§ Support SMBIOS 2.3 (or above) Spec

§ Support Windows XP.

§ Support flash function including both DOS and Windows

interface for new BIOS update.

§ Support US keyboard .

§ Support boot from LAN , USB FDD/FLASH , HDD and CDROM

Drive.

§ Support Phoenix First BIOS.

CPU Auto detecting the CPU type and speed for Intel Dothan based

system.
Support Intel Geyserville III Technology .

DRAM Auto sizing and detection. Support PC-200/266/333 DDR

SDRAM.

Cache § Level 2 SRAM auto sizing and detection.

§ Always enable CPU L1 and L2 cache.
Shadow Always enable VGA and System BIOS shadow
Display § System auto detects LCD or CRT presence on boot and lid

closed.

§ Support Panning while LCD in a display resolution greater than
supported.

§ Support Microsoft Direct 3D.

§ Support AGP 4x BUS.

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Hard Disk

Multi Boot Allow the user to select boot from FDD, HDD and CD-ROM
Plug and Play Support PnP Run Time Service and conflict-free allocation of

Smart Battery Support BIOS interface to pass battery information to the

Keyboard Controller Support Fn hot keys, one Win95 hot keys, built-in Glide Pad.
PCMCIA Compliant with PCMCIA 2.1 specification
Power Management

Support (ACPI Mode)

§ Enhanced IDE spec.

§ Support auto IDE detection.

§ Support LBA mode for larger capacity HDD.

§ Support Ultra DMA 33/66/100.

§ Support Fast PIO mode 1-4 transfer.

§ Support 32 bit PIO transfer.

§ Support Multi-Sector transfer.

§ Support SMART monitoring.

resource during POST

application via SMBus

The power management is compliant with ACPI 1.0B

specification and supports the following power state:

§ S0 (Full-On) Mode

§ S3 (STR) Mode

§ S4 (STD) Mode

§ S5 (Soft-Off) Mode

3.3 Subsystem Software Functions

This section provides introduction on the software functions of the notebook subsystems and
BIOS related function.

3.3.1 Key Chipset Summary

Following are the main chipsets used in the notebook:

Controller Chip Vendor Description

Processor
North Bridge
South Bridge
Video Controller
PCMCIA Controller
Audio Chip
Audio Codec
Keyboard Controller
PMU Controller
ROM BIOS
Clock Generator
Temperature Sensor
IEE 1394

LAN
Modem

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Intel Mobile Dothan
Intel MontaraGM+
Intel ICH4
Intel Embedded in MontaraGM+
TI PCI4510
Intel South Bridge Integrated
Intel ICH4
Misubishi M38857M8
NEC PMU08
SST 49LF004A
IMI CY28346
NS MAX6690
TI PCI4510

Intel ICH4-M+BroadCom BCM4401
Intel MDC AC’97

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3.3.2 System Memory

The system memory consists of SDRAM memory on 64-bit bus and the module size options
are 128/256/512/1GMB upward. The BIOS will automatically detect the amount of memory in
the system and configure CMOS accordingly during the POST (Power-On Self Test) process.
This must be done in a way that requires no user interaction.

Base SO-DIMM DRAM slot Expansion SO-DIMM DRAM

slot

(Bank 0&1) (Bank 2&3)

128MB NIL 128MB
128MB 128MB 256MB
128MB 256MB 384MB
128MB 512MB 640MB
128MB 1GB 1128MB
256MB NIL 256MB
256MB 128MB 384MB
256MB 256MB 512MB
256MB 512MB 768MB
256MB 1GB 1256MB
512MB NIL 512MB
512MB 128MB 640MB
512MB 256MB 768MB
512MB 512MB 1GB

1GB 1GB 2GB

Total Size

3.3.3 Video

The Video subsystem used External DDR memory of Video memory. The system will
support the true ZV port, the Microsoft Direct 3D assist, simultaneous display, monitor
sense for auto display on boot and VESA Super VGA function call.

Supported Video Mode

The following is the display modes supported by the Intel Mobility Video control in
LCD only, CRT only, and simultaneous mode. The VGA BIOS will allow mode sets of
resolutions greater than the panel size but only show as much mode display as will fit
on the panel.

Supported standard VGA modes:

The VGA BIOS supports the IBM VGA Standard 7-bit VGA modes numbers.

Mode Pixel Resolution Colors Memory

00h/01h 40*25 16 Text
02h/03h 80*25 16 Text
04h/05h 320*200 4 2-bit Planar

06h 640*200 2 1-bit Planar
07h 80*25 Mono Text
0Dh 320*200 16 4-bit Planar

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0Eh 640*200 16 4-bit Planar
0Fh 640*350 Mono 1-bit Planar
10h 640*350 16 4-bit Planar
11h 640*480 2 2-bit Planar
12h 640*480 16 4-bit Planar
13h 320*200 256 8-bit Planar

Note: All Standard VGA Modes are limited to the standard VGA refresh rates.

Supported extended video modes:

CRT device will support all listed VESA mode; and other devices such as PANEL & TV may
be limited to the mode support due to their characteristics.

VESA
Mode

100h 640 x 400 8-bit Packed 70 2MB
101h 640 x 480 8-bit Packed 60, 72, 75, 85 2MB
102h 800 x 600 4-bit Planar 60, 72, 75, 85, 100 2MB
103h 800 x 600 8-bit Packed 60, 72, 75, 85, 100 2MB
104h 1024 x 768 4-bit Planar 43(I), 60, 70, 75, 85, 100 2MB
105h 1024 x 768 8-bit Packed 43(I), 60, 70, 75, 85, 100 2MB
106h 1280 x 1024
107h 1280 x 1024
10Eh 320 x 200 16-bit Packed 70
10Fh 320 x 200 32-bit Unpacked 70
111h 640 x 480 16-bit Packed 60, 72, 75, 85
112h 640 x 480 32-bit Unpacked 60, 72, 75, 85
114h 800 x 600 16-bit Packed 60, 72, 75, 85, 100
115h 800 x 600 32-bit Unpacked 60, 72, 75, 85, 100
117h 1024 x 768 16-bit Packed 43(I), 60, 70, 75, 85, 100
118h 1028 x 768 32-bit Unpacked 43(I), 60, 70, 75, 85, 100
11Ah 1280 x 1024

11Bh 1280 x 1024
11Dh 640 x 400 16-bit Packed 70
11Eh 640 x 400 32-bit Packed 70

120h 1600 x 1200

122h 1600 x 1200

124h 1600 x 1200
12Ah 640 x 480 24-bit Packed 60, 72, 75, 85
12Bh 800 x 600 24-bit Packed 60, 72, 75, 85, 100
12Ch 1024 x 768 24-bit Packed 43(I), 60, 70, 75, 85, 100
12Dh 1280 x 1024
12Eh 320 x 200 8-bit Packed 70

131h 320 x 200 8-bit Packed 72

133h 320 x 200 16-bit Packed 72

Pixel

Resolution

Memory Model Refresh Rates In (Hz)

4-bit Planar 43(I), 60, 75, 85

8-bit Packed 43(I), 60, 75, 85

16-bit Packed 43(I), 60, 75, 85

32-bit Unpacked 43(I), 60, 75, 85

8-bit Packed 48(I), 60, 75, 85

16-bit Packed 48(I), 60, 75, 85

32-bit Unpacked 48(I), 60, 75, 85

24-bit Packed 43(I), 60, 75, 85

Minimum

Memory

2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
4MB
4MB
8MB
2MB
2MB
2MB
4MB
8MB
2MB
2MB
4MB
4MB
2MB
2MB
2MB

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134h 320 x 200 32-bit Packed 72
13Bh* 1400 x 1050
13Ch* 1400 x 1050
13Eh* 1400 x 1050

141h 400 x 300 8-bit Packed 72

143h 400 x 300 16-bit Packed 72

144h 400 x 300 32-bitUnpacked 72

151h 512 x 384 8-bit Packed 70

153h 512 x 384 16-bit Packed 70

154h 512 x 384 32-bitUnpacked 70

171h 720 x 480 8-bit Packed 75

173h 720 x 480 16-bit Packed 75

174h 720 x 480 24-bit Packed 75

175h 720 x 480 32-bitUnpacked 75

176h 720 x 576 8-bit Packed 75

178h 720 x 576 16-bit Packed 75

179h 720 x 576 24-bit Packed 75

17Ah 720 x 576 32-bitUnpacked 75

Note: “*” The modes may not be available. Their availability should be determined by VESA
function calls.

Panel Type Initialization

The VGA BIOS will issue INT 15h function call during POST. This function call allows
the system BIOS to specify the panel type to the VGA BIOS. The system BIOS should
get the panel type from GPIO pins before the VGA chip initialized, and pass this
information to VGA BIOS through INT 15 Function 4E00h.

LCD Panel ID pin Definition:

VT82C686B GPI Pins

GPI [23]

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0

GPI

[17]

GPI

[11]

8-bit Packed 60, 75

16-bit Packed 60, 75

32-bitUnpacked 60, 75

GPI
[10]

ID0
ID1

ID2

ID3

Panel Type

2MB
2MB
4MB
8MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB

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1 1 0 1
1 1 1 0
1 1 1 1

3.3.4 Enhanced IDE

The system BIOS must be ready to support 4 IDE devises on two controllers. The BIOS
support Ultra DMA33/66/100 and also supports automatic configuration of drives using
both the LBA and CHS large drive remapping method. In addition to supporting standard
drives through an auto-configuration process that does NOT require user involvement or
confirmation. The system should automatically do this at POST time in a way that is
transparent to the user. If a drive is connected to the bus, the drive should be
automatically recognized, configured and available for use under MS-DOS 6.2x.

3.3.5 Audio

The audio subsystem will support the requirements identified by the AC’97 specification. Both
software and hardware will control the volume level for the internal audio subsystem. In
addition to the volume control, the user will be able to mute the sound to completely cut off
the volume using both software and hardware.

3.3.7 PCMCIA

The PCMCIA controller chip of the notebook provides the following features:

• Individually accessed, dual-buffer implementation

• Support for 2 separate CardBus slots (one type III or two type II stacked)

• Support for 3.3v, 5v and 12v (flash programming) cards

3.3.8 LED Indicator

The table below lists down the functions of the Status LED indicator:

Indicator Function Description
IDE accessing LEDΠThis LED will turn on while accessing the IDE Device.
Battery Charging LED Turn on (Blue) – Battery is under charging mode

Turn off – Battery full charged or no battery
CapsLock LEDΠThis LED will turn on when the function of CapsLock is active.
ScrollLock LEDΠThis LED will turn on when the function of ScrollLock is active.
NumLock LEDΠThis LED will turn on when the function of NumLock is active.
Power Status LED Yellow – System is powered on.

Yellow Blinking- System is entered suspend mode.

Trun off – Battery Low.
Mail LEDΠThis LED will turn on while Mail was arrived.

i

Π- These LEDs will be turned off during Suspend mode.

3.3.9 Hot Keys Definition

All Hot keys must be active at all times under all operation systems.

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Function Function Handler
Fn + F3 Toggle Display (LCD/CRT/TV/LCD&CRT) BIOS Handler

Fn + F2 RF ON/OFF BIOS Handler
Fn + F6 System Speaker On/Off BIOS Handler

Fn + F8 Brightness Increase Controlled by PMU08
Fn + F9 Brightness Decrease Controlled by PMU08
ScrLock Scroll Lock
Internet
Button
Mail Button Mail Function Key Controlled by Driver

3.3.10 Plug & Play

The BIOS supports the Plug and Play Specification 1.0A. (Include ESCD)
This section describes the device management. The system board devices and its resources
are as follows:

Device Connect
I/O IRQ DMA Memory

DMA Controller Static 00~0F, 81~8F - DMA5 ­Interrupt Controller Static 20~21, A0~A1 IRQ2 - ­System Timer Static 40~43 IRQ0 - ­RTC Static 70~71 IRQ8 - ­ISA Bus Static - - - ­System Speaker Static 61 - - ­System Board Static - - - E0000~FFFFF
PnP Mother Board Static 80 - - ­Keyboard Controller Static 60, 64 IRQ1 - ­PMU08 Controller Static 68, 6C - - ­Math Coprocessor Static F0~FF IRQ13 - ­Glide Pad Static - IRQ12 - ­Video Controller Static 3B0~3BB,

Dual IDE Controller Static 170~177, 1F0~1F7,
CardBus Controller Dynamic 3E0~3E1 IRQ10 - -

Audio chip Dynamic 220~22F, 300~301,
IEEE1394 Dynamic IRQ10

Modem Dynamic 3E8~3EF IRQ10 - ­LAN Dynamic 1080~10FF IRQ10 - ­USB Host Controller Dynamic EF80~EF9F IRQ5 - -

3.3.11 PCI Device

The table below summarizes the PCI IDSEL Pin Allocation:

Internet Function Key Controlled by Driver

Resources

Type

IRQ5 - A0000~BFFFF

3C0~3DF

IRQ14, 15 - -

3F6

IRQ5 DMA3 -

388~38B

,
C0000~CFFFF

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IDSEL Pin PCI Device
Device Number Function

Number
AD23 Device 07 Function 0 RICOH Card Bus
Function 1 RICOH IEEE1394
AD17 Device 01 Function 0 MINI PCI

The table below summarizes the INT Pin Allocation:

INT Pin PCI Device
INTA CardBus/MiniPCI/LAN
INTB Cardbus/MiniPCI
INTC
INTD

The table below summarizes the PCI bus master Allocation:

Arbiter Signal

REQ00/GNT00

REQ20/GNT20
REQ30/GNT30

REQ10/GNT10 RICOH Card Bus Controller

Agents

(Master)

Device Name

Function Use

3.3.12 SMBus Devices

The SMBus is a two-wire interface through which the system can communicate
with power-related chips. The BIOS should initialize the SMBus devices during
POST.

ICH4 SMBus Connection Devices

SMBus Device Host/Slave Address BIOS Need to Initialization
SO-DIMM Slave A0h/A2h Memory Auto Sizing (SPD).
CY28346

CLK Generator

PMU 08 SMBus Connection Devices

SMBus Device Host/Slave Addres

PMU08 Master 10h Enable PS01 decode interface
MAX6690 (Thermal

sensor)
Battery (1st Battery) Slave A8h No Need

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Slave D2h Program the desired clock frequency

(Pin23 output 24MHz, Pin22 output
48MHz)

BIOS Need to Initialization
s
A7 ~
A1

Slave 9Ch Program the desired temperature

range

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/O Map

I

Hex Address Device
000 - 01F 8237-1
020 - 021 8259-1
022
040 - 05F 8254
060 - 064 Keyboard Controller
068 – 06C PMU08 Controller
070 - 07F RTC & NMI Mask
080 - 08F DMA Page Registers
092 System Control Port
0A0 - 0A1 8259-2
0B2 Advanced Power Management Control Port
0B3 Advanced Power Management Status Port
0C0 – 0DF 8237-2
0F0 – 0FF Math Coprocessor
170 - 177 IDE Secondary Command Block
1F0 - 1F7 IDE Primary Command Block
220 - 22F Sound Blaster
279 ISA PnP Address
330 - 333 MIDI
376 IDE Secondary Control Block
388 - 38B FM Synthesizer
3B0 - 3DF Video Controller
3E0 - 3E1 PCMCIA Controller
3F0 - 3F5, 3F7 Floppy Disk Controller
3F6 IDE Primary Control Block
A79 ISA PnP Address
CF8 – CFF PCI BUS configuration Register

ISA DMA Map

DMA Channel Device
DMA 0 Unused
DMA 1 Unused
DMA 2 Floppy Disk
DMA 3 Audio
DMA 4 Unused
DMA 5 Unused
DMA 6 Unused
DMA 7 Unused

Memory Map

Address Range Length Description
00000 - 9FFFFh 640 KB System Memory
A0000 – BFFFFh 128 KB Video Memory
C0000 – C9FFFh 40 KB Video ROM
CA000 – DBFFFh 72 KB Unused
DC000 - DFFFFh 16 KB DMI information
E0000 – FFFFFh 128 KB System ROM BIOS

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IRQ Map

IRQ# Description
IRQ 0 System Timer
IRQ 1 Keyboard
IRQ 2
IRQ 3
IRQ 4
IRQ 5 Audio/VGA/USB
IRQ 6 Floppy Disk Drive
IRQ 7
IRQ 8 RTC Alarm
IRQ 9 ACPI
IRQ10 LAN / Modem or Combo, (Card Bus), IEEE 1394
IRQ11 Reserved for PCMCIA card
IRQ12 Glide Pad
IRQ13 FPU (FERR)
IRQ14 Hard Disk Drive
IRQ15 CD-ROM or DVD-ROM

3.3.13 GPIO Pin Assignment

The GPI and GPO pins connected to system devices. The BIOS can get device’s
status and control the device via the GPI and GPO pins.

ICH4 GPI pin assignment

GPIO
Number
GPIO0 PanelID0 I Panel ID setting
GPIO1 PanelID1 I Panel ID setting

GPIO2 PanelID2 I Panel ID setting
GPIO3 PanelID3 I Panel ID setting

GPIO8
GPIO11 LPC_QPME0 1 O 0:LPC_QPME0 Event Enable
GPIO12 EC_SCI0 I 0:PMU SCI Detect
GPIO13 PM_RI0 I 0:PMU GPIO detect

GPIO25 CB_HWSUSP0 1 O R5C551 Hardware suspend
GPIO32 SPDMUX0 1 O SMBus select 1

GPIO33 SPDMUX1 1 0 SMBus select 0

Signal Name Default I/O Notes

Q_SMI0 I 0:External K/B SMI0

1:Normal operation
1:Normal operation -­1:PMU SCI not Detect
1:PMU GPIO not Detect

control pin

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3.3.14 PMU08 GPIO pin assignment

GPIO
number
GPIO B6 PM_SLP_S

GPIO B5 N.C. -- -- No used
GPIO B4 N.C. -- -- No used

GPIO B1 N.C. 1 O No used
GPIO B0 N.C. -- -- No use

GPIO A7 N.C -- -- No use
GPIO A6 PCMRI0 1 I PC Card Ring event

GPIO A0 LID0 1 I LCD Open/Close Status

GPIO C1 NC -- -- No Use

Signal
Name

10

Default I/O Notes Remar
1 I Suspend Plane A control for

ICH4

0: POS, STR and STD

suspend state.

1: not suspend state.

0: Ring

1: No Ring

0: LCD Close

1: LCD Open

k

GPIO B7 PM_RI0 1 O Wake Up event request

0: Wake SMI(SCI)

1: There is no demand.

GPIO B2 N.C. -- - No Use
GPIO B0 N.C. -- -- No Use
GPIO A5 PRSTMSK0 1 O PCI Reset Mask

0: Reset Mask

1: Reset Enable

GPIO A4 PCMUTE0 1 O Mute PC Speaker
GPIO A1 N.C. -- -- No use
GPIO C2 CHGLED Charge Battery indicator :

1 : charging Battery

0 : Stop charging Battery

GPIO C3 N.C. -- -- No Use
GPIO C0 N.C. -- -- No Use

3.4 ACPI

General Requirements

The BIOS must meet the following general Power Management requirements:
Refers to the portion of the firmware that is compatible with the ACPI 1.0b specifications.
Support for Power ON(S0 state), Suspend-to-RAM (S3 state) , Suspend-to-Disk mode (S4
state) and Soft OFF(S5 state).

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Global System State Definitions

Global system states (Gx states) apply to the entire system and are visible to the user.
Following is a list of the system states:
G0/S0 - Working:

A computer state where the system dispatches user mode (application) threads and they
execute. In this state, devices (peripherals) are dynamically having their power state
changed. The user will be able to select (through some user interface) various
performance/power characteristics of the system to have the software optimize for
performance or battery life. The system responds to external events in real time. It is not safe
to disassemble the machine in this state.

G1 - Sleeping:

A computer state where the computer consumes a small amount of power, user mode
threads are not being executed, and the system “appears” to be off (from an end user’s
perspective, the display is off, etc.). Latency for returning to the Working state varies on the
wakeup environment selected prior to entry of this state (for example, should the system
answer phone calls, etc.). Work can be resumed without rebooting the OS because large
elements of system context are saved by the hardware and the rest by system software. It is
not safe to disassemble the machine in this state.

G2/S5 - Soft Off:

A computer state where the computer consumes a minimal amount of power. No user
mode or system mode code is run. This state requires a large latency in order to return to
the Working state. The system’s context will not be preserved by the hardware. The system
must be restarted to return to the Working state. It is not safe to disassemble the machine.

G3 – Mechanical Off:

A computer state that is entered and left by a mechanical means. It is implied by the entry
of this off state through a mechanical means that the no electrical current is running through
the circuitry and it can be worked on without damaging the hardware or endangering the
service personnel. The OS must be restarted to return to the Working state. No hardware
context is retained. Except for the real time clock, power consumption is zero.

Sleeping State Definitions

Sleeping states (Sx states) are types of sleeping states within the global sleeping state, G1.
The Sx states are briefly defined below. For a detailed definition of the system behavior within
each Sx state, refer to ACPI specification section 7.5.2. For a detailed definition of the
transitions between each of the Sx states, refer to ACPI specification section 9.1.

S1 Sleeping State:

The S1 sleeping state is a low wake-up latency sleeping state. In this state, no system

context is lost (CPU or chip set) and hardware maintains all system context.

S3 Sleeping State:

The S3 sleeping state is a low wake-up latency sleeping state where all system context is
lost except system memory. CPU, cache, and chip set context are lost in this state.
Hardware maintains memory context and restores some CPU and L2 configuration context.
Control starts from the processor’s reset vector after the wake-up event.

S4 Sleeping State:

The S4 sleeping state is the lowest power, longest wake-up latency sleeping state
supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware
platform has powered off all devices. Platform context is saved in disk.

S5 Soft Off State:

The S5 state is similar to the S4 state except the OS does not save any context nor
enable any devices to wake the system. The system is in the “SOFT” off state and requires a

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complete boot when awakened. Software uses a different state value to distinguish between
the S5 state and the S4 state to allow for initial boot operations within the BIOS to
distinguish whether or not the boot is going to wake from a saved memory image.

System Power Plane

The system components are grouped as the following parties to let the system to

control the On/Off of power under different power management modes.

3.4.1 System Power Plane

The system components are grouped as the following parties to let the system to control the
On/Off of power under different power management modes.

The power plane is divided as following:

Power Group Power

Control Pin
+B Nil IMM, (9V~20V)
+3VA Nil RTC I/F, PMU08
+12V PWRON PCMCIA Card, AC97 Codec
+5V PWRON PCMCIA Slot 5V
+3V PWRON VGA, PCMCIA, PCMCIA Slot 3V, DRAM, Twister(DRAM I/F),

+5VS SUSB# FLASH ROM, HDD, CD-ROM, USB, Internal K/B, Glide Pad,
+3VS SUSB# ISA I/F Power, Clock Generator & Buffer (W137)

+RTCVCCS Nil RTC

3.4.2 Power Management Mode Transition Flow Chart

From a user-visible level, the system can be thought of as being one of the states in the
following diagram:

Controlled Devices

M3885x, MAX3243
Audio AMP, Fan

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Sleeping

S1

SLP_TYPx=S1

and

SLP_EN

SLP_TYPx=S2

and

SLP_EN

SLP_TYPx=S3

and

SLP_EN

SLP_TYPx=S4

and

SLP_EN

S2

Sleeping

S3

Sleeping

S4

G2 (S5) -

Soft Off

ACPI
Boot

(SCI_EN=1)

SLP_TYPx=S5

and

SLP_EN

or

PWRBTN_OR

Wake
Event

G0 (S0) -

Working

S4BIOS_REQ

to

SMI_CMD

Sleeping

OEM S4 BIOS

Handler

SLP_TYPx=S4

and

SLP_EN

3.4.3 Power States transition event

The following table summarizes the entry events and wake-up events of each power:
The following table summarize the entry events and wake-up events of each power state

Power State Entry Event Wake up Event
S3 OSPM control

Lid Close
Power Button
Sleep Button
Battery Low

Power Button
Ring Wake up
RTC Alarm
LAN Wake Up
Lid open

G1

S4 OSPM control,

Power button

Power Button

RTC Alarm
Sleep button
Lid Close
Battery Low

S5 Power Button

Battery Low

Power Button
OSPM control

x OSPM: OS-directed Power Management

Device Power Control Methodology
Power state of local devices table

This section illustrates the power control status of each key device/component of the

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Software Functional Overview

system under each power management mode.

PowerState
Component
CPU Stop

L2 CACHE ON Power Down Power Off Power Off
MontaraGM ON Stop Clock Power Off (except Vcc) Power Off
ICH4 ON ON Power Off (except

DRAM ON Self Refresh Self Refresh Power Off
Clock Synthesizer ON Low Power Power Off Power Off
CDROM ON Power Down Power Off Power Off
HDD ON Power Down Power Off Power Off
FDD ON Power Down Power Off Power Off
KBC ON ON Power Down Power Off
PMU08 ON ON Power Down Power Down
VGA/VRAM ON Power Down Power Down Power Off
PCMCIA ON Power Down Power Down Power Off
AUDIO ON Power Down Power Off Power Off
Audio AMP ON Power Down Power Off Power Off
LCD Backlight ON Power Off Power Off Power Off
LAN ON Power Down Power Down Power Down
Internal Modem ON Power Down Power Down Power Down

Device Power control Methodology During S3 Mode

This section illustrates the control methodology of each device/component and its details
under Stand by mode.

Device Power Down Controlled by Description
CPU Hardware Controlled by SUSB# pin
L2 CACHE Hardware Power off
ICH4 Hardware Controlled by SUSB# pin
DRAM Software Self Refresh
Clock Synthesizer Hardware Controlled by SUSB# pin
CDROM Hardware Power off
HDD Hardware Power off
FDD Hardware Power off
KBC Software Controlled by M3885xM8 power

PMU08 Sofeware Controlled by PMU08 power down
VGA/VRAM Software Controlled by MontaraGM

PCMCIA Software Controlled by SUSB# pin
AUDIO Hardware Controlled by ICH4
Audio AMP Hardware Controlled by BIOS
LCD Backlight Hardware Power off
LAN Hardware Controlled by Driver enter Dx status
Internal Modem Hardware Controlled by Driver enter Dx ststus

Doze Stand By STR STD/SOff

Stop Clock Power Off Power Off

Grant

Power Off (except

SUSVcc, RTCVcc )

down command
command

SUSVcc, RTCVcc)

Power Button
The function of Lid Switch is depends on the ACPI aware OS.

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Software Functional Overview

Lid Switch (Cover Switch)
The function of Lid Switch is depends on the ACPI aware OS.

3.4.4 Expanding Event Through the Embedded Controller

The following figure shows the relationships between the devices that are wired to the
embedded controller, the embedded controller queries, and ACPI general

Figure 3-2 The Relationships between ACPI, Controller, and Device

SCI Source and GPE Event from PMU08

The system will issue a beep to inform user while the following SCI alerted:

PMU08 Input Event GPE Event Handler
ADPIN# AC Plug In/Out GPI12 AML Handler
BAT0# Battery Plug In/Out GPI12 AML Handler
GPIOA0 LID Event GPI13 AML Handler
GPIOA3 Keyboard SMI GPI8 AML Handler
GPIOA6 PCMCIA Ring In GPI13 AML Handler
GPIOA7 COM Port Ring In GPI13 AML Handler
THRM Thermal Event GPI12 AML Handler

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Software Functional Overview

Control Method Battery Subsystem

EC should support all the battery information to ACPI-OS

−

Designed Battery capacity

−

Designed Voltage

−

Designed Low battery capacity

− Designed Low – Low battery capacity

− Latest Full charged capacity

− Present Remaining capacity

− Present drain rate

−

Present voltage

−

Present Battery Status

ACPI BIOS should support an independent device object in the name space, and
implement the following methods.

3.4.5 Thermal Control

There are primary cooling policies that the OS use to control the thermal state of the
hardware

Cooling Policy
Action cooling Fan On Always On
Action cooling Fan High On

Fan High Off
Passive cooling Throttling CPU On
Throttling CPU Off
Critical trip point System Shutdown

3.5 Battery Management

Action

Temperature Setting

Over 70 oC
Below 65oC
Over 90 oC
Below 85oC
Over 110 oC

3.5.1 Battery Sub-system

§ The charger will stop charge the battery when the following condition is detected.

- The temperature of the system is too high

- The remaining capacity is 95% and more.
Note that the battery life is depending on different configuration running. E.g. with CD­ROM battery life is shorter, document keyin only battery life is longer, PMU disable
battery life is short, PMU enable battery life is longer.

- Battery reading methodology is through PMU08 SMBus.

3.5.2 Battery Low

When the battery voltage is approaching to the Low level, the PMU08 will generate a
battery low SMI. The system will do the following action.

1) The Power Indicator will become blinking.

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Software Functional Overview

2) The system will issue a Warning beep.

3.5.3 Battery Low - Low

When the battery voltage is approaching to the Low-Low level, the PMU08 will
generate a battery low-low SMI. The system will do the following action.

1) The Power Indicator will keep on Blinking.

2) The system will enter Suspend To Disk mode even the power management is
disabled. The function of power-on or Resume will be inhibited until the battery
Low – Low condition is removed.

3.5.4 AC Adapter

When plug in the AC adapter, the system will do the following action:

- The charger will charge the Main Battery, if remaining capacity is not full.

- The Battery Charging Indicator will turn on if the battery is in changing mode.

3.6 PMU08

The Embedded controller PMU08 acts as a supplement for power management control. It
supports a lot of functions via SMBus interface.

3.6.1 The System EC RAM with PMU08

Embedded Controller Command Set
The EC I/F command set allows the OS to communicate with the PMU08.
For detail information refer to ACPI 1.0B specification.

Com
man

EC I/F Command

Read Embedded
Controller

(RD_EC)

Write Embedded
Controller

(WR_EC)

d
Byte
Enco

ding

0x80

0x81

Byte

Register R/W

#1 EC_SC W

#2

#3

#1 EC_SC W

#2

EC_DAT

A

EC_DAT

A

EC_DAT

A

Description Interrupt

Command
byte Header

W

Address byte
to read

R

Read data to
host

Command
byte Header

W

Address byte
to write

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

Interrupt on
IBF=0

Interrupt on
IBF=0

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7 6 5 4 3 2 1 0

R(/W)

Design

Battery

Design

Software Functional Overview

Burst Enable
Embedded
Controller

(BE_EC)

Burst Disable
Embedded
Controller

(BD_EC)
Query Embedded

Controller
(QR_EC)

0x82

0x83 #1 EC_SC W

0x84

#3

#1 EC_SC W

#2

#1 EC_SC W

#2

EC_DAT

A

EC_DAT

A

EC_DAT

A

W Data to write

R

R

Command
byte Header

Burst
acknowledge
byte

Command
byte Header

Command
byte Header

Query value to
host

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

3.6.2 PMU08 EC RAM List

The micro controller PMU08 acts as a supplement for power management control. It supports
the following functions via SMBus Command

Functio

n

1st

Battery
[ _BIF ]

Address

00h

*3

Regist

er

Name

Power
unit

R/W

Bit Number

DATA[15:0] *1 - 0xffff

( 0x80 , 0xC0 )

Logic Default Description

0x0000: mWh [Fixed
value]

0xffff: Unknown

02h

capacit

*3

y
Last

Full

04h

Charg
e

*3

Capaci
ty

06h

Techn

*3

ology

08h

Voltage R(/W) DATA[15:0] *1 - 0xffff

*3

R(/W) DATA[15:0] *1 - 0xffff

R(/W) DATA[15:0] *1 - 0xffff

R(/W) DATA[15:0] *1 - 0xffff

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0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000 : Primary
0x0001: Secondary [Fixed

value]
0xffff: Unknown.

0x0000-0xfffe(mV)
0xffff: Unknown

7 6 5 4 3 2 1 0

Design

Design

Battery

Battery

Software Functional Overview

Functio

n

Address

0Ah

*3

0Ch

*3

0Eh

*3

10h

*3

12h

*3

Regist

er

R/W

Name

capacit
y of
Warnin
g

capacit
y of
Low

capacit
y
Granul
arity 1

capacit
y
Granul
arity 2

Model
number R(/W) DATA[15:0] *1 - 0xffff 0x0000 [Not support]

R(/W) DATA[15:0] *1 - 0xffff

R(/W) DATA[15:0] *1 - 0xffff

R(/W) DATA[15:0] *1 - 0xffff

R(/W) DATA[15:0] *1 - 0xffff

Bit Number

Logic Default Description

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

14h

*3

16h

*3

Serial
Number R(/W) DATA[15:0] *1 - 0xffff 0x0000 [Not support]

CELL_TYPE [3:0] This
code depends on battery
data format. In the future,
this code may be added.

0x00: NiMH
0x01: Li-ion

0x10: Non-rechargeable
battery (Reserved)

Batter
y type

R(/W)

DATA[15:

8] *1

All bits

are 0

CELL_T

YPE
[7:0]

- 0xffff

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7 6 5 4 3 2 1 0

All bits

should be described in the

name

7 6 5 4 3 2 1 0

C R I T C H G DCHG

[ _BST

present

[ _BTP

Software Functional Overview

Functio

n

Functio

n

1st

Battery

]

1st

Battery

]

2nd

Battery
[ _BIF ]

Address

18h

*3

Address

1Ah

*3

1Ch

*3

1Eh

*3

20h

*3

22h

24h

to

3Ch

Regist

er

R/W

Name

OEM
Inform
ation

Regist

Name

Battery
State R (/W)

Battery
Presen
t rate

Battery
Remai
ning
Capaci
ty

Battery
Voltag

e
Battery

Trip
Point

R(/W)

er

R/W

R
(/W)

R
(/W)

R
(/W)

R/W

*2 *2 *2 *2

Bit Number

DATA

[15:8]

*1

are 0

DATA[15:3]

All bits are 0

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 -

Vender

[7:0]

Bit Number

*1

Logic Default Description

Vender [7:0] This code
depends on battery data
format.

And the following name
ASL with the same

character code.
In the future, these codes

will be added.

- 0xffff

Logic Default Description

- -

0x000

0: “MoliEnergy”
1: “Panasonic”
2: “” (SANYO

does not agree the vender

display)
3: “TBCL”

(Toshiba)
4: “Sony”

DCHG=1:
CHG =1:
CRIT =1:

0x0000-0xfffe(mW)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mV)
0xffff: Unknown

0x0000: Clear the trip
point

0

0x0001-0xffff(mWh)

*2 *2

The battery is
discharged

The battery is
charged

The battery is
critical
(Empty)

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7 6 5 4 3 2 1 0

[ _BST

[ _BTP

Battery

Charge

Battery

Battery

Charge

Battery

ery

Software Functional Overview

Functio

n

*3

2nd

Battery

]

2nd

Battery

]

-

1st

Battery

[_BIF]

Regist

Address

3Eh

to

44h

*3

46h *2 *2 *2 *2

48h

49h

4Ah

er

R/W

Name

*2 *2 *2 *2

Last

Full

ty

R
(/W)

R
(/W)

R
(/W)

data
Size

Design
capacit
y

Capaci

Bit Number

DATA [7:0] - -

DATA [23:16] *1 *7 - 0xff

DATA [23:16] *1 *7 - 0xff

Logic Default Description

*2 *2

*2 *2

0x01: DATA size is
3byte.(PMU06A)

0x00: DATA size is 2 byte.
(PMU06) *8

PMU06A use this data
with 02/03h. *7 *8

PMU06A use this data
with 04/05h. *7 *8

1st

Battery
[_BST]

1st

Battery
[_BTP]

2nd

Battery

[_BIF]

2nd

Battery
[_BST]

2nd

Battery
[_BTP]

4Bh

4Ch

4Dh

4Eh

4Fh

50h

Remai
ning

Capaci
ty

Trip
Point

Design
capacit
y

Last

Full

Capaci

ty

Remai
ng
Capaci
ty

Batt
Trip

Point

R

DATA [23:16] *1 *7 - 0xff

(/W)

R

DATA [23:16] *1 *7 - 0x00

(/W)

R

DATA [23:16] *1 *7 - 0xff

(/W)

R/(/W

DATA [23:16] *1 *7 - 0xff

)

R

DATA [23:16] *1 *7 - 0xff

(/W)

R

DATA [23:16] *1 *7 0x00

(/W)

PMU06A use this data
with 1E/1Fh. *7 *8

PMU06A use this data
with 22/23h. *7 *8

PMU06A use this data
with 26/27h. *7 *8

PMU06A use this data
with 28/29h. *7 *8

PMU06A use this data
with 42/43h. *7 *8

PMU06A use this data
with 46/47h. *7 *8

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7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

available when PMU slave

D O N E A L R M R E S

RES

RE

S

available when PMU slave

Software Functional Overview

Functio

n

Functio

n

PMU

Access

SMBus

Address

51h

to

6Bh

*3

Address

6Ch

6Dh

6Eh

6Fh

70h

*7

Regist

er

Name

Reserv
ed

Regist

er

Name

PMU_L

OW_

ADR

PMU_

HIG_

ADR

CHEC

K_

SUM

PMU_
DATA

SMB_
PTCL

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W PROTOCOL [7:0] - -

Bit Number

Don’t care - -

Bit Number

DATA [7:0] - -

DATA [15:8] - -

DATA [7:0] - -

DATA [7:0] - -

Logic Default Description

Logic Default Description

These registers are
mode or charger mode is

selected.
For detail information,

refer to PMU slave
communication section in
this document

71h

*7

72h

73h
74h

to

93h
94h

95h

96h

to

97h

SMB_
STS

SMB_
ADDR

SMB_
CMD

SMB_
DATA

[0-31]
SMB_

BCNT
SMB_
ALAR

M_
ADDR
AMB_
ALAR

M_
DATA

[0-1]

R/W

R/W

R/W

R/W

R/W

R
(/W)

R
(/W)

STATUS

[4:0]

ADDRESS

[6:0]

COMMAND - -

DATA - -

RES

BCNT [4:0] - -

[7:5]

ADDRESS [6:0]

DATA - -

- -

- -

- -

For detail information,
refer to ACPI 1.0
specification

[13.9 SMBus Host
controller Interface via
Embedded controller]

These registers are not
mode or charger mode is

selected.

The PMU06 has access
protect function for the
EEPROM in the battery,
to cancel the protection,
set the access protect
cancel bit.

For detail, refer to
SMBus section

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7 6 5 4 3 2 1 0

PRT

protection is

7 6 5 4 3 2 1 0

available when PMU slave

D O N E A L R M R E S

RES

RE

S

available when PMU slave

Software Functional Overview

Functio

n

Reserv

ed

Functio

n

PMU

Access

SMBus

Address

98h

99h

to

9Fh

Address

6Ch

6Dh

6Eh

6Fh
70h

*7

71h

*7

72h

73h
74h

to

93h
94h

95h

Regist

er

Name

SMB_
CNRL

Reserv
ed

Regist

er

Name

PMU_L

OW_

ADR

PMU_

HIG_

ADR

CHEC

K_

SUM

PMU_

DATA

SMB_
PTCL

SMB_
STS

SMB_
ADDR

SMB_
CMD

SMB_
DATA

[0-31]
SMB_

BCNT
SMB_
ALAR

M_
ADDR

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W PROTOCOL [7:0] - -

R/W

R/W

R/W

R/W

R/W

R
(/W)

Bit Number

RES [7:1]

Don't care - -

Bit Number

DATA [7:0] - -

DATA [15:8] - -

DATA [7:0] - -

DATA [7:0] - -

STATUS

[4:0]

ADDRESS

[6:0]

COMMAND - -

DATA - -

RES

BCNT [4:0] - -

[7:5]

ADDRESS [6:0]

Logic Default Description

0x00

Logic Default Description

- -

- -

- -

TheSMBus

PRT =1:

These registers are
mode or charger mode is

selected.
For detail information,

refer to PMU slave
communication section in
this document

For detail information,
refer to ACPI 1.0
specification

[13.9 SMBus Host
controller Interface via
Embedded controller]

These registers are not
mode or charger mode is

selected.

The PMU06 has access
protect function for the
EEPROM in the battery,
to cancel the protection,
set the access protect
cancel bit.

For detail, refer to
SMBus section

address (A8­AE)

cancelled.

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7 6 5 4 3 2 1 0

PRT

protection is

7 6 5 4 3 2 1 0

*3

O N

AC adapter

*3

*3

T P E M P L O WWA R E R R D C H G C H G C O N

*3

*3

Software Functional Overview

Functio

n

Reserv

ed

Function

Status

Address

96h

to

97h

98h

99h

to

9Fh

Addr

ess

A0h

ADP_STS R(/W

Regist

er

Name

AMB_
ALAR

M_
DATA

[0-1]

SMB_
CNRL

Reserv
ed

Register

Name

R/W

R
(/W)

R/W

R/W

R/W

)

Bit Number

DATA - -

RES [7:1]

Don't care - -

Bit Number

RES [7:1]

Logic Default Description

0x00

Logic

C

- -

PRT =1:

Defau

lt

TheSMBus
address (A8­AE)

cancelled.

Description

CON =
1:

is
connected

A1h

A2h

A3h

A4h

BAT1_ST
S

(1st
Battery)

BAT2_ST
S

(2nd
Battery)

Reserve
d

BAT1_C
AP

R(/W
)

R(/W
)

R/W
R(/W

)

- -

B

- -

Don’t care - -

BCAP - -

Battery trip
point is

BTP
=1:

EMP
=1:

LOW
=1:

WAR=1
:

ERR
=1:

DCHG=
1:

CHG=1
:

CON=1
:

0x00-0x64 = 0­100(%)

detected.
Battery is

empty.
Battery is

Low
battery
state.

Battery is
Warning
state.

Battery is
Error state.

Battery is
discharged
.

Battery is
charged.

Battery is
connected.

FIC MD02 Service Manual 3-25

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7 6 5 4 3 2 1 0

*3

*3

R E S

same time, the least

*5

*5

*5

0

To clear the notified

event flag without

unexpected event

loss, clear the

corresponding bit

For this operation,

this register has

special writing

(STS_X) AND

*5

B T P S M B A L R G P I

E

B A T B A T A D P

Software Functional Overview

Function

Addr

ess

A5h

A6h

A7h

A8h

A9h

AAh

ABh

Register

Name

BAT2_C
AP

Reserve
d

SMB_Ale
rt_

ADDR

GPIO-A_
EVT_ST

S
GPIO-B_
EVT_ST

S

GPIO-C_
EVT_ST

S

RUN_
EVT_ST

S

R/W

R(/W
)

R/W

R/W ADDRESS[6:0]

R/W

R/W 0 STS_B [6:0] 0x00

R/W 0 0 0 0 0

R/W

Bit Number

BCAP - -

Don’t care - -

STS_A [7:0] 0x00

STS

_C

[1:0]

R

S

Logic

- 0x00

Read
0:No event
1:EVT

detection
Write
0:Clear

event
1:Ignore

Read
0:No event
1:EVT

Defau

lt

0x00

0x00

Description
0x7F =

Unknown
0x80 = Not

installed

SMBAlert output
device address

The alert response
function is available
when this register is
cleared (0x00) only.

When the several
devices assert the
alert signal at the

address is stored to
this register. And
when this register
is cleared , next
alert address is
stored to this
register.

flag only.

manner as follows.

STS_X

(Written data)

BTP2 =1:
SMB

=1 :

BTP2
event is
detected

SMBus

ß

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7 6 5 4 3 2 1 0

*5

2

T O

2 1

*5

T H

*5

T H

*5

R R L O W H I G H

To clear the notified

event flag without

unexpected event

loss, clear the

corresponding bit

For this operation,

er has

special writing

(STS_X) AND

B T P 2 S M B A L R T

ADP

Software Functional Overview

Function

Addr

ess

ACh

ADh

AEh

AFh

Register

Name

WAKE_
EVT_ST

S

RUN_
EVT_ST

S_2
WAKE
EVT_ST

S_2

THERMA
L_EVT_S
TS

R/W

R/W

R/W Reserved [7:1]

R/W Reserved [7:1]

R/W

Bit Number

E

Reserved

[7:3]

Logic

detection
Write
0:Clear

event
1:Ignore

Defau

Description

lt

ALRT=1
:

GPIO
=1 :

BATn=1 :
ADP

=1 :
TH

=1 :
HIGH=1 :
LOW

=1 :
ERR

=1 :

0x00

0x00

0x00

flag only.

this regist
manner as follows.

0x00

STS_X

event is
detected.

SMBAlert
is
detected.

GPIO
event is
detected.

Battery
event is
detected.

Battery
event is
detected.

Thermal
event is
detected

High
alarm
point is
detected.

Low
alarm
point is
detected.

Polling
communi
cation
failure
with retry.

ß

Event/

GPIO

Control

B0h

B1h

EC_RUN
_

ENB
EC_WAK

E_
ENB

R/W

R/W

0: Disable
1: Enable

RES[4:1]

0: Disable
1: Enable

FIC MD02 Service Manual 3-27

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(Written data)

BTP2
:

0x00

SMB
:

ALRT

0x00

:
ADP:

BTP2 event
SMBus

event.
SMBAlert

event.
Adapter

event.

7 6 5 4 3 2 1 0

B T P E M P L O WWA R E R R C A P C / D CO

N

DATA_C

Software Functional Overview

Function

Addr

ess

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

Register

Name

BATT_R
UN_

ENB

BATT_W
AKE

_ENB

GPIO-A_
IO_CON

F
GPIO-A_
DATA
GPIO-A_
RUN_EN

B
GPIO-A_

EVT_PO
L

GPIO-A_
WAKE_E

NB
GPIO-B_
IO_CON

F
GPIO-B_
DATA
GPIO-B_
RUN_EN

B
GPIO-B_

EVT_PO
L

GPIO-B_
WAKE_E

NB

GPIO-C_
DATA

R/W

R/W

R/W

R/W

R/W

R/W RUN_ENB_A [7:0]

R/W

R/W

R/W 1 CONF_B [6:0]

R/W 0 DATA_B [6:0] -

R/W 0

R/W 0 POL_B [6:0]

R/W 0

R/W

Bit Number

CONF_A [7:0]

DATA_A [7:0] -

POL_A [7:0]

WAKE_ENB_A

[7:0]

RUN_ENB_B

[6:0]

WAKE_ENB_B

[6:0]

RES
[7 :4]

*4

[3:0]

Logic

0: Disable
1: Enable

0: Disable
1: Enable

0: Input
1: Output

0: Disable
1: Enable

0: Falling
edge

1: Rising
edge

0: Disable
1: Enable

0: Input
1: Output

0: Disable
1: Enable

0: Falling
edge

1: Rising
edge

0: Disable
1: Enable

-

Defau

0x00

0x00

0x00

0x00

0x00

0x00

0x80

0x00

0x00

0x00

Description

lt

Battery trip
point

BTP:

Empty.

EMP:

Low battery

LOW:

Warning

WAR:

Error

ERR:

Capacity

CAP:

learning

C/D:

Charge/Disc
harge

CON:

Battery
presence

For detail
information, refer to
GPIO section in this
document.

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7 6 5 4 3 2 1 0

0

C

0

E_

_C

Software Functional Overview

Function

Event/

GPIO

Control

Addr

ess

BFh

C0h

C1h

Register

Name

GPIO-C_
RUN_EN

B

GPIO-C_
EVT_PO

L

GPIO-C_
WAKE_E

NB

R/W

R/W 0 0 0 0 0

R/W 0 0 0 0 0

R/W 0 0 0 0 0

Bit Number

[1:0

0

RU
N_

EN

0: Disable

B_

1: Enable

]

PO

0: Falling

L_

edge

C

1: Rising

[1:

edge

0]

WA

K

0: Disable

EN

B

1: Enable

[1:

0]

Logic

Defau

lt

0x00

0x00

0x00

Description

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7 6 5 4 3 2 1 0

W A K E S C I

R E S

Q _ R U N

W A K E _ O U T SUS_X

output when

=0: Runtime

event ststus

=1: Runtime

event status

Query data.

Software Functional Overview

Function

Addr

ess

Register

Name

R/W

Bit Number

Logic

Defau

lt

Description

=0: Wake#
output is
“Level”.

=1: Wake#
output is
“Pulse”.

=0: SCI is
always
output by
event

detection
and
SCI_EVT
shows

the
query data
is stored.

And
next SCI is
not output

until
SCI_EVT is
cleared.

=1: SCI is

WAKE

SCI

Q_RU
N

WAKE
_OUT

SUS_X

C2h

EVT_CO
NT

R/W

RES

[7:6]

0x00

*

4

3-30 FIC MD02 Service Manual

the

command
set is not
executed

and
OBF=0.

SCI_EVT
shows the
output

SCI is
for event
notification.

is

reflected to
RUN_EVT_
STS

register.

is

reflected to

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7 6 5 4 3 2 1 0

T

H

To

*6

*6

*6

H

R D Y #

H G 2 CH

G1

Software Functional Overview

Function

Register

Addr

ess

Name

EC_RUN
_

C3h

ENB_2
EC_WAK

C4h

E_
ENB_2

C5h

Reserved R/W
C7h
C8h

GPI_AD0 R AD0_DATA [7:0]

C9h

GPI_AD1 R AD1_DATA [7:0]

CAh

Reserve

d

D/A_CO

CBh

NT

R/W

R/W

R/W

R/W

R/W

Bit Number

Reserved [7:1]

Don’t care

DATA [7:0] - 0xff

Logic

0: Disable
1: Enable

0: Disable
1: Enable

- -

- -

- -

Don’t care - -

C

Defau

lt

0x00

0x00

Description

TH: Thermal event

For detail
information, refer to
GPIO section in this
document.

0x00-0xfe: D/A
converter output
data

0xff : Battery
capacity(%) output

Battery
control

D0h

D1h

BAT_CH

G_

CONT

BAT_DC

H_

PRI

G

RES[7:

R/W

R/W RES[7:3]

_

5]

RE

S

[3:2

]

C

PAT
[2:0]

- -

- 0x00

CHG_RDY# =0 :
Charge ready

CHGn =1 :
The nth battery is
charged

Battery discharge
priority

0 : 2 1
1 : 1 2
2 : 2 1
3 : 2 1
4 : 1 2
5 : 1 2

6 : Same as 0
7 : Simultaneously

discharge (Read
only :

This data can be
set using PMU
register)

FIC MD02 Service Manual 3-31

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7 6 5 4 3 2 1 0

C H G 2 DCHG1

*3

Software Functional Overview

Function

Addr

ess

D2h

D3h

D5h

D7h

D8h

D9h

Dah

Register

Name

BAT_DC
H_

CONT

BAT_WA
R_

ABS

BAT_LO
W_

ABS

BAT_WA
R_

REL

BAT_LO
W_

REL

FULL_D
ATA

CC_CUR
_

DATA

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R DATA [7:0] - 0x00

Bit Number

D

RES[7:2]

DATA[15:0] *1 -

DATA[15:0] *1 -

DATA [7:0] - 0x10

DATA [7:0] - 0x06

DATA [7:0] - 0xbe

Logic

0: Not
discharge

1: Discharge

Defau

lt

-

0x00

00

0x00

00

Description

The discharge
battery can be
selected one of the
batteries can be
discharged.

Absolute capacity
battery Warning
detection point

0x0000-0xffff
(mWh)

Absolute capacity
battery Low
detection point

0x0000-0xffff
(mWh)

Relative capacity
battery Warning
detection point

00-C8h (0-100%
step 0.5%)

Relative capacity
battery Low
detection point

00-C8h (0-100%
step 0.5%)

Full charge cancel
point

00-C8h (0-100%
step 0.5%)

Battery charging
current setting

0x01-0xff (0.02-

5.10A step 0.02A)
0x00 Depends

on the battery
This register is

“read only”, to
change the value,
use the register in
PMU registers area.

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7 6 5 4 3 2 1 0

To

To

C _ R E G

B A Y _ L E D PO

W_ L ED

EC_REG =1:

does not

initialize

system

power is

indicates

discharg

e status

LED_BA

when the

battery is

installed.

O

S_

ST

S

Software Functional Overview

Function

PMU
control

Register

Addr

ess

DBh

BTP2 R/W
DCh

DDh

Reserved R/W
DFh

PMU_CO
E0h

NT

Name

R/W

R/W RES[7:3]

Bit Number

DATA [15:0] -

Don't care - -

Logic

E

- 0x00

Defau

Description

lt

0x0000: Clear the
trip point

0x0001-0xffff :
(mWh)

0x00

When all of the

00

battery’s capacities
lesser than this
setting value, the
BTP2 is detected if
event is enabled.

BAY_LED
=1:

POW_LED
=1:

PMU

EC
register
when

off.
PMU

the
Battery

to the
Y#n,

ACPI_AC

C_

E1h

ENB

R/W

RES [7:1]

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- 0x00

OS_STS
= 1:

= 0:

The
Power
LED
blink

ACPI
mode

Legacy
mode

7 6 5 4 3 2 1 0

RES

If the received data

ue, the

event will be

If the received data

LE this value, the

event will be

Signed value

To

After writing to the

addressed

Set the 00h to this

Software Functional Overview

Function

Thermal
Sensor
Polling

Register

Addr

ess

Name

OFF_TIM

E2h

E

POLLING
_

E3h

ADDRES
S

HIGH_

E4h

ALARM

LOW_

E5h

ALARM

POLLING
_

E6h

INTERVA
L

POLLING
_

E7h

DATA
HARDW

ARE_SH

E8h

UT_DOW
N

POLLING
_

E9h

COMMA
ND

RETRY_

EAh

COUNT

EBh

Reserved R/W

EFh

R/W

R/W

R/W

R/W

R/W

R/W

R(/W
)

R/W

R/W

R/W

Bit Number

DATA [7:0] - 0x64

Slave Address

[6:0]

DATA [7:0] Signed value 0x00

DATA [7:0] Signed value 0x00

DATA [7:0] 0x00

DATA [7:0] Signed value 0x00

DATA [7:0]

DATA [7:0] 0x00

DATA [7:0] 0x10

Don't care

Logic

0x00

Defau

Description

lt

Power switch over
ride function timer

01h-FFh (0.1-

25.5esc step

0.1sec)
00h : Reserved

Address: 0x00-0x7F
The polling slave

address setting
If this address is 00,

the Polling is
disabled.

GE this val
detected.

detected.
0x00 :Pollin

g disable
0x01 – 0xFF [x

250ms] (250ms to

63.75sec)
This register shows

data at latest
polling.

If the thermal
sensor read value

0x7D

GE this value, the
PMU automatically
off the power.

Polling command
(data register)
address.

0x00 - 0xFF: Retry
count value (0-255)

PMU
control

F0h

BURST_
FLG_CL
R

R/W

DATA [7:0] - -

3-34 FIC MD02 Service Manual

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register
A8h-AFh,

register.

7 6 5 4 3 2 1 0

To

Software Functional Overview

Function

Register

Addr

ess

F1h

Reserved R/W
FFh

Name

R/W

Bit Number

Don't care

Logic

Defau

Description

lt

3.6.3 Security

The user may enter up to eight standard text characters for a password. The password
includes two levels. The higher priority is the Supervisor Password. The lower priority is the
User Password. The Supervisor Password can access all the system resource, while the User
Password may not access the floppy disk when it is protected by Supervisor Password. Also,
the User Password may not access the floppy disk when the Supervisor Password protects it.

When the security function is enabled, the system will request the user to enter password
during the following situation:

• Power On → The system will prompt the user to enter the password before booting
the OS. If the user key in the wrong password for 3 times, then the system will halt..

• Entering CMOS Setup → The system will prompt the user to enter the password
before entering the CMOS Setup. If the user keys in the wrong password for 3 times,
then the system will halt.

3.7 CMOS Setup Utility

The Setup utility is used to configure the system. The Setup contains the information
regarding the hardware for boot purpose. The changed settings will take effect after the
system rebooted. Refer to Chapter 1 on running BIOS Setup Program for more detailed
information.

3.8 Definitions of Terms

10Base-T (Ethernet) -

10Mbps (10 megabits per second).

100Base-T (Fast Ethernet) ­transfer rates up to 100Mbps.
ACPI

- Advanced Configuration and Power Management Interface, a power

management specification developed by Intel, Microsoft, and Toshiba.

CardBus -

supporting a wider bus (32 bits instead of 16 bits), CardBus also supports bus mastering
and operation speeds up to 33MHz.

Clock Throttling

started at a known duty cycle using the STPCLK# pin to enter and exit Stop Grant mode.
Clock throttling is used for power saving, thermal management, and reducing the
processing speed.

DIMM (SODIMM) -

chips. A Single In-line Memory Module (SIMM) has a 32-bit path to the memory chips
whereas a DIMM has 64-bit path. Because the Pentium processor requires a 64-bit path
to memory, you need to install SIMMs two at a time. With DIMMs, you can install one
DIMM at a time. SODIMM is Small Outline Dual In-line Memory Module used in
notebook computers.

DMI -

The 32-bit version of the PCMCIA PC Card standard. In addition to

Desktop Management Interface, an API to enable software to collect information

A networking standard that supports data transfer rates up to

A relatively new networking standard that supports data

– South bridge function that allows the CPU clock to be stopped and

Dual In-line Memory Module, a small circuit board that holds memory

FIC MD02 Service Manual 3-35

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Software Functional Overview

about a computer environment about a computer environment. For example, using DMI
a program can determine what hardware and expansion boards are installed on a
computer.

GPI - General Purpose Input.
GPO ­Lid Switch

be turned off.

MPEG-2 -

to the family of digital video compression standards developed by the group. There are
two major MPEG standards : MPEG-1 and MPEG-2. The most common
implementations of the MPEG-1 standard provide a video resolution 352x240 at 30
frames per second(fps). A newer standard, MPEG-2, offers resolution of 720x480 and
1280x720 at 60 fps, with full CD-quality audio.
North Bridge - The CPU to PCI interface, also contains the memory and cache
controllers.

South Bridge - The PCI to ISA interface, also contains many legacy devices.
SMM
SMI

enter SMM. SMM functions include power management, USB legacy keyboard control,
security, hot keys, and thermal monitoring.
SMB - System Management Bus, that is used for managing smart batteries, reading
SDRAM configuration information, and other miscel1aneous system function.

TBD -

discussed with related engineers.

Ultra DMA-33 ­burst mode data transfer rates of 33.3 MBps.
USB -

single USB port can be used to connect up to 127 peripheral devices, such as mice,
modems, and keyboards. USB also supports Plug-and-Play installation and hot plugging.

General Purpose Output.

- A switch that indicates the notebook LCD Panel has been closed and it can

Moving Picture Experts Group, a working group of ISO. The term also refers

- System Management Mode, Mode of operation while an SMI is active.

- System Management Interrupt, non-maskable interrupt that causes the system to

To Be Discussed. The mentioned specification is not final that should be

A protocol developed by Quantum Corporation and Intel that supports

A new external bus standard that supports data transfer rates of 12 MBps. A

3-36 FIC MD02 Service Manual

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