Fic mb02 Service Manual CHAP3

Chapter

Software Functional Overview

3.1 Overview

The MB02 is an IBM PC/AT compatible Notebook PC , which supports the Intel Micro­PGA Pentium M CPU processors family. The following are the major features that
MB02 supports.

Microsoft PC99 logo and Win XP logo approval.

§

Offer 1024x768 XGA display with 13.3 XGA LCD panel.

§

§ Support ACPI 1.0B (or above).

§ Support PCI 2.1 (or above).

§ Support AGP 2.0.

Support SMBIOS 2.3.

§

Support DDR266/200 SDRAM.

§

Support 100/133 Mhz CPU front side bus.

§

3.2 Summary of the BIOS Specification

The summary of the BIOS specification is as the below description:

Controller Chip Description

Shadow Always enable VGA and System BIOS shadow
Display

Hard Disk

Multi Boot Allow the user to select boot from FDD, HDD and CD-ROM
Plug and Play Support PnP Run Time Service and conflict-free allocation of

Smart Battery Support BIOS interface to pass battery information to the

Keyboard Controller Support Fn hot keys, one Win95 hot keys, built-in Glide Pad.
PCMCIA Compliant with PCMCIA 2.1 specification

§ System auto detects LCD or CRT presence on boot and lid

closed.

§ Support Panning while LCD in a display resolution greater

than supported.

§ Support Microsoft Direct 3D.

§ Support AGP 4x BUS.

§ Enhanced IDE spec.

Support auto IDE detection.

§

§ Support LBA mode for larger capacity HDD.

§ Support Ultra DMA 33/66/100.

§ Support Fast PIO mode 1-4 transfer.

§ Support 32 bit PIO transfer.

§ Support Multi-Sector transfer.

§ Support SMART monitoring.

resource during POST

application via SMBus

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Software Functional Overview

Power Management
Support (ACPI Mode)

The power management is compliant with ACPI 1.0B

specification and supports the following power state:

§ S0 (Full-On) Mode

§ S3 (STR) Mode

§ S4 (STD) Mode

§ S5 (Soft-Off) Mode

3.3 Subsystem Software Functions

This section provides introduction on the software functions of the notebook subsystems and
BIOS related function.

3.3.1 Key Chipset Summary

Following are the main chipsets used in the notebook:

Controller Chip Vendor Description

Processor
North Bridge
South Bridge
Video Controller
PCMCIA Controller
Audio Chip
Audio Codec
Keyboard Controller
PMU Controller
ROM BIOS
Clock Generator
Temperature Sensor
IEE 1394

LAN
Modem

Intel Mobile Banias
Intel Montara GM
Intel ICH4
Intel Embedded in Montara GM
RICOH R5C551
Intel South Bridge Integrated
Intel ICH4
Misubishi M3885x
NEC PMU08
SST 49LF004A
IMI CY28346
NS MAX6690
RICOH R5C551

Intel ICH4
Intel MDC AC’97

3.3.2 System Memory

The system memory consists of SDRAM memory on 64-bit bus and the module size options
are 128/256/512/1GMB upward. The BIOS will automatically detect the amount of memory
in the system and configure CMOS accordingly during the POST (Power-On Self Test)
process. This must be done in a way that requires no user interaction.

Base SO-DIMM DRAM

slot

Expansion SO-DIMM DRAM

slot

Total Size

(Bank 0&1) (Bank 2&3)

NIL 128MB 128MB
NIL 256MB 256MB

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Software Functional Overview

NIL 512MB 512MB
128MB NIL 128MB
128MB 128MB 256MB
128MB 256MB 384MB
128MB 512MB 640MB
256MB NIL 256MB
256MB 128MB 384MB
256MB 256MB 512MB
256MB 512MB 768MB
512MB NIL 512MB
512MB 128MB 640MB
512MB 256MB 768MB
512MB 512MB 1024MB

3.3.3 Video

The Video subsystem used External DDR memory of Video memory. The system will
support the true ZV port, the Microsoft Direct 3D assist, simultaneous display, monitor
sense for auto display on boot and VESA Super VGA function call.

Supported Video Mode

The following is the display modes supported by the SIS Mobility Video control in
LCD only, CRT only, and simultaneous mode. The VGA BIOS will allow mode sets of
resolutions greater than the panel size but only show as much mode display as will fit
on the panel.

Supported standard VGA modes:

The VGA BIOS supports the IBM VGA Standard 7-bit VGA modes numbers.

Mode Pixel Resolution Colors Memory

00h/01h 40*25 16 Text
02h/03h 80*25 16 Text
04h/05h 320*200 4 2-bit Planar

06h 640*200 2 1-bit Planar

07h 80*25 Mono Text
0Dh 320*200 16 4-bit Planar
0Eh 640*200 16 4-bit Planar

0Fh 640*350 Mono 1-bit Planar

10h 640*350 16 4-bit Planar

11h 640*480 2 2-bit Planar

12h 640*480 16 4-bit Planar

13h 320*200 256 8-bit Planar

Note: All Standard VGA Modes are limited to the standard VGA refresh rates.

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Supported extended video modes:

CRT device will support all listed VESA mode; and other devices such as PANEL & TV may
be limited to the mode support due to their characteristics.

VESA

Mode

100h 640 x 400 8-bit Packed 70 2MB
101h 640 x 480 8-bit Packed 60, 72, 75, 85 2MB
102h 800 x 600 4-bit Planar 60, 72, 75, 85, 100 2MB
103h 800 x 600 8-bit Packed 60, 72, 75, 85, 100 2MB
104h 1024 x 768 4-bit Planar 43(I), 60, 70, 75, 85, 100 2MB
105h 1024 x 768 8-bit Packed 43(I), 60, 70, 75, 85, 100 2MB
106h 1280 x 1024 4-bit Planar 43(I), 60, 75, 85
107h 1280 x 1024 8-bit Packed 43(I), 60, 75, 85
10Eh 320 x 200 16-bit Packed 70
10Fh 320 x 200 32-bit Unpacked 70
111h 640 x 480 16-bit Packed 60, 72, 75, 85
112h 640 x 480 32-bit Unpacked 60, 72, 75, 85
114h 800 x 600 16-bit Packed 60, 72, 75, 85, 100
115h 800 x 600 32-bit Unpacked 60, 72, 75, 85, 100
117h 1024 x 768 16-bit Packed 43(I), 60, 70, 75, 85, 100
118h 1028 x 768 32-bit Unpacked 43(I), 60, 70, 75, 85, 100
11Ah 1280 x 1024 16-bit Packed 43(I), 60, 75, 85
11Bh 1280 x 1024 32-bit Unpacked 43(I), 60, 75, 85
11Dh 640 x 400 16-bit Packed 70
11Eh 640 x 400 32-bit Packed 70
120h 1600 x 1200 8-bit Packed 48(I), 60, 75, 85
122h 1600 x 1200 16-bit Packed 48(I), 60, 75, 85
124h 1600 x 1200 32-bit Unpacked 48(I), 60, 75, 85
12Ah 640 x 480 24-bit Packed 60, 72, 75, 85
12Bh 800 x 600 24-bit Packed 60, 72, 75, 85, 100
12Ch 1024 x 768 24-bit Packed 43(I), 60, 70, 75, 85, 100
12Dh 1280 x 1024 24-bit Packed 43(I), 60, 75, 85
12Eh 320 x 200 8-bit Packed 70
131h 320 x 200 8-bit Packed 72
133h 320 x 200 16-bit Packed 72

134h 320 x 200 32-bit Packed 72
13Bh* 1400 x 1050 8-bit Packed 60, 75
13Ch* 1400 x 1050 16-bit Packed 60, 75
13Eh* 1400 x 1050 32-bitUnpacked 60, 75

Pixel

Resolution

Memory Model Refresh Rates In (Hz) Minimum

Memory

2MB

2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
4MB
4MB
8MB
2MB
2MB
2MB
4MB
8MB
2MB
2MB
4MB
4MB
2MB
2MB
2MB
2MB
2MB
4MB
8MB

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Software Functional Overview

141h 400 x 300 8-bit Packed 72
143h 400 x 300 16-bit Packed 72
144h 400 x 300 32-bitUnpacked 72
151h 512 x 384 8-bit Packed 70
153h 512 x 384 16-bit Packed 70
154h 512 x 384 32-bitUnpacked 70
171h 720 x 480 8-bit Packed 75
173h 720 x 480 16-bit Packed 75
174h 720 x 480 24-bit Packed 75
175h 720 x 480 32-bitUnpacked 75
176h 720 x 576 8-bit Packed 75
178h 720 x 576 16-bit Packed 75
179h 720 x 576 24-bit Packed 75

17Ah 720 x 576 32-bitUnpacked 75

Note: “*” The modes may not be available. Their availability should be determined by VESA
function calls.

2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB
2MB

Panel Type Initialization

The VGA BIOS will issue INT 15h function call during POST. This function call
allows the system BIOS to specify the panel type to the VGA BIOS. The system BIOS
should get the panel type from GPIO pins before the VGA chip initialized, and pass
this information to VGA BIOS through INT 15 Function 4E00h.

LCD Panel ID pin Definition:

VT82C686B GPI Pins

GPI
[23]

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0

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GPI
[17]

GPI
[11]

GPI
[10]

ID0
ID1

ID2

ID3

Panel Type

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Software Functional Overview

1 1 0 1

1 1 1 0

1 1 1 1

3.3.4 Enhanced IDE

The system BIOS must be ready to support 4 IDE devises on two controllers. The BIOS
support Ultra DMA33/66/100 and also supports automatic configuration of drives using
both the LBA and CHS large drive remapping method. In addition to supporting
standard drives through an auto-configuration process that does NOT require user
involvement or confirmation. The system should automatically do this at POST time in a
way that is transparent to the user. If a drive is connected to the bus, the drive should be
automatically recognized, configured and available for use under MS-DOS 6.2x.

3.3.5 Audio

The audio subsystem will support the requirements identified by the AC’97 specification.
Both software and hardware will control the volume level for the internal audio subsystem. In
addition to the volume control, the user will be able to mute the sound to completely cut off
the volume using both software and hardware.

3.3.7 PCMCIA

The PCMCIA controller chip of the notebook provides the following features:

• Individually accessed, dual-buffer implementation

Support for 2 separate CardBus slots (one type III or two type II stacked)

•

• Support for 3.3v, 5v and 12v (flash programming) cards

3.3.8 LED Indicator

The table below lists down the functions of the Status LED indicator:

Indicator Function Description
IDE accessing LEDΠThis LED will turn on while accessing the IDE Device.
Battery Charging LED Turn on (Blue) – Battery is under charging mode

Turn off – Battery full charged or no battery

CapsLock LEDΠThis LED will turn on when the function of CapsLock is active.
ScrollLock LEDΠThis LED will turn on when the function of ScrollLock is active.
NumLock LEDΠThis LED will turn on when the function of NumLock is active.
Power Status LED Blue – System is powered on.

Blue Blinking- System is entered suspend mode.
Trun off – Battery Low.

Mail LEDΠThis LED will turn on while Mail was arrived.

i

Π- These LEDs will be turned off during Suspend mode.

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170~177, 1F0~1F7,

220~22F, 300~301,

Software Functional Overview

3.3.9 Hot Keys Definition

All Hot keys must be active at all times under all operation systems.

Function Function Handler
Fn + F3 Toggle Display (LCD/CRT/TV/LCD&CRT) BIOS Handler

Fn + F2 RF ON/OFF BIOS Handler
Fn + F6 System Speaker On/Off BIOS Handler

Fn + F8 Brightness Increase Controlled by PMU08
Fn + F9 Brightness Decrease Controlled by PMU08
ScrLock Scroll Lock
Internet
Button
Mail Button Mail Function Key Controlled by Driver

3.3.10 Plug & Play

The BIOS supports the Plug and Play Specification 1.0A. (Include ESCD)
This section describes the device management. The system board devices and its resources are
as follows:

Device Connect

I/O IRQ DMA Memory
DMA Controller Static 00~0F, 81~8F - DMA5 ­Interrupt Controller Static 20~21, A0~A1 IRQ2 - ­System Timer Static 40~43 IRQ0 - ­RTC Static 70~71 IRQ8 - ­ISA Bus Static - - - ­System Speaker Static 61 - - ­System Board Static - - - E0000~FFFFF
PnP Mother Board Static 80 - - ­Keyboard Controller Static 60, 64 IRQ1 - ­PMU08 Controller Static 68, 6C - - ­Math Coprocessor Static F0~FF IRQ13 - ­Glide Pad Static - IRQ12 - ­Video Controller Static 3B0~3BB,

Dual IDE Controller Static

CardBus Controller Dynamic 3E0~3E1 IRQ10 - ­Audio chip Dynamic

IEEE1394 Dynamic IRQ10
Modem Dynamic 3E8~3EF IRQ10 - ­LAN Dynamic 1080~10FF IRQ10 - ­USB Host Controller Dynamic EF80~EF9F IRQ5 - -

Internet Function Key Controlled by Driver

Resources

Type

IRQ5 - A0000~BFFFF

3C0~3DF

IRQ14, 15 - -

3F6

IRQ5 DMA3 -

388~38B

,
C0000~CFFFF

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3.3.11 PCI Device

The table below summarizes the PCI IDSEL Pin Allocation:

IDSEL Pin PCI Device
Device Number Function

Number
AD23 Device 07 Function 0 RICOH Card Bus
Function 1 RICOH IEEE1394
AD17 Device 01 Function 0 MINI PCI

The table below summarizes the INT Pin Allocation:

INT Pin PCI Device
INTA CardBus/MiniPCI/LAN
INTB Cardbus/MiniPCI
INTC
INTD

The table below summarizes the PCI bus master Allocation:

Device Name

Arbiter Signal Agents

REQ00/GNT00

REQ20/GNT20
REQ30/GNT30

REQ10/GNT10 RICOH Card Bus Controller

(Master)

Function Use

3.3.12 SMBus Devices

The SMBus is a two-wire interface through which the system can communicate
with power-related chips. The BIOS should initialize the SMBus devices during
POST.

ICH4 SMBus Connection Devices

SMBus Device Host/Slave Address BIOS Need to Initialization
SO-DIMM Slave A0h/A2h Memory Auto Sizing (SPD).

CY28346
CLK Generator

Slave D2h Program the desired clock frequency

(Pin23 output 24MHz, Pin22 output
48MHz)

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PMU 08 SMBus Connection Devices

SMBus Device Host/Slave Addres

s
A7 ~

A1
PMU08 Master 10h Enable PS01 decode interface
MAX6690 (Thermal
sensor)
Battery (1st Battery) Slave A8h No Need

I/O Map

Hex Address Device
000 - 01F 8237-1
020 - 021 8259-1
022
040 - 05F 8254
060 - 064 Keyboard Controller
068 – 06C PMU08 Controller
070 - 07F RTC & NMI Mask
080 - 08F DMA Page Registers
092 System Control Port
0A0 - 0A1 8259-2
0B2 Advanced Power Management Control Port
0B3 Advanced Power Management Status Port
0C0 – 0DF 8237-2
0F0 – 0FF Math Coprocessor
170 - 177 IDE Secondary Command Block
1F0 - 1F7 IDE Primary Command Block
220 - 22F Sound Blaster
279 ISA PnP Address
330 - 333 MIDI
376 IDE Secondary Control Block
388 - 38B FM Synthesizer
3B0 - 3DF Video Controller
3E0 - 3E1 PCMCIA Controller
3F0 - 3F5, 3F7 Floppy Disk Controller
3F6 IDE Primary Control Block
A79 ISA PnP Address
CF8 – CFF PCI BUS configuration Register

ISA DMA Map

DMA Channel Device
DMA 0 Unused
DMA 1 Unused
DMA 2 Floppy Disk
DMA 3 Audio

Slave 9Ch Program the desired temperature

BIOS Need to Initialization

range

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DMA 4 Unused
DMA 5 Unused
DMA 6 Unused
DMA 7 Unused

Memory Map

Address Range Length Description
00000 - 9FFFFh 640 KB System Memory
A0000 – BFFFFh 128 KB Video Memory
C0000 – C9FFFh 40 KB Video ROM
CA000 – DBFFFh 72 KB Unused
DC000 - DFFFFh 16 KB DMI information
E0000 – FFFFFh 128 KB System ROM BIOS

IRQ Map

IRQ# Description
IRQ 0 System Timer
IRQ 1 Keyboard
IRQ 2
IRQ 3
IRQ 4
IRQ 5 Audio/VGA/USB
IRQ 6 Floppy Disk Drive
IRQ 7
IRQ 8 RTC Alarm
IRQ 9 ACPI
IRQ10 LAN / Modem or Combo, (Card Bus), IEEE 1394
IRQ11 Reserved for PCMCIA card
IRQ12 Glide Pad
IRQ13 FPU (FERR)
IRQ14 Hard Disk Drive
IRQ15 CD-ROM or DVD-ROM

3.3.13 GPIO Pin Assignment

The GPI and GPO pins connected to system devices. The BIOS can get device’s
status and control the device via the GPI and GPO pins.

ICH4 GPI pin assignment

GPIO
Number
GPIO0 PanelID0 I Panel ID setting
GPIO1 PanelID1 I Panel ID setting

GPIO2 PanelID2 I Panel ID setting
GPIO3 PanelID3 I Panel ID setting

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Signal Name Default I/O Notes

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R5C551 Hardware suspend control

Software Functional Overview

GPIO8 Q_SMI0 I 0:External K/B SMI0

1:Normal operation

GPIO11 LPC_QPME0 1 O 0:LPC_QPME0 Event Enable

1:Normal operation --

GPIO12 EC_SCI0 I 0:PMU SCI Detect

1:PMU SCI not Detect

GPIO13 PM_RI0 I 0:PMU GPIO detect

1:PMU GPIO not Detect

GPIO25 CB_HWSUS

P0

GPIO32 SPDMUX0 1 O SMBus select 1
GPIO33 SPDMUX1 1 0 SMBus select 0

3.3.14 PMU08 GPIO pin assignment

1 O

pin

GPIO
number
GPIO B6 PM_SLP_S

GPIO B5 N.C. -- -- No used
GPIO B4 N.C. -- -- No used

GPIO B1 N.C. 1 O No used
GPIO B0 N.C. -- -- No use

GPIO A7 N.C -- -- No use
GPIO A6 PCMRI0 1 I PC Card Ring event

GPIO A0 LID0 1 I LCD Open/Close Status

GPIO C1 NC -- -- No Use

GPIO B7 PM_RI0 1 O Wake Up event request

GPIO B2 N.C. -- - No Use

Signal
Name

10

Default I/O Notes Remar

1 I Suspend Plane A control for

ICH4
0: POS, STR and STD
suspend state.
1: not suspend state.

0: Ring
1: No Ring

0: LCD Close
1: LCD Open

0: Wake SMI(SCI)
1: There is no demand.

k

GPIO B0 N.C. -- -- No Use
GPIO A5 PRSTMSK0 1 O PCI Reset Mask

0: Reset Mask
1: Reset Enable

GPIO A4 PCMUTE0 1 O Mute PC Speaker
GPIO A1 N.C. -- -- No use

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Software Functional Overview

GPIO C2 CHGLED Charge Battery indicator :

1 : charging Battery
0 : Stop charging Battery

GPIO C3 N.C. -- -- No Use
GPIO C0 N.C. -- -- No Use

3.4 ACPI

General Requirements

The BIOS must meet the following general Power Management requirements:
Refers to the portion of the firmware that is compatible with the ACPI 1.0b specifications.
Support for Power ON(S0 state), Suspend-to-RAM (S3 state) , Suspend-to-Disk mode (S4
state) and Soft OFF(S5 state).

Global System State Definitions

Global system states (Gx states) apply to the entire system and are visible to the user.
Following is a list of the system states:
G0/S0 - Working:

A computer state where the system dispatches user mode (application) threads and
they execute. In this state, devices (peripherals) are dynamically having their power
state changed. The user will be able to select (through some user interface) various
performance/power characteristics of the system to have the software optimize for
performance or battery life. The system responds to external events in real time. It is
not safe to disassemble the machine in this state.

G1 - Sleeping:

A computer state where the computer consumes a small amount of power, user
mode threads are not being executed, and the system “appears” to be off (from an
end user’s perspective, the display is off, etc.). Latency for returning to the Working
state varies on the wakeup environment selected prior to entry of this state (for
example, should the system answer phone calls, etc.). Work can be resumed without
rebooting the OS because large elements of system context are saved by the
hardware and the rest by system software. It is not safe to disassemble the machine
in this state.

G2/S5 - Soft Off:

A computer state where the computer consumes a minimal amount of power. No
user mode or system mode code is run. This state requires a large latency in order to
return to the Working state. The system’s context will not be preserved by the
hardware. The system must be restarted to return to the Working state. It is not safe
to disassemble the machine.

G3 – Mechanical Off:

A computer state that is entered and left by a mechanical means. It is implied by
the entry of this off state through a mechanical means that the no electrical current is

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Software Functional Overview

running through the circuitry and it can be worked on without damaging the
hardware or endangering the service personnel. The OS must be restarted to return to
the Working state. No hardware context is retained. Except for the real time clock,
power consumption is zero.

Sleeping State Definitions

Sleeping states (Sx states) are types of sleeping states within the global sleeping
state, G1. The Sx states are briefly defined below. For a detailed definition of the
system behavior within each Sx state, refer to ACPI specification section 7.5.2. For a
detailed definition of the transitions between each of the Sx states, refer to ACPI
specification section 9.1.

S1 Sleeping State:

The S1 sleeping state is a low wake-up latency sleeping state. In this state, no

system context is lost (CPU or chip set) and hardware maintains all system context.

S3 Sleeping State:

The S3 sleeping state is a low wake-up latency sleeping state where all system
context is lost except system memory. CPU, cache, and chip set context are lost in
this state. Hardware maintains memory context and restores some CPU and L2
configuration context. Control starts from the processor’s reset vector after the wake­up event.

S4 Sleeping State:

The S4 sleeping state is the lowest power, longest wake-up latency sleeping state
supported by ACPI. In order to reduce power to a minimum, it is assumed that the
hardware platform has powered off all devices. Platform context is saved in disk.

S5 Soft Off State:

The S5 state is similar to the S4 state except the OS does not save any context nor
enable any devices to wake the system. The system is in the “SOFT” off state and
requires a complete boot when awakened. Software uses a different state value to
distinguish between the S5 state and the S4 state to allow for initial boot operations
within the BIOS to distinguish whether or not the boot is going to wake from a saved
memory image.

System Power Plane

The system components are grouped as the following parties to let the system to

control the On/Off of power under different power management modes.

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3.4.1 System Power Plane

The system components are grouped as the following parties to let the system to control the
On/Off of power under different power management modes.

The power plane is divided as following:

Power Group Power

Control Pin
+B Nil IMM, (9V~20V)
+3VA Nil RTC I/F, PMU08
+12V PWRON PCMCIA Card, AC97 Codec
+5V PWRON PCMCIA Slot 5V
+3V PWRON VGA, PCMCIA, PCMCIA Slot 3V, DRAM, Twister(DRAM

+5VS SUSB# FLASH ROM, HDD, CD-ROM, USB, Internal K/B, Glide Pad,

+3VS SUSB# ISA I/F Power, Clock Generator & Buffer (W137)
+RTCVCCS Nil RTC

3.4.2 Power Management Mode Transition Flow Chart

From a user-visible level, the system can be thought of as being one of the states in the
following diagram:

Controlled Devices

I/F), M3885x, MAX3243

Audio AMP, Fan

G2 (S5) -

Soft Off

ACPI
Boot

(SCI_EN=1)

SLP_TYPx=S5

and

SLP_EN

or

PWRBTN_OR

Wake
Event

G0 (S0) -

Working

S4BIOS_REQ

to

SMI_CMD

OEM S4 BIOS

Handler

SLP_TYPx=S1

SLP_EN

SLP_TYPx=S2

SLP_TYPx=S4

and

and

SLP_EN

SLP_TYPx=S3

and

SLP_EN

and

SLP_EN

SLP_TYPx=S4

and

SLP_EN

S1

Sleeping

S2

Sleeping

G1

S3

Sleeping

S4

Sleeping

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Software Functional Overview

3.4.3 Power States transition event

The following table summarizes the entry events and wake-up events of each power:
The following table summarize the entry events and wake-up events of each power state

Power State Entry Event Wake up Event
S3 OSPM control

Lid Close
Power Button
Sleep Button
Battery Low

Power Button
Ring Wake up
RTC Alarm
LAN Wake Up
Lid open

S4 OSPM control,

Power button
Sleep button
Lid Close
Battery Low

S5 Power Button

Battery Low
OSPM control

x OSPM: OS-directed Power Management

Power Button
RTC Alarm

Power Button

Device Power Control Methodology
Power state of local devices table

This section illustrates the power control status of each key device/component of the
system under each power management mode.

PowerState
Component
CPU Stop

L2 CACHE ON Power Down Power Off Power Off
MontaraGM ON Stop Clock Power Off (except

ICH4 ON ON Power Off (except

DRAM ON Self Refresh Self Refresh Power Off
Clock Synthesizer ON Low Power Power Off Power Off
CDROM ON Power Down Power Off Power Off
HDD ON Power Down Power Off Power Off
FDD ON Power Down Power Off Power Off
KBC ON ON Power Down Power Off
PMU08 ON ON Power Down Power Down
VGA/VRAM ON Power Down Power Down Power Off
PCMCIA ON Power Down Power Down Power Off
AUDIO ON Power Down Power Off Power Off
Audio AMP ON Power Down Power Off Power Off
LCD Backlight ON Power Off Power Off Power Off

Doze Stand By STR STD/SOff

Stop Clock Power Off Power Off

Grant

Power Off

Vcc)

Power Off (except

SUSVcc, RTCVcc )

SUSVcc, RTCVcc)

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Software Functional Overview

LAN ON Power Down Power Down Power Down
Internal Modem ON Power Down Power Down Power Down

Device Power control Methodology During S3 Mode

This section illustrates the control methodology of each device/component and its details
under Stand by mode.

Device Power Down Controlled by Description
CPU Hardware Controlled by SUSB# pin
L2 CACHE Hardware Power off
ICH4 Hardware Controlled by SUSB# pin
DRAM Software Self Refresh
Clock Synthesizer Hardware Controlled by SUSB# pin
CDROM Hardware Power off
HDD Hardware Power off
FDD Hardware Power off
KBC Software Controlled by M3885xM8 power

down command

PMU08 Sofeware Controlled by PMU08 power down

command
VGA/VRAM Software Controlled by MontaraGM
PCMCIA Software Controlled by SUSB# pin
AUDIO Hardware Controlled by ICH4
Audio AMP Hardware Controlled by BIOS
LCD Backlight Hardware Power off
LAN Hardware Controlled by Driver enter Dx status
Internal Modem Hardware Controlled by Driver enter Dx ststus

Power Button

The function of Lid Switch is depends on the ACPI aware OS.

Lid Switch (Cover Switch)

The function of Lid Switch is depends on the ACPI aware OS.

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Software Functional Overview

3.4.4 Expanding Event Through the Embedded Controller

The following figure shows the relationships between the devices that are wired to the
embedded controller, the embedded controller queries, and ACPI general

Figure 3-2 The Relationships between ACPI, Controller, and Device

SCI Source and GPE Event from PMU08

The system will issue a beep to inform user while the following SCI alerted:

PMU08 Input Event GPE Event Handler
ADPIN# AC Plug In/Out GPI12 AML Handler
BAT0# Battery Plug In/Out GPI12 AML Handler
GPIOA0 LID Event GPI13 AML Handler
GPIOA3 Keyboard SMI GPI8 AML Handler
GPIOA6 PCMCIA Ring In GPI13 AML Handler
GPIOA7 COM Port Ring In GPI13 AML Handler
THRM Thermal Event GPI12 AML Handler

Control Method Battery Subsystem

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Software Functional Overview

EC should support all the battery information to ACPI-OS

− Designed Battery capacity

Designed Voltage

−

− Designed Low battery capacity

Designed Low – Low battery capacity

−

− Latest Full charged capacity

Present Remaining capacity

−

− Present drain rate

Present voltage

−

Present Battery Status

−

ACPI BIOS should support an independent device object in the name space, and
implement the following methods.

3.4.5 Thermal Control

There are primary cooling policies that the OS use to control the thermal state of the
hardware

Cooling Policy
Action cooling Fan On Always On

Action cooling Fan High On
Fan High Off
Passive cooling Throttling CPU On
Throttling CPU Off
Critical trip point System Shutdown

Action

Temperature Setting

Over 70 oC
Below 65oC
Over 90 oC
Below 85oC
Over 110 oC

3.5 Battery Management

3.5.1 Battery Sub-system

§ The charger will stop charge the battery when the following condition is detected.

- The temperature of the system is too high

- The remaining capacity is 95% and more.
Note that the battery life is depending on different configuration running. E.g. with
CD-ROM battery life is shorter, document keyin only battery life is longer, PMU
disable battery life is short, PMU enable battery life is longer.

- Battery reading methodology is through PMU08 SMBus.

3.5.2 Battery Low

When the battery voltage is approaching to the Low level, the PMU08 will generate a
battery low SMI. The system will do the following action.

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Software Functional Overview

1) The Power Indicator will become blinking.

2) The system will issue a Warning beep.

3.5.3 Battery Low - Low

When the battery voltage is approaching to the Low-Low level, the PMU08 will
generate a battery low-low SMI. The system will do the following action.

1) The Power Indicator will keep on Blinking.

2) The system will enter Suspend To Disk mode even the power management is
disabled. The function of power-on or Resume will be inhibited until the battery
Low – Low condition is removed.

3.5.4 AC Adapter

When plug in the AC adapter, the system will do the following action:

- The charger will charge the Main Battery, if remaining capacity is not full.

- The Battery Charging Indicator will turn on if the battery is in changing mode.

3.6 PMU08

The Embedded controller PMU08 acts as a supplement for power management control. It
supports a lot of functions via SMBus interface.

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Software Functional Overview

3.6.1 The System EC RAM with PMU08

Embedded Controller Command Set
The EC I/F command set allows the OS to communicate with the PMU08.
For detail information refer to ACPI 1.0B specification.

Com

EC I/F Command

mand
Byte
Enco

ding

Byte

Register

R/W

Description Interrupt

Read Embedded
Controller

(RD_EC)

Write Embedded
Controller

(WR_EC)

Burst Enable
Embedded Controller

(BE_EC)

Burst Disable
Embedded Controller

(BD_EC)
Query Embedded

Controller
(QR_EC)

0x80

0x81

0x82

0x83 #1 EC_SC W

0x84

#1 EC_SC W Command byte

#2 EC_DATA W

#3 EC_DATA R

#1 EC_SC W

#2

EC_DATA W

#3

EC_DATA W Data to write

#1 EC_SC W

#2 EC_DATA R

#1 EC_SC W

#2 EC_DATA R

Header
Address byte to

read
Read data to

host
Command byte

Header
Address byte to

write

Command byte
Header

Burst
acknowledge
byte

Command byte
Header

Command byte
Header

Query value to
host

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

Interrupt on
IBF=0

Interrupt on
IBF=0

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

Interrupt on
IBF=0

No Interrupt

Interrupt on
OBF=1

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Software Functional Overview

3.6.2 PMU08 EC RAM List

The micro controller PMU08 acts as a supplement for power management control. It supports
the following functions via SMBus Command

Function Address

1st Battery

[ _BIF ]

00h

*3

02h

*3

04h

*3

06h

*3

08h

*3

0Ah

*3

0Ch

*3

0Eh

*3

10h

*3

12h

*3

14h

*3

16h

*3

Register

Name

Power
unit

Design
capacity

Last Full
Charge
Capacity

Battery
Technolo
gy

Design
Voltage

Design
capacity
of
Warning

Design
capacity
of Low

Battery
capacity
Granulari
ty 1

Battery
capacity
Granulari
ty 2

Model
number

Serial
Number

Battery
type

R/W

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

R(/W)

Bit Number

7 6 5 4 3 2 1 0

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff 0x0000 [Not support]

DATA[15:0] *1 - 0xffff 0x0000 [Not support]

DATA[15:8]

All bits are 0

CELL_TYP

*1

( 0x80 , 0xC0 )

Logic Default Description

E

[7:0]

- 0xffff

0x0000: mWh [Fixed value]
0xffff: Unknown
0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000 : Primary
0x0001: Secondary [Fixed value]
0xffff: Unknown.
0x0000-0xfffe(mV)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

CELL_TYPE [3:0] This code
depends on battery data format. In
the future, this code may be added.

0x00: NiMH
0x01: Li-ion

0x10: Non-rechargeable battery
(Reserved)

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C R I T C H G D C H G

PMU06A use this data with 02/03h.

PMU06A use this data with 04/05h.

Software Functional Overview

Function Address

18h

*3

Function Address

1Ah

*3

1st Battery

[ _BST ]

1st Battery

[ _BTP ]

2nd

Battery
[ _BIF ]

2nd

Battery

[ _BST ]

2nd

Battery

[ _BTP ]

-

1st Battery

[_BIF]

1Ch

*3

1Eh

*3

20h

*3

22h

24h

to

3Ch

*3

3Eh

to

44h

*3

46h *2 *2 *2 *2 *2 *2

48h

49h

4Ah

Register

R/W

Name

OEM
Informati
on

Battery
State

Battery
Present
rate

Battery
Remainin
g
Capacity

Battery
present
Voltage

Battery
Trip Point

Battery
data

Size

Design
capacity

Last Full

Capacity

R(/W)

Register

R/W

Name

R (/W)

R (/W)

R (/W)

R (/W)

R/W DATA[15:0] *1 - 0x0000

*2 *2 *2 *2 *2 *2

*2 *2 *2 *2 *2 *2

R (/W)

R (/W) DATA [23:16] *1 *7 - 0xff

R (/W) DATA [23:16] *1 *7 - 0xff

Charge

Bit Number

7 6 5 4 3 2 1 0

DATA

[15:8]

All bits

are 0

7 6 5 4 3 2 1 0

DATA[15:3] *1

All bits are 0

Vender [7:0] - 0xffff

*1

Bit Number

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA[15:0] *1 - 0xffff

DATA [7:0] - -

Logic Default Description

Logic Default Description

- -

Vender [7:0] This code depends on
battery data format.

And the following name should be
described in the ASL with the same
character code.

In the future, these codes will be
added.

0: “MoliEnergy”
1: “Panasonic”
2: “” (SANYO does not

agree the vender
name display)
3: “TBCL” (Toshiba)
4: “Sony”

The battery is

DCHG=1:
CHG =1:
CRIT =1:

0x0000-0xfffe(mW)
0xffff: Unknown

0x0000-0xfffe(mWh)
0xffff: Unknown

0x0000-0xfffe(mV)
0xffff: Unknown

0x0000: Clear the trip point
0x0001-0xffff(mWh)

0x01: DATA size is
3byte.(PMU06A)

0x00: DATA size is 2 byte.
(PMU06) *8

*7 *8

*7 *8

discharged
The battery is

charged
The battery is

critical (Empty)

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PMU06A use this data with 1E/1Fh.

PMU06A use this data with 22/23h.

PMU06A use this data with 26/27h.

PMU06A use this data with 28/29h.

PMU06A use this data with 42/43h.

PMU06A use this data with 46/47h.

PMU slave mode or charger mode is

For detail information, refer to PMU

slave communication section in this

O N E A L R M R E S

E S

E S

Software Functional Overview

Function Address

1st Battery

[_BST]

1st Battery

[_BTP]

2nd

Battery

[_BIF]

2nd

Battery
[_BST]

2nd

Battery
[_BTP]

Function Address

PMU

Access

SMBus

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

to

6Bh

*3

6Ch

6Dh

6Eh

6Fh

70h

*7

71h

*7

72h

73h
74h

to

93h
94h

95h

Register

Name

Battery
Remainin
g

Capacity
Battery

Trip
Point

Design
capacity

Last Full

Charge

Capacity

Battery
Remaing
Capacity

Battery
Trip

Point

Reserved

Register

Name

PMU_LO

W_

ADR

PMU_HI

G_

ADR

CHECK_

SUM

PMU_DA

TA

SMB_PT
CL

SMB_ST
S

SMB_AD
DR

SMB_CM
D

SMB_DA
TA

[0-31]
SMB_BC

NT
SMB_
ALARM_
ADDR

R/W

R (/W) DATA [23:16] *1 *7 - 0xff

R (/W) DATA [23:16] *1 *7 - 0x00

R (/W) DATA [23:16] *1 *7 - 0xff

R/(/W) DATA [23:16] *1 *7 - 0xff

R (/W) DATA [23:16] *1 *7 - 0xff

R (/W) DATA [23:16] *1 *7 0x00

R/W Don’t care - -

R/W

R/W DATA [7:0] - -

R/W DATA [15:8] - -

R/W DATA [7:0] - -

R/W DATA [7:0] - -

R/W PROTOCOL [7:0] - -

R/W

R/W

R/W COMMAND - -

R/W DATA - -

R/W

R (/W) ADDRESS [6:0]

Bit Number

7 6 5 4 3 2 1 0

Bit Number

7 6 5 4 3 2 1 0

D

STATUS

[4:0]

ADDRESS

[6:0]

RES

[7:5]

BCNT [4:0]

Logic Default Description

Logic Default Description

- -

R

- -

- -

R

- -

*7 *8

*7 *8

*7 *8

*7 *8

*7 *8

*7 *8

These registers are available when

selected.

document

For detail information, refer to
ACPI 1.0 specification

[13.9 SMBus Host controller
Interface via Embedded controller]

These registers are not available
when PMU slave mode or charger
mode is selected.

The PMU06 has access protect
function for the EEPROM in the
battery, to cancel the protection,
set the access protect cancel bit.

For detail, refer to SMBus section

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RT

TheSMBus address

AE) protection

PMU slave mode or charger mode is

For detail information, refer to PMU

ave communication section in this

O N E A L R M R E S

E S

E S

RT

TheSMBus address

AE) protection

Software Functional Overview

Function Address

96h

to

97h

98h

99h

Reserved

Function Address

PMU

Access

SMBus

Reserved

to

9Fh

6Ch

6Dh

6Eh

6Fh

70h

*7

71h

*7

72h

73h
74h

to

93h
94h

95h

96h

to

97h

98h

99h

to

9Fh

Register

AMB_
ALARM_
DATA [0-

1]

SMB_CN
RL

Reserved R/W Don't care - -

PMU_LO

PMU_HI

CHECK_

PMU_DA

SMB_PT
CL

SMB_ST
S

SMB_AD
DR

SMB_CM
D

SMB_DA
TA

[0-31]
SMB_BC

NT
SMB_
ALARM_
ADDR
AMB_
ALARM_
DATA [0-

1]

SMB_CN
RL

Reserved R/W Don't care - -

Name

Register

Name

W_

ADR

G_

ADR

SUM

TA

R/W

R (/W)

R/W RES [7:1]

R/W

R/W DATA [7:0] - -

R/W DATA [15:8] - -

R/W DATA [7:0] - -

R/W DATA [7:0] - -

R/W PROTOCOL [7:0] - -

R/W

R/W

R/W COMMAND - -

R/W DATA - -

R/W

R (/W) ADDRESS [6:0]

R (/W)

R/W RES [7:1]

Bit Number

7 6 5 4 3 2 1 0

DATA - -

Bit Number

7 6 5 4 3 2 1 0

D

STATUS

[4:0]

ADDRESS

[6:0]

RES
[7:5]

BCNT [4:0]

DATA - -

Logic Default Description

P

0x00

Logic Default Description

- -

R

- -

- -

R

- -

P

0x00

PRT =1:

These registers are available when

selected.

sl
document

For detail information, refer to
ACPI 1.0 specification

[13.9 SMBus Host controller
Interface via Embedded controller]

These registers are not available
when PMU slave mode or charger
mode is selected.

The PMU06 has access protect
function for the EEPROM in the
battery, to cancel the protection,
set the access protect cancel bit.

For detail, refer to SMBus section

PRT =1:

(A8­is cancelled.

(A8­is cancelled.

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*3

O N

*3

*3

B T P E M P L O W W A R E R R D C H G C H G C O N

*3

*3

*3

*3

E S

same time, the least address

*5

*5

*5

0

To clear the notified event

flag without unexpected

event loss, clear the

For this operation, this

register has special writing

(STS_X)

Function

Status

Addre

Register Bit Number

ss

A0h

ADP_STS R(/W)

Software Functional Overview

Name

R/W

7 6 5 4 3 2 1 0

RES [7:1]

Logic Default Description

C

- - CON = 1:

AC adapter is
connected

A1h

BAT1_STS
(1st Battery)

A2h

BAT2_STS
(2nd Battery)

A3h

Reserved

A4h

BAT1_CAP R(/W)

A5h

BAT2_CAP R(/W)

A6h

Reserved

SMB_Alert_

A7h

ADDR

R(/W)

R(/W)

R/W Don’t care - -

BCAP - -

BCAP - -

R/W Don’t care - -

R

R/W ADDRESS[6:0]

- -

- -

- 0x00

Battery trip
point is
detected.

Battery is

BTP =1:
EMP =1:
LOW =1:
WAR=1:
ERR =1:
DCHG=1:
CHG=1:
CON=1:

0x00-0x64 = 0-100(%)
0x7F = Unknown
0x80 = Not installed

SMBAlert output device
address

The alert response function
is available when this
register is cleared (0x00)
only.

When the several devices
assert the alert signal at the

empty.
Battery is Low

battery state.
Battery is

Warning state.
Battery is Error

state.
Battery is

discharged.
Battery is

charged.
Battery is

connected.

A8h

A9h

AAh

GPIO-A_
EVT_STS
GPIO-B_
EVT_STS

GPIO-C_
EVT_STS

R/W STS_A [7:0] 0x00

R/W 0

R/W 0 0 0 0 0

STS_B [6:0] 0x00

Read
0:No event
1:EVT detection
Write

STS

0:Clear event

_C

1:Ignore

[1:0]

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is stored to this register.
And when this register is
cleared , next alert address
is stored to this register.

corresponding bit flag only.

manner as follows.

0x00

STS_X

AND (Written data)

ß

*5

*5

T P 2 S M B A L R T G P I O

E

B A T 2 B A T 1 A D P

*5

H

*5

H

*5

E R R L O W H I G H

To clear the notified event

flag without unexpected

vent loss, clear the

For this operation, this

register has special writing

(STS_X)

T P 2 S M B A L R T

D P

T P E M P L O W W A R E R R C A P C / D C O N

For detail information, refer

Software Functional Overview

Function

Addre

ss

ABh

ACh

ADh

AEh

Register Bit Number

Name

RUN_
EVT_STS

WAKE_
EVT_STS

RUN_
EVT_STS_2

WAKE
EVT_STS_2

R/W

7 6 5 4 3 2 1 0

R/W 0x00

B

R/W

R/W Reserved [7:1]

R/W Reserved [7:1]

Logic Default Description

BTP2 event
is detected

SMBus event
is detected.

SMBAlert is

BTP2 =1:

SMB =1 :
Read
0:No event

R

S

1:EVT detection
Write
0:Clear event
1:Ignore

T

T

ALRT=1 :

GPIO =1 :

BATn=1 :

ADP =1 :

TH =1 :

HIGH=1 :

0x00

LOW =1 :

ERR =1 :

0x00

e

corresponding bit flag only.

0x00

detected.
GPIO event

is detected.
Battery event

is detected.
Battery event

is detected.
Thermal

event is
detected

High alarm
point is
detected.

Low alarm
point is
detected.

Polling
communicati
on failure
with retry.

Event/

GPIO

Control

AFh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

THERMAL_
EVT_STS

EC_RUN_
ENB
EC_WAKE_
ENB

BATT_RUN
_

ENB

BATT_WA
KE

_ENB

GPIO-A_
IO_CONF
GPIO-A_
DATA
GPIO-A_
RUN_ENB
GPIO-A_
EVT_POL

R/W Reserved [7:3]

B

R/W

R/W

R/W

B

R/W

R/W CONF_A [7:0]

R/W DATA_A [7:0] -

R/W RUN_ENB_A [7:0]

R/W POL_A [7:0]

RES[4:1]

0: Disable

A

1: Enable
0: Disable
1: Enable

0: Disable
1: Enable

0: Disable
1: Enable

0: Input
1: Output

0: Disable
1: Enable
0: Falling edge
1: Rising edge

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

manner as follows.

STS_X ß

AND (Written data)

BTP2:

BTP2 event

SMB :

SMBus event.

ALRT:

SMBAlert event.

ADP:

Adapter event.

BTP:

Battery trip point

EMP:

Empty.

LOW:

Low battery

WAR:

Warning

ERR:

Error

CAP:

Capacity learning

C/D:

Charge/Discharge

CON:

Battery presence

to GPIO section in this

document.

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0

C

0

E_

_C

Software Functional Overview

Function

Event/

GPIO

Control

Addre

ss

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

C0h

C1h

Register Bit Number

Name

GPIO-A_
WAKE_EN

B
GPIO-B_
IO_CONF
GPIO-B_
DATA
GPIO-B_
RUN_ENB
GPIO-B_
EVT_POL
GPIO-B_
WAKE_EN

B

GPIO-C_
DATA

GPIO-C_
RUN_ENB

GPIO-C_
EVT_POL

GPIO-C_
WAKE_EN

B

R/W

7 6 5 4 3 2 1 0

R/W WAKE_ENB_A [7:0]

R/W 1 CONF_B [6:0]

R/W 0 DATA_B [6:0] -

R/W 0 RUN_ENB_B [6:0]

R/W 0

R/W 0 WAKE_ENB_B [6:0]

R/W

R/W 0 0 0 0 0

R/W 0 0 0 0 0

R/W 0 0 0 0 0

POL_B [6:0]

RES [7 :4]

*4

DATA_C

[3:0]

RUN

_

ENB

[1:0]

PO

L_C

[1:0

WA

K

0

ENB

Logic Default Description

0: Disable
1: Enable

0: Input
1: Output

0: Disable
1: Enable
0: Falling edge
1: Rising edge

0: Disable
1: Enable

-

0: Disable

_

1: Enable

0: Falling edge
1: Rising edge

]

0: Disable
1: Enable

0x00

0x80

0x00

0x00

0x00

0x00

0x00

0x00

[1:0]

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W A K E S C I

R E S

*4 Q _ R U N

W A K E _ O U T S

US _ X

output when the

shows the output

=0: Runtime and

(GPIO B6 is

=1: Runtime and

(GPIO B6 is

Software Functional Overview

Function

Addre

Register Bit Number

ss

Name

C2h EVT_CONT R/W

R/W

7 6 5 4 3 2 1 0

RES

[7:6]

Logic Default Description

0x00

WAKE

SCI

Q_RUN

WAKE_

OUT

SUS_X

=0: Wake#
output is
“Level”.

=1: Wake#
output is
“Pulse”.

=0: SCI is
always output
by event

detection
and SCI_EVT
shows

the query
data is stored.

And next
SCI is not
output

until
SCI_EVT is
cleared.

=1: SCI is

command
set is not
executed

and OBF=0.
SCI_EVT

SCI is for
event
notification.

=0: Runtime
event ststus is

reflected to
RUN_EVT_STS

register.
=1: Runtime

event status is
reflected to

Query data.
=0: Wake event

output is always
enable.( in

S0-S3)
=1: Wake event

output is enable
when

SUS_X=L.

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Wakeup is
selected by

SUS_B.

enable)

Wakeup is
selected by

SUS_A.

used as SUS_A
input.)

H

To

*6

*6

formation, refer

*6

C H

R D Y #

H G 2 C H G 1

C H G 2 D C H G 1

Software Functional Overview

Function

Battery
control

Addre

Register Bit Number

ss

Name

EC_RUN_

C3h

ENB_2
EC_WAKE_

C4h

ENB_2

C5h

Reserved R/W
C7h
C8h

GPI_AD0 R AD0_DATA [7:0] - -

C9h

GPI_AD1 R AD1_DATA [7:0] - -

CAh

Reserved

CBh D/A_CONT R/W DATA [7:0] - 0xff

BAT_CHG_

D0h

CONT

R/W

7 6 5 4 3 2 1 0

R/W

Reserved [7:1]

R/W

Don’t care

R/W Don’t care - -

C

RES

[3:2]

R/W RES[7:5]

G
_

Logic Default Description

0: Disable

T

1: Enable
0: Disable
1: Enable

0x00

0x00

- -

- -

TH: Thermal event

For detail in
to GPIO section in this
document.

0x00-0xfe: D/A converter
output data

0xff : Battery
capacity(%) output

CHG_RDY# =0 : Charge
ready

CHGn =1 : The nth
battery is charged

D1h

D2h

D3h

D5h

D7h

BAT_DCH_

PRI

BAT_DCH_

CONT

BAT_WAR_

ABS

BAT_LOW_

ABS

BAT_WAR_

REL

R/W RES[7:3]

R/W

R/W DATA[15:0] *1 - 0x0000

R/W DATA[15:0] *1 - 0x0000

R/W DATA [7:0] - 0x10

RES[7:2]

PAT
[2:0]

D

- 0x00

0: Not discharge
1: Discharge

-

Battery discharge priority

0 : 2 1
1 : 1 2
2 : 2 1
3 : 2 1
4 : 1 2
5 : 1 2

6 : Same as 0
7 : Simultaneously

discharge (Read only :
This data can be set

using PMU register)

The discharge battery can
be selected one of the
batteries can be discharged.

Absolute capacity battery
Warning detection point

0x0000-0xffff (mWh)
Absolute capacity battery

Low detection point
0x0000-0xffff (mWh)
Relative capacity battery

Warning detection point
00-C8h (0-100% step 0.5%)

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*3

This register is “read only”,

the value, use the

To

To

C _ R E G

B A Y _ L E D P O

W_ L E D

not initialize

EC register

when system

power is off.

indicates the

status to the

LED_BAY#

n, when the

The Power

S _ S T S

S

Software Functional Overview

Function

Addre

Register Bit Number

ss

Name

BAT_LOW_

D8h

REL

D9h

FULL_DAT
A

CC_CUR_

Dah

DATA

DBh

BTP2 R/W DATA [15:0] - 0x0000

DCh

DDh

Reserved R/W Don't care - -

DFh

R/W

7 6 5 4 3 2 1 0

R/W DATA [7:0] - 0x06

R/W DATA [7:0] - 0xbe

R DATA [7:0] - 0x00

Logic Default Description

Relative capacity battery
Low detection point

00-C8h (0-100% step 0.5%)
Full charge cancel point
00-C8h (0-100% step 0.5%)
Battery charging current

setting
0x01-0xff (0.02-5.10A step

0.02A)
0x00 Depends on the

battery

to change
register in PMU registers
area.

0x0000: Clear the trip point
0x0001-0xffff : (mWh)
When all of the battery’s

capacities lesser than this
setting value, the BTP2 is
detected if event is enabled.

PMU does

PMU
control

Thermal
Sensor
Polling

E

E0h PMU_CONT R/W RES[7:3]

O

ACPI_ACC_

E1h

ENB

E2h OFF_TIME R/W DATA [7:0] - 0x64

POLLING_

E3h

ADDRESS

R/W RES [7:1]

R/W Slave Address [6:0] RE

- 0x00

- 0x00

0x00

EC_REG =1:

BAY_LED =1:

POW_LED =1:

OS_STS = 1:
= 0:

Power switch over ride
function timer

01h-FFh (0.1-25.5esc step

0.1sec)
00h : Reserved

Address: 0x00-0x7F
The polling slave address

setting
If this address is 00, the

Polling is disabled.

PMU

Battery
discharge

battery is
installed.

LED blink

ACPI mode
Legacy

mode

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If the received data GE this

value, the event will be

If the received data LE this

value, the event will be

To

After writing to the register

To

Software Functional Overview

Function

PMU
control

Addre

Register Bit Number

ss

Name

HIGH_
E4h

ALARM

LOW_
E5h

ALARM

POLLING_
E6h

INTERVAL

POLLING_
E7h

DATA

HARDWAR
E8h

E_SHUT_D

OWN

POLLING_
E9h

COMMAND

RETRY_

EAh

COUNT

EBh

Reserved R/W Don't care
EFh

BURST_FL
F0h

G_CLR

F1h

Reserved R/W Don't care
FFh

R/W

7 6 5 4 3 2 1 0

R/W DATA [7:0] Signed value 0x00

R/W DATA [7:0] Signed value 0x00

R/W DATA [7:0] 0x00

R(/W)

R/W DATA [7:0] Signed value 0x7D

R/W DATA [7:0] 0x00

R/W DATA [7:0] 0x10

R/W DATA [7:0] - -

DATA [7:0] Signed value 0x00

Logic Default Description

detected.

detected.
0x00 :Polling

disable
0x01 – 0xFF [x 250ms]

(250ms to 63.75sec)
This register shows data at

latest polling.
If the thermal sensor read

value GE this value, the
PMU automatically off the
power.

Polling command (data
register) address.

0x00 - 0xFF: Retry count
value (0-255)

addressed A8h-AFh,
Set the 00h to this register.

3.6.3 Security

The user may enter up to eight standard text characters for a password. The password includes
two levels. The higher priority is the Supervisor Password. The lower priority is the User
Password. The Supervisor Password can access all the system resource, while the User
Password may not access the floppy disk when it is protected by Supervisor Password. Also,
the User Password may not access the floppy disk when the Supervisor Password protects it.

When the security function is enabled, the system will request the user to enter password
during the following situation:

• Power On → The system will prompt the user to enter the password before booting

the OS. If the user key in the wrong password for 3 times, then the system will halt..

Entering CMOS Setup → The system will prompt the user to enter the password

•

before entering the CMOS Setup. If the user keys in the wrong password for 3 times,
then the system will halt.

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Software Functional Overview

3.7 CMOS Setup Utility

The Setup utility is used to configure the system. The Setup contains the information
regarding the hardware for boot purpose. The changed settings will take effect after the
system rebooted. Refer to Chapter 1 on running BIOS Setup Program for more detailed
information.

3.8 Definitions of Terms

10Base-T (Ethernet) - A networking standard that supports data transfer rates up to
10Mbps (10 megabits per second).

100Base-T (Fast Ethernet) ­transfer rates up to 100Mbps.
ACPI - Advanced Configuration and Power Management Interface, a power

management specification developed by Intel, Microsoft, and Toshiba.
CardBus - The 32-bit version of the PCMCIA PC Card standard. In addition to
supporting a wider bus (32 bits instead of 16 bits), CardBus also supports bus mastering
and operation speeds up to 33MHz.

Clock Throttling

started at a known duty cycle using the STPCLK# pin to enter and exit Stop Grant mode.
Clock throttling is used for power saving, thermal management, and reducing the
processing speed.
DIMM (SODIMM) - Dual In-line Memory Module, a small circuit board that holds
memory chips. A Single In-line Memory Module (SIMM) has a 32-bit path to the
memory chips whereas a DIMM has 64-bit path. Because the Pentium processor
requires a 64-bit path to memory, you need to install SIMMs two at a time. With
DIMMs, you can install one DIMM at a time. SODIMM is Small Outline Dual In-line
Memory Module used in notebook computers.
DMI - Desktop Management Interface, an API to enable software to collect information
about a computer environment about a computer environment. For example, using DMI
a program can determine what hardware and expansion boards are installed on a
computer.

GPI - General Purpose Input.
GPO - General Purpose Output.
Lid Switch - A switch that indicates the notebook LCD Panel has been closed and it can

be turned off.
MPEG-2 - Moving Picture Experts Group, a working group of ISO. The term also
refers to the family of digital video compression standards developed by the group.
There are two major MPEG standards : MPEG-1 and MPEG-2. The most common
implementations of the MPEG-1 standard provide a video resolution 352x240 at 30
frames per second(fps). A newer standard, MPEG-2, offers resolution of 720x480 and
1280x720 at 60 fps, with full CD-quality audio.
North Bridge - The CPU to PCI interface, also contains the memory and cache
controllers.

South Bridge - The PCI to ISA interface, also contains many legacy devices.
SMM - System Management Mode, Mode of operation while an SMI is active.
SMI - System Management Interrupt, non-maskable interrupt that causes the system to

enter SMM. SMM functions include power management, USB legacy keyboard control,
security, hot keys, and thermal monitoring.
SMB - System Management Bus, that is used for managing smart batteries, reading
SDRAM configuration information, and other miscel1aneous system function.

– South bridge function that allows the CPU clock to be stopped and

A relatively new networking standard that supports data

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Software Functional Overview

TBD -To Be Discussed. The mentioned specification is not final that should be
discussed with related engineers.
Ultra DMA-33 - A protocol developed by Quantum Corporation and Intel that supports
burst mode data transfer rates of 33.3 MBps.
USB - A new external bus standard that supports data transfer rates of 12 MBps. A
single USB port can be used to connect up to 127 peripheral devices, such as mice,
modems, and keyboards. USB also supports Plug-and-Play installation and hot plugging.

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