Fic AT11, Amilo M7440 Schematic
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First International Computer,Inc
D D
Board name : Mother Board Schematic
Project : AT11
Version : 0.2
C C
Protable Computer Group HW Department
1. Schematic Page Description :
2. PCI & IRQ & DMA Description :
3. Block Diagram :
4. Nat name Description :
Initial Date : September 24 , 2004
5. Board Stack up Description :
6. Schematic modify Item and History :
7. power on & off & S3 Sequence :
8. Layout Guideline :
9. switch setting
B B
Manager Sign by: Angus Ho
Drawing by : Casy Wang
LAN Circuit check by : Jimmys Ho
A A
Audio Circuit check by : Jimmys Ho
Total confirm by :
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Title
Size Document Number Rev
C
2
Date: Sheet
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Title
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1. Schematic Page Description :
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D D
1. Title
2. Schematic Page Description
3. Block Diagram
4. ANNOTATIONS
5. Schematic Modify
6. Timing Diagram
7. CPU Layout Guideline
8. DDR & CLK GEN Layout Guideline
9. mFcPGA Dothan (1/2)
10. mFcPGA Dothan (2/2)
11. POWER (CPU CORE)
12. Thermal / FAN CNN
C C
13. ALVISO (1/6)(LVDS/PCI/VGA/TV)
14. ALVISO (2/6)(DMI/CLK/PM)
15. ALVISO (3/6)(DDR II)
16. ALVISO (4/6)(HOST)
17. ALVISO (5/6)(POWER)
18. ALVISO (6/6)(VSS/NCTF)
19. ICH6-M (1/4)(PCI/CPU/IRQ/LAN)
21. ICH6-M (3/4)(POWER)
22. ICH6-M (4/4)(GROUND)
23. Clock Generator
24. DDR SO-DIMM1
25. DDR SO-DIMM2
26. SWITCH & TV_OUT
27. TI 7411(IEE1394)
28. TI 7411(CARDBUS)
29. CARDBUS POWER SW./CNN
30. Firm Ware Hub (FWH)
31. LED INDICATER & LCD CNN
32. LPC PMU08
33. USB CNN1
34. USB CNN2
35. RTC / SMBUS
36. SATA / CD-ROM CNN
37. Calexico MINI PCI
38. PCBEEP/SWITCH
39. LPC KBC M3885X
20. ICH6-M (2/4)(IDE/AC97/USB2/PMU/GPIO)
2. PCI & IRQ & DMA Description :
B B
IDSEL
AD17
AD23 CardBus (TI 4510)
AD24 LAN 82562EZ
IRQA
IRQB
IRQC
IRQD
BUSMASTER
A A
REQ
REQ0 / GNT0
REQ1 / GNT1
REQ2 / GNT2
CHIP
Mini PCI(Wireless LAN)
CHIPPCIINT
MiniPCI/CardBus
MiniPCI/CardBus
VGA/LAN
ICH6-M Embeded USB2.0
CHIP
MiniPCI
CardBus
Mini PCI(Wireless LAN)
LAN(82562EZ)REQ4 / GNT4
8
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
7
6
System timer
Keyboard
(Casacde)
LAN / MODEM
Serial Port
AUDIO / VGA / USB
FLOPPY DISK
LPT
RTC
ACPI
MODEM/LAN
Cardbus
PS/2 mouse
FPU
HDD
CDROM
5
40. PCI / LPC Pull Up/Down
41. DIP/LID SW; SCREW
42. Reset Circuit
43. Over Voltage Protect
44. Power (DDR 1.8VDDS/ 0.9VDDM)
45. Power (1.5VDDA/VDDS/1.8VDDM/2.5VDDM)
46. ADIN&DCIN
47. Power (3VDDS/5VDDS/3VDDM/5VDDM)
48. MDC CNN
49. AC97 CODEC (ALC655)
50. AUDIO AMP / SPEAKER
51. HEADPHONE & SPDIF
52. MICIN
53. Power (VCCP/1.5VDDM)
54. ADAPTOR IN & Battery Voltage Sense
55. Charge Circuit
56. CRT PORT
57. PEG & DD CNN
58. LAN BCM4401 & BCM5788
59. TRANSFORMER & RJ45, RJ11
DMA Channel
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
4
3
DeviceIRQ Channel Desciption
MODEM / LAN
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
2
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Schematic Page & PCI /IRQ/ DMA Description
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3. Block Diagram :
Intel
D D
Thermal
Sensor
CRT
GMT795
P56
P12
TV Port
P26
PEG-M22-P
LCD
C C
ACIN
P46
PMU3V/5V
B B
3VDDA/5VDDA
3VDDS/5VDDS
3VDDM/5VDDM
2.5VDDM
1.5VDDA/DDS
1.8VDDM
1.5VDDM
DDR_1.8VDDS
A A
DDR_0.9VDDM
8
P57
P57
P47
P47
P45
P45
P45
P45
P44
P44
USB3
USB3
P31
SATA HDD
P33
7
P36
USB2
P37
USB2
USB 2.0
USB1
USB1
P34
P33
AUDIO AMP
HEADPHONE
Mic IN
P50
P51
P52
K/B CTRL
LPC M3886X
6
PEG BUS
P57
SATA BUS
USB0
Dual Layout
MDC CNN
Dothan/Yonah
Processor
Intel
915GM
1257 uFCBGA
P13,14,15,16,17,18
ICH6-M
USB0
P33
AZALIA
CODEC
AC'97
CODEC
ALC655
GPINT K/B
609 BGA
AC-Link
P49
P49
P48
5
P9,10
Host Bus
Mem Bus
DMI Interface
P19,20,21,22
LPC BUS
FLASH ROM
( F/W Hub)
4Mb/8Mb
P30P39
IDE BUS
LCI
32Bit PCI BUS
Mini PCI
Calexico2
4
CPU
CORE
P11
VCCP
CPU
VCRE
GMCH
P53
DDRII
DIMM1(Socket)
400MHZ/533MHZ
DDRII
DIMM0(Socket)
400MHZ/533MHZ
CDROM
LAN
BCM4401
P58
PCMCIA
TI 7411
(1394)
P27, 28
P37
TPS 2220
P29
LPC
PMU08
P32
3
P36
RJ45 CNN
P24
P25
P59
1394 CNN
3 IN 1
CARDREADER
P27
P29
PCMCIA SLOT0
CLK ICS954226
PCI/LPC Pull up/Down
LID/DIP SW
MAIN SW CNN
Over Voltage
Protect
Battery
charger
BAT CON
FAN CNN
RTC
RESET
P29
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
2
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
BLOCK DIAGRAM
P12
P35
P42
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P23
P40
P41
P26
P43
P55
P54
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4. Net name Description :
Voltage Rails
DCIN
PMU5V 5.0V always on power rail by LATCH or ACIN
D D
PMU3V 3.3V always on power rail by LATCH or ACIN
3VDDA 3.3V always on power rail by DCON or PSUSC0
3VDDS 3.3V power rail
5VDDS 5.0V power rail
3VDDM
Vcore_CPU
VCCP 1.05V for AGTL+ Termination Voltage
Vcore_MGCH
1.5VDDM 1.5V switched power rail
1.5VDDS 1.5V power rail
1.5VDDA 1.5V always on power rail
2.5VDDM 2.5V power rail for GMCH GIO
DDR_1.8VDDS 1.8V power rail for DDRII
DDR_0.9VDDM 0.9V DDRII Termination Voltage
C C
Part Naming Conventions
C
CN
D
F
L
Q
R
B B
RP
U
Y
Capacitor
=
=
Connector
=
Diode
=
Fuse
=
Inductor
Transistor
=
=
Resistor
=
Resistor Pack
=
Arbitrary Logic Device
=
Crystal and Osc
Net Name Suffix
0=
Active Low signal
Signal Conditioning
=
_D_
_Q_
_L_
A A
Damped (by a resistor)
=
Isolated (by a Q-switch)
=
Filtered (by an inductor or bead)
8
Primary DC system power supply
5.0V always on power rail by DCON or PSUSC05VDDA
3.3V switched power rail
5.0V switched power rail5VDDM
Core Voltage 1.468V~0.956V for CPU
1.05V or 1.5V for ALVISO core
1.8V for CPU PLL Voltage1.8VDDM
7
6
POWER RAIL
VCORE_CPU
VCCP
VCCP_MGCH
VCORE_MGCH ALVISO
1.8VDDM/1.5VDDM
DDR_1.8VDDS 1.8V
1.5VDDM
1.5VDDS
1.5VDDA
2.5VDDM
0.9VDDM 0.9V
3VDDM
3VDDS
3VDDA
5VDDM
5VDDS PCMCIA VCCA
5VDDA
PMU3V
PMU5V 0.0615A
DESTINATION
Dothan
Dothan
ALVISO
Dothan (PLL)
ALVISO
DDR2 MODULE
ALVISO
(LVDS, TVDAC,PCIE)
ICH6M (PLL)
ICH6M
(SUS/LAN)
ALVISO 2.5V
(PCIE_A,LVDSIO,CRTDAC,HV)
DDR RAM
ICH6M
ALVISO (TV DAC)
TI4510
MiniPCI
FWH BIOS
LPC KBC
AC97 CODEC
CLK GEN
LVDS
TI4510
MiniPCI
PCMCIA VCCA
ICH6M
AMP2020
CDROM
HDD
INT KB/ INT MS
INVERTER
ICH6M
USB
PMU08
PMU08
5
5.Board Stack up Description
PCB Layers
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Layers : 8 Depth 1.2mm Impence 55 ohms +/- 10%
(DDR2)
(CORE)
(SUS)ICH6M
(IO)
(SUS)
VOLTAGE
0.956~1.308V
1.05V
1.05V
1.05V 4A
1.8V
1.5V
(VCCASM)
(DMI)
1.5V
1.5V
3.3V
3.3V
3.3V
4
S0 CURRENT
27A
2.5A
0.85A
0.2A
2.7A
1.8A
2.95A
0.15A
0.2A
0.13A
0.024A (Evaluation)
0.0461A
0.36A
0.4A
0.36A
0.4A
0.0615A (Idle)
0.0461A
0.0461A
0.0615A
7mA
0.0615A
Component Side, Microstrip signal Layer
Ground Plane
Stripline Layer(High Speed)
Stripline Layer(High Speed)
Power Plane
Stripline Layer(High Speed)
Ground Plane
Solder Side,Microstrip signal Layer
(Evaluation)0.6A
(Idle)
(Run)
(Run)
(Run)
(Run)
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
2
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
ANNOTATIONS
3
(Idle)
(Idle)
(Idle)
0.338A
0.677~0.8A
0.52A
0.569A
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6.Schematic modify Item and History :
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PHASE INSOLUTIONROOT CAUSEBUG
D D
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HISTORY:
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C C
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B B
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Version Notice
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7. power on & off & S3 Sequence :
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Power On Sequencing Timing Diagram
VID
VR_ON
Vcc-core
CPU_UP
Tboot
Tsft_star_vcc
Tcpu_up
Vboot
Tboot-vid-tr
Vid
Vccp
Vccp_UP
Tvccp_up
ICH6M Timing
3.3VDDM
2.5VDDM
MAX Delta
Voltage=300mV
3.3VDDM(LAN)
2.5VDDM(LAN)
MAX Delta
Voltage=300mV
3.3VDDA
1.5VDDA
MAX Delta
Voltage=300mV
3.3VDDS(LAN)
2.5VDDS(LAN)
MAX Delta
Voltage=300mV
Vccgmch
GMCHPWRGD
Tgmch_pwrgd
CLK_ENABLE#
IMVP4_PWRGD
C C
BATTERY ONLY POWER ON TIMING
POWSW0
PMU5V/PMU3V
DCON
VDDA
MAINSW0_ICH
PM_RSTRST0
PM_SLP_S30/S40/S50
PSUSC0
B B
A A
SUSTAT_B0
VDDM,VDDS
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP/1.2VDDM
VCORE_ON
VR_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGD
PCI_RST0
AGTL+_CPURST0
Tcpu_pwrgd
To ODEM/other PCI device
From ODEM to CPU
1.5VDDM
VCCP
MAX Delta
Voltage=300mV
5VREF
3VDDM
MAX Delta
Voltage=300mV
5VREF_SUS
3VDDA
MAX Delta
Voltage=300mV
No Requirement
3VDDM<--->1.5VDDM
2.5VDDM<--->1.5VDDM
2.5VDDM<--->5VREF
1.5VDDM<--->5VREF
S3 SUSPEND AND RESUME TIMING
POWSW0
PMU5V/PMU3V
PM_RSMRST0
PM_SLP_S30
PM_SLP_S40/S50
PSUSC0
SUSTAT_B0
PM_PWROK
SYS_PWROK
VRON_VCCP
VCCP,1.2VDDM
VCORE_ON
VCORE_CPU
CK408_PWRGD0
PM_VGATE
CPU_PWRGOOD
PCI_RST0
AGTL+_CPURST0
DCON
VDDA
VDDS
VDDM
VR_ON
H
H
H
H
H
H
H
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Timing Diagram
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8. Layout Guideline :
System Bus Common Clock Signal Layout Guide :
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
RS[2..0]# , TRDY# , RESET#.
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
Strip-line(Int. Layer)
D D
Micro-strip(Ext. Layer)
Source Synchronous DATA :
Signals Name
DATA#[15..0] , D INV0#
DATA#[31..16] , DIN V1#
DATA#[47..32] , DINV2# +/- 25 mils
DATA#[63..48] , DIN V3#
Topology1:
DATA#[63..0] , DINV# [3..0] , DSTBN#[3..0] , DSTBP#[3..0]
Signal Names Data to Data Strobe to
DATA#[63..0]
DINV#[3..0]
DSTBN#[3..0]
DSTBP#[3..0]
No trace witdth to trace space ratio requirement relaxation
C C
B B
A A
NOTE:
allowedcomplementary strobes.
The only recommended trace spacing ratio is 3:1
Topology2:
DATA#[63..0] , DINV# [3..0] , DSTBN#[3..0] , DSTBP#[3..0]
Signal Names Data to Data Strobe to
DATA#[63..0]
DINV#[3..0]
DSTBN#[3..0]
DSTBP#[3..0]
No trace witdth to trace space ratio requirement relaxation
NOTE:
allowedcomplementary strobes.
The only recommended trace spacing ratio is 3:1
Topology3:
DATA#[63..0] , DINV# [3..0] , DSTBN#[3..0] , DSTBP#[3..0]
Signal Names Data to Data Strobe to
DATA#[63..0]
DINV#[3..0]
DSTBN#[3..0]
DSTBP#[3..0]
No trace witdth to trace space ratio requirement relaxation
NOTE:
allowedcomplementary strobes.
The only recommended trace spacing ratio is 3:1
Source Synchronous ADDRESS :
Address#[31..3] , RE Q#[4..0] , ADSTB#[1..0]
Transmission Line Type
Strip-line
Signals Name
A#[16..3] , REQ#[4..0]
A#[31..17
5
1.0 ~ 6.5 inch 55+/-10% 4 & 8(Int. Layer)
Signals Matching
+/- 100 mils +/- 25 mils
+/- 100 mils
+/- 100 mils
+/- 100 mils
Transmission
Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Transmission
Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Transmission
Line Type
Strip-line
Strip-line
Strip-line
Strip-line
Total Trace Length
(inches) (inches)
Total Trace Length
(inches) (inches)
Total Trace Length
(inches) (inches)
Total Trace Length
Signals Matching
+/- 200 mils
+/- 200 mils
Strobes associated
with the group
DSTBP0#,DSTBN0#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#
Min Max
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
Min Max
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
Min Max
0.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
Strobes associated
with the group
ADSTB0#
ADSTB1#
Normal
Impedance
55+/-10%
55+/-10%
55+/-10%
55+/-10% 4 & 12
Normal
Impedance
55+/-10%
55+/-10%
55+/-10%
55+/-10% 4 & 12
Normal
Impedance
55+/-10%
55+/-10%
55+/-10%
55+/-10% 4 & 12
Normal Impedance
55+/-10%
5 & 10(Ext. Layer)
Strobe Matching
+/- 25 mils
+/- 25 mils
Spacing (mils)
Strobe to
Strobe
4 & 8
4 & 8
4 & 12
Spacing (mils)
Strobe to
Strobe
4 & 6
4 & 6
4 & 12
Spacing (mils)
Strobe to
Strobe
4 & 8
4 & 8
4 & 12
Spacing (mils)
4 & 80.5 ~ 6.5 inch
Strobe Matching
+/- 200 mils
+/- 200 mils
4
Data
Data
Data
NA
NA
4 & 8
4 & 8
NA
NA
4 & 6
4 & 6
NA
NA
4 & 8
4 & 8
Topology : IERR# , FERR#
CPU
Receiver
L1
R1
Topology : PROCHOT#
CPU
VCCP
L1
L2
Topology : PWRGOOD
Topology : THERMTRIP#
MCH
CPU
Topology : CPUSLP#
ICH6
Topology : LIN T1 / NMI , LINT0 / INTR , A2 0M# , IGNNE# , DPSLP# , SMI# , STPCLK#
Rtest
L2 L1
(No Stuff)
ICH6
L2
Rtt
Voltage
Translation
Device
L1
L2L1
L1
L3
CPUICH4
CPU
CPU
Receiver
ICH6-M
L3
VCCP
L2
L1
0.5" - 12"
Rtt
L2
Rss
L4
0" - 3.0"
0" - 3.0"
0.5" - 12"
L1
0.5" - 12"
0.5" - 12"
L1
VCCP
0.5" - 12"
Rtt
0.5" - 12"
VCCP
L1
0.5" - 12"
Rtt
0.5" - 12"
L1
MCH
0.5" - 12" Micro-strip
0.5" - 12"
Transmission Line
L1
Micro-strip0.5" - 12"
Strip-line0.5" - 12"
Topology : CPU RESET# without ITP
Transmission Line
ICH6
CPU
L1
L1
1" - 6.5"
Micro-strip1" - 6.5"
Strip-line
Topology : CPU RESET# with ITP
MCH
L1
VCCP
Rtt
L2
L3
Rs
ITP
1.0" - 6.0" 22.6 +/-1%
Differential Impedance Targets for Routing :
Signal Type
Host Clock
DMI
EXT-PCI
SDVO
LVDS
SATA
USB2.0
PCI EXPRESS
DDR2
3
Routing Geometry
5 -mil trace width on 7- mil spacing 100 Ω +/- 15 %
5 -mil trace width on 7- mil spacing
5 -mil trace width on 7- mil spacing
5 -mil trace width on 7- mil spacing
5 -mil trace width on 7- mil spacing 100 Ω +/- 15 %
5 -mil trace width on 7- mil spacing
4 -mil trace width on 7- mil spacing
5 -mil trace width on 7- mil spacing
5 -mil trace width on 7- mil spacing
L3
0" - 3.0"
L2
0" - 3.0"
0" - 3.0"
L2
0" - 3.0"
0" - 3.0"
L2
0" - 3.0"
0" - 3.0"
L2
0.5" -12.0"
0.5" - 12.0"
L2 + L3CPU
6.0" max
R1
56 +/-5%0" - 3.0" 56 +/-5%
56 +/-5% 56 +/-5%
Rtt
56 +/-5%
56 +/-5%
Rtt
330 +/-5%
330 +/-5%
Rtt
56 +/-5%
56 +/-5%
Rtest
0
0
L3
0.5" max
Impedance
100 Ω +/- 15 %
100 Ω +/- 15 %
100 Ω +/- 15 %
100 Ω +/- 15 %
90 Ω +/- 15 %
100 Ω +/- 15 %
85 Ω +/- 15 %
Rtt Transmission Line
Micro-strip
Strip-line
Transmission Line
Micro-strip
Strip-line
Transmission Line
Micro-strip
Strip-line
RsL1
Transmission Line
Rtt
54.9 +/-1%
Rss
75 +/-5%
75 +/-5%
Transmission Line
Strip-line
Signal Matching
+/- 20 mils
+/- 5 mils
+/- 20 mils
+/- 20 mils
+/- 20 mils
+/- 10 mils
+/- 75 mil
+/- 37 mils
+/- 20 mil
2
Micro-strip
Strip-line
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
CPU Layout Guideline
1
of
763Wednesday, February 16, 2005
0.1
5
4
3
2
1
ALVISO DDR2 Layout Guidelines
Note that all length matching formulas are based on GMCH die-pad to SO-DIMM pin total length
D D
C C
B B
A A
DDR2 Signal Groups
Group Signal Name
Clocks
Data
Control
Command
Compensation
Feedback
SCK[5:0]
SCK#[5:0]
SA_DQ[63:0] ; SB_DQ[63:0]
SA_DQS[7:0] ; SA_DQS[7:0]
SA_DM[7:0] ; SB_DM[7:0]
SCKE[3:0]
SCS#[3:0]
SM_ODT[3:0]
SA_MA[13:0] ; SB_MA[13:0]
SA_BA[1:0] ; SB_BA[1:0]
SA_RAS# ; SB_RAS#
SA_CAS# ; SB_CAS#
SA_WE# ; SB_WE#
SMRCOMPN ; SMRCOMPP
SMSLEWIN ; SMSLEWOUT
SMVREF[1:0]
SA_RCVENOUT# ; SB_RCVENOUT#
SA_RCVENIN# ; SB_RCVENIN#
Length Matching Formulas
Signal Group Minimum Length Maximum Length
Control to Clock
Command to Clock
CPC to Clock
Strobe to Clock
Data to Strobe
Clock Signals Topologies and Routing Guidelines
GMCH
Pin
P1
Package Length
Range
4/4/8 7/4/12 8/5/10
L2 S1
L1
SL SL
Min:0.5"
Max:5.0"
SO-DIMM PADS
MS
Data Signals Topologies and Routing Guidelines
4/4 8/8
P1
L1 L2
SO-DIMM
PADS
S1SL SL MS
5/10
GMCH
Pin
Package Length
Range
Control Signals Topologies and Routing Guidelines
GMCH
Pin
P1
Package Length
Range
4/4 8/8 4/8,5/10
L2
L1
SL SL
SO-DIMM PADS
L3
S1
MSMS
SL
56 ohm 5%
Command Signals Topologies and Routing Guidelines
GMCH
Pin
P1
Package Length
Range
L1
SL SL SL MSMS S1
5
L2 L3
SO-DIMM
PADS
Clock - 1.0"
Clock - 1.0"
Clock - 1.0"
Clock - 1.0"
Strobe - 25 mils Strobe + 25 mils
7 mil trace, 4 mil pair space
Clock length tolerence within the pair : +/- 10 mil
Clock to Clock Length Matching : +/- 10 mils
Minimum Pair to Pair Spacing : ? mils
Minimum Spacing to other DDR Signals : 12 mils
Minimum Spacing to other non-DDR Signals : 20 mils
Trace Length L1 : Max 0.5", S1 : Max 200 mils
Total Length --L1+L2+S1: Min 0.5" , Max 5.0"
Minimum Spacing to other DDR Signals : 12 mils
Minimum Spacing to other non-DDR Signals : 20 mils
Trace Width : 4mils
Trace Spacing : 6mils
Total Length --L1+L2+S1: Min 0.5" , Max 4.5"
Trace Length L1 : Max 0.5", S1 : Max 200 mils
DQ/DM to DQSLength Matching : +/- 10 mils
inner layerL2 Segment : 4 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 5 mils
inner layerL2 Segment : 6 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 10 mils
Minimum CTRL trace Spacing : 8 mils
Minimum Spacing to other DDR Signals : 12 mils
Minimum Spacing to other non-DDR Signals : 20 mils
Trace Length L1 : Max 0.5"
Total Length --L1+L2+S1: Min 0.5" , Max 4.5"
CTRL to SCK/SCK# Length Matching : (CTRL-1.5")
</= CTRL </= ( CLK 1.0")
Minimum Spacing to other DDR Signals : 12 mils
Minimum Spacing to other non-DDR Signals : 20 mils
Trace Width : 4mils
56 ohm 5%
Trace Spacing : 6mils
Total Length --L1+L2+S1: Min 0.5" , Max 4.5"
Trace Length L1 : Max 0.5", S1 : Max 200 mils
Trace Length L3 : Max 1.5"
Length Matching : CMD to SCK/SCK#
4
Clock + 0.5"
Clock + 2.0"
Clock + 0.5"
Clock + 0.5"
L3 : Max 1.5"
inner layerL2 Segment : 4 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 5 mils
inner layerL2 Segment : 6 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 10 mils
CMD , SODIMM0 P1+L1+L2
CMD , SODIMM1 P1+L1+L3
Min : Clock - 1.5" , Max : Clock -1.0"
Data Strobe Signals Topologies and Routing Guidelines
GMCH
Pin
P1
Package Length
Range
CK410-M
LENGTHCLOCKS
3
L1 : Max 0.5"
L2 : Max 200mils
L3 : Max 0.5"
L4 : Min 2" Max 8 "
L1 : Max 0.5"
L2 : Max 200mils
L3 : Max 200 mils
L4 : Min 200 mils
Max 12"
L1 : Max 0.5"
L2 : Max 200mils
L3 : Max 200 mils
L4 : Min 4" Max 10"
L1 : Max 0.5"
L2 : Min 2" Max 20"
L1 : Max 0.5"
L2 : Min 2" Max 20"
L2 : Z +(0" to 10")
,Max 20"
L2 : Z +(0" to 6")
,Max 20"
L1 : Max 0.5"
L2 : Max 18"
HCLKCPU[1..0]
HCLKNB[1..0]
HCLKITP[1..0]
SRC CLK
DOT CLK
CLOCKS TRACE MUTCHING
USB (48MHZ)
CLK
PCI/PCIF
CLK
PCLKICH
PCLKFWH
PCLKSIO
PCLKLAN
14MCLK_SIO
14MCLK_ICH
14MCLK_AC97
4/4/12
8/4/12
4/4/8
L2 S1
SL SL MS
RS
L1 L2
MS
L1 L2
MS
RS
4 / 7 mils
4 / 7 mils
50 mils
(spacing
to other)
4 / 7 mils
25 mils
(spacing
to other)
TRACE / SPACE SKEW
4 mils
(stripline)
20 mils
(spacing
to other)
4 mils
(stripline)
10 mils
(spacing
to other)
4 mils
(stripline)
10 mils
(spacing
to other)
5/5/10 SO-DIMM PADS
L4
MS
MS
SL
L4
SL
L3L3
MS MS
TRACE MUTCHING
L1+/L1- : +/- 10 mils
L2+/L2- : +/- 10 mils
L3+/L3- : +/- 10 mils
L1+L2+L3 /L1- + L2- + L3-
: +/- 10 mils
L4+/L4- : 200 +/- 10
mils (for PGA Topology)
L4+/L4- : 500 +/- 10
mils (for BGA Topology)
L1+L2+L4 /L1- + L2- + L4-
: +/- 25 mils
+/- 10 mils 33 ohms
NA
NA
(L1+L2) to ICH6-M
must be within 500
nils to (L1+L2) to
SIO/AC97
CPU,GMCH
2
Minimum Spacing to other DDR Signals : 12 mils
Minimum Spacing to other non-DDR Signals : 20 mils
Trace Width : 4mils
DQS to DQS# Spacing : 4mils
Minmun DQS to DQ Spacing :
Total Length --L1+L2+S1: Min 0.5" , Max 4.5"
Trace Length L1 : Max 0.5", S1 : Max 200 mils
Length Matching : DQS to SCK/SCK#
33 ohms
+/- 5%
+/- 5% to
33 ohms
+/- 5%
+/- 5%
inner layerL2 Segment : 4 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 5 mils
outer layerL2 Segment : 5 mils
inner layerL2 Segment : 6 mils,Total
Length < /= 3000 mils
inner layerL2 Segment : 8 mils,Total
Length > 3000 mils
outer layerL2 Segment : 10 mils
( Clock - 1.0") </= DQS </= ( Clock + 0.5")
MS
CK410-M
49.9 ohms
+/- 1%
49.9 ohms
+/- 1%
49.9 ohms
+/- 1%
L1 L2 CPU,GMCHL4
MS
R1
RtRs
IMPEDANCE
100 ohms
+/- 15%
differential mode
55 ohms
+/- 15%
single mode
55 ohms
+/- 15%
100 ohms
+/- 15%
MS
MS
SKEW
350ps Total
Budget
100ps for flight
skew
100ps for pin to
pin skew
150ps for jitter
NA22 ohms
SL
SL
Differentials pairs with
the same length
(within 10 mil)
1.
2.CPU & NB trace
mismatch within
450 mil
* 66MCLK_ICH &
AGPCLK_GMCH
AGPCLK_ATI
Length mismatch
within 100 mils
1.Making PCI length with
2.Max skew = 1ns
IMPEDANCE
33 ohms
+/- 5%
12.1 ohms
+/- 1%
33 ohms
+/- 5%
12.1 ohms
+/- 1%
55 ohms
+/- 15%
55 ohms
+/- 15%
55 ohms
+/- 15%
Title
AT11 < Dothan + 915GM + ICH6-M >
Size Document Number Rev
C
DDRII/CLK Gen Layout Guideline
Date: Sheet
NONE
NONE
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
1
NOTESTRACE / SPACE
minimum various
NOTESR1LENGTH Rt
of
863Wednesday, February 16, 2005
0.1
A
AGTL+_HA0[31..3](16) AGTL+_HD0[63..0] (16)
AGTL+_HA03
AGTL+_HA04
AGTL+_HA05
AGTL+_HA06
AGTL+_HA07
AGTL+_HA08
AGTL+_HA09
AGTL+_HA010
AGTL+_HA011
AGTL+_HA012
AGTL+_HA013
AGTL+_HA014
4 4
AGTL+_ADSTB00(16)
AGTL+_HREQ0[4..0](16)
AGTL+_ADSTB10(16)
AGTL+_ADS0(16)
ITP_TCK
ITP_TDI
ITP_TMS
AGTL+_BNR0(16)
AGTL+_BR00(16)
AGTL+_DEFER0(16)
AGTL+_DRDY0(16)
AGTL+_DBSY0(16)
AGTL+_HIT0(16)
AGTL+_HITM0(16)
VCCP(10,17,18,19,20,21,23,53)
CPU_INIT0(19)
AGTL+_LOCK0(16)
AGTL+_RS0[2..0](16)
AGTL+_TRDY0(16)
AGTL+_CPURST0(16)
VCCP(10,17,18,19,20,21,23,53)
CPU_PWRGOOD(19)
CPU_A20M0(19)
CPU_FERR0_OD(19)
CPU_IGNNE0(19)
CPU_INTR(19)
CPU_NMI(19)
CPU_SMI0(19)
CPU_STPCLK0(19)
CPU_SLP0(16,19)
CPU_DPSLP0(19)
AGTL+_BPRI0(16)
AGTL+_DPWR0(16)
VCCP(10,17,18,19,20,21,23,53)
R550 SHW 0 5% 1/16W 0603
VCCP(10,17,18,19,20,21,23,53)
R546
56.2 1% 1/16W 0402
R536 56 5% 1/16W 0402
R534
39.2 1% 1/16W 0603
R549
150 5% 1/16W 0603
680 5% 1/16W 0402
3 3
Place testpoint on IERR# with
a GND 0.1" away
2 2
THRMTRIP0 should coonect to
ICH6 and ALVISO without
T-ing (No stub)
CPU_BCLK(23)
CPU_BCLK0(23)
CPU_ITP_BCLK
CPU_ITP_BCLK0
1 1
THERMDA(12)
THERMDC(12)
THRMTRIP0(14,20)
ITP_TDO_OD
ITP_TRST0
AGTL+_PRDY0
AGTL+_PREQ0
A
AGTL+_HA015
AGTL+_HA016
AGTL+_HREQ00
AGTL+_HREQ01
AGTL+_HREQ02
AGTL+_HREQ03
AGTL+_HREQ04
AGTL+_HA017
AGTL+_HA018
AGTL+_HA019
AGTL+_HA020
AGTL+_HA021
AGTL+_HA022
AGTL+_HA023
AGTL+_HA024
AGTL+_HA025
AGTL+_HA026
AGTL+_HA027
AGTL+_HA028
AGTL+_HA029
AGTL+_HA030
AGTL+_HA031
CPU_IERR0_OD
AGTL+_RS00
AGTL+_RS01
AGTL+_RS02
R531
200 1% 1/16W 0603
R535
B
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3
R2
P3
T2
P1
T1
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
N2
L1
N4
L4
H2
M2
K3
K4
A4
B5
J2
H1
K1
L2
M3
B11
E4
C2
D3
A3
D1
D4
B4
C6
A6
B7
J3
C19
B18
A18
C17
B17
B15
B14
A16
A15
A13
C12
A12
C11
B13
A10
B10
R547
27.4 1% 1/16W 0402
B
U1-1
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB1#
ADS#
BNR#
BR0#
DEFER#
DRDY#
DBSY#
HIT#
HITM#
IERR#
INIT#
LOCK#
RS0#
RS1#
RS2#
TRDY#
RESET#
PWRGOOD
A20M#
FERR#
IGNNE#
LINT0
LINT1
SMI#
STPCLK#
SLP#
DPSLP#
BPRI#
DPWR#
THERMDA
THERMDC
THERMTRIP#
PROCHOT#
BCLK0
BCLK1
ITP_CLK0
ITP_CLK1
TCK
TDI
TDO
TMS
TRST#
PRDY#
PREQ#
SCKT Foxconn SMT PZ47903-2741-01
Address Group0 Control Signal Legacy CPU Thermal Host CLK ITP700 PortAddress Group1
GTLREF2/DPRSTP#
20-10166-30
Data Group0Data Group1Data Group2Data Group3
DINV0#
DSTBN0#
DSTBP0#
DINV1#
DSTBN1#
DSTBP1#
DINV2#
DSTBN2#
DSTBP2#
DINV3#
DSTBN3#
DSTBP3#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
GTLREF0/RSVD
GTLREF1
GTLREF3/RSVD
RSVD0
RSVD1
RSVD2/BSEL1
RSVD3
RSVD4/BSEL0
RSVD5/PSI#
TEST1
TEST2
COMP0
COMP1
COMP2
COMP3
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
AGTL+_HD00
A19
AGTL+_HD01
A25
AGTL+_HD02
A22
AGTL+_HD03
B21
AGTL+_HD04
A24
AGTL+_HD05
B26
AGTL+_HD06
A21
AGTL+_HD07
B20
AGTL+_HD08
C20
AGTL+_HD09
B24
AGTL+_HD010
D24
AGTL+_HD011
E24
AGTL+_HD012
C26
AGTL+_HD013
B23
AGTL+_HD014
E23
AGTL+_HD015
C25
D25
C23
C22
AGTL+_HD016
H23
AGTL+_HD017
G25
AGTL+_HD018
L23
AGTL+_HD019
M26
AGTL+_HD020
H24
AGTL+_HD021
F25
AGTL+_HD022
G24
AGTL+_HD023
J23
AGTL+_HD024
M23
AGTL+_HD025
J25
AGTL+_HD026
L26
AGTL+_HD027
N24
AGTL+_HD028
M25
AGTL+_HD029
H26
AGTL+_HD030
N25
AGTL+_HD031
K25
J26
K24
L24
AGTL+_HD032
Y26
AGTL+_HD033
AA24
AGTL+_HD034
T25
AGTL+_HD035
U23
AGTL+_HD036
V23
AGTL+_HD037
R24
AGTL+_HD038
R26
AGTL+_HD039
R23
AGTL+_HD040
AA23
AGTL+_HD041
U26
AGTL+_HD042
V24
AGTL+_HD043
U25
AGTL+_HD044
V26
AGTL+_HD045
Y23
AGTL+_HD046
AA26
AGTL+_HD047
Y25
T24
W25
W24
AGTL+_HD048
AB25
AGTL+_HD049
AC23
AGTL+_HD050
AB24
AGTL+_HD051
AC20
AGTL+_HD052
AC22
AGTL+_HD053
AC25
AGTL+_HD054
AD23
AGTL+_HD055
AE22
AGTL+_HD056
AF23
AGTL+_HD057
AD24
AGTL+_HD058
AF20
AGTL+_HD059
AE21
AGTL+_HD060
AD21
AGTL+_HD061
AF25
AGTL+_HD062
AF22
AGTL+_HD063
AF26
AD20
AE24
AE25
C8
B8
A9
C9
A7
AD26
CPU_NC_E26
E26
G1
CPU_NC_AC1
AC1
CPU_NC_B2
B2
CPU_NC_AF7
AF7
C14
CPU_NC_C3
C3
C16
E1
R532 1K 5% 1/16W 0402(NU)
C5
R529 1K 5% 1/16W 0402(NU)
F23
P25
P26
AB2
AB1
Less than 0.5"
AGTL+_HD0[63..0]AGTL+_HA0[31..3]
AGTL+_DINV00 (16)
AGTL+_DSTBN00 (16)
AGTL+_DSTBP00 (16)
AGTL+_DINV10 (16)
AGTL+_DSTBN10 (16)
AGTL+_DSTBP10 (16)
AGTL+_DINV20 (16)
AGTL+_DSTBN20 (16)
AGTL+_DSTBP20 (16)
AGTL+_DINV30 (16)
AGTL+_DSTBN30 (16)
AGTL+_DSTBP30 (16)
AGTL+_BPM00
AGTL+_BPM10 (14)
AGTL+_BPM20 (14)
R552 0 5% 1/16W 0402(NU)
AGTL+_BPM30
GTLREF = 2/3 VCCP
Max Length : 0.5"
Place within 2"
R520 27.4 1% 1/16W 0402
R523 54.9 1% 1/16W 0603
R515 27.4 1% 1/16W 0402
R514 54.9 1% 1/16W 0603
C
ITP_DBRESET0 (20)
R512
2K 1% 1/16W CF 0402
IMVP4 POWER STATUS INCADITOR
Comp(0,2) must be routed width
18 mils Zo=27.4ohm ,make trace
length shorter than 0.5"
Comp(1,3) must be routed width
5 mils Zo=55 ohm ,make trace
length shorter than 0.5"
C
R5111K 1% 1/16W 0402
CPU_DPRSTP0 (19)
CPU_BSEL1 (23)
CPU_BSEL0 (23)
PM_PSI0 (11)
D
VCCP (10,17,18,19,20,21,23,53)
D
E
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
CPU ( Dothan ) 1/2
E
of
963Thursday, April 14, 2005
0.1
A
B
C
D
E
VCORE_CPU(11,32,43)
U1-2
D6 D10
VCC0 VCCP0
D8
VCC1
D18
VCC2
D20
VCC3
D22
VCC4
E5
VCC5
4 4
Intel Recommend Option 5
4 X 220UF & 35 X 10UF 0805 X5R
C435 10uF 6.3V 10% 0805 X5R TAIYO
C430 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C448 10uF 6.3V 10% 0805 X5R TAIYO
C434 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C455 T-CAP 220uF 2V-35 to +10% SMT7343 SP CAP EEFSX00221 PANASONIC
C439 T-CAP 220uF 2V-35 to +10% SMT7343 SP CAP EEFSX00221 PANASONIC
C458 T-CAP 220uF 2V-35 to +10% SMT7343 SP CAP EEFSX00221 PANASONIC
+
+
3 3
C457 T-CAP 220uF 2V-35 to +10% SMT7343 SP CAP EEFSX00221 PANASONIC(NU)
C456 T-CAP 220uF 2V-35 to +10% SMT7343 SP CAP EEFSX00221 PANASONIC
+
+
+
C426 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C463 10uF 6.3V 10% 0805 X5R TAIYO
C437 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C454 10uF 6.3V 10% 0805 X5R TAIYO
C429 10uF 6.3V 10% 0805 X5R TAIYO
C441 10uF 6.3V 10% 0805 X5R TAIYO
C462 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C428 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C464 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C466 10uF 6.3V 10% 0805 X5R TAIYO
C452 10uF 6.3V 10% 0805 X5R TAIYO
C427 10uF 6.3V 10% 0805 X5R TAIYO
C445 10uF 6.3V 10% 0805 X5R TAIYO
C433 10uF 6.3V 10% 0805 X5R TAIYO
C465 10uF 6.3V 10% 0805 X5R TAIYO
C58 10uF 6.3V 10% 0805 X5R TAIYO
C432 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C451 10uF 6.3V 10% 0805 X5R TAIYO
C438 10uF 6.3V 10% 0805 X5R TAIYO
C459 10uF 6.3V 10% 0805 X5R TAIYO
C449 10uF 6.3V 10% 0805 X5R TAIYO
C446 10uF 6.3V 10% 0805 X5R TAIYO
C460 10uF 6.3V 10% 0805 X5R TAIYO
C61 10uF 6.3V 10% 0805 X5R TAIYO
C447 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C461 10uF 6.3V 10% 0805 X5R TAIYO
C59 10uF 6.3V 10% 0805 X5R TAIYO
C453 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C450 10uF 6.3V 10% 0805 X5R TAIYO(NU)
C60 10uF 6.3V 10% 0805 X5R TAIYO
C431 10uF 6.3V 10% 0805 X5R TAIYO
E7
VCC6
E9
VCC7
E17
VCC8
E19
VCC9
E21
VCC10
F6
VCC11
F8
VCC12
F18
VCC13
F20
VCC14
F22
VCC15
G5
VCC16
G21
VCC17
H6
VCC18
H22
VCC19
J5
VCC20
J21
VCC21
K22
VCC22
U5
VCC23
V6
VCC24
V22
VCC25
W5
VCC26
W21
VCC27
Y6
VCC28
Y22
VCC29
AA5
VCC30
AA7
VCC31
AA9
VCC32
AA11
VCC33
AA13
VCC34
AA15
VCC35
AA17
VCC36
AA19
VCC37
AA21
VCC38
AB6
VCC39
AB8
VCC40
AB10
VCC41
AB12
VCC42
AB14
VCC43
AB16
VCC44
AB18
VCC45
AB20
VCC46
AB22
VCC47
AC9
VCC48
AC11
VCC49
AC13
VCC50
AC15
VCC51
AC17
VCC52
AC19
VCC53
AD8
VCC54
AD10
VCC55
AD12
VCC56
AD14
VCC57
AD16
VCC58
AD18
VCC59
AE9
VCC60
AE11
VCC61
AE13
VCC62
AE15
VCC63
AE17
VCC64
AE19
VCC65
AF8
VCC66
AF10
VCC67
AF12
VCC68
AF14
VCC69
AF16
VCC70
AF18
VCC71
SCKT Foxconn SMT PZ47903-2741-01
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VCCA0
VCCA1
VCCA2
VCCA3
VCCsense
SHW 0 5% 1/16W 0402
R533
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21
P23
W4
F26
VCCA1
B1
VCCA2
N1
VCCA3
AC26
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AE7
C78 0.1uF 16V 10% 0603 X7R
R36
54.9 1% 1/16W 0603(NU)
C86 0.1uF 16V 10% 0603 X7R
C81 0.1uF 16V 10% 0603 X7R(NU)
Note: Dothan Processor 533MHZ A2
STEP use both 1.8V&1.5V
Dothan Processor 533MHZ B
STEP only use 1.5V
VR_VID0 (11)
VR_VID1 (11)
VR_VID2 (11)
VR_VID3 (11)
VR_VID4 (11)
VR_VID5 (11)
C80 0.1uF 16V 10% 0603 X7R(NU)
C77 0.1uF 16V 10% 0603 X7R(NU)
C85 0.1uF 16V 10% 0603 X7R(NU)
C83 0.1uF 16V 10% 0603 X7R
C90 10uF 6.3V 10% 0805 X5R TAIYO
C91 0.01uF 16V 10% 0402 X7R(NU)
20-10166-30
2 2
Layout note :
Provide a test point (with no stub) to connect a
differential probe between VCCSENSE and VSSENSE
at the location where the two 54.9ohm resistors
terminate the 55ohm transmission line
Layout note :
VCCSENSE and VSSENSE lines
should be of equal length
VCCP(9,17,18,19,20,21,23,53)
C76 0.1uF 16V 10% 0603 X7R
C79 0.1uF 16V 10% 0603 X7R
C84 0.1uF 16V 10% 0603 X7R
R850 5% 1/8W 0805
R840 5% 1/8W 0805(NU)
C471
+
T150uF 2V ±20% 18mΩ SMT7343 LOW ESR EEFCD0D151R PANASONIC
1.5VDDM (13,14,17,19,21,53,57)
1.8VDDM (36,45,57)
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
U1-3
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSSsense
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
AF6
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
SCKT Foxconn SMT PZ47903-2741-01
20-10166-30
One Ground
R37
54.9 1% 1/16W 0603(NU)
One Via
1 1
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
CPU ( Dothan ) 2/2
E
of
10 63Thursday, April 14, 2005
0.1
5
4
3
2
1
VCORE_CPU
DCIN(31,44,46,53,55,57)
C94
C472
10uF 25V ±10% SMT1206 X6S TMK316C106KL-T TAIYO
C104
100KΩ 1% 1/16W MF SMT0402
VCORE_AGND
R528
R543
17.4K 1% 1/16W 0402
C470
R545
3.57K 1% 1/8W 0805
+
T15uF 25V ±20% 90mΩ 7343 25TQC15M SANYO(NU)
C92
0.022uF 16V 10% 0402 X7R
D D
VCORE_AGND
R81
VCORE_AGND
C C
VCORE_AGND
PM_VGATE(14,20)
B B
R96
SHW 0 5% 1/16W 0402
PM_DPRSLPVR(20)
VCORE_AGND
3VDDM(17,19,20,21,23,24,25,26,27,28,30,31,32,35,36,37,38,39,40,41,44,47,49,50,53,56,57,58)
R527
200K 1% 1/16W 0603
VRON_VCCP(53)
R74 SHW 0 5% 1/16W 0402
R78 SHW 0 5% 1/16W 0402
R79 SHW 0 5% 1/16W 0402
STPCPU0(20,23)
R80 0 5% 1/16W 0402(NU)
PM_PSI0(9)
R86 SHW 0 5% 1/16W 0402
VR_VID0(10)
R87 SHW 0 5% 1/16W 0402
VR_VID1(10)
R88 SHW 0 5% 1/16W 0402
VR_VID2(10)
R89 SHW 0 5% 1/16W 0402
VR_VID3(10)
R90 SHW 0 5% 1/16W 0402
VR_VID4(10)
R91 SHW 0 5% 1/16W 0402
VR_VID5(10)
R542
2K 0.5% 1/16W 0603
C99
NU_ 0.1UF 10V 10% SMT0402 X5R
1.21KΩ 1% 1/16W MF SMT0603
2200pF 50V 10% 0402 X7R
10uF 25V ±10% SMT1206 X6S TMK316C106KL-T TAIYO
5VDDM(12,21,31,36,37,39,41,45,47,50,51,52,56,57)
R75
10 5% 1/16W 0603
1UF 10V 10% SMT0603 X5R
C87
VCORE_AGND
C100
NU_ 0.1UF 10V 10% SMT0402 X5R
C97
NU_3300pF 50V 10% SMD0402 X7R
R544
NU_0 1% 1/16W 0603
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
LNR-IC ISL6218CV-T TSSOP 38PIN INTERSIL
12
C98
0.012uF 50V ±10% SMT0603
C469
C468
C467
10uF 25V ±10% SMT1206 X6S TMK316C106KL-T TAIYO
10uF 25V ±10% SMT1206 X6S TMK316C106KL-T TAIYO
0.1µF 10% 25V 0805 X7R
C88
1uF 25V 10% 1206 X7R
VCORE_AGND
U2
VDD
DACOUT
DSV
FSET
NC
EN
DRSEN
DSEN#
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT VSS
VCORE_AGND
VBAT
ISEN1
PHASE1
BOOT1
VSSP1
VDDP
VSEN
DRSV
OCSET
UG1
LG1
NC
NC
NC
NC
NC
NC
STV
VCORE_AGND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCORE_AGND
D27
P N
4.3K 0.5% 1/10W SMT0603(NU)
DIODE STKY CH751H-40 40V CHENMKO
R525
R76 510 1% 1/16W 0603
C96
4.7uF 25V ±20% SMT0805 X5R ECJ2FB1E475M PANASONIC
R541
121K 1% 1/16W 0603
C102
C101
1uF 10V 10% 0805 X7R
C103
2200pF 50V 10% 0603 X7R
560pF 50V 5% SMT0603 X7R
D S
40mil
C93
0.22uF 10V 10% 0603 X7R
R82
2.2 1% 1/16W SMT0402
≧
54.9KΩ 1% 1/16W CF SMT0603
R540
R539
45.3KΩ 1% 1/16W MF SMT0603
R538
75KΩ 1% 1/16W SMT0402 Lead-Free
VCORE_AGND
Q5
TR M-FET-N AOD404 30V 85A TO-252 3PIN AOS
G
DS
Q46
40mil
≧
40mil
≧
G
G
TRANS M-FET-N AOD414 30V 85A TO-252 3PIN AOS
R524
Boost Voltage 1.2V
Deeper Sleep Voltage 0.748V
0.62uH 30A SPM12550T-R62M300 ±20% TDK
L6
DS
Q48
D26
TRANS M-FET-N AOD414 30V 85A TO-252 3PIN AOS
2mΩ 20% 2W SMTRL7520WT-R002-M CYNTEC
C444
DIODE STKY SM340A 40V 3A DO-214C (SMA) SECOS
1000pF 50V 10% 0603 X7R
VCORE_CPU 25A
For Banias Celeren CPU
C440 1uF +80-20% 16V 0805 Y5V(NU)
OCP Setting
1.Iocset=1.75V/(54.9K+45.3K+75K)=10uA
2.Isen1=10uA/(1/4)/0.87=45.9uA
3.Isen1*Rsence=Iocp*Rds_on (Lowside)
Iocp=(Isen1*Rsence)/Rds_on (Lowside)
VCORE_CPU (10,32,43)
DIODE ZENER RLZ2.4B 2.53V 0.02A 4% 0.4W
D25
R95
1K 1% 1/16W 0402
R99
DS
Q50
TR M-FET-N 2N7002E 60V SOT-23 SILICONIX
A A
5
G
10K 1% 1/16W 0402
SHW 0 5% 1/16W 0402
R98
Q49
DS
TR M-FET-N 2N7002E 60V SOT-23 SILICONIX
G
4
CK408_PWRGD0 (23)
VCORE_ON (53)
R68 Close C93
SPWR 0 5% 1/8W 0805
2 VIA 2 VIA
VCORE_AGND
R526
IMVP IV
Load line slope : -3mV/A
Vdroop : 25A*3mV/A=75mV
Idroop : 75mV/6.04K=12.4uA
12.4uA/0.875/0.5 = 28.34uA
Rds(on) *Io = Isen * Rsen
(6m/2)*25A=28.34uA*Rsen
R3 = 2.64K
3
2
Title
Size Document Number Rev
C
Date: Sheet
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Vcore
1
of
11 63Thursday, April 14, 2005
0.1
8
7
6
5
4
3
2
1
5VDDM(11,21,31,36,37,39,41,45,47,50,51,52,56,57)
30mil
D D
R910
10K 5% 1/16W 0402(NU)
Trace=10mil and together
KBC_FAN_ON(39)
5VDDM(11,21,31,36,37,39,41,45,47,50,51,52,56,57)
3VDDS(27,28,29,32,35,37,38,42,43,44,47,48,51)
C C
R556
R555
0 5% 1/16W 0402
HOT_DOWN(43,55)
QSMCLK_PMU(35)
QSMDAT_PMU(35)
R553
10mil
10K 5% 1/16W 0402
SUSCLKO(20)
10K 5% 1/16W 0402
R554
20mil
10K 5% 1/16W 0402
10mil
U28
LNR-IC G795S1U SSOP-16L 16PIN GMT
1
Test
15
DVCC
10
THERM#
14
SCL
13
SDA
12
ALERT#
11
CLK
Q80
*TRANS M-FET-P SI2301DS SMT SOT-23 VISHAY-SILICONIX(NU)
32
1
C825
0.1uF 25V 80-20% 0603 Y5V(NU)
R911
1K 1% 1/16W 0402 (NU)
CE
B
Q81
NPN DTC144WU 50V 100mA SMT ROHM(NU)
5VDDM(11,21,31,36,37,39,41,45,47,50,51,52,56,57)
R551
10K 5% 1/16W 0402
TRACE 30MIL
16
FAN1
100MHZ 600Ω 25% SMT0603 HCB1608K-601T10 BULL WILL
3
FG1
5
VCC
2
THERM_SET
GND
4
DXP1
SGND1
DXP2
SGND2
6
7
8
9
R100
10K 5% 1/16W 0402
30mil
C474
C 0.1uF 16V 80-20% 0402 Y5V
C473
2200pF 50V 10% 0402 X7R
100MHZ 600Ω 25% SMT0603 HCB1608K-601T10 BULL WILL
L8
L7
R94
100 5% 1/10W 0603
trace10mil and together
1
1
CN13
2
2
3
3
CON ENTERY SMT 3PIN P=1.25 3802-03
20-24197-00
5VDDS (29,31,33,34,38,41,43,44,45,47,53)
THERMDA (9)
THERMDC (9)
1.Far away the CRT,clock generator,memory bus,PCI bus.
2.As close CPU as possible.
10 mil
10 mil
10 mil
MINIMUM
10 mil
GND
THERMDA
THERMDC
GND
THERMAL SENSOR
B B
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet
2
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
Thermal / FAN CNN
of
12 63Thursday, April 14, 2005
1
0.1
5
4
3
2
1.5VDDM(10,14,17,19,21,53,57)
1
D D
MCH_CLK_3GPLL0(23)
MCH_CLK_3GPLL(23)
TV_DAC_A(26)
TV_DAC_B(26)
TV_DAC_C(26)
Note:
CRT_Red,CRT_Green,CRT_Blue
are groud reference
C C
B B
VECLK(56,57)
VEDAT(56,57)
BLUE(26)
GREEN(26)
RED(26)
VSYNC(26)
HSYNC(26)
LVDS_ENALCD(31)
LVDS_ENABKL(31,40)
DDC_PDATA(31)
DDC_PCLK(31)
LVDS_TXCLK_LN(31)
LVDS_TXCLK_LP(31)
LVDS_TXCLK_UN(31)
LVDS_TXCLK_UP(31)
LVDS_TXOUT_U2P(31)
LVDS_TXOUT_U1P(31)
LVDS_TXOUT_U0P(31)
LVDS_TXOUT_U2N(31)
LVDS_TXOUT_U1N(31)
LVDS_TXOUT_U0N(31)
LVDS_TXOUT_L2P(31)
LVDS_TXOUT_L1P(31)
LVDS_TXOUT_L0P(31)
LVDS_TXOUT_L2N(31)
LVDS_TXOUT_L1N(31)
LVDS_TXOUT_L0N(31)
R146150 1% 1/16W 0402(NU)
R147150 1% 1/16W 0402(NU)
R148150 1% 1/16W 0402(NU)
NC_LCD_BRIGHTNESS
NC_LCTLA_CLK
NC_LCTLB_DATA
R606 4.99K 1% 1/16W SMT0402
R616150 1% 1/16W 0402(NU)
R618150 1% 1/16W 0402(NU)
R620150 1% 1/16W 0402(NU)
R635 39 1% 1/16W 0603
R634 39 1% 1/16W 0603
R646 0 5% 1/16W 0402(NU)
R636 0 5% 1/16W 0402(NU)
R615
255 1% 0402
R644 0 5% 1/16W 0402(NU)
R643 0 5% 1/16W 0402(NU)
R654 0 5% 1/16W 0402(NU)
BLUE
GREEN
RED
NC_915GM_C31
NC_915GM_F28
NC_915GM_F27
NC_ALVISO_H24
NC_ALVISO_H25
BLUE#
GREEN#
RED#
REFSET
LIBG
U5A
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
AB29
GCLKN
AC29
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCACLK
E23
DDCADATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
F26
LVDDEN
F25
PANELBKLTEN
E25
PANELBKLTCTL
F22
DDCPDATA
F23
DDCPCLK
C23
LCTLACLK
C22
LCTLBDATA
B30
ICLKAN
B29
ICLKAP
C25
ICLKBN
C24
ICLKBP
C26
LBDATAP2
D27
LBDATAP1
C28
LBDATAP0
C27
LBDATAN2
D28
LBDATAN1
C29
LBDATAN0
B31
LADATAP2
A33
LADATAP1
A34
LADATAP0
B32
LADATAN2
B33
LADATAN1
B34
LADATAN0
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
LVDS
D36
EXP_COMPI
D34
EXP_ICOMPO
E30
MISC
TV
VGA
EXP_RXN0
F34
EXP_RXN1
G30
EXP_RXN2
H34
EXP_RXN3
J30
EXP_RXN4
K34
EXP_RXN5
L30
EXP_RXN6
M34
EXP_RXN7
N30
EXP_RXN8
P34
EXP_RXN9
R30
EXP_RXN10
T34
EXP_RXN11
U30
EXP_RXN12
V34
EXP_RXN13
W30
EXP_RXN14
Y34
EXP_RXN15
D30
EXP_RXP0
E34
EXP_RXP1
F30
EXP_RXP2
G34
EXP_RXP3
H30
EXP_RXP4
J34
EXP_RXP5
K30
EXP_RXP6
L34
EXP_RXP7
M30
EXP_RXP8
N34
EXP_RXP9
P30
EXP_RXP10
R34
EXP_RXP11
T30
EXP_RXP12
U34
EXP_RXP13
V30
EXP_RXP14
W34
EXP_RXP15
E32
EXP_TXN0
F36
EXP_TXN1
G32
EXP_TXN2
H36
EXP_TXN3
J32
EXP_TXN4
K36
EXP_TXN5
L32
EXP_TXN6
M36
EXP_TXN7
N32
EXP_TXN8
P36
EXP_TXN9
R32
EXP_TXN10
T36
EXP_TXN11
U32
EXP_TXN12
V36
EXP_TXN13
W32
EXP_TXN14
Y36
EXP_TXN15
PCI-EXPRESS GRAPHICS
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
R660
24.9 1% 1/16W MF 0603
NB_PEG_RXP15 (57)
NB_PEG_RXP14 (57)
NB_PEG_RXP13 (57)
NB_PEG_RXP12 (57)
NB_PEG_RXP11 (57)
NB_PEG_RXP10 (57)
NB_PEG_RXP9 (57)
NB_PEG_RXP8 (57)
NB_PEG_RXP7 (57)
NB_PEG_RXP6 (57)
NB_PEG_RXP5 (57)
NB_PEG_RXP4 (57)
NB_PEG_RXP3 (57)
NB_PEG_RXP2 (57)
NB_PEG_RXP1 (57)
NB_PEG_RXP0 (57)
NB_PEG_RXN15 (57)
NB_PEG_RXN14 (57)
NB_PEG_RXN13 (57)
NB_PEG_RXN12 (57)
NB_PEG_RXN11 (57)
NB_PEG_RXN10 (57)
NB_PEG_RXN9 (57)
NB_PEG_RXN8 (57)
NB_PEG_RXN7 (57)
NB_PEG_RXN6 (57)
NB_PEG_RXN5 (57)
NB_PEG_RXN4 (57)
NB_PEG_RXN3 (57)
NB_PEG_RXN2 (57)
NB_PEG_RXN1 (57)
NB_PEG_RXN0 (57)
C274 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C272 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C270 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C268 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C266 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C264 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C262 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C260 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C258 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C256 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C254 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C252 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C250 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C248 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C246 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C244 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C275 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C273 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C271 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C269 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C267 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C265 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C263 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C261 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C259 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C257 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C255 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C253 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C251 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C249 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C247 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
C245 MO-CAP 0.1uF 10V 10% X5R SMT0402(NU)
VGA_PEG_RXP15 (57)
VGA_PEG_RXP14 (57)
VGA_PEG_RXP13 (57)
VGA_PEG_RXP12 (57)
VGA_PEG_RXP11 (57)
VGA_PEG_RXP10 (57)
VGA_PEG_RXP9 (57)
VGA_PEG_RXP8 (57)
VGA_PEG_RXP7 (57)
VGA_PEG_RXP6 (57)
VGA_PEG_RXP5 (57)
VGA_PEG_RXP4 (57)
VGA_PEG_RXP3 (57)
VGA_PEG_RXP2 (57)
VGA_PEG_RXP1 (57)
VGA_PEG_RXP0 (57)
VGA_PEG_RXN15 (57)
VGA_PEG_RXN14 (57)
VGA_PEG_RXN13 (57)
VGA_PEG_RXN12 (57)
VGA_PEG_RXN11 (57)
VGA_PEG_RXN10 (57)
VGA_PEG_RXN9 (57)
VGA_PEG_RXN8 (57)
VGA_PEG_RXN7 (57)
VGA_PEG_RXN6 (57)
VGA_PEG_RXN5 (57)
VGA_PEG_RXN4 (57)
VGA_PEG_RXN3 (57)
VGA_PEG_RXN2 (57)
VGA_PEG_RXN1 (57)
VGA_PEG_RXN0 (57)
REFSET
R599 0 5% 1/16W 0402(NU)
BLUE
R600 0 5% 1/16W 0402(NU)
GREEN
R602 0 5% 1/16W 0402(NU)
RED
R604 0 5% 1/16W 0402(NU)
BLUE#
R601 0 5% 1/16W 0402(NU)
R617 0 5% 1/16W 0402
GREEN#
R603 0 5% 1/16W 0402(NU)
R619 0 5% 1/16W 0402
RED#
R605 0 5% 1/16W 0402(NU)
R621 0 5% 1/16W 0402
2.5VDDM_CRTDAC(17)
1.5K 1% 1/16W 0402
R658
A A
5
4
LIBG
PM BOM:
R606, R146, R147, R148 0ohm 0402
R616, R618, R620 (NU)
R599, R600, R602, R604 0ohm 0402
R601, R603, R605 0ohm 0402
R617, R619, R621, R615 (NU)
R658 (NU)
3
GM BOM:
R146, R147, R148 150ohm 1%
R606 4.99K 1%
R599, R600, R602, R604 (NU)
R601, R603, R605 (NU)
R617, R619, R621 0ohm 0402
R634, R635 39ohm 1%
R636, R646 (NU)
R616, R618, R620 150ohm 1%
R658 1.5Kohm 1%
Title
Size Document Number Rev
2
Date: Sheet
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
C
ALVISO(LVDS/PCIE/VGA/TV/MISC)
1
0.1
of
13 63Thursday, April 14, 2005
5
4
3
2
1
For ITP Port used only
R563
R564 0 5% 1/16W 0402(NU)
R572 10K 5% 1/16W 0402
D D
DMI_TXN[3..0](19)
DMI_TXP[3..0](19)
DMI_RXN[3..0](19)
DMI_RXP[3..0](19)
MGH_SMCLK_DDR0(24)
MGH_SMCLK_DDR1(24)
MGH_SMCLK_DDR3(25)
MGH_SMCLK_DDR4(25)
MGH_SMCLK_DDR00(24)
MGH_SMCLK_DDR10(24)
R624 40.2 1% 1/16W 0603
MGH_SMCLK_DDR30(25)
MGH_SMCLK_DDR40(25)
2.5VDDM(17,21,31,45,56,57)
DDR_1.8VDDS(17,24,43,44,45)
MGH_SM_CKE0(24)
MGH_SM_CKE1(24)
MGH_SM_CKE2(25)
MGH_SM_CKE3(25)
MGH_SM_CS00(24)
MGH_SM_CS10(24)
MGH_SM_CS20(24,25)
MGH_SM_CS30(25)
M_OCDCOMP0
M_OCDCOMP1
MCH_ODT0(24)
MCH_ODT1(24)
R596 40.2 1% 1/16W 0603
MCH_ODT2(25)
MCH_ODT3(25)
C C
Laout note:
Route as short as possible
Laout note:
Route as short as possible
B B
A A
DDR_VREF(24,25,44)
R565
80.6 1% 0603
R566
80.6 1% 0603
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
NC_ALVISO_AE11
NC_ALVISO_AC10
NC_ALVISO_AE10
NC_ALVISO_AD10
MGH_RCOMP0
MGH_RCOMP
MGH_SMXSLEW
MGH_SMYSLEW
R656
10K 5% 1/16W 0402
R657
10K 5% 1/16W 0402
MGH_RCOMP0
MGH_RCOMP
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AE11
AC10
AN33
AE10
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AM11
AN10
AK10
AK11
AF37
AE27
AE28
AF10
PM_EXTTS00
PM_EXTTS10
CFG7
(CPU Strap) LOW=DT/Transportable CPU
U5B
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
Y31
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
Y33
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
AL1
SM_CK1
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
SM_CK5
SM_CK0#
AK1
SM_CK1#
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
AL15
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
AD1
SMVREF1
SMXSLEWIN
SMXSLEWOUT
AF9
SMYSLEWIN
SMYSLEWOUT
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
CFG5 LOW=DMIx2
HIGH=Mobile CPU
DDR MUXING
CFG5
HIGH=DMIx4
CFG7
DMI
CFG/RSVD
PM
CLKS
NC
R570
2.2K 5% 1/16W 0402(NU)
CFG9
Graphics
Lane
R162
2.2K 5% 1/16W 0402(NU)
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREFCLKN
DREFCLKP
DREF_SSCLKN
DREF_SSCLKP
NC10
CFG6
LOW=Reverse LanePCIE
HIGH=Normal
operation
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
100 1% 1/16W 0402
A24
A23
C37
D37
NC_ALVISO_AP37
AP37
NC_ALVISO_AN37
AN37
NC_ALVISO_AP36
AP36
NC_ALVISO_AP2
AP2
NC_ALVISO_AP1
AP1
NC_ALVISO_AN1
AN1
NC_ALVISO_B1
B1
NC_ALVISO_A2
A2
NC_ALVISO_B37
B37
NC_ALVISO_A36
A36
NC_ALVISO_A37
A37
CFG6
LOW=DDR2(DDR Strap)
NC=DDR
CFG9
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
PM_EXTTS00
PM_EXTTS10
R664
AGTL+_BPM20 (9)
AGTL+_BPM10 (9)VCCP_GMCH(16,17,18)
0 5% 1/16W 0402(NU)
MCH_BSEL1 (23)
MCH_BSEL0 (23)
T1
1
T2
1
T3
1
T4
1
T5
1
T6
1
T7
1
T8
1
T9
1
T10
1
T11
1
T12
1
T13
1
T14
1
T15
1
T16
1
T17
1
T18
1
T19
1
T20
1
T21
1
T22
1
T23
1
T25
1
T26
1
T27
1
T28
1
PM_BMBUSY0 (20)
PM_EXTTS00
THRMTRIP0 (9,20)
PM_VGATE (11,20)
PLT_RST0 (19,30,36,57)
R145
2.2K 5% 1/16W 0402
CFG16
(FSB
Dynamic
ODT)
R571
2.2K 5% 1/16W 0402
CFG[2:0] 10k ohms pull up or
pull down or direct connect
form processor
T24
1
C497
MO-CAP 0.1uF 10V 10% X5R SMT0402
INTEL SUGGESTED
MCH_DREFCLK0 (23)
MCH_DREFCLK (23)
MCH_SSCLK0 (23)
MCH_SSCLK (23)
CFG16
R595
2.2K 5% 1/16W 0402(NU)
LOW=DT/Transportable CPU
HIGH=Mobile CPU
CFG18
(VCC SEL)
(VTT SEL)
LOW=1.05V
HIGH=1.5V
CFG18
LOW=1.05VCFG19
HIGH=1.2V
CFG19
MCH_SSCLK
MCH_DREFCLK
MCH_DREFCLK0
MCH_SSCLK0
2.5VDDM(17,21,31,45,56,57)
R655
1K 5% 1/16W 0402(NU)
2.5VDDM(17,21,31,45,56,57)
R645
1K 5% 1/16W 0402(NU)
GM BOM:
R1519, R1520, R1521, R1522 (NU)
PM BOM:
R1519, R1520, R1521, R1522 0ohm 0402
1.5VDDM(10,13,17,19,21,53,57)
0 5% 1/16W 0402(NU)
R641
R642
0 5% 1/16W 0402(NU)
0 5% 1/16W 0402(NU)
R633
R640
0 5% 1/16W 0402(NU)
CFG[17:3] have internal pullup resistors
CFG[19:18] have internal pulldwon resistors
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
ALVISO(DMI/CLK/PM)
1
of
14 63Thursday, April 14, 2005
0.1
5
4
3
2
1
D D
SMA_DATA[63..0](24) SMB_DATA[63..0](25)SMA_SDQS[7..0] (24)
C C
B B
SMA_DATA0
SMA_DATA1
SMA_DATA2
SMA_DATA3
SMA_DATA4
SMA_DATA5
SMA_DATA6
SMA_DATA7
SMA_DATA8
SMA_DATA9
SMA_DATA10
SMA_DATA11
SMA_DATA12
SMA_DATA13
SMA_DATA14
SMA_DATA15
SMA_DATA16
SMA_DATA17
SMA_DATA18
SMA_DATA19
SMA_DATA20
SMA_DATA21
SMA_DATA22
SMA_DATA23
SMA_DATA24
SMA_DATA25
SMA_DATA26
SMA_DATA27
SMA_DATA28
SMA_DATA29
SMA_DATA30
SMA_DATA31
SMA_DATA32
SMA_DATA33
SMA_DATA34
SMA_DATA35
SMA_DATA36
SMA_DATA37
SMA_DATA38
SMA_DATA39
SMA_DATA40
SMA_DATA41
SMA_DATA42
SMA_DATA43
SMA_DATA44
SMA_DATA45
SMA_DATA46
SMA_DATA47
SMA_DATA48
SMA_DATA49
SMA_DATA50
SMA_DATA51
SMA_DATA52
SMA_DATA53
SMA_DATA54
SMA_DATA55
SMA_DATA56
SMA_DATA57
SMA_DATA58
SMA_DATA59
SMA_DATA60
SMA_DATA61
SMA_DATA62
SMA_DATA63
U5C
AG35
SADQ0
AH35
SADQ1
AL35
SADQ2
AL37
SADQ3
AH36
SADQ4
AJ35
SADQ5
AK37
SADQ6
AL34
SADQ7
AM36
SADQ8
AN35
SADQ9
AP32
SADQ10
AM31
SADQ11
AM34
SADQ12
AM35
SADQ13
AL32
SADQ14
AM32
SADQ15
AN31
SADQ16
AP31
SADQ17
AN28
SADQ18
AP28
SADQ19
AL30
SADQ20
AM30
SADQ21
AM28
SADQ22
AL28
SADQ23
AP27
SADQ24
AM27
SADQ25
AM23
SADQ26
AM22
SADQ27
AL23
SADQ28
AM24
SADQ29
AN22
SADQ30
AP22
SADQ31
AM9
SADQ32
AL9
SADQ33
AL6
SADQ34
AP7
SADQ35
AP11
SADQ36
AP10
SADQ37
AL7
SADQ38
AM7
SADQ39
AN5
SADQ40
AN6
SADQ41
AN3
SADQ42
AP3
SADQ43
AP6
SADQ44
AM6
SADQ45
AL4
SADQ46
AM3
SADQ47
AK2
SADQ48
AK3
SADQ49
AG2
SADQ50
AG1
SADQ51
AL3
SADQ52
AM2
SADQ53
AH3
SADQ54
AG3
SADQ55
AF3
SADQ56
AE3
SADQ57
AD6
SADQ58
AC4
SADQ59
AF2
SADQ60
AF1
SADQ61
AD4
SADQ62
AD5
SADQ63
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
SARCVENOUT#
DDR SYSTEM MEMORY A
SADQS0
SADQS1
SADQS2
SADQS3
SADQS4
SADQS5
SADQS6
SADQS7
SADQS0#
SADQS1#
SADQS2#
SADQS3#
SADQS4#
SADQS5#
SADQS6#
SADQS7#
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SADM0
SADM1
SADM2
SADM3
SADM4
SADM5
SADM6
SADM7
SABS0#
SABS1#
SABS2#
SARAS#
SACAS#
SAWE#
SARCVENIN#
SMA_SDQS0
AK36
SMA_SDQS1
AP33
SMA_SDQS2
AN29
SMA_SDQS3
AP23
SMA_SDQS4
AM8
SMA_SDQS5
AM4
SMA_SDQS6
AJ1
SMA_SDQS7
AE5
SMA_SDQSN0 SMB_SDQSN0
AK35
SMA_SDQSN1
AP34
SMA_SDQSN2
AN30
SMA_SDQSN3
AN23
SMA_SDQSN4
AN8
SMA_SDQSN5
AM5
SMA_SDQSN6
AH1
SMA_SDQSN7
AE4
SMA_MA0
AL17
SMA_MA1
AP17
SMA_MA2
AP18
SMA_MA3
AM17
SMA_MA4
AN18
SMA_MA5
AM18
SMA_MA6
AL19
SMA_MA7
AP20
SMA_MA8
AM19
SMA_MA9
AL20
SMA_MA10
AM16
SMA_MA11
AN20
SMA_MA12
AM20
SMA_MA13
AM15
SMA_DQM0
AJ37
SMA_DQM1
AP35
SMA_DQM2
AL29
SMA_DQM3
AP24
SMA_DQM4
AP9
SMA_DQM5
AP4
SMA_DQM6
AJ2
SMA_DQM7
AD3
AK15
AK16
AL21
AP16
AN15
AP15
NC_SMA_RCVENOUT0
AF28
NC_SMA_RCVENIN0
AF29
SMA_SDQSN[7..0] (24)
SMA_MA[13..0] (24)
SMA_DQM[7..0] (24)
SMA_SBS00 (24)
SMA_SBS10 (24)
SMA_SBS20 (24)
SMA_SRAS0 (24)
SMA_SCAS0 (24)
SMA_SWE0 (24)
SMB_DATA0
SMB_DATA1
SMB_DATA2
SMB_DATA3
SMB_DATA4
SMB_DATA5
SMB_DATA6
SMB_DATA7
SMB_DATA8
SMB_DATA9
SMB_DATA10
SMB_DATA11
SMB_DATA12
SMB_DATA13
SMB_DATA14
SMB_DATA15
SMB_DATA16
SMB_DATA17
SMB_DATA18
SMB_DATA19
SMB_DATA20
SMB_DATA21
SMB_DATA22
SMB_DATA23
SMB_DATA25
SMB_DATA26
SMB_DATA27
SMB_DATA28
SMB_DATA29
SMB_DATA30
SMB_DATA31
SMB_DATA32
SMB_DATA33
SMB_DATA34
SMB_DATA35
SMB_DATA36
SMB_DATA37
SMB_DATA38
SMB_DATA39
SMB_DATA40
SMB_DATA41
SMB_DATA42
SMB_DATA43
SMB_DATA44
SMB_DATA45
SMB_DATA46
SMB_DATA47
SMB_DATA48
SMB_DATA49
SMB_DATA50
SMB_DATA51
SMB_DATA52
SMB_DATA53
SMB_DATA54
SMB_DATA55
SMB_DATA56
SMB_DATA57
SMB_DATA58
SMB_DATA59
SMB_DATA60
SMB_DATA61
SMB_DATA62
SMB_DATA63
U5D
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
SBDQ27
AH24
SBDQ28
AH23
SBDQ29
AG22
SBDQ30
AJ21
SBDQ31
AG10
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
AH11
SBDQ36
AH10
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
AH5
SBDQ43
AK8
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
AK4
SBDQ47
AG5
SBDQ48
AG4
SBDQ49
AD8
SBDQ50
AD9
SBDQ51
AH4
SBDQ52
AG6
SBDQ53
AE8
SBDQ54
AD7
SBDQ55
AC5
SBDQ56
AB8
SBDQ57
AB6
SBDQ58
AA8
SBDQ59
AC8
SBDQ60
AC7
SBDQ61
AA4
SBDQ62
AA5
SBDQ63
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
SARCVENOUT#
DDR SYSTEM MEMORY B
SBDQS0
SBDQS1
SBDQS2
SBDQS3
SBDQS4
SBDQS5
SBDQS6
SBDQS7
SBDQS0#
SBDQS1#
SBDQS2#
SBDQS3#
SBDQS4#
SBDQS5#
SBDQS6#
SBDQS7#
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SBDM0
SBDM1
SBDM2
SBDM3
SBDM4
SBDM5
SBDM6
SBDM7
SBBS0#
SBBS1#
SBBS2#
SBRAS#
SBCAS#
SBWE#
SARCVENIN#
SMB_SDQS0
AF34
SMB_SDQS1
AK32
SMB_SDQS2
AJ28
SMB_SDQS3
AK23
SMB_SDQS4
AM10
SMB_SDQS5
AH6
SMB_SDQS6
AF8
SMB_SDQS7
AB4
AF35
SMB_SDQSN1
AK33
SMB_SDQSN2
AK28
SMB_SDQSN3
AJ23
SMB_SDQSN4
AL10
SMB_SDQSN5
AH7
SMB_SDQSN6
AF7
SMB_SDQSN7
AB5
SMB_MA0
AH17
SMB_MA1
AK17
SMB_MA2
AH18
SMB_MA3
AJ18
SMB_MA4
AK18
SMB_MA5
AJ19
SMB_MA6SMB_DATA24
AK19
SMB_MA7
AH19
SMB_MA8
AJ20
SMB_MA9
AH20
SMB_MA10
AJ16
SMB_MA11
AG18
SMB_MA12
AG20
SMB_MA13
AG15
SMB_DQM0
AF32
SMB_DQM1
AK34
SMB_DQM2
AK27
SMB_DQM3
AK24
SMB_DQM4
AJ10
SMB_DQM5
AK5
SMB_DQM6
AE7
SMB_DQM7
AB7
AJ15
AG17
AG21
AK14
AH14
AH16
NC_SMB_RCVENOUT0
AF14
NC_SMB_RCVENIN0
AF15
SMB_SDQS[7..0] (25)
SMB_SDQSN[7..0] (25)
SMB_MA[13..0] (24,25)
SMB_DQM[7..0] (25)
SMB_SBS00 (25)
SMB_SBS10 (25)
SMB_SBS20 (25)
SMB_SRAS0 (25)
SMB_SCAS0 (25)
SMB_SWE0 (25)
A A
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
ALVISO(DUAL DDR)
1
of
15 63Thursday, April 14, 2005
0.1
5
4
3
2
1
VCCP_GMCH(14,17,18)
R124
221 1% 1/16W 0603
MCH_HXSWING
D D
C C
MCH_HXRCOMP
R125 100 1% 1/16W 0402
VCCP_GMCH(14,17,18)
R121
221 1% 1/16W 0603
MCH_HYSWING
R122 100 1% 1/16W 0402
VCCP_GMCH(14,17,18)
R561
54.9 ±1% 1/16W 0402
MCH_HXSCOMP
VCCP_GMCH(14,17,18)
R123
54.9 ±1% 1/16W 0402
MCH_HYSCOMP
R126
24.9 1% 1/16W MF 0603
C122
0.1uF 16V 80-20% 0402 Y5V
C119
0.1uF 16V 80-20% 0402 Y5V
0.3125* VCCP
0.3125* VCCP
AGTL+_HA0[31..3](9)
AGTL+_HREQ0[4..0](9)
AGTL+_ADSTB00(9)
AGTL+_ADSTB10(9)
MCH_BCLK0(23)
MCH_BCLK(23)
AGTL+_DSTBN00(9)
AGTL+_DSTBN10(9)
AGTL+_DSTBN20(9)
AGTL+_DSTBN30(9)
AGTL+_DSTBP00(9)
AGTL+_DSTBP10(9)
AGTL+_DSTBP20(9)
AGTL+_DSTBP30(9)
AGTL+_DINV00(9)
AGTL+_DINV10(9)
AGTL+_DINV20(9)
AGTL+_DINV30(9)
AGTL+_CPURST0(9)
AGTL+_DPWR0(9)
CPU_SLP0(9,19)
For B step CPU
MCH_HYRCOMP
MCH_HYSCOMP
MCH_HYSWING
MCH_HXRCOMP
MCH_HXSCOMP
MCH_HXSWING
MCH_HVREF
NC_MGH_HEDRDY0
NC_MGH_HPCREQ0
R548
0 5% 1/16W 0402
AGTL+_HA03
AGTL+_HA04
AGTL+_HA05
AGTL+_HA06
AGTL+_HA07
AGTL+_HA08
AGTL+_HA09
AGTL+_HA010
AGTL+_HA011
AGTL+_HA012
AGTL+_HA013
AGTL+_HA014
AGTL+_HA015
AGTL+_HA016
AGTL+_HA017
AGTL+_HA018
AGTL+_HA019
AGTL+_HA020
AGTL+_HA021
AGTL+_HA022
AGTL+_HA023
AGTL+_HA024
AGTL+_HA025
AGTL+_HA026
AGTL+_HA027
AGTL+_HA028
AGTL+_HA029
AGTL+_HA030
AGTL+_HA031
AGTL+_HREQ00
AGTL+_HREQ01
AGTL+_HREQ02
AGTL+_HREQ03
AGTL+_HREQ04
G9
C9
A10
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
D7
C7
E13
AB1
AB2
C1
C2
D1
G4
R3
G5
R2
W4
H8
U5
H10
J11
G6
A11
G8
E9
B7
F9
A7
B8
A8
B9
T1
L1
P1
K1
V3
K2
K3
T7
F6
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADSTB0#
HADSTB1#
HCLKINN
HCLKINP
HYRCOMP
HYSCOMP
HYSWING
HXRCOMP
HXSCOMP
HXSWING
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HCPURST#
HVREF
HEDRDY#
HDPWR#
HPCREQ#
HCPUSLP#
U5E
HOST
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HADS#
HTRDY#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS0#
HRS1#
HRS2#
AGTL+_HD00
E4
AGTL+_HD01
E1
AGTL+_HD02
F4
AGTL+_HD03
H7
AGTL+_HD04
E2
AGTL+_HD05
F1
AGTL+_HD06
E3
AGTL+_HD07
D3
AGTL+_HD08
K7
AGTL+_HD09
F2
AGTL+_HD010
J7
AGTL+_HD011
J8
AGTL+_HD012
H6
AGTL+_HD013
F3
AGTL+_HD014
K8
AGTL+_HD015
H5
AGTL+_HD016
H1
AGTL+_HD017
H2
AGTL+_HD018
K5
AGTL+_HD019
K6
AGTL+_HD020
J4
AGTL+_HD021
G3
AGTL+_HD022
H3
AGTL+_HD023
J1
AGTL+_HD024
L5
AGTL+_HD025
K4
AGTL+_HD026
J5
AGTL+_HD027
P7
AGTL+_HD028
L7
AGTL+_HD029
J3
AGTL+_HD030
P5
AGTL+_HD031
L3
AGTL+_HD032
U7
AGTL+_HD033
V6
AGTL+_HD034
R6
AGTL+_HD035
R5
AGTL+_HD036
P3
AGTL+_HD037
T8
AGTL+_HD038
R7
AGTL+_HD039
R8
AGTL+_HD040
U8
AGTL+_HD041
R4
AGTL+_HD042
T4
AGTL+_HD043
T5
AGTL+_HD044
R1
AGTL+_HD045
T3
AGTL+_HD046
V8
AGTL+_HD047
U6
AGTL+_HD048
W6
AGTL+_HD049
U3
AGTL+_HD050
V5
AGTL+_HD051
W8
AGTL+_HD052
W7
AGTL+_HD053
U2
AGTL+_HD054
U1
AGTL+_HD055
Y5
AGTL+_HD056
Y2
AGTL+_HD057
V4
AGTL+_HD058
Y7
AGTL+_HD059
W1
AGTL+_HD060
W3
AGTL+_HD061
Y3
AGTL+_HD062
Y6
AGTL+_HD063
W2
F8
B5
F7
E6
D6
D4
B3
E7
A5
D5
C6
A4
C5
B4
AGTL+_HD0[63..0] (9)
AGTL+_ADS0 (9)
AGTL+_TRDY0 (9)
AGTL+_DRDY0 (9)
AGTL+_DEFER0 (9)
AGTL+_HITM0 (9)
AGTL+_HIT0 (9)
AGTL+_LOCK0 (9)
AGTL+_BR00 (9)
AGTL+_BNR0 (9)
AGTL+_BPRI0 (9)
AGTL+_DBSY0 (9)
AGTL+_RS00 (9)
AGTL+_RS01 (9)
AGTL+_RS02 (9)
B B
A A
5
MCH_HYRCOMP
R120
24.9 1% 1/16W MF 0603
VCCP_GMCH(14,17,18)
R585
100 1% 1/16W 0402
MCH_HVREF
R584
200 1% 1/16W 0603
2/3 * VCCP
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
4
3
2
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
ALVISO(HOST)
1
of
16 63Thursday, April 14, 2005
0.1
5
3
V1.5VDDM_DLVDS
1.5VDDM,14,19,21,53,57)
D D
2.5VDDM
,31,45,56,57)
2.5VDDM
,31,45,56,57)
C C
B B
,10,18,19,20,21,23,53)
A A
R193
0 5% 1/8W 0805
0.1uF 16V 10% 0603 X7R
0.1uF 16V 10% 0603 X7R
0.1uF 16V 10% 0603 X7R
VCORE_GMCH
C181
R210
0 5% 1/8W 0805
C217
R209
0 5% 1/8W 0805
C198
PM BOM:
L109, L110, L111, L112, L113 (NU)
C826, C828, C830, C832, C834 (NU)
C836, R978, R979, R980, D51 (NU)
C825, C827, C829, C831, C833, C835 0ohm 0402
R144, C167 (NU)
R145 0ohm 0402
5
V2.5VDDM_ALVDS
V2.5VDDM_TXLVDS
C199
10uF 6.3V 10% 0805 X5R TAIYO
VCORE_GMCH(9,10,18,19,20,21,23,53)
C220
0.01uF 16V 10% 0402 X7R
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC(NU)
C216
4.7uF 10V 80-20% 0805 Y5V
VCORE_GMCH(9,10,18,19,20,21,23,53)
DIODE RB751V-40 30V 30mA UMD2 ROHM
2.5VDDM(14,21,31,45,56,57)
Layot note: VSSA_CRTDAC Route
caps within 250 mil of ALVISO.
Route FB within 3" of ALVISO
VCCP(9,10,18,19,20,21,23,53)
2.2uF 10V 10% SMT0805 X7R TAIYO
1.5VDDM(10,13,14,19,21,53,57)
D4
P N
R169
SPWR 0 5% 1/16W 0603
VCCP (9,10,18,19,20,21,23,53)
820mA
R113
0 5% 1/8W 0805
SPWR 0 5% 1/8W 0805
R211
VCCP_GMCH(14,16,18)
C120
4
4A
C527 10uF 6.3V 10% 0805 X5R TAIYO
C510 10uF 6.3V 10% 0805 X5R TAIYO
C525 10uF 6.3V 10% 0805 X5R TAIYO
L57
C222
+
R170
1K 5% 1/16W 0603
1uH±5% 245mA NL201614T-1R0J TDK
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC
L58
1uH±5% 245mA NL201614T-1R0J TDK
10uH±5% 98mA NL201614T-100J TDK
10uH±5% 98mA NL201614T-100J TDK
USE BEAD 180 OHMS
L15
100MHZ 120Ω 0603 FCM1608K-121T06
2.5VDDM_SYNC
R622
C518
0.1uF 16V 10% 0603 X7R
0 5% 1/16W 0402
C112
4.7uF 6.3V ±10% 0805 C2012X5R0J475K TDK
4
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC(NU)
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC(NU)
C521
C526 0.1uF 16V 20% 0402 Y5V
C498 0.1uF 16V 20% 0402 Y5V
L69
L70
Route VSSA_CRTDAC gnd form GMCH
to decoupling cap ground lead and
then connect to the gnd plane
C499
C520 0.1uF 16V 20% 0402 Y5V
+
+
0.1uF 16V 10% 0603 X7R
C476
C477
+
C479
0.1uF 16V 10% 0603 X7R
+
C478
0.1uF 16V 10% 0603 X7R
C524
+
C221
0.1uF 16V 10% 0603 X7R
+
2.5VDDM_CRTDAC(13)
0.1uF 16V 10% 0603 X7R
C156
C481 0.47uF 16V 10% 0805 X7R
C480 0.47uF 16V 10% 0805 X7R
C118 0.22uF 10V 10% 0603 X7R
C121 0.22uF 10V 10% 0603 X7R
R623
0 5% 1/16W 0402(NU)
68mA
C508
22nF 25V ±10% 0402 X7R
60mA
60mA
1.5VDDM_DPLLA
60mA
C519
1.5VDDM_DPLLB
60mA
C541
1.5VDDM_HMPLL
2mA
3
1.5VDDM_MPLL
VCCP_GMCH_CAP1
VCCP_GMCH_CAP2
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
3
2
3.3VDDM_TVDACA
3.3VDDM_TVDACB
3.3VDDM_TVDACC
3.3VDDM_ATVBG
1.5VDDS_QTVDAC
2mA
2.5VDDS_HV
GMCH_DDR_1.8VDDS(18)
C500 10uF 10% 10V 1210 X7R
C529 10uF 10% 10V 1210 X7R
0.1uF 16V 10% 0603 X7R
10uF 10% 10V 1210 X7R
V2.5VDDM_TXLVDS
1.5VDDM_3GPLL
C528
0.1uF 16V 10% 0603 X7R
R663
SPWR 0 5% 1/16W 0603
C495
C506
C507
C509
C505
C496
C139
C512
C229
10uF 10% 10V 1210 X7R
C549
10uF 10% 10V 1210 X7R
VCC_GMCH(9,10,18,19,20,21,23,53)
U5F
T29
VCC0
R29
VCC1
N29
VCC2
M29
VCC3
K29
VCC4
J29
VCC5
V28
VCC6
U28
VCC7
T28
VCC8
R28
VCC9
P28
VCC10
N28
VCC11
M28
VCC12
L28
VCC13
K28
VCC14
J28
VCC15
H28
VCC16
G28
VCC17
V27
VCC18
U27
VCC19
T27
VCC20
R27
VCC21
P27
VCC22
N27
VCC23
M27
VCC24
L27
VCC25
K27
VCC26
J27
VCC27
H27
VCC28
K26
VCC29
H26
VCC30
K25
VCC31
J25
VCC32
K24
VCC33
K23
VCC34
K22
VCC35
K21
VCC36
W20
VCC37
U20
VCC38
T20
VCC39
K20
VCC40
V19
VCC41
U19
VCC42
K19
VCC43
W18
VCC44
V18
VCC45
T18
VCC46
K18
VCC47
K17
VCC48
AA1
VCCAHPLL
AA2
VCCAMPLL
B23
VCCADPLLA
C35
VCCADPLLB
AC1
VCCHMPLL0
AC2
VCCHMPLL1
F19
VCCA_CRTDAC0
E19
VCCA_CRTDAC1
G19
VSSA_CRTDAC
H20
VCCSYNC
K13
VTT0
J13
VTT1
K12
VTT2
W11
VTT3
V11
VTT4
U11
VTT5
T11
VTT6
R11
VTT7
P11
VTT8
N11
VTT9
M11
VTT10
L11
VTT11
K11
VTT12
W10
VTT13
V10
VTT14
U10
VTT15
T10
VTT16
R10
VTT17
P10
VTT18
N10
VTT19
M10
VTT20
K10
VTT21
J10
VTT22
Y9
VTT23
W9
VTT24
U9
VTT25
R9
VTT26
P9
VTT27
N9
VTT28
M9
VTT29
L9
VTT30
J9
VTT31
N8
VTT32
M8
VTT33
N7
VTT34
M7
VTT35
N6
VTT36
M6
VTT37
A6
VTT38
N5
VTT39
M5
VTT40
N4
VTT41
M4
VTT42
N3
VTT43
M3
VTT44
N2
VTT45
M2
VTT46
B2
VTT47
V1
VTT48
N1
VTT49
M1
VTT50
G1
VTT51
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
F17
VCCATVDACA0
E17
VCCATVDACA1
D18
VCCATVDACB0
C18
VCCATVDACB1
F18
VCCATVDACC0
E18
VCCATVDACC1
H18
VCCATVBG
G18
VSSATVBG
D19
VCCDTVDAC
H17
VCCDQTVDAC
B22
VCCHV0
B21
VCCHV1
A21
VCCHV2
V1.8_DDR_CAP1
AM37
VCCSM0
V1.8_DDR_CAP2
AH37
VCCSM1
V1.8_DDR_CAP3
AP29
VCCSM2
AD28
VCCSM3
AD27
VCCSM4
AC27
VCCSM5
AP26
VCCSM6
AN26
VCCSM7
AM26
VCCSM8
AL26
VCCSM9
AK26
VCCSM10
AJ26
VCCSM11
AH26
VCCSM12
AG26
VCCSM13
AF26
VCCSM14
AE26
VCCSM15
AP25
VCCSM16
AN25
VCCSM17
AM25
VCCSM18
AL25
VCCSM19
AK25
VCCSM20
AJ25
VCCSM21
AH25
VCCSM22
AG25
VCCSM23
AF25
VCCSM24
AE25
VCCSM25
POWER
AE24
VCCSM26
AE23
VCCSM27
AE22
VCCSM28
AE21
VCCSM29
AE20
VCCSM30
AE19
VCCSM31
AE18
VCCSM32
AE17
VCCSM33
AE16
VCCSM34
AE15
VCCSM35
AE14
VCCSM36
AP13
VCCSM37
AN13
VCCSM38
AM13
VCCSM39
AL13
VCCSM40
AK13
VCCSM41
AJ13
VCCSM42
AH13
VCCSM43
AG13
VCCSM44
AF13
VCCSM45
AE13
VCCSM46
AP12
VCCSM47
AN12
VCCSM48
AM12
VCCSM49
AL12
VCCSM50
AK12
VCCSM51
AJ12
VCCSM52
AH12
VCCSM53
AG12
VCCSM54
AF12
VCCSM55
AE12
VCCSM56
AD11
VCCSM57
AC11
VCCSM58
AB11
VCCSM59
AB10
VCCSM60
AB9
VCCSM61
V1.8_DDR_CAP4
AP8
VCCSM62
V1.8_DDR_CAP5
AM1
VCCSM63
V1.8_DDR_CAP6
AE1
VCCSM64
AF18
VCCASM3
AF19
VCCASM2
AP19
VCCASM1
AF20
VCCASM0
AE37
VCC3G0
W37
VCC3G1
U37
VCC3G2
R37
VCC3G3
N37
VCC3G4
L37
VCC3G5
J37
VCC3G6
A27
VCCTXLVDS2
A28
VCCTXLVDS1
B28
VCCTXLVDS0
A25
VCCDLVDS2
B25
VCCDLVDS1
B26
VCCDLVDS0
A35
VCCALVDS
Y29
VCCA3GPLL0
Y28
VCCA3GPLL1
Y27
VCCA3GPLL2
F37
VCCA3GBG
G37
VSSA3GBG
1.5VDDM_TVDAC
C227
C228
0.1uF 16V 10% 0603 X7R
0.1uF 16V 10% 0603 X7R
C197
0.1uF 16V 10% 0603 X7R
Note:
All VCCSM
pin
shorted
internally
1CH 1.3A
2CH 2.7A
Note:
All
VCCSM
pin
shorted internally
C131 0.1uF 16V 10% 0603 X7R
C116 0.1uF 16V 10% 0603 X7R
C117 0.1uF 16V 10% 0603 X7R
60mA
60mA
10mA
2.5VDDM_3GBG
C543
0.1uF 16V 10% 0603 X7R
2
V1.5VDDM_DLVDS
V2.5VDDM_ALVDS
L64
0.1uF 16V 10% 0603 X7R
22nF 25V ±10% 0402 X7R
100MHZ 120Ω 0603 FCM1608K-121T06
C493
L65
22nF 25V ±10% 0402 X7R
0.1uF 16V 10% 0603 X7R
100MHZ 120Ω 0603 FCM1608K-121T06
C494
L11
22nF 25V ±10% 0402 X7R
0.1uF 16V 10% 0603 X7R
100MHZ 120Ω 0603 FCM1608K-121T06
C148
L14
22nF 25V ±10% 0402 X7R
0.1uF 16V 10% 0603 X7R
100MHZ 120Ω 0603 FCM1608K-121T06
C155
22nF 25V ±10% 0402 X7R
0.1uF 16V 10% 0603 X7R
C504
L62
22nF 25V ±10% 0402 X7R
0.1uF 16V 10% 0603 X7R
100MHZ 120Ω 0603 FCM1608K-121T06
C486
C166
C165
10uF 10% 10V 1210 X7R
0.1uF 16V 10% 0603 X7R
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC(NU)
T 220uF 2.5V ±20% 35mΩ SMT3528 LOW ESR PSLB20E227M(35) NEC
C180
C511 0.1uF 16V 10% 0603 X7R(NU)
+
+
1.5VDDM_DDRDLL(10,13,14,19,21,53,57)
C147
+
SP-CAP 47uF 4V ±20% ESR:28mΩ 7343 H=1.2mm EEFFD0G470R PANASONIC
1.5VDDM_PCIE(10,13,14,19,21,53,57)
C230
C231
+
SP-CAP 47uF 4V ±20% ESR:28mΩ 7343 H=1.2mm EEFFD0G470R PANASONIC
3GPLL_R_L
0.15mA
Title
Size Document Number Rev
Date: Sheet
1uH±5% 245mA NL201614T-1R0J TDK
2.5VDDM (14,21,31,45,56,57)
AT11 < Dothan + 915GM + ICH6-M >
C
ALVISO(POWER)
1
3.3VDDM_TVDAC
DIODE RB751V-40 30V 30mA UMD2 ROHM
D2
PN
1.5VDDM (10,13,14,19,21,53,57)
R163
10 5% 1/16W 0603
R149
SPWR 0 5% 1/8W 0805
R594
SPWR 0 5% 1/8W 0805
R168
R164
C487 0.1uF 16V 10% 0603 X7R(NU)
0 5% 1/4W 1206
SPWR 0 5% 1/8W 0805
1.5VDDM (10,13,14,19,21,53,57)
1.5VDDM (10,13,14,19,21,53,57)
3VDDM (11,19,20,21,23,24,25,26,27,28,30,31,32,35,36,37,38,
1.5VDDM (10,13,14,19,21,53,57)
2.5VDDM (14,21,31,45,56,57)
DDR_1.8VDDS (14,24,43,44,45)
400MHZ 1CH 0.23A
400MHZ 2CH 0.43A
533MHZ 1CH 0.3A
533MHZ 2CH 0.6A
1A
L71
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
3GPLL_FB_L
1
R670
SPWR 0 5% 1/8W 0805
17 63Thursday, April 14, 2005
1.5VDDM (10,13,14,19,21,53,57)
of
0.1
5
D D
AF23
H23
AL22
AH22
J22
E22
D22
A22
AN21
AF21
F21
C21
AK20
V20
G20
F20
E20
D20
A20
AN19
AG19
W19
T19
J19
H19
C19
AL18
U18
B18
A18
AN17
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
AJ17
VSS166
VSS167
AF17
VSS168
G17
VSS169
C17
VSS170
AL16
VSS171
K16
VSS172
H16
VSS173
4
D16
VSS174
A16
VSS175
K15
VSS176
C15
VSS177
AN14
VSS178
AL14
VSS179
AJ14
VSS180
AG14
K14
VSS181
J14
VSS182
VSS183
F14
VSS184
B14
VSS185
A14
VSS186
J12
VSS187
D12
VSS188
B12
VSS189
AN11
VSS190
AL11
VSS191
AJ11
VSS192
AG11
VSS193
AF11
VSS194
AA11
VSS195
Y11
VSS196
H11
VSS197
F11
VSS198
AA10
VSS199
Y10
VSS200
L10
VSS201
D10
VSS202
AN9
VSS203
AH9
VSS204
3
AE9
AC9
AA9V9T9K9H9A9AL8Y8P8L8E8C8AN7
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
AK7
VSS219
VSS220
AG7
VSS221
AA7V7G7
VSS222
VSS223
VSS224
AJ6
VSS225
AE6
VSS226
AC6
VSS227
AA6T6P6L6J6B6AP5
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
AL5W5E5
VSS234
VSS235
AN4
AF4Y4U4P4L4H4C4
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
AJ3
VSS245
VSS246
AC3
VSS247
AB3
VSS248
AA3C3A3
VSS249
VSS250
VSS251
AN2
VSS252
AL2
VSS253
2
AH2
VSS254
AE2
AD2V2T2P2L2
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
B27
VSS261
J26
VSS262
G26
VSS263
E26
VSS264
A26
VSS265
AN24
VSS266
AL24
VSS267
J2G2D2
VSS268
VSS269
VSS270
B36
Y1
U5G
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
VSS271
VSSALVDS
1
VSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
AG37
Y37
V37
T37
P37
M37
K37
H37
E37
AN36
AL36
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
W31
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
C C
GMCH_DDR_1.8VDDS(17)
VSS104
Y30
C30
AM29
AJ29
AG29
AD29
AA29
V29
U29
P29
L29
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W29
W27
VSS135
G27
E27
AJ24
AG24
J24
F24
D24
B24
VCC_GMCH (9,10,17,19,20,21,23,53)
AD26
AC26
AD25
AC25
AD24
AC24
AD23
AC23
AD22
AC22
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
AD13
AC13
AB13
AD12
AC12
AB12
W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21
U21
T21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
N18
M18
L18
W17
V17
U17
T17
P17
N17
M17
L17
U5H
ASIC ALVIO GMCH FCBGA 1257PIN INTEL
VCCNCTF0
VCCNCTF1
VCCNCTF2
VCCNCTF3
VCCNCTF4
VCCNCTF5
VCCNCTF6
VCCNCTF7
VCCNCTF8
VCCNCTF9
VCCNCTF10
VCCNCTF11
VCCNCTF12
VCCNCTF13
VCCNCTF14
VCCNCTF15
VCCNCTF16
VCCNCTF17
VCCNCTF18
VCCNCTF19
VCCNCTF20
VCCNCTF21
VCCNCTF22
VCCNCTF23
VCCNCTF24
VCCNCTF25
VCCNCTF26
VCCNCTF27
VCCNCTF28
VCCNCTF29
VCCNCTF30
VCCNCTF31
VCCNCTF32
VCCNCTF33
VCCNCTF34
VCCNCTF35
VCCNCTF36
VCCNCTF37
VCCNCTF38
VCCNCTF39
VCCNCTF40
VCCNCTF41
VCCNCTF42
VCCNCTF43
VCCNCTF44
VCCNCTF45
VCCNCTF46
VCCNCTF47
VCCNCTF48
VCCNCTF49
VCCNCTF50
VCCNCTF51
VCCNCTF52
VCCNCTF53
VCCNCTF54
VCCNCTF55
VCCNCTF56
VCCNCTF57
VCCNCTF58
VCCNCTF59
VCCNCTF60
VCCNCTF61
VCCNCTF62
VCCNCTF63
VCCNCTF64
VCCNCTF65
VCCNCTF66
VCCNCTF67
VCCNCTF68
VCCNCTF69
VCCNCTF70
VCCNCTF71
VCCNCTF72
VCCNCTF73
VCCNCTF74
VCCNCTF75
VCCNCTF76
VCCNCTF77
VCCNCTF78
First International Computer, Inc.
2FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
Title
Size Document Number Rev
C
Date: Sheet
(886-2)8751-8751
AT11 < Dothan + 915GM + ICH6-M >
ALVISO(VSS/NCTF)
1
of
18 63Thursday, April 14, 2005
0.1
VSSNCTF11
VSSNCTF12
VSSNCTF13
Y23
AB22
AA22
VSSNCTF14
VSSNCTF15
VSSNCTF16
Y22
AB21
AA21
NCTF
VSSNCTF17
VSSNCTF18
VSSNCTF19
VSSNCTF20
VSSNCTF21
VSSNCTF22
Y21
R21
AB20
AA20
AB19
AA19
VSSNCTF23
VSSNCTF24
VSSNCTF25
AB18
AA18
AB17
VSSNCTF26
VSSNCTF27
VSSNCTF28
AA17
Y17
R17
VSSNCTF29
VSSNCTF30
VSSNCTF31
AB16
AA16
Y16
VSSNCTF32
VSSNCTF33
W16
V16
U16
VSSNCTF34
VSSNCTF35
VSSNCTF36
VSSNCTF37
T16
R16
P16
3
VSSNCTF38
VSSNCTF39
VSSNCTF40
N16
M16
L16
VSSNCTF41
VSSNCTF42
VSSNCTF43
AB15
AA15
Y15
VSSNCTF44
VSSNCTF45
VSSNCTF46
W15
V15
U15
VSSNCTF47
VSSNCTF48
VSSNCTF49
T15
R15
P15
VSSNCTF50
VSSNCTF51
VSSNCTF52
N15
M15
L15
VSSNCTF53
VSSNCTF54
VSSNCTF55
AB14
AA14
Y14
VSSNCTF56
VSSNCTF57
VSSNCTF58
W14
V14
U14
VSSNCTF59
VSSNCTF60
VSSNCTF61
T14
R14
P14
VSSNCTF62
VSSNCTF63
VSSNCTF64
N14
M14
L14
VSSNCTF65
VSSNCTF66
VSSNCTF67
AA13
Y13
AA12
VSSNCTF68
Y12
2
VCCSMNCTF0
VCCSMNCTF1
VCCSMNCTF2
VCCSMNCTF3
VCCSMNCTF4
VCCSMNCTF5
VCCSMNCTF6
VCCSMNCTF7
VCCSMNCTF8
VCCSMNCTF9
VCCSMNCTF10
VCCSMNCTF11
VCCSMNCTF12
VCCSMNCTF13
VCCSMNCTF14
VCCSMNCTF15
VCCSMNCTF16
VCCSMNCTF17
VCCSMNCTF18
VCCSMNCTF19
VCCSMNCTF20
VCCSMNCTF21
VCCSMNCTF22
VCCSMNCTF23
VCCSMNCTF24
VCCSMNCTF25
VCCSMNCTF26
VCCSMNCTF27
VCCSMNCTF28
VCCSMNCTF29
VCCSMNCTF30
VSSNCTF0
VSSNCTF1
AB26
AA26
Y26
VSSNCTF2
VSSNCTF3
VSSNCTF4
AB25
AA25
Y25
VCCSMNCTF31
VSSNCTF5
VSSNCTF6
VSSNCTF7
AB24
AA24
Y24
VSSNCTF8
VSSNCTF9
VSSNCTF10
AB23
AA23
B B
VTTNCTF0
VTTNCTF1
VTTNCTF2
VTTNCTF3
VTTNCTF4
VTTNCTF5
VTTNCTF6
VTTNCTF7
VTTNCTF8
VTTNCTF9
VTTNCTF10
VTTNCTF11
VTTNCTF12
VTTNCTF13
VTTNCTF14
VTTNCTF15
VTTNCTF16
W13
V13
U13
T13
R13
P13
N13
M13
L13
W12
VCCP_GMCH(14,16,17)
A A
5
VTTNCTF17
V12
U12
T12
R12
P12
N12
M12
L12
4
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