Fic a985 Service Manual CHAP4
Chapter
Hardware Functional Overview
4.1 Overview
The FIC A985 notebook consists of several important functions and subsystems including:
• System Processor – implemented on the motherboard using the Intel uFCPGA
Pentium 4 –M Northwood at 400 MHz Front System Bus speed.
• System North Bridge Core Logic – implemented on the motherboard using the SIS
650 chipset.
- CPU Interface
- AGP BUS Controller
- DDR DRAM Controller
- MuTIOL Media I/O
• System South Bridge Core Logic – implemented on the motherboard using the SIS
961 chipset.
- Integrated MuTIOL Connect to PCI Bridge
- Dual IDE Master/Slave Controller, Integrated DMA
• Clock Frequency Generator – implemented on the motherboard using the ICS 952001
clock generator chip.
• Cache Memory Subsystem – implemented on-die on the Intel CPU.
- L1 cache (Pentium Processor Internal)
- 12KB code and 8KB data, which implemented 8 way set associative and write
back
- L2 cache (Pentium Processor Internal)
- 256KB Advanced Transfer Cache,8 way associativity
- 8-way set associative, 32-byte line size, 1 line per sector
• Video Subsystem – embedded in SIS 650
- High Performance and high quality 3D accelerator
- Integrated VB bridge
- High performance 2D accelerator
- Complete TV-OUT/Digital Flat Panel Solution
• VRAM – embedded in SIS 650
- Share system memory from 8MB up to 64MB
• PCMCIA Subsystem – implemented on the motherboard using the O2Micro OZ6912
PCI-CARDBUS BRIDGE controller chip.
- Support Type II x2 (without door)
• Sound – implemented or integrated in south bridge (SIS 961)
- AC’97 CODEC
- Realtek ALC201
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Hardware Functional Overview
- AC’97 Revision 2.1 Compliant
- Supports Consumer IEC958 Output Port (SPDIF OUT)
• USB and Bluetooth – implemented or integrated in south bridge (SIS 961)
- USB v1.1 and Intel Universal HCI v.1.1 Compatible
- Eighteen level (doublewords) data FIFO with full scatter and gather capability
- Root hub and four function ports
- Integrated physical layer transceivers with optional over-current detection status
on USB inputs
- Legacy keyboard and PS/2 mouse support
• Keyboard and Pointing Device Subsystem – implemented on the motherboard using
the Keyboard assembly, and the Glidepad assembly.
• I/O Subsystem – implement included on the SIS 961.
• RTC + NVRAM – integrated in south bridge (SIS 961)
- Real Time Clock with 256 byte extend CMOS
- IBM AT Clock/ Calendar/ Alarm (14 Bytes)
• Modem /LAN or Combo Feature Card – implemented on the motherboard using the
mini-PCI bus module socket.
- Modem ASKEY 1456VQL19R-4 Mini-PCI Solution (Type-3A)
- V.90, K56flex, ITU-T V.34, V.32, RJ11 Jack
- TIA/EIA 602, V.42
- ITU-T V.17, V.29, V.27ter, V.21 Ch2
- TIA/EIA 578 Class1 FAX
- Wake up on Ring
- LAN Mini-PCI (Realtek)
- Support for auto-negotiation (10BASE-T and 100BASE-TX)
- Wake up On LAN
- 3Com Combo Mini-PCI Solution (Type-3A)
• Power Subsystem – implemented on the motherboard, LCD Inverter Board, Battery
Pack, and AC adapter.
• Micro-P Subsystem – embedded controller on the motherboard using Mitsubishi
PMU08
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Hardware Functional Overview
4.2 System Hardware Block Diagram
Figure 4-1 A985 Diagram
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Hardware Functional Overview
4.3 Chipset Summary
The A985 notebook consists of following major chipsets:
Controller Chip Vendor Description
Processor Intel uPGA 478 Intel Pentium
4 1.6/1.7/1.8/1.9/2.0/2.1/2.2 GHz
(Desktop, FSB 400 MHz)
Pentium 4: Integrated 256KB L2 Cache
Core Logic SIS SIS 650 + SIS 961
Video Controller Embedded in
SIS 650
PCMCIA Controller O2Micro OZ6912 Single Slot PCI-CARDBUS Bridge
Supper I/O Controller SMSC LPC47N267
Audio Chip Embedded in
SIS 961
Sound Codec Chip Realtek ALC201
Keyboard Controller EME KB38867
PMU Controller Mitsubishi PMU08, Mitsubishi M38859FFHP
Gas Gauge IC Included in PMU08
ROM BIOS
Clock Generator ICS ICS952001
Temperature Sensor NS MAX1617
Modem NDC
LAN Realtek 8100BL
Bluetooth SIS Embedded in SIS 961 USB interface
IEEE1394 Lucent Fw 322
SST
Integrated VGA Core with shared 16/32/64MB
memory
Integrated in South Bridge (SIS 961(
49LF040A
AC97 Interface
4.4 System Processor (CPU)
The FIC A985 runs on Intel Pentium 4 based on uFCPGA 478-pin packaging. It supports
CPU with up to 2.2GHz clock speed rating. The processor operates in conjunction with the
RAM and ROM memory and the system control logic (e.g. SIS 650) to process software
instructions (BIOS, Windows, and Applications).
4.4.1 Intel Pentium 4 Features
Using Intel’s advanced 0.13u process technology enables the Pentium 4 processor to further
extend its leadership with larger cache, higher frequency, and lower power. The Intel®
Pentium® 4 processor with 512KB L2 cache on 0.13 micron process is designed for highperformance desktops and entry level workstations. It is binary compatible with previous Intel
Architecture processors. The Pentium 4 processor provides great performance for applications
running on advanced operating systems such as Windows* 98, Windows* Me, Windows*
2000, and Windows* XP. Systems based on Pentium 4 processors also include the latest
features to simplify system management and lower the total cost of ownership for large and
small business environments. The Pentium 4 processor at 2.40 GHz delivers headroom to take
advantage of tomorrow’s emerging business and consumer usages
The Pentium 4 processor has been designed for the next decade of computing. The product
will clearly deliver better performance on basic everyday usages; however, the product is
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Hardware Functional Overview
designed for much more interactive, highly integrative usage models such as collaborative
workgroups, Internet audio and streaming video, image processing, video content creation,
speech, 3-D, games, multimedia and multi-tasking user environments. It also delivers a
world-class user experience across basic standalone office applications. The Pentium 4
processor offers great performance for today’s and tomorrow’s applications.
Intel's Pentium 4 processor, based on the Intel® NetBurst™ micro-architecture, includes
several new performance enhancing features :
• Hyper Pipelined Technology:
A deeper pipeline enables instructions inside the processor to be queued and executed
at a much faster rate, and allows the Pentium 4 processor to achieve the world's
highest clock speeds for desktop PCs.
• Streaming SIMD Extensions 2:
Streaming SIMD Extensions 2 consists of 144 new instructions including SIMD
double precision floating point, SIMD 128-bit integer, and new cache and memory
management instructions. Streaming SIMD Extensions 2 enhances performance to
accelerate video, speech, encryption, imaging, and the most demanding of Internet
computing, and non-threaded workstation applications.
• 400-MHz Intel NetBurst Micro-Architecture System Bus:
With three times the bandwidth of previous processors, the 400 MHz system bus
speeds the transfer of information from the processor to the rest of the system,
improving throughput and performance. This breakthrough technology extends the
potential for superior processing speeds to the rest of the system.
• Dynamic Execution:
Extends the Dynamic Execution features found in the previous generation P6 microarchitecture. Improved branch prediction accelerates the flow of work to the
processor and helps overcome the deeper pipeline. Very deep out-of-order speculative
execution carries out over 100 instructions speculatively, ensuring that the processor's
superscalar execution units remain busy, improving overall execution.
• Enhanced Floating Point/Multimedia Unit:
A 128-bit floating-point port and a second port for data movement enable smooth
lifelike 3D and graphics.
• Execution Trace Cache:
Advanced L1 instruction cache removes decoder pipeline latency, and caches
"decoded" instructions, thus improving efficiency and hit rate to cached instructions.
The 12 Kµop portion of the L1 cache supplies decoded instructions into the processor
pipeline. There is also an 8 KB data portion of L1 cache.
• Rapid Execution Engine:
The Integer Arithmetic Logic Unit (ALU) clocked at twice the frequency provides
four ALUs of computing bandwidth and allows lower latency execution increasing
performance for certain integer operations.
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4.5 System Core Logic
The system core logic function of the notebook is implemented on the CPU module and
motherboard using the SiS650 IGUI HMAC. SiS650 IGUI Host Memory Controller
integrates a high performance host interface for Intel Pentium 4 processor, a high
performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO. SiS650
Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated
on-die termination to support Intel Pentium 4 processors. SiS650 provides a 12-level InOrder-Queue to support maximum outstanding transactions up to 12. It integrated a high
performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware
Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC
systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain
t he bandwidth demand from t he integrated GUI or external AGP master, host processor, as
well as the multi I/O masters. In addition to integrated GUI, SiS650 also can support external
AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and
mat ure SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL
Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-t
hreaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master
devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-t
hreaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidt h
from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-t hreaded I/O Link
Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link
layer to/from SiS961
An Unified Memory Controller supporting DDR200/266 DRAM is incorporated, delivering a
high performance data transfer to/from memory subsystem from/to the Host processor, the
integrated graphic engine or external AGP master, or the I/O bus masters. The memory
controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in
ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the Shared
Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated
from 8MB to 64MB.
4.5.1 SiS650 IGUI HMAC 3D Graphic Chipset Features
The SiS650 chipset is ideal for the high performance, high quality, high energy efficient and
high integration notebook AGP / PCI / ISA computer systems. The Integrated GUI features a
high performance 3D accelerator with 2 Pixel / 4 Text ure, and a 128 bit 2D accelerator with
1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware
acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video
link interfaced to SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to
expand the SiS 650 functionality to support the secondary display, in addition to the default
primary CRT display. The SiS 301B Video Bridge integrates an NTSL/PAL video encoder
with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear
scaling capability for TFT LCD panel support, and an analog RGB port to support a
secondary CRT. The primary CRT display and the extended secondary display (TV, TFT
LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that both can generate
the display in independent resolutions, color depths, and frame rates.
The SiS650 functions and capabilities include:
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