FIC 486-PIO2 Original FIC manual

1 - 2

Overview

■

Optional Flash

■

Award BIOS.

■

Supports 128K/256K/512K direct-mapped
write-back/write-through cache

■

72-pin

SIMM

provides page mode DRAM operation.

■

Supports system and video BIOS cacheable, also video· :

BIOS

stiadow. .

■

Supports decoupled DRAM refresh.

■

Optional built-in ZIF socket that accepts Intel's
OverDriveni processors namely -

■

Supports onboard regulator

■

Supports four 16-bit

■

Supports four

■

Built-in internai

■

Provides built-in power management features necessary for
GreenPCs.

■

Enhanced IDE support allows for
devices. ·

■

Built-in IDE

■

NS

PC87311/312™ or NS

serial/ooe parallel port.

■

Supports ECP/EPP Protocol

ROM.

sockets supports

ISA

expansion slots.

PCI

bus

expansion slots.

real

tirne clock/calendar.

HDD

/

FDD

controllers.

memory.

up

to

128MB

DRAM,

P24D

, P24T.

for

low-voltage processors.

up

to four host interface

PC87332™

(NS

PC87332™

chipset

only

for

).

two

(

(

f

(

t .

Overview

Mainboard Layout

2

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a,

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:

➔

, chipset. When plugging your new processor into
; _ _

-··· .

FA

EA

K

ER

R

fü'

r

---

NOTE : The 486-PI0-2 provldes a socket for the processor

..

... socket, please observe proper_allgnment_ and p~~ition. _

804

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JC2

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the

PGA

1 - 3

1

486-PI0-2

486-PI0-2

2-2

Ma,nboard Sellings

Malnboard Seltings

- -

--

-

2 · 3

➔

➔

CAUTION
rtftr

: Wlltn u1lng I low-volllgt

10

page

Intel 488SX

RNA

RNC

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NOTE : Uatrs
Hltlng1
11ttl

no1 lt.led ln lhla m1nu

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RNC

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486-PI0-2

t

e

◄

86-PI0-2

2-4

Mainboard Settings

Mainboard Settings

2-5

Intel P24T

_

1

1

1

t~~

i

.J

1

i

L__J

1

1

1

J

Intel

P24T

(for the
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cache

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Write-through

cache
function)

(

f (

Intel P24D

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~~F

RNA

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~

liMlii

■

1111Uiiii

1

■

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3

1

l

nte

I

P24D

1

L_

Intel

P24D

(for the
write-back
cache
function)

(for the
write-through
cache
function)

486-PI0-2

f

486-PI0-2

2-6

2-7

- ·

lntel0X4

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--,

3-2

Memory Subsystem

Memory Subsystem

3 - 3

lnstalling DRAM

SIMM Banks

The 486-PI0-2 can accommodate on-board memory from I to

128MB using SIMMs (Single-In-Line Memory Modules

mainboard has four memory banks - Bank 0,

1, 2 and 3 can accept either a

SIMM in each socket.

DRAM Configuration

Memory can
shown in the next table:

TOTAL

MEMORY

1MB 1MB

2MB

3MB

4MB

5MB

6MB

7MB

be

installed in a variety

BANKO

.

(72.PIN)

1MB

1MB

1MB

1MB

·-

1MB

4MB

1MB
1MB
1MB
4MB
4MB

--

1MB
1MB
4MB

4MB
1MB
4MB

1MB

, 4MB , 16MB

of

BÀNK1

(72-PIN)

BANIO

(72.PIN)

1MB

1MB
1MB
1

MB

4MB

1MB

4MB

1MB
1MB

4MB

1MB

4MB

1MB 1MB

4MB

4MB

1MB

1,

2, 3. Bank 0,

or

32Mff

configurations, as

BANK3

(72.PIN}

1MB
1MB

1

1MB
1MB

MB

-·

1MB

_

1MB
1MB

1MB
1MB

4MB

1MB

1MB

4~8
1MB

4MB
1MB
4MB
1MB

1MB
1MB

1MB
1MB

1MB
1MB
1MB
1MB

).

Thè

TOTAL

MEMORY

BANKO

(72-PIN)

BANK1

(72-PIN)

BANK2 BANK3

(72.PIN)

(72.PIN)

4MB 4MB

8MB

9MB

.-

10MB

12MB

13MB

16MB

17MB

1

18MB
19MB

20MB

21MB

22MB
24MB

25MB
28MB

33MB

~-

1:

f

34MB

4MB 4MB

4MB 4MB

1MB

4MB

4MB
1MB

4MB 4MB

1MB
1MB
1MB

1MB
4MB 4MB
4MB

4MB

4MB
4MB

,

1MB

4MB

'

4MB
1MB

4MB

1MB

16MB

4MB

16MB

1MB

1MB

16MB
1MB 1MB
1MB

16MB

16MB
1MB
4MB

16MB

16MB
4MB

4MB

·~---

4MB
4MB
4MB
4MB

4MB

1MB
1MB

16MB

4MB

16MB

1MB
16MB
16MB

4MB
16MB
16MB

1MB
4MB
1MB

16MB
16MB
16MB

1MB

1MB
1MB

1MB

4MB

4MB
4MB

1MB
4MB
4MB
4MB

1MB
4MB
4MB
4MB 4MB
4MB 4MB
4MB

16MB

4MB

16MB

16MB

"

1MB

1

6MB
1MB
1MB
1MB

16MB
16MB

4MB

16MB

4MB

16MB

1MB
1MB

16MB

4MB
4MB 4MB
4MB

---·--·

·-

4MB

16MB
16MB 16MB
16MB
16MB

1

.

4MB

4MB
4MB
4MB

1

MB

4MB

4MB

4MB

1MB

,

1MB

1MB

·

4MB

4MB

16MB
16MB

1

486-PI0-2

486-PI0-2

3-4

Memory Subsystem

Memory Subsystem

3-5

TOTAL

Ml!MORY

36MB

37MB
40MB 4MB 4MB

48MB
49MB 1MB

52MB

64MB

65MB

66MB

iANKO
(72;PIN)

4MB 16MB

4MB

1MB 4MB

4MB 1MB

-----

--

-

·-

·

4MB

1MB
1MB
1MB 1MB 32MB
1MB 32MB

32MB 32MB

_ _ 4MB

BANK1
(12.PIN)

4MB

-•

-

16MB
16MB 16MB
16MB 16MB
32MB

64MB

32MB

32MB 32MB

68MB

32MB
32MB

32MB 4MB 32MB

16MB 32MB 32MB

16MB 32MB
32MB 16MB

32MB

69MB

72MB

80MB

81MB

84MB

96MB
97MB

128MB

32MB

-

-·

1MB

1MB
4MB 1MB 32MB 32MB
4MB 32MB
4MB
4MB

32MB 32MB
32MB 16MB 32MB

32MB 32MB 16MB

1MB

1MB 32MB
4MB

4MB

32MB 32MB

..

.

1MB 32MB

32MB

BANK2 '

.

(72.PINl

16MB

16MB 16MB
16MB 16MB
16MB 16MB
16MB
16MB

16MB

32MB

32MB

1MB

1MB

4MB

32MB 32MB

4MB

4MB

4MB 32MB

32MB 32MB

4MB 32MB

· 1MB

4MB 4MB

16MB 32MB

32MB

32MB

32MB

1

BANK3
(72.PINI

16M~_
16MB
16MB

16MB
16MB ;

32MB
32MB

1MB

32MB
32MB

32MB
32MB

32MB
32MB

f

...

((

--

Installation Instructions

➔

NOTE : Always observe· static electricity precautions. See
''Handling Precautions" at the

--

~r!

--------~

this manual.

~!

----

-

--

-

--

-·

··

1. Locate the SIMM banks on the mainboard.
Insert the SfMM edge connector at a 90-degree angle

2_

onto the socket.

Carefully push the SIMM down and back into the socket

C

((

3.
until the retaining clips

the socket snap, h"lding the

of

SlMM in place. The holes in the SIMM should match the

the socket's retaining clips.

on

pins

remove the SIMM/s, pull the retaining latch

To

both ends

on

of

the socket and reverse the procedure above.

____

:

_ ) _ .

NOTE

banks.accept.double-RASSIM~-.

Ali

:.

486-PI0-2

·-----------

J

__

486-PI0-2

3-

8

512K CliCh

e 8

RAM

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M2

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M3

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M4

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28K

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128Kx8
128Kx8

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I0-2

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-16

Award BIOS Setup

Map

1WS

By

To

to allow the system BIOS to aufomat-

pending data from the PCI device.

of

Write

DRAM.

to

Activated

IRQ

PCI

We suggest that you set this 'to its default configtiiation
unless you are a qualified technician.

The options are: Level (Default), Edge

PCI IDE

CPU

PCI

PCI Master Prefetch

PCI Master

IRQ

PCI-AUTO"

"

Set

ically detect the add-on PCI IDE card interrupt used by
the PCI bard disk drive.

The options are: PCI-AUTO (Default), PCI-SLOTl,
PCI-SLOT2, PC1-SLOT3, PCI-SLOT4, ISA

PCI Write Buffer

to

When enabled, allows data and address access to the
internai buffer ofVT82C505 so that the processor can be
released from the wait state.

The options are: Enabled (Default), Disabled

Master Write Buffer

When enabled, allows the PCI write operation

ing the processor
Processor is released from waiting state by a signal from
the master card.

The options are: Enabled (Default), Disabled

When enabled, allows the data and address
the internai buffer ofVT82C505 to reduce master drive
access time.

The options are: Enabled (Default), Disabled

When enabled, allows one more wait state cycle delay~
when the PCI master drive writes data

inform-

by

be saved in

to

C

'

cjc

Award BIOS Setup

interrupt Assignments

BLOT

PCI Slot 1

PCI Slot 2

Slot3

PCI

Slot4

PCI

Load BIOS Defaults

BIOS defaults contàin the most appropriatc values
parameters that allow minimum system performance. The OEM
manufacturer may change the defaults through MODBTN be­fore the binary image bums into the'ROM.

Load

Setup Defaults

Selecting this field loads the factory defaults for BIOS and
Chipset Features which

Slots

PCI

of

INTOFSLOT

A

B

C

D

A

B

C

D

A

B

C

D

A

B

i

C

D

system automatically detects.

the

4 -

INT OF VTl2CS05

A

B

C

D

B

C

D

A

C

D

A

B

D

A

B

C

the system

of

17

The options are: Enabled, Disabled (Default)

486-PI0-2

486-PI0-2