Fairchild Semiconductor TMC2490A Datasheet

www.fairchildsemi.com

TMC2490A

Multistandard Digital Video Encoder

Features

• All-digital video encoding

• Internal digital subcarrier synthesizer

• 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE 125M input format

• CCIR-624/SMPTE-170M compliant output

• Switchable chrominance bandwidth

• Switchable pedestal with gain compensation

• Pre-programmed horizontal and vertical timing

• 13.5 Mpps pixel rate

• Master or slave (CCIR656) operation

• MPEG interface

• Internal interpolation ﬁlters simplify output reconstruction ﬁlters

• 10-bit D/A converters for video reconstruction

• Supports NTSC and PAL standards

• Closed-caption waveform insertion

• Simultaneous S-Video (Y/C) output

• Controlled edge rates

• Single +5V power supply

• 44 lead PLCC package

• Parallel and serial control interface

Applications

• Set-top digital cable television receivers

• Set-top digital satellite television receivers

• Studio parallel CCIR-601 to analog conversion

Description

The TMC2490A video encoder converts digital component video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE 125M format) into a standard analog baseband television (NTSC, NTSC-EIA, and all PAL standards) signal with a modulated color subcarrier. Both composite (single lead) and S-Video (separate chroma and luma) formats are active simultaneously at all three analog outputs. Each video output generates a standard video signal capable of driving a singlyor doubly-terminated 75 Ohm load.

The TMC2490A is intended for all non-Macrovision encoder applications.

The TMC2490A is fabricated in a submicron CMOS process and is packaged in a 44-lead PLCC. Performance is guaranteed over the full 0 ° C to 70 ° C operating temperature range.

Block Diagram

PIXEL DATA

PXCK

HSYNC

SELC

DEMUX AND

SYNC

EXTRACT

7-0

VSYNC, B/T

PDC/CBSEL

LPF

INTERPOLATOR

4:2:2 TO 4:4:4

DIGITAL

SYNC AND

BLANK

GENERATOR

SERIAL

PARALLEL

B-Y

R-Y

LPF

SUBCARRIER

SYNTHESIZER

SERIAL/PARALLEL CONTROL

ADR

MODULATOR

SDA R/W

CHROMA

SCL

INTER-

POLATION

FILTER

7-0

INTER-

POLATION

FILTER

GLOBAL

CONTROL

RESET

SER

10-BIT D/A

REF

CHROMA

LUMA

COMPOSITE

REF

BYP

REF

65-2490(1)A-01

REV. 1.0.2 2/27/02

S-VIDEO

TMC2490A PRODUCT SPECIFICATION

Functional Description

The TMC2490A is a fully-integrated digital video encoder with simultaneous composite and Y/C (S-Video) outputs, compatible with NTSC, NTSC-EIA, and all PAL television standards.

Digital component video is accepted at the PD port in 8-bit parallel CCIR-601/656 format. It is demultiplexed into luminance and chrominance components. The chrominance components modulate a digitally synthesized subcarrier. The luminance and chrominance signals are then separately interpolated to twice the input pixel rate and converted to analog signals by 10-bit D/A converters. They are also digitally combined and the resulting composite signal is output by a third 10-bit D/A converter.

The TMC2490A operates from a single clock at 27 MHz, twice the system pixel rate. Programmable control registers allow software control of subcarrier frequency and phase

parameters. Incoming YC lated to YC

Internal control registers can be accessed over a standard 8-bit parallel microprocessor port or a 2-pin (clock and data) serial port.

444 format for encoding.

Sync Generator

The TMC2490A operates in master or slave mode. In slave mode, it extracts its horizontal and vertical sync timing and ﬁeld information from the CCIR-656 SAV (Start of Active Video) and EAV (End of Active Video) signal in the incoming data stream. In master mode, it generates a 13.5 MHz timebase and sends line and ﬁeld synchronizing signals to the host system.

Horizontal and vertical synchronization pulses in the analog output are digitally generated by the TMC2490A with controlled rise and fall times on all sync edges, the beginning and end of active video, and the burst envelope.

MSB LSB

422 digital video is interpo-

(n) PD

Y (n) PD

Chroma Modulator

A digital subcarrier synthesizer generates the reference for a quadrature modulator, producing a digital chrominance signal. The chroma bandwidth may be programmed to 650 kHz or 1.3 MHz.

Interpolation Filters

Interpolation ﬁlters on the luminance and chrominance signals double the pixel rate to 27Mpps before D/A conversion. This low-pass ﬁltering and oversampling process reduces sin(x)/x roll-off, and greatly simpliﬁes the analog reconstruction ﬁlter required after the D/A converters.

D/A Converters

Analog outputs of the TMC2490A are driven by three 10-bit D/A converters, The outputs drive standard video levels into

37.5 or 75 Ohm loads. An internal voltage reference is used to provide reference current for the D/A converters. An external ﬁxed or variable voltage reference source can also be used. The video signal levels from the TMC2490A may be adjusted to overcome the insertion loss of analog low-pass output ﬁlters by varying R

REF

or V

REF

Parallel and Serial Microprocessor Interfaces

The parallel microprocessor interface employs 11 pins. These are shared with the serial interface. A single pin, SER, selects between the two interface modes.

In parallel interface mode, one address pin is decoded to enable access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D write) for that address. The control register address pointer auto-increments to address 22h and then remains there.

A 2-line serial interface is also provided on the TMC2490A for initialization and control. The same set of registers accessed by the parallel port is available to the serial port.

The RESET registers to their initialized conditions, disables the analog

outputs, and places the encoder in a reset mode. At the rising edge of RESET NTSC-M format.

port, followed by the desired data (read or

7-0

pin sets all internal state machines and control

, the encoder is automatically initialized in

Figure 1. Pixel Data Format

(n) PD

Y (n+1) PD

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PRODUCT SPECIFICATION TMC2490A

Pin Assignments

SCL/CS

SER

D D D D

GND

D D D D

/ADR

SDA/R/W

SA1PD0GND

65432

1819202122232425262728

HSYNC

VSYNC,T/B

CBSEL,PDC

VDDPD1PD2PD3PD4PD

TMC2490A

SELC

RESET

4443424140

GND

PXCK

REFRREF

Pin Descriptions

Pin Name Pin Number Value Pin Function Description

Clock

PXCK 25 TTL

Data Input Port

7-0

38–44, 3 TTL

Microprocessor Interface

7-0

9–12, 14–17 TTL

RESET 22 TTL

, ADR 5 TTL

4 TTL

Pixel Clock Input. This 27.0 MHz clock is internally divided by 2

to generate the internal pixel clock. PXCK drives the entire TMC2490A, except the asynchronous microprocessor interface. All internal registers are strobed on the rising edge of PXCK.

Pixel Data Inputs. Video data enters the TMC2490A on

(Figure 1).

7-0

Data I/O, General Purpose I/O, Chroma Input Port. When SER

is HIGH, all control parameters are loaded into and read back over this 8-bit port. When SER = LOW, D composite sync output, D porch, D

are General Purpose Outputs, and D

2-5

Purpose Inputs.

Master Reset Input. Bringing RESET LOW forces the internal

state machines to their starting states and disables all outputs.

Serial/Parallel Port Select. When SER

conjunction with SA

selects one of four addresses for the

TMC2490A.

Serial/Parallel Port Select. When SER is LOW, SA

conjunction with SA

selects one-of-four addresses for the

TMC2490A. When SER is HIGH, this control governs whether the parallel microprocessor interface selects a table address or reads/writes table contents.

GND CHROMA V

DDA

BYP

LUMA GND COMPOSITE GND

65-2490(1)A-02

can serve as a

outputs a burst flag during the back

are General

6-7

is LOW, SA

TMC2490A PRODUCT SPECIFICATION

Pin Descriptions

Pin Name Pin Number Value Pin Function Description

SDA, R/W

SCL, CS

SER 8 TTL

Outputs

CHROMA 35 1.35V p-p Chrominance-only Video. Analog output of chrominance D/A

COMPOSITE 30 1.35V p-p Composite NTSC/PAL Video. Analog output of composite D/A

LUMA 32 1.35V p-p Luminance-only Video. Analog output of luminance D/A

Analog Interface

BYP

REF

SYNC Out

HSYNC 18 TTL

VSYNC

CBSEL

SELC 21 TTL

Power Supply

GND 2, 13, 24, 29,

, T/B 19 TTL

, PDC 20 TTL

DDA

(continued)

6 R-Bus/TTL Serial Data/Read/Write Control. When SER is LOW, SDA is the

data line of the serial interface. When SER is HIGH, the pin is the read/write control for the parallel interface. When R/W LOW, the microprocessor can write to the control registers over D

. When R/W

7-0

contents of any selected control register over D

7 R-Bus/TTL Serial Clock/Chip Select. When SER is LOW, SCL is the clock

line of the serial interface. When SER is HIGH, the pin is the chip select control for the parallel interface. When CS microprocessor interface port, D and ignored. When CS is LOW, the microprocessor can read or write parameters over D

Serial/Parallel Port Select. When LOW, the 2-line serial

interface is activated. Pins 5, 6, and 7 function as SA SCL respectively. When HIGH, the parallel interface port is active and pins 5, 6, and 7 function as ADR, R/W, and CS respectively.

converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load.

33 0.1 µ F

28 787 Ω

27 +1.235V Voltage Reference Input. External voltage reference input,

1, 23, 26, 37 +5V

0.0V

31, 36

34 +5V

Reference Bypass Capacitor. Connection point for 0.1 µ F

decoupling capacitor to V

Current-setting Resistor. Connection point for external current-

setting resistor for D/A converters. The resistor is connected between R proportional to the value of R

internal voltage reference output, nominally 1.235 V.

Horizontal Sync Output.

Vertical Sync Output or Odd/Even Field ID Output .

Pixel Data Phase Output or Video Blanking Output.

Luma/Chroma MUX Control.

Power Supply. Positive power supply.

Ground.

Analog Power Supply. Positive power supply.

is HIGH and CS is LOW, it can read the

7-0

is HIGH, the

, is set to HIGH impedance

7-0

at pin 34.

and GND. Output video levels are inversely

REF

and CS are

, SDA, and

REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Control Registers

The TMC2490A is initialized and controlled by a set of registers which determine the operating modes.

An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line

Table 1. Control Register Map

Reg Bit Mnemonic Function

TMC2490A Identiﬁcation Registers (Read only)

00 7-0 PARTID2 Reads back 97h

01 7-0 PARTID1 Reads back 24h

02 7-0 PARTID0 Reads back 90h (91h)

03 7-0 REVID Silicon revision #

Global Control Register

04 7 MASTER Master Mode

04 6 NGSEL NTSC Gain Select

04 5 YCDELAY Luma to chroma delay

04 4 RAMPEN Modulated ramp enable

04 3 YCDIS LUMA, CHROMA disable

04 2 COMPDIS COMPOSITE disable

04 1-0 FORMAT Television standard select

Video Output Control Register

05 7 PALN Select PAL-N Subcarrier

05 6 BURSTF

05 5 CHRBW Chroma bandwidth select

05 4 SYNCDIS Sync pulse disable

05 3 BURDIS Color burst disable

05 2 LUMDIS Luminance disable

05 1 CHRDIS Chrominance disable

05 0 PEDEN Pedestal enable

Field ID Register

06 7-6 Reserved Program LOW

06 5-3 FIELD Field ID (Read only)

06 2-0 Reserved Program LOW

Reserved Registers

07-0D7-0 Reserved Program LOW

Burst flag disable

serial interface port. The parallel port, D pins CS SDA and SCL.

Notes:

1. For each register listed above, all bits not specified are

, R/W, and ADR. The serial port is controlled by

Reg Bit Mnemonic Function

General Purpose Port Register

0E 7 PORT7-6 General purpose Inputs

0E 6 PORT5-2 General purpose Outputs

0E 1 BURSTF Burst Flag Output

0E 0 CSYNC Composite Sync Output

General Control Register

0F 7 PED21 VBI Pedestal Enable

0F 5 VSEL Vertical Sync Select

0F 4 CBSEL CBSEL/PDC Pin Function

0F 3 VBIEN VBI Pixel Data Enable

0F 1-0 HDSEL HSYNC Delay

Reserved Registers

10-1F7-0 Reserved May be left unprogrammed

Closed-Caption Insertion Registers

20 7-0 CCD1 First Byte of CC Data

21 7-0 CCD2 Second Byte of CC Data

22 7 CCON Enable CC Data Packet

22 6 CCRTS Request To Send Data

22 5 CCPAR Auto Parity Generation

22 4 CCFLD CC Field Select

22 3-0 CCLINE CC Line Select

reserved and should be set to logic LOW to ensure proper operation.

, is governed by

7-0

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TMC2490A PRODUCT SPECIFICATION

Table 2. Default Register Values on Reset

Reg Dﬂt Reg Dﬂt Reg Dﬂt Reg Dﬂt Reg Dﬂt

00 97 04 00 08 00 0C 00 20 80

01 24 05 01 09 00 0D 00 21 80

02 90(91) 06 00 0A 00 0E 00 22 00

03 xx 07 00 0B 00 0F F2

Control Register Deﬁnitions

Reg Bit Name Description

00 7–0 PARTID2 Reads back 97h

01 7–0 PARTID1 Reads back 24h

02 7–0 PARTID0 Reads back 90h (91h)

03 7–0 REVID Reads back a value corresponding to the revision letter of the silicon.

Global Control Register (04)

76543210

MASTER NGSEL YCDELAY RAMPEN YCDIS COMPDIS FORMAT

Reg Bit Name Description

04 7 MASTER Master Mode. When MASTER = 1, the encoder generates its own video

timing and outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL). When MASTER = 0, the TMC2490A extracts timing from the embedded EAV codeword in the video datastream and optionally outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL).

04 6 NGSEL NTSC Gain Selection.

04 5 YCDELAY Luma to chroma delay. When HIGH, the luminance path within the

TMC2490A is delayed by one PXCK period. The delay applies to both COMPOSITE and LUMA outputs and may be used to compensate for group delay variation of external filters. When LOW, luminance and chrominance have the same latency.

04 4 RAMPEN Modulated ramp enable. When HIGH, the TMC2490A outputs a modulated

ramp test signal. When LOW, incoming digital video is encoded.

04 3 YCDIS LUMA, CHROMA disable. When HIGH, the LUMA and CHROMA outputs

are disabled. Set LOW for normal enabled operation.

04 2 COMPDIS COMPOSITE disable. When HIGH, the COMPOSITE output is disabled.

Set LOW for normal enabled operation.

04 1–0 FORMAT Television standard select. Selects basic H&V timing parameters and

subcarrier frequency. Pedestal level and chrominance bandwidth are independently programmed.

0 0 NTSC 0 1 PAL-B,G,H,I,N 1 0 PAL-M 1 1 Reserved

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PRODUCT SPECIFICATION TMC2490A

Control Register Deﬁnitions (continued)

Video Output Control Register (05)

76543210

PALN BURSTF CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN

Reg Bit Name Description

05 7 PALN Select PAL-N Subcarrier. When HIGH, selects PAL-N subcarrier

frequency. When LOW, the encoder produces the PAL-B,G,H,I subcarrier. Program LOW for NTSC and PAL-M video.

05 6 BURSTF Burst flag disable. When BURSTF is LOW, a clamp gate signal is

produced on the D1 output and register 0E bit 1.

05 5 CHRBW Chroma bandwidth select. When LOW, the chrominance bandwidth is

±650 kHz. When HIGH, the chrominance bandwidth is ±1.3 MHz.

05 4 SYNCDIS Sync pulse disable. When HIGH, horizontal and vertical sync pulses on the

COMPOSITE video output are suppressed (to blanking level). Color burst, active video, and the CSYNC composite video operation.

05 3 BURDIS Color burst disable. When HIGH, color burst is suppressed to the blanking

level. Set LOW for normal operation.

05 2 LUMDIS Luminance disable. When HIGH, incoming Y values are forced to black

level. Color burst, CHROMA, and sync are not affected. Set LOW for normal operation.

05 1 CHRDIS Chrominance disable. When HIGH, incoming color components CB and

CR are suppressed, enabling monochrome operation. Output color burst is not affected. Set LOW for normal color operation.

05 0 PEDEN Pedestal enable. When LOW, black and blanking are the same level for

ALL lines. When HIGH, a 7.5 IRE pedestal is inserted into the output video for NTSC and PAL-M lines 23-262 and 286-525 only. Chrominance and luminance gain factors are adjusted to keep video levels within range. PEDEN is valid for NTSC and PAL-M only and should be LOW for all other formats.

output remain active. Set LOW for normal

Field Data Register (06)

76543210

Reserved FIELD Reserved

Reg Bit Name Description

06 7–6 Reserved Program LOW.

06 5–3 FIELD Field ID (Read only). A value of 000 corresponds to field 1 and 111

corresponds to field 8.

06 2–0 Reserved Program LOW.

TMC2490A PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Reserved Registers (07–0D)

76543210

Reserved

Reg Bit Name Description

07–0D7–0 Reserved Program LOW.

General Purpose Port Register (0E)

76543210

PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 BURSTF CSYNC

Reg Bit Name Description

0E 7–6 PORT7–6 General purpose Inputs. When in serial control mode, these register read-

only bits indicate the state present on data port pins D7 and D6.

0E 5–2 PORT5–2 General purpose Outputs. When in serial control mode or when reading

register 0E in parallel control mode, these register read/write bits drive data pins D5–D2 to the state contained in the respective register bits.

0E 1 BURSTF Burst Flag Output. Produces Burst Flag on data pin D1 when in serial

0E 0 CSYNC Composite Sync Output. Produces Composite Sync on data pin D0 when

control mode, or when reading register 0E.

in serial control mode, or when reading register 0E.

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PRODUCT SPECIFICATION TMC2490A

Control Register Deﬁnitions (continued)

General Control Register (0F)

76543210

PED21 Reserved VSEL CBSEL VBIEN Reserved

Reg Bit Name Description

0F 7 PED21 VBI Pedestal Enable. When HIGH and FORMAT is 00 (NTSC) or 10

(PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only and should be LOW for all other formats.

0F 6 Reserved Program HIGH.

0F 5 VSEL Vertical Sync Select. When LOW, the TMC2490A outputs a traditional

vertical sync on VSYNC identification on the VSYNC

0F 4 CBSEL CBSEL/PDC pin function. When CBSEL = 0, the PDC signal is produced

on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced on the CBSEL/PDC pin.

0F 3 VBIEN VBI Pixel Data Enable. When VBIEN = 0, the vertical interval lines are

blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines.

0F 2 Reserved Program LOW.

0F 1–0 HDEL Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the

PD port.

HDEL Result

00 H and V syncs are aligned with luminance pixel 735 (Y735) 01 H and V syncs are aligned with Blue color difference pixel 735

(Cb736) 10 H and V syncs are aligned with luminance pixel 736 (Y736) 11 H and V syncs are aligned with Red color difference pixel 735

(Cr736)

. When HIGH, the chip outputs odd/even field

pin, with 0 denoting an odd field.

Refer to Figure 2a, HDEL Timing

Reserved Registers (10–1F)

76543210

Reserved

Reg Bit Name Description

10–1F7–0 Reserved May be left unprogrammed

PRODUCT SPECIFICATION TMC2490A

Control Register Deﬁnitions (continued)

Closed-Caption Insertion (20)

76543210

CCD1

Reg Bit Name Description

20 7–0 CCD1 First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an

ODD Parity bit if CCPAR is HIGH.

Closed-Caption Insertion (21)

76543210

CCD2

Reg Bit Name Description

21 7–0 CCD2 Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by

an ODD Parity bit if CCPAR is HIGH.

Closed-Caption Insertion (22)

76543210

CCON CCRTS CCPAR CCFLD CCLINE

Reg Bit Name Description

22 7 CCON Enable CC Data Packet. Command the CC data generator to send either

CC data or a NULL byte whenever the specified line is transmitted.

22 6 CCRTS Request To Send Data. This bit is set HIGH by the user when bytes 20 and

21 have been loaded with the next two bytes to be sent. When the encoder reaches the falling edge of the HSYNC preceding the line specified in bits 4-0 of this register, data will be transferred from registers 20 and 21, and RTS will be reset LOW. A new pair of bytes may then be loaded into registers 20 and 21. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL bytes will be sent.

22 5 CCPAR Auto Parity Generation. When set HIGH, the encoder replaces the MSB of

bytes 20 and 21 with a calculated ODD parity. When set LOW, the CC processor transmits the 16 bits exactly as loaded into registers 20 and 21.

22 4 CCFLD CC Field Select. When LOW, CC data is transmitted on the selected line of

ODD fields. When HIGH, it is sent on EVEN fields.

22 3–0 CCLINE CC Line Select. Defines (with an offset) the line on which CC data is

transmitted.

PRODUCT SPECIFICATION TMC2490A

General Purpose Port

The TMC2490A provides a general purpose I/O port for system utility functions. Input, output, and sync functions are implemented. Register 0E is the General Purpose Register.

Full functionality is provided when the encoder is in Serial control mode (SER able in parallel interface mode (SER = HIGH).

General Purpose Input (serial mode only)

Bits 7 and 6 of Register 0E are general purpose inputs. When the encoder is in serial control mode, data bits D mirrored to these register locations. When Register 0E is read, the states of bits 7 and 6 reﬂect the TTL logic levels present on D7 and D6, respectively, at the time of read command execution. Writing to these bits has no effect.

This function is not available when the encoder is in parallel control mode.

General Purpose Output

Register 0E read/write bits 5-2 are connected to pins D respectively, when the encoder is in serial control mode. The output pins continually reﬂects the values most recently written into register 0E (1 = HIGH, 0 = LOW). Note that these pins are always driven outputs when the encoder is in serial control mode.

When register 0E is read, these pins report the values previously stored in the corresponding register bits, i.e., it acts as a read/write register. When the encoder is in parallel control mode, this reading produces the output bit values on the corresponding data pins, just as in the serial control mode. However, the values are only present when reading register 0E. The controller can command a continuous read on this register to produce continuous outputs from these pins.

Burst Flag and Composite Sync (output/ read-only)

Register 0E bit 1 is associated with the encoder burst ﬂag. It is a 1 (HIGH) from just before the start of the color burst to just after the end of the burst. It is a 0 (LOW) at all other times.

Register 0E bit 0 outputs the encoder composite sync status. It is a 0 (LOW) during horizontal and vertical sync tips. It is a 1 (HIGH) at all other times.

= LOW). Most of the functions are avail-

and D6 are

5-2

In serial control mode, these same data output pins (D always act as a burst ﬂag and composite sync TTL outputs, the conditions of the serial control notwithstanding. The states of the ﬂags may be read over the serial port, but due to the low frequency of the serial interface, it may be difﬁcult to get meaningful information.

1-0

)

Pixel Interface

The TMC2490A interfaces with an 8-bit 13.5 Mpps (27 MHz) video datastream. It will automatically synchronize with embedded Timing Reference Signals, per CCIR-656. It also includes a master sync generator on-chip, which can produce timing reference outputs.

CCIR-656 Mode

When operating in CCIR-656 Mode (MASTER = 0), the TMC2490A identiﬁes the SAV and EAV 4-byte codewords embedded in the video datastream to derive all timing. Both SAV and EAV are required.

MASTER Mode

When in MASTER Mode (MASTER = 1), the Encoder produces its own timing, and provides HSYNC, VSYNC (or B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source.

SELC Output

The SELC output toggles at 13.5 MHz (1/2 the pixel rate), providing a phase reference for the multiplexed luma/chroma CCIR-656 datastream. It is HIGH during the rising edge of the clock intended to load chroma data. This is useful when interfacing with a 16-bit data source, and can drive a Y/C multiplexer.

CBSEL Output

The CBSEL output identiﬁes the CB element of the CB-Y-

-Y CCIR-656 data sequence. It is HIGH during the rising

edge of the clock to load C tionally swapping the CB and CR color components when operating in MASTER mode and reading data from a framestore.

PDC Output

The PDC output is a blanking signal, indicating when the encoder expected to receive pixel data. When PDC is HIGH, the incoming PD is encoded.

data. This will prevent uninten-

These register bits may be read at any time over either the serial or parallel control port. Since they are dynamic, their states will change as appropriate during a parallel port read. In fact, if the parallel control port is commanded to read register 0E continually, the pins associated with these bits behave as burst ﬂag and composite sync timing outputs.

REV. 1.0.2 2/27/02 11

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